drm/i915: make the panel fitter work on pipes B and C on IVB
[linux-2.6.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *      Eric Anholt <eric@anholt.net>
25  */
26
27 #include <linux/cpufreq.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include "drmP.h"
36 #include "intel_drv.h"
37 #include "i915_drm.h"
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
43
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_update_watermarks(struct drm_device *dev);
48 static void intel_increase_pllclock(struct drm_crtc *crtc);
49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
50
51 typedef struct {
52         /* given values */
53         int n;
54         int m1, m2;
55         int p1, p2;
56         /* derived values */
57         int     dot;
58         int     vco;
59         int     m;
60         int     p;
61 } intel_clock_t;
62
63 typedef struct {
64         int     min, max;
65 } intel_range_t;
66
67 typedef struct {
68         int     dot_limit;
69         int     p2_slow, p2_fast;
70 } intel_p2_t;
71
72 #define INTEL_P2_NUM                  2
73 typedef struct intel_limit intel_limit_t;
74 struct intel_limit {
75         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
76         intel_p2_t          p2;
77         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
78                         int, int, intel_clock_t *, intel_clock_t *);
79 };
80
81 /* FDI */
82 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
83
84 static bool
85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
86                     int target, int refclk, intel_clock_t *match_clock,
87                     intel_clock_t *best_clock);
88 static bool
89 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
90                         int target, int refclk, intel_clock_t *match_clock,
91                         intel_clock_t *best_clock);
92
93 static bool
94 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
95                       int target, int refclk, intel_clock_t *match_clock,
96                       intel_clock_t *best_clock);
97 static bool
98 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
99                            int target, int refclk, intel_clock_t *match_clock,
100                            intel_clock_t *best_clock);
101
102 static inline u32 /* units of 100MHz */
103 intel_fdi_link_freq(struct drm_device *dev)
104 {
105         if (IS_GEN5(dev)) {
106                 struct drm_i915_private *dev_priv = dev->dev_private;
107                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
108         } else
109                 return 27;
110 }
111
112 static const intel_limit_t intel_limits_i8xx_dvo = {
113         .dot = { .min = 25000, .max = 350000 },
114         .vco = { .min = 930000, .max = 1400000 },
115         .n = { .min = 3, .max = 16 },
116         .m = { .min = 96, .max = 140 },
117         .m1 = { .min = 18, .max = 26 },
118         .m2 = { .min = 6, .max = 16 },
119         .p = { .min = 4, .max = 128 },
120         .p1 = { .min = 2, .max = 33 },
121         .p2 = { .dot_limit = 165000,
122                 .p2_slow = 4, .p2_fast = 2 },
123         .find_pll = intel_find_best_PLL,
124 };
125
126 static const intel_limit_t intel_limits_i8xx_lvds = {
127         .dot = { .min = 25000, .max = 350000 },
128         .vco = { .min = 930000, .max = 1400000 },
129         .n = { .min = 3, .max = 16 },
130         .m = { .min = 96, .max = 140 },
131         .m1 = { .min = 18, .max = 26 },
132         .m2 = { .min = 6, .max = 16 },
133         .p = { .min = 4, .max = 128 },
134         .p1 = { .min = 1, .max = 6 },
135         .p2 = { .dot_limit = 165000,
136                 .p2_slow = 14, .p2_fast = 7 },
137         .find_pll = intel_find_best_PLL,
138 };
139
140 static const intel_limit_t intel_limits_i9xx_sdvo = {
141         .dot = { .min = 20000, .max = 400000 },
142         .vco = { .min = 1400000, .max = 2800000 },
143         .n = { .min = 1, .max = 6 },
144         .m = { .min = 70, .max = 120 },
145         .m1 = { .min = 10, .max = 22 },
146         .m2 = { .min = 5, .max = 9 },
147         .p = { .min = 5, .max = 80 },
148         .p1 = { .min = 1, .max = 8 },
149         .p2 = { .dot_limit = 200000,
150                 .p2_slow = 10, .p2_fast = 5 },
151         .find_pll = intel_find_best_PLL,
152 };
153
154 static const intel_limit_t intel_limits_i9xx_lvds = {
155         .dot = { .min = 20000, .max = 400000 },
156         .vco = { .min = 1400000, .max = 2800000 },
157         .n = { .min = 1, .max = 6 },
158         .m = { .min = 70, .max = 120 },
159         .m1 = { .min = 10, .max = 22 },
160         .m2 = { .min = 5, .max = 9 },
161         .p = { .min = 7, .max = 98 },
162         .p1 = { .min = 1, .max = 8 },
163         .p2 = { .dot_limit = 112000,
164                 .p2_slow = 14, .p2_fast = 7 },
165         .find_pll = intel_find_best_PLL,
166 };
167
168
169 static const intel_limit_t intel_limits_g4x_sdvo = {
170         .dot = { .min = 25000, .max = 270000 },
171         .vco = { .min = 1750000, .max = 3500000},
172         .n = { .min = 1, .max = 4 },
173         .m = { .min = 104, .max = 138 },
174         .m1 = { .min = 17, .max = 23 },
175         .m2 = { .min = 5, .max = 11 },
176         .p = { .min = 10, .max = 30 },
177         .p1 = { .min = 1, .max = 3},
178         .p2 = { .dot_limit = 270000,
179                 .p2_slow = 10,
180                 .p2_fast = 10
181         },
182         .find_pll = intel_g4x_find_best_PLL,
183 };
184
185 static const intel_limit_t intel_limits_g4x_hdmi = {
186         .dot = { .min = 22000, .max = 400000 },
187         .vco = { .min = 1750000, .max = 3500000},
188         .n = { .min = 1, .max = 4 },
189         .m = { .min = 104, .max = 138 },
190         .m1 = { .min = 16, .max = 23 },
191         .m2 = { .min = 5, .max = 11 },
192         .p = { .min = 5, .max = 80 },
193         .p1 = { .min = 1, .max = 8},
194         .p2 = { .dot_limit = 165000,
195                 .p2_slow = 10, .p2_fast = 5 },
196         .find_pll = intel_g4x_find_best_PLL,
197 };
198
199 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
200         .dot = { .min = 20000, .max = 115000 },
201         .vco = { .min = 1750000, .max = 3500000 },
202         .n = { .min = 1, .max = 3 },
203         .m = { .min = 104, .max = 138 },
204         .m1 = { .min = 17, .max = 23 },
205         .m2 = { .min = 5, .max = 11 },
206         .p = { .min = 28, .max = 112 },
207         .p1 = { .min = 2, .max = 8 },
208         .p2 = { .dot_limit = 0,
209                 .p2_slow = 14, .p2_fast = 14
210         },
211         .find_pll = intel_g4x_find_best_PLL,
212 };
213
214 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
215         .dot = { .min = 80000, .max = 224000 },
216         .vco = { .min = 1750000, .max = 3500000 },
217         .n = { .min = 1, .max = 3 },
218         .m = { .min = 104, .max = 138 },
219         .m1 = { .min = 17, .max = 23 },
220         .m2 = { .min = 5, .max = 11 },
221         .p = { .min = 14, .max = 42 },
222         .p1 = { .min = 2, .max = 6 },
223         .p2 = { .dot_limit = 0,
224                 .p2_slow = 7, .p2_fast = 7
225         },
226         .find_pll = intel_g4x_find_best_PLL,
227 };
228
229 static const intel_limit_t intel_limits_g4x_display_port = {
230         .dot = { .min = 161670, .max = 227000 },
231         .vco = { .min = 1750000, .max = 3500000},
232         .n = { .min = 1, .max = 2 },
233         .m = { .min = 97, .max = 108 },
234         .m1 = { .min = 0x10, .max = 0x12 },
235         .m2 = { .min = 0x05, .max = 0x06 },
236         .p = { .min = 10, .max = 20 },
237         .p1 = { .min = 1, .max = 2},
238         .p2 = { .dot_limit = 0,
239                 .p2_slow = 10, .p2_fast = 10 },
240         .find_pll = intel_find_pll_g4x_dp,
241 };
242
243 static const intel_limit_t intel_limits_pineview_sdvo = {
244         .dot = { .min = 20000, .max = 400000},
245         .vco = { .min = 1700000, .max = 3500000 },
246         /* Pineview's Ncounter is a ring counter */
247         .n = { .min = 3, .max = 6 },
248         .m = { .min = 2, .max = 256 },
249         /* Pineview only has one combined m divider, which we treat as m2. */
250         .m1 = { .min = 0, .max = 0 },
251         .m2 = { .min = 0, .max = 254 },
252         .p = { .min = 5, .max = 80 },
253         .p1 = { .min = 1, .max = 8 },
254         .p2 = { .dot_limit = 200000,
255                 .p2_slow = 10, .p2_fast = 5 },
256         .find_pll = intel_find_best_PLL,
257 };
258
259 static const intel_limit_t intel_limits_pineview_lvds = {
260         .dot = { .min = 20000, .max = 400000 },
261         .vco = { .min = 1700000, .max = 3500000 },
262         .n = { .min = 3, .max = 6 },
263         .m = { .min = 2, .max = 256 },
264         .m1 = { .min = 0, .max = 0 },
265         .m2 = { .min = 0, .max = 254 },
266         .p = { .min = 7, .max = 112 },
267         .p1 = { .min = 1, .max = 8 },
268         .p2 = { .dot_limit = 112000,
269                 .p2_slow = 14, .p2_fast = 14 },
270         .find_pll = intel_find_best_PLL,
271 };
272
273 /* Ironlake / Sandybridge
274  *
275  * We calculate clock using (register_value + 2) for N/M1/M2, so here
276  * the range value for them is (actual_value - 2).
277  */
278 static const intel_limit_t intel_limits_ironlake_dac = {
279         .dot = { .min = 25000, .max = 350000 },
280         .vco = { .min = 1760000, .max = 3510000 },
281         .n = { .min = 1, .max = 5 },
282         .m = { .min = 79, .max = 127 },
283         .m1 = { .min = 12, .max = 22 },
284         .m2 = { .min = 5, .max = 9 },
285         .p = { .min = 5, .max = 80 },
286         .p1 = { .min = 1, .max = 8 },
287         .p2 = { .dot_limit = 225000,
288                 .p2_slow = 10, .p2_fast = 5 },
289         .find_pll = intel_g4x_find_best_PLL,
290 };
291
292 static const intel_limit_t intel_limits_ironlake_single_lvds = {
293         .dot = { .min = 25000, .max = 350000 },
294         .vco = { .min = 1760000, .max = 3510000 },
295         .n = { .min = 1, .max = 3 },
296         .m = { .min = 79, .max = 118 },
297         .m1 = { .min = 12, .max = 22 },
298         .m2 = { .min = 5, .max = 9 },
299         .p = { .min = 28, .max = 112 },
300         .p1 = { .min = 2, .max = 8 },
301         .p2 = { .dot_limit = 225000,
302                 .p2_slow = 14, .p2_fast = 14 },
303         .find_pll = intel_g4x_find_best_PLL,
304 };
305
306 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
307         .dot = { .min = 25000, .max = 350000 },
308         .vco = { .min = 1760000, .max = 3510000 },
309         .n = { .min = 1, .max = 3 },
310         .m = { .min = 79, .max = 127 },
311         .m1 = { .min = 12, .max = 22 },
312         .m2 = { .min = 5, .max = 9 },
313         .p = { .min = 14, .max = 56 },
314         .p1 = { .min = 2, .max = 8 },
315         .p2 = { .dot_limit = 225000,
316                 .p2_slow = 7, .p2_fast = 7 },
317         .find_pll = intel_g4x_find_best_PLL,
318 };
319
320 /* LVDS 100mhz refclk limits. */
321 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
322         .dot = { .min = 25000, .max = 350000 },
323         .vco = { .min = 1760000, .max = 3510000 },
324         .n = { .min = 1, .max = 2 },
325         .m = { .min = 79, .max = 126 },
326         .m1 = { .min = 12, .max = 22 },
327         .m2 = { .min = 5, .max = 9 },
328         .p = { .min = 28, .max = 112 },
329         .p1 = { .min = 2, .max = 8 },
330         .p2 = { .dot_limit = 225000,
331                 .p2_slow = 14, .p2_fast = 14 },
332         .find_pll = intel_g4x_find_best_PLL,
333 };
334
335 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
336         .dot = { .min = 25000, .max = 350000 },
337         .vco = { .min = 1760000, .max = 3510000 },
338         .n = { .min = 1, .max = 3 },
339         .m = { .min = 79, .max = 126 },
340         .m1 = { .min = 12, .max = 22 },
341         .m2 = { .min = 5, .max = 9 },
342         .p = { .min = 14, .max = 42 },
343         .p1 = { .min = 2, .max = 6 },
344         .p2 = { .dot_limit = 225000,
345                 .p2_slow = 7, .p2_fast = 7 },
346         .find_pll = intel_g4x_find_best_PLL,
347 };
348
349 static const intel_limit_t intel_limits_ironlake_display_port = {
350         .dot = { .min = 25000, .max = 350000 },
351         .vco = { .min = 1760000, .max = 3510000},
352         .n = { .min = 1, .max = 2 },
353         .m = { .min = 81, .max = 90 },
354         .m1 = { .min = 12, .max = 22 },
355         .m2 = { .min = 5, .max = 9 },
356         .p = { .min = 10, .max = 20 },
357         .p1 = { .min = 1, .max = 2},
358         .p2 = { .dot_limit = 0,
359                 .p2_slow = 10, .p2_fast = 10 },
360         .find_pll = intel_find_pll_ironlake_dp,
361 };
362
363 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
364                                                 int refclk)
365 {
366         struct drm_device *dev = crtc->dev;
367         struct drm_i915_private *dev_priv = dev->dev_private;
368         const intel_limit_t *limit;
369
370         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
371                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
372                     LVDS_CLKB_POWER_UP) {
373                         /* LVDS dual channel */
374                         if (refclk == 100000)
375                                 limit = &intel_limits_ironlake_dual_lvds_100m;
376                         else
377                                 limit = &intel_limits_ironlake_dual_lvds;
378                 } else {
379                         if (refclk == 100000)
380                                 limit = &intel_limits_ironlake_single_lvds_100m;
381                         else
382                                 limit = &intel_limits_ironlake_single_lvds;
383                 }
384         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
385                         HAS_eDP)
386                 limit = &intel_limits_ironlake_display_port;
387         else
388                 limit = &intel_limits_ironlake_dac;
389
390         return limit;
391 }
392
393 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
394 {
395         struct drm_device *dev = crtc->dev;
396         struct drm_i915_private *dev_priv = dev->dev_private;
397         const intel_limit_t *limit;
398
399         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
400                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
401                     LVDS_CLKB_POWER_UP)
402                         /* LVDS with dual channel */
403                         limit = &intel_limits_g4x_dual_channel_lvds;
404                 else
405                         /* LVDS with dual channel */
406                         limit = &intel_limits_g4x_single_channel_lvds;
407         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
408                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
409                 limit = &intel_limits_g4x_hdmi;
410         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
411                 limit = &intel_limits_g4x_sdvo;
412         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
413                 limit = &intel_limits_g4x_display_port;
414         } else /* The option is for other outputs */
415                 limit = &intel_limits_i9xx_sdvo;
416
417         return limit;
418 }
419
420 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
421 {
422         struct drm_device *dev = crtc->dev;
423         const intel_limit_t *limit;
424
425         if (HAS_PCH_SPLIT(dev))
426                 limit = intel_ironlake_limit(crtc, refclk);
427         else if (IS_G4X(dev)) {
428                 limit = intel_g4x_limit(crtc);
429         } else if (IS_PINEVIEW(dev)) {
430                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
431                         limit = &intel_limits_pineview_lvds;
432                 else
433                         limit = &intel_limits_pineview_sdvo;
434         } else if (!IS_GEN2(dev)) {
435                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
436                         limit = &intel_limits_i9xx_lvds;
437                 else
438                         limit = &intel_limits_i9xx_sdvo;
439         } else {
440                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
441                         limit = &intel_limits_i8xx_lvds;
442                 else
443                         limit = &intel_limits_i8xx_dvo;
444         }
445         return limit;
446 }
447
448 /* m1 is reserved as 0 in Pineview, n is a ring counter */
449 static void pineview_clock(int refclk, intel_clock_t *clock)
450 {
451         clock->m = clock->m2 + 2;
452         clock->p = clock->p1 * clock->p2;
453         clock->vco = refclk * clock->m / clock->n;
454         clock->dot = clock->vco / clock->p;
455 }
456
457 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
458 {
459         if (IS_PINEVIEW(dev)) {
460                 pineview_clock(refclk, clock);
461                 return;
462         }
463         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
464         clock->p = clock->p1 * clock->p2;
465         clock->vco = refclk * clock->m / (clock->n + 2);
466         clock->dot = clock->vco / clock->p;
467 }
468
469 /**
470  * Returns whether any output on the specified pipe is of the specified type
471  */
472 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
473 {
474         struct drm_device *dev = crtc->dev;
475         struct drm_mode_config *mode_config = &dev->mode_config;
476         struct intel_encoder *encoder;
477
478         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
479                 if (encoder->base.crtc == crtc && encoder->type == type)
480                         return true;
481
482         return false;
483 }
484
485 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
486 /**
487  * Returns whether the given set of divisors are valid for a given refclk with
488  * the given connectors.
489  */
490
491 static bool intel_PLL_is_valid(struct drm_device *dev,
492                                const intel_limit_t *limit,
493                                const intel_clock_t *clock)
494 {
495         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
496                 INTELPllInvalid("p1 out of range\n");
497         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
498                 INTELPllInvalid("p out of range\n");
499         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
500                 INTELPllInvalid("m2 out of range\n");
501         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
502                 INTELPllInvalid("m1 out of range\n");
503         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
504                 INTELPllInvalid("m1 <= m2\n");
505         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
506                 INTELPllInvalid("m out of range\n");
507         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
508                 INTELPllInvalid("n out of range\n");
509         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
510                 INTELPllInvalid("vco out of range\n");
511         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
512          * connector, etc., rather than just a single range.
513          */
514         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
515                 INTELPllInvalid("dot out of range\n");
516
517         return true;
518 }
519
520 static bool
521 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
522                     int target, int refclk, intel_clock_t *match_clock,
523                     intel_clock_t *best_clock)
524
525 {
526         struct drm_device *dev = crtc->dev;
527         struct drm_i915_private *dev_priv = dev->dev_private;
528         intel_clock_t clock;
529         int err = target;
530
531         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
532             (I915_READ(LVDS)) != 0) {
533                 /*
534                  * For LVDS, if the panel is on, just rely on its current
535                  * settings for dual-channel.  We haven't figured out how to
536                  * reliably set up different single/dual channel state, if we
537                  * even can.
538                  */
539                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
540                     LVDS_CLKB_POWER_UP)
541                         clock.p2 = limit->p2.p2_fast;
542                 else
543                         clock.p2 = limit->p2.p2_slow;
544         } else {
545                 if (target < limit->p2.dot_limit)
546                         clock.p2 = limit->p2.p2_slow;
547                 else
548                         clock.p2 = limit->p2.p2_fast;
549         }
550
551         memset(best_clock, 0, sizeof(*best_clock));
552
553         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
554              clock.m1++) {
555                 for (clock.m2 = limit->m2.min;
556                      clock.m2 <= limit->m2.max; clock.m2++) {
557                         /* m1 is always 0 in Pineview */
558                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
559                                 break;
560                         for (clock.n = limit->n.min;
561                              clock.n <= limit->n.max; clock.n++) {
562                                 for (clock.p1 = limit->p1.min;
563                                         clock.p1 <= limit->p1.max; clock.p1++) {
564                                         int this_err;
565
566                                         intel_clock(dev, refclk, &clock);
567                                         if (!intel_PLL_is_valid(dev, limit,
568                                                                 &clock))
569                                                 continue;
570                                         if (match_clock &&
571                                             clock.p != match_clock->p)
572                                                 continue;
573
574                                         this_err = abs(clock.dot - target);
575                                         if (this_err < err) {
576                                                 *best_clock = clock;
577                                                 err = this_err;
578                                         }
579                                 }
580                         }
581                 }
582         }
583
584         return (err != target);
585 }
586
587 static bool
588 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
589                         int target, int refclk, intel_clock_t *match_clock,
590                         intel_clock_t *best_clock)
591 {
592         struct drm_device *dev = crtc->dev;
593         struct drm_i915_private *dev_priv = dev->dev_private;
594         intel_clock_t clock;
595         int max_n;
596         bool found;
597         /* approximately equals target * 0.00585 */
598         int err_most = (target >> 8) + (target >> 9);
599         found = false;
600
601         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
602                 int lvds_reg;
603
604                 if (HAS_PCH_SPLIT(dev))
605                         lvds_reg = PCH_LVDS;
606                 else
607                         lvds_reg = LVDS;
608                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
609                     LVDS_CLKB_POWER_UP)
610                         clock.p2 = limit->p2.p2_fast;
611                 else
612                         clock.p2 = limit->p2.p2_slow;
613         } else {
614                 if (target < limit->p2.dot_limit)
615                         clock.p2 = limit->p2.p2_slow;
616                 else
617                         clock.p2 = limit->p2.p2_fast;
618         }
619
620         memset(best_clock, 0, sizeof(*best_clock));
621         max_n = limit->n.max;
622         /* based on hardware requirement, prefer smaller n to precision */
623         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
624                 /* based on hardware requirement, prefere larger m1,m2 */
625                 for (clock.m1 = limit->m1.max;
626                      clock.m1 >= limit->m1.min; clock.m1--) {
627                         for (clock.m2 = limit->m2.max;
628                              clock.m2 >= limit->m2.min; clock.m2--) {
629                                 for (clock.p1 = limit->p1.max;
630                                      clock.p1 >= limit->p1.min; clock.p1--) {
631                                         int this_err;
632
633                                         intel_clock(dev, refclk, &clock);
634                                         if (!intel_PLL_is_valid(dev, limit,
635                                                                 &clock))
636                                                 continue;
637                                         if (match_clock &&
638                                             clock.p != match_clock->p)
639                                                 continue;
640
641                                         this_err = abs(clock.dot - target);
642                                         if (this_err < err_most) {
643                                                 *best_clock = clock;
644                                                 err_most = this_err;
645                                                 max_n = clock.n;
646                                                 found = true;
647                                         }
648                                 }
649                         }
650                 }
651         }
652         return found;
653 }
654
655 static bool
656 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
657                            int target, int refclk, intel_clock_t *match_clock,
658                            intel_clock_t *best_clock)
659 {
660         struct drm_device *dev = crtc->dev;
661         intel_clock_t clock;
662
663         if (target < 200000) {
664                 clock.n = 1;
665                 clock.p1 = 2;
666                 clock.p2 = 10;
667                 clock.m1 = 12;
668                 clock.m2 = 9;
669         } else {
670                 clock.n = 2;
671                 clock.p1 = 1;
672                 clock.p2 = 10;
673                 clock.m1 = 14;
674                 clock.m2 = 8;
675         }
676         intel_clock(dev, refclk, &clock);
677         memcpy(best_clock, &clock, sizeof(intel_clock_t));
678         return true;
679 }
680
681 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
682 static bool
683 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
684                       int target, int refclk, intel_clock_t *match_clock,
685                       intel_clock_t *best_clock)
686 {
687         intel_clock_t clock;
688         if (target < 200000) {
689                 clock.p1 = 2;
690                 clock.p2 = 10;
691                 clock.n = 2;
692                 clock.m1 = 23;
693                 clock.m2 = 8;
694         } else {
695                 clock.p1 = 1;
696                 clock.p2 = 10;
697                 clock.n = 1;
698                 clock.m1 = 14;
699                 clock.m2 = 2;
700         }
701         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
702         clock.p = (clock.p1 * clock.p2);
703         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
704         clock.vco = 0;
705         memcpy(best_clock, &clock, sizeof(intel_clock_t));
706         return true;
707 }
708
709 /**
710  * intel_wait_for_vblank - wait for vblank on a given pipe
711  * @dev: drm device
712  * @pipe: pipe to wait for
713  *
714  * Wait for vblank to occur on a given pipe.  Needed for various bits of
715  * mode setting code.
716  */
717 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
718 {
719         struct drm_i915_private *dev_priv = dev->dev_private;
720         int pipestat_reg = PIPESTAT(pipe);
721
722         /* Clear existing vblank status. Note this will clear any other
723          * sticky status fields as well.
724          *
725          * This races with i915_driver_irq_handler() with the result
726          * that either function could miss a vblank event.  Here it is not
727          * fatal, as we will either wait upon the next vblank interrupt or
728          * timeout.  Generally speaking intel_wait_for_vblank() is only
729          * called during modeset at which time the GPU should be idle and
730          * should *not* be performing page flips and thus not waiting on
731          * vblanks...
732          * Currently, the result of us stealing a vblank from the irq
733          * handler is that a single frame will be skipped during swapbuffers.
734          */
735         I915_WRITE(pipestat_reg,
736                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
737
738         /* Wait for vblank interrupt bit to set */
739         if (wait_for(I915_READ(pipestat_reg) &
740                      PIPE_VBLANK_INTERRUPT_STATUS,
741                      50))
742                 DRM_DEBUG_KMS("vblank wait timed out\n");
743 }
744
745 /*
746  * intel_wait_for_pipe_off - wait for pipe to turn off
747  * @dev: drm device
748  * @pipe: pipe to wait for
749  *
750  * After disabling a pipe, we can't wait for vblank in the usual way,
751  * spinning on the vblank interrupt status bit, since we won't actually
752  * see an interrupt when the pipe is disabled.
753  *
754  * On Gen4 and above:
755  *   wait for the pipe register state bit to turn off
756  *
757  * Otherwise:
758  *   wait for the display line value to settle (it usually
759  *   ends up stopping at the start of the next frame).
760  *
761  */
762 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
763 {
764         struct drm_i915_private *dev_priv = dev->dev_private;
765
766         if (INTEL_INFO(dev)->gen >= 4) {
767                 int reg = PIPECONF(pipe);
768
769                 /* Wait for the Pipe State to go off */
770                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
771                              100))
772                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
773         } else {
774                 u32 last_line;
775                 int reg = PIPEDSL(pipe);
776                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
777
778                 /* Wait for the display line to settle */
779                 do {
780                         last_line = I915_READ(reg) & DSL_LINEMASK;
781                         mdelay(5);
782                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
783                          time_after(timeout, jiffies));
784                 if (time_after(jiffies, timeout))
785                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
786         }
787 }
788
789 static const char *state_string(bool enabled)
790 {
791         return enabled ? "on" : "off";
792 }
793
794 /* Only for pre-ILK configs */
795 static void assert_pll(struct drm_i915_private *dev_priv,
796                        enum pipe pipe, bool state)
797 {
798         int reg;
799         u32 val;
800         bool cur_state;
801
802         reg = DPLL(pipe);
803         val = I915_READ(reg);
804         cur_state = !!(val & DPLL_VCO_ENABLE);
805         WARN(cur_state != state,
806              "PLL state assertion failure (expected %s, current %s)\n",
807              state_string(state), state_string(cur_state));
808 }
809 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
810 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
811
812 /* For ILK+ */
813 static void assert_pch_pll(struct drm_i915_private *dev_priv,
814                            enum pipe pipe, bool state)
815 {
816         int reg;
817         u32 val;
818         bool cur_state;
819
820         if (HAS_PCH_CPT(dev_priv->dev)) {
821                 u32 pch_dpll;
822
823                 pch_dpll = I915_READ(PCH_DPLL_SEL);
824
825                 /* Make sure the selected PLL is enabled to the transcoder */
826                 WARN(!((pch_dpll >> (4 * pipe)) & 8),
827                      "transcoder %d PLL not enabled\n", pipe);
828
829                 /* Convert the transcoder pipe number to a pll pipe number */
830                 pipe = (pch_dpll >> (4 * pipe)) & 1;
831         }
832
833         reg = PCH_DPLL(pipe);
834         val = I915_READ(reg);
835         cur_state = !!(val & DPLL_VCO_ENABLE);
836         WARN(cur_state != state,
837              "PCH PLL state assertion failure (expected %s, current %s)\n",
838              state_string(state), state_string(cur_state));
839 }
840 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
841 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
842
843 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
844                           enum pipe pipe, bool state)
845 {
846         int reg;
847         u32 val;
848         bool cur_state;
849
850         reg = FDI_TX_CTL(pipe);
851         val = I915_READ(reg);
852         cur_state = !!(val & FDI_TX_ENABLE);
853         WARN(cur_state != state,
854              "FDI TX state assertion failure (expected %s, current %s)\n",
855              state_string(state), state_string(cur_state));
856 }
857 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
858 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
859
860 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
861                           enum pipe pipe, bool state)
862 {
863         int reg;
864         u32 val;
865         bool cur_state;
866
867         reg = FDI_RX_CTL(pipe);
868         val = I915_READ(reg);
869         cur_state = !!(val & FDI_RX_ENABLE);
870         WARN(cur_state != state,
871              "FDI RX state assertion failure (expected %s, current %s)\n",
872              state_string(state), state_string(cur_state));
873 }
874 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
875 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
876
877 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
878                                       enum pipe pipe)
879 {
880         int reg;
881         u32 val;
882
883         /* ILK FDI PLL is always enabled */
884         if (dev_priv->info->gen == 5)
885                 return;
886
887         reg = FDI_TX_CTL(pipe);
888         val = I915_READ(reg);
889         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
890 }
891
892 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
893                                       enum pipe pipe)
894 {
895         int reg;
896         u32 val;
897
898         reg = FDI_RX_CTL(pipe);
899         val = I915_READ(reg);
900         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
901 }
902
903 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
904                                   enum pipe pipe)
905 {
906         int pp_reg, lvds_reg;
907         u32 val;
908         enum pipe panel_pipe = PIPE_A;
909         bool locked = true;
910
911         if (HAS_PCH_SPLIT(dev_priv->dev)) {
912                 pp_reg = PCH_PP_CONTROL;
913                 lvds_reg = PCH_LVDS;
914         } else {
915                 pp_reg = PP_CONTROL;
916                 lvds_reg = LVDS;
917         }
918
919         val = I915_READ(pp_reg);
920         if (!(val & PANEL_POWER_ON) ||
921             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
922                 locked = false;
923
924         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
925                 panel_pipe = PIPE_B;
926
927         WARN(panel_pipe == pipe && locked,
928              "panel assertion failure, pipe %c regs locked\n",
929              pipe_name(pipe));
930 }
931
932 void assert_pipe(struct drm_i915_private *dev_priv,
933                  enum pipe pipe, bool state)
934 {
935         int reg;
936         u32 val;
937         bool cur_state;
938
939         /* if we need the pipe A quirk it must be always on */
940         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
941                 state = true;
942
943         reg = PIPECONF(pipe);
944         val = I915_READ(reg);
945         cur_state = !!(val & PIPECONF_ENABLE);
946         WARN(cur_state != state,
947              "pipe %c assertion failure (expected %s, current %s)\n",
948              pipe_name(pipe), state_string(state), state_string(cur_state));
949 }
950
951 static void assert_plane(struct drm_i915_private *dev_priv,
952                          enum plane plane, bool state)
953 {
954         int reg;
955         u32 val;
956         bool cur_state;
957
958         reg = DSPCNTR(plane);
959         val = I915_READ(reg);
960         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
961         WARN(cur_state != state,
962              "plane %c assertion failure (expected %s, current %s)\n",
963              plane_name(plane), state_string(state), state_string(cur_state));
964 }
965
966 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
967 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
968
969 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
970                                    enum pipe pipe)
971 {
972         int reg, i;
973         u32 val;
974         int cur_pipe;
975
976         /* Planes are fixed to pipes on ILK+ */
977         if (HAS_PCH_SPLIT(dev_priv->dev)) {
978                 reg = DSPCNTR(pipe);
979                 val = I915_READ(reg);
980                 WARN((val & DISPLAY_PLANE_ENABLE),
981                      "plane %c assertion failure, should be disabled but not\n",
982                      plane_name(pipe));
983                 return;
984         }
985
986         /* Need to check both planes against the pipe */
987         for (i = 0; i < 2; i++) {
988                 reg = DSPCNTR(i);
989                 val = I915_READ(reg);
990                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
991                         DISPPLANE_SEL_PIPE_SHIFT;
992                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
993                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
994                      plane_name(i), pipe_name(pipe));
995         }
996 }
997
998 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
999 {
1000         u32 val;
1001         bool enabled;
1002
1003         val = I915_READ(PCH_DREF_CONTROL);
1004         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1005                             DREF_SUPERSPREAD_SOURCE_MASK));
1006         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1007 }
1008
1009 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1010                                        enum pipe pipe)
1011 {
1012         int reg;
1013         u32 val;
1014         bool enabled;
1015
1016         reg = TRANSCONF(pipe);
1017         val = I915_READ(reg);
1018         enabled = !!(val & TRANS_ENABLE);
1019         WARN(enabled,
1020              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1021              pipe_name(pipe));
1022 }
1023
1024 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1025                             enum pipe pipe, u32 port_sel, u32 val)
1026 {
1027         if ((val & DP_PORT_EN) == 0)
1028                 return false;
1029
1030         if (HAS_PCH_CPT(dev_priv->dev)) {
1031                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1032                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1033                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1034                         return false;
1035         } else {
1036                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1037                         return false;
1038         }
1039         return true;
1040 }
1041
1042 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1043                               enum pipe pipe, u32 val)
1044 {
1045         if ((val & PORT_ENABLE) == 0)
1046                 return false;
1047
1048         if (HAS_PCH_CPT(dev_priv->dev)) {
1049                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1050                         return false;
1051         } else {
1052                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1053                         return false;
1054         }
1055         return true;
1056 }
1057
1058 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1059                               enum pipe pipe, u32 val)
1060 {
1061         if ((val & LVDS_PORT_EN) == 0)
1062                 return false;
1063
1064         if (HAS_PCH_CPT(dev_priv->dev)) {
1065                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1066                         return false;
1067         } else {
1068                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1069                         return false;
1070         }
1071         return true;
1072 }
1073
1074 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1075                               enum pipe pipe, u32 val)
1076 {
1077         if ((val & ADPA_DAC_ENABLE) == 0)
1078                 return false;
1079         if (HAS_PCH_CPT(dev_priv->dev)) {
1080                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1081                         return false;
1082         } else {
1083                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1084                         return false;
1085         }
1086         return true;
1087 }
1088
1089 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1090                                    enum pipe pipe, int reg, u32 port_sel)
1091 {
1092         u32 val = I915_READ(reg);
1093         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1094              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1095              reg, pipe_name(pipe));
1096 }
1097
1098 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1099                                      enum pipe pipe, int reg)
1100 {
1101         u32 val = I915_READ(reg);
1102         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1103              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1104              reg, pipe_name(pipe));
1105 }
1106
1107 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1108                                       enum pipe pipe)
1109 {
1110         int reg;
1111         u32 val;
1112
1113         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1114         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1115         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1116
1117         reg = PCH_ADPA;
1118         val = I915_READ(reg);
1119         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1120              "PCH VGA enabled on transcoder %c, should be disabled\n",
1121              pipe_name(pipe));
1122
1123         reg = PCH_LVDS;
1124         val = I915_READ(reg);
1125         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1126              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1127              pipe_name(pipe));
1128
1129         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1130         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1131         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1132 }
1133
1134 /**
1135  * intel_enable_pll - enable a PLL
1136  * @dev_priv: i915 private structure
1137  * @pipe: pipe PLL to enable
1138  *
1139  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1140  * make sure the PLL reg is writable first though, since the panel write
1141  * protect mechanism may be enabled.
1142  *
1143  * Note!  This is for pre-ILK only.
1144  */
1145 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1146 {
1147         int reg;
1148         u32 val;
1149
1150         /* No really, not for ILK+ */
1151         BUG_ON(dev_priv->info->gen >= 5);
1152
1153         /* PLL is protected by panel, make sure we can write it */
1154         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1155                 assert_panel_unlocked(dev_priv, pipe);
1156
1157         reg = DPLL(pipe);
1158         val = I915_READ(reg);
1159         val |= DPLL_VCO_ENABLE;
1160
1161         /* We do this three times for luck */
1162         I915_WRITE(reg, val);
1163         POSTING_READ(reg);
1164         udelay(150); /* wait for warmup */
1165         I915_WRITE(reg, val);
1166         POSTING_READ(reg);
1167         udelay(150); /* wait for warmup */
1168         I915_WRITE(reg, val);
1169         POSTING_READ(reg);
1170         udelay(150); /* wait for warmup */
1171 }
1172
1173 /**
1174  * intel_disable_pll - disable a PLL
1175  * @dev_priv: i915 private structure
1176  * @pipe: pipe PLL to disable
1177  *
1178  * Disable the PLL for @pipe, making sure the pipe is off first.
1179  *
1180  * Note!  This is for pre-ILK only.
1181  */
1182 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1183 {
1184         int reg;
1185         u32 val;
1186
1187         /* Don't disable pipe A or pipe A PLLs if needed */
1188         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1189                 return;
1190
1191         /* Make sure the pipe isn't still relying on us */
1192         assert_pipe_disabled(dev_priv, pipe);
1193
1194         reg = DPLL(pipe);
1195         val = I915_READ(reg);
1196         val &= ~DPLL_VCO_ENABLE;
1197         I915_WRITE(reg, val);
1198         POSTING_READ(reg);
1199 }
1200
1201 /**
1202  * intel_enable_pch_pll - enable PCH PLL
1203  * @dev_priv: i915 private structure
1204  * @pipe: pipe PLL to enable
1205  *
1206  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1207  * drives the transcoder clock.
1208  */
1209 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1210                                  enum pipe pipe)
1211 {
1212         int reg;
1213         u32 val;
1214
1215         if (pipe > 1)
1216                 return;
1217
1218         /* PCH only available on ILK+ */
1219         BUG_ON(dev_priv->info->gen < 5);
1220
1221         /* PCH refclock must be enabled first */
1222         assert_pch_refclk_enabled(dev_priv);
1223
1224         reg = PCH_DPLL(pipe);
1225         val = I915_READ(reg);
1226         val |= DPLL_VCO_ENABLE;
1227         I915_WRITE(reg, val);
1228         POSTING_READ(reg);
1229         udelay(200);
1230 }
1231
1232 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1233                                   enum pipe pipe)
1234 {
1235         int reg;
1236         u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1237                 pll_sel = TRANSC_DPLL_ENABLE;
1238
1239         if (pipe > 1)
1240                 return;
1241
1242         /* PCH only available on ILK+ */
1243         BUG_ON(dev_priv->info->gen < 5);
1244
1245         /* Make sure transcoder isn't still depending on us */
1246         assert_transcoder_disabled(dev_priv, pipe);
1247
1248         if (pipe == 0)
1249                 pll_sel |= TRANSC_DPLLA_SEL;
1250         else if (pipe == 1)
1251                 pll_sel |= TRANSC_DPLLB_SEL;
1252
1253
1254         if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1255                 return;
1256
1257         reg = PCH_DPLL(pipe);
1258         val = I915_READ(reg);
1259         val &= ~DPLL_VCO_ENABLE;
1260         I915_WRITE(reg, val);
1261         POSTING_READ(reg);
1262         udelay(200);
1263 }
1264
1265 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1266                                     enum pipe pipe)
1267 {
1268         int reg;
1269         u32 val, pipeconf_val;
1270         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1271
1272         /* PCH only available on ILK+ */
1273         BUG_ON(dev_priv->info->gen < 5);
1274
1275         /* Make sure PCH DPLL is enabled */
1276         assert_pch_pll_enabled(dev_priv, pipe);
1277
1278         /* FDI must be feeding us bits for PCH ports */
1279         assert_fdi_tx_enabled(dev_priv, pipe);
1280         assert_fdi_rx_enabled(dev_priv, pipe);
1281
1282         reg = TRANSCONF(pipe);
1283         val = I915_READ(reg);
1284         pipeconf_val = I915_READ(PIPECONF(pipe));
1285
1286         if (HAS_PCH_IBX(dev_priv->dev)) {
1287                 /*
1288                  * make the BPC in transcoder be consistent with
1289                  * that in pipeconf reg.
1290                  */
1291                 val &= ~PIPE_BPC_MASK;
1292                 val |= pipeconf_val & PIPE_BPC_MASK;
1293         }
1294
1295         val &= ~TRANS_INTERLACE_MASK;
1296         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1297                 if (HAS_PCH_IBX(dev_priv->dev) &&
1298                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1299                         val |= TRANS_LEGACY_INTERLACED_ILK;
1300                 else
1301                         val |= TRANS_INTERLACED;
1302         else
1303                 val |= TRANS_PROGRESSIVE;
1304
1305         I915_WRITE(reg, val | TRANS_ENABLE);
1306         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1307                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1308 }
1309
1310 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1311                                      enum pipe pipe)
1312 {
1313         int reg;
1314         u32 val;
1315
1316         /* FDI relies on the transcoder */
1317         assert_fdi_tx_disabled(dev_priv, pipe);
1318         assert_fdi_rx_disabled(dev_priv, pipe);
1319
1320         /* Ports must be off as well */
1321         assert_pch_ports_disabled(dev_priv, pipe);
1322
1323         reg = TRANSCONF(pipe);
1324         val = I915_READ(reg);
1325         val &= ~TRANS_ENABLE;
1326         I915_WRITE(reg, val);
1327         /* wait for PCH transcoder off, transcoder state */
1328         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1329                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1330 }
1331
1332 /**
1333  * intel_enable_pipe - enable a pipe, asserting requirements
1334  * @dev_priv: i915 private structure
1335  * @pipe: pipe to enable
1336  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1337  *
1338  * Enable @pipe, making sure that various hardware specific requirements
1339  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1340  *
1341  * @pipe should be %PIPE_A or %PIPE_B.
1342  *
1343  * Will wait until the pipe is actually running (i.e. first vblank) before
1344  * returning.
1345  */
1346 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1347                               bool pch_port)
1348 {
1349         int reg;
1350         u32 val;
1351
1352         /*
1353          * A pipe without a PLL won't actually be able to drive bits from
1354          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1355          * need the check.
1356          */
1357         if (!HAS_PCH_SPLIT(dev_priv->dev))
1358                 assert_pll_enabled(dev_priv, pipe);
1359         else {
1360                 if (pch_port) {
1361                         /* if driving the PCH, we need FDI enabled */
1362                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1363                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1364                 }
1365                 /* FIXME: assert CPU port conditions for SNB+ */
1366         }
1367
1368         reg = PIPECONF(pipe);
1369         val = I915_READ(reg);
1370         if (val & PIPECONF_ENABLE)
1371                 return;
1372
1373         I915_WRITE(reg, val | PIPECONF_ENABLE);
1374         intel_wait_for_vblank(dev_priv->dev, pipe);
1375 }
1376
1377 /**
1378  * intel_disable_pipe - disable a pipe, asserting requirements
1379  * @dev_priv: i915 private structure
1380  * @pipe: pipe to disable
1381  *
1382  * Disable @pipe, making sure that various hardware specific requirements
1383  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1384  *
1385  * @pipe should be %PIPE_A or %PIPE_B.
1386  *
1387  * Will wait until the pipe has shut down before returning.
1388  */
1389 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1390                                enum pipe pipe)
1391 {
1392         int reg;
1393         u32 val;
1394
1395         /*
1396          * Make sure planes won't keep trying to pump pixels to us,
1397          * or we might hang the display.
1398          */
1399         assert_planes_disabled(dev_priv, pipe);
1400
1401         /* Don't disable pipe A or pipe A PLLs if needed */
1402         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1403                 return;
1404
1405         reg = PIPECONF(pipe);
1406         val = I915_READ(reg);
1407         if ((val & PIPECONF_ENABLE) == 0)
1408                 return;
1409
1410         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1411         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1412 }
1413
1414 /*
1415  * Plane regs are double buffered, going from enabled->disabled needs a
1416  * trigger in order to latch.  The display address reg provides this.
1417  */
1418 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1419                                       enum plane plane)
1420 {
1421         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1422         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1423 }
1424
1425 /**
1426  * intel_enable_plane - enable a display plane on a given pipe
1427  * @dev_priv: i915 private structure
1428  * @plane: plane to enable
1429  * @pipe: pipe being fed
1430  *
1431  * Enable @plane on @pipe, making sure that @pipe is running first.
1432  */
1433 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1434                                enum plane plane, enum pipe pipe)
1435 {
1436         int reg;
1437         u32 val;
1438
1439         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1440         assert_pipe_enabled(dev_priv, pipe);
1441
1442         reg = DSPCNTR(plane);
1443         val = I915_READ(reg);
1444         if (val & DISPLAY_PLANE_ENABLE)
1445                 return;
1446
1447         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1448         intel_flush_display_plane(dev_priv, plane);
1449         intel_wait_for_vblank(dev_priv->dev, pipe);
1450 }
1451
1452 /**
1453  * intel_disable_plane - disable a display plane
1454  * @dev_priv: i915 private structure
1455  * @plane: plane to disable
1456  * @pipe: pipe consuming the data
1457  *
1458  * Disable @plane; should be an independent operation.
1459  */
1460 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1461                                 enum plane plane, enum pipe pipe)
1462 {
1463         int reg;
1464         u32 val;
1465
1466         reg = DSPCNTR(plane);
1467         val = I915_READ(reg);
1468         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1469                 return;
1470
1471         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1472         intel_flush_display_plane(dev_priv, plane);
1473         intel_wait_for_vblank(dev_priv->dev, pipe);
1474 }
1475
1476 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1477                            enum pipe pipe, int reg, u32 port_sel)
1478 {
1479         u32 val = I915_READ(reg);
1480         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1481                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1482                 I915_WRITE(reg, val & ~DP_PORT_EN);
1483         }
1484 }
1485
1486 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1487                              enum pipe pipe, int reg)
1488 {
1489         u32 val = I915_READ(reg);
1490         if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
1491                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1492                               reg, pipe);
1493                 I915_WRITE(reg, val & ~PORT_ENABLE);
1494         }
1495 }
1496
1497 /* Disable any ports connected to this transcoder */
1498 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1499                                     enum pipe pipe)
1500 {
1501         u32 reg, val;
1502
1503         val = I915_READ(PCH_PP_CONTROL);
1504         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1505
1506         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1507         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1508         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1509
1510         reg = PCH_ADPA;
1511         val = I915_READ(reg);
1512         if (adpa_pipe_enabled(dev_priv, pipe, val))
1513                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1514
1515         reg = PCH_LVDS;
1516         val = I915_READ(reg);
1517         if (lvds_pipe_enabled(dev_priv, pipe, val)) {
1518                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1519                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1520                 POSTING_READ(reg);
1521                 udelay(100);
1522         }
1523
1524         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1525         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1526         disable_pch_hdmi(dev_priv, pipe, HDMID);
1527 }
1528
1529 static void i8xx_disable_fbc(struct drm_device *dev)
1530 {
1531         struct drm_i915_private *dev_priv = dev->dev_private;
1532         u32 fbc_ctl;
1533
1534         /* Disable compression */
1535         fbc_ctl = I915_READ(FBC_CONTROL);
1536         if ((fbc_ctl & FBC_CTL_EN) == 0)
1537                 return;
1538
1539         fbc_ctl &= ~FBC_CTL_EN;
1540         I915_WRITE(FBC_CONTROL, fbc_ctl);
1541
1542         /* Wait for compressing bit to clear */
1543         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1544                 DRM_DEBUG_KMS("FBC idle timed out\n");
1545                 return;
1546         }
1547
1548         DRM_DEBUG_KMS("disabled FBC\n");
1549 }
1550
1551 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1552 {
1553         struct drm_device *dev = crtc->dev;
1554         struct drm_i915_private *dev_priv = dev->dev_private;
1555         struct drm_framebuffer *fb = crtc->fb;
1556         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1557         struct drm_i915_gem_object *obj = intel_fb->obj;
1558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1559         int cfb_pitch;
1560         int plane, i;
1561         u32 fbc_ctl, fbc_ctl2;
1562
1563         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1564         if (fb->pitches[0] < cfb_pitch)
1565                 cfb_pitch = fb->pitches[0];
1566
1567         /* FBC_CTL wants 64B units */
1568         cfb_pitch = (cfb_pitch / 64) - 1;
1569         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1570
1571         /* Clear old tags */
1572         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1573                 I915_WRITE(FBC_TAG + (i * 4), 0);
1574
1575         /* Set it up... */
1576         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1577         fbc_ctl2 |= plane;
1578         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1579         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1580
1581         /* enable it... */
1582         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1583         if (IS_I945GM(dev))
1584                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1585         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1586         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1587         fbc_ctl |= obj->fence_reg;
1588         I915_WRITE(FBC_CONTROL, fbc_ctl);
1589
1590         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1591                       cfb_pitch, crtc->y, intel_crtc->plane);
1592 }
1593
1594 static bool i8xx_fbc_enabled(struct drm_device *dev)
1595 {
1596         struct drm_i915_private *dev_priv = dev->dev_private;
1597
1598         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1599 }
1600
1601 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1602 {
1603         struct drm_device *dev = crtc->dev;
1604         struct drm_i915_private *dev_priv = dev->dev_private;
1605         struct drm_framebuffer *fb = crtc->fb;
1606         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1607         struct drm_i915_gem_object *obj = intel_fb->obj;
1608         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1609         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1610         unsigned long stall_watermark = 200;
1611         u32 dpfc_ctl;
1612
1613         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1614         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1615         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1616
1617         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1618                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1619                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1620         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1621
1622         /* enable it... */
1623         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1624
1625         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1626 }
1627
1628 static void g4x_disable_fbc(struct drm_device *dev)
1629 {
1630         struct drm_i915_private *dev_priv = dev->dev_private;
1631         u32 dpfc_ctl;
1632
1633         /* Disable compression */
1634         dpfc_ctl = I915_READ(DPFC_CONTROL);
1635         if (dpfc_ctl & DPFC_CTL_EN) {
1636                 dpfc_ctl &= ~DPFC_CTL_EN;
1637                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1638
1639                 DRM_DEBUG_KMS("disabled FBC\n");
1640         }
1641 }
1642
1643 static bool g4x_fbc_enabled(struct drm_device *dev)
1644 {
1645         struct drm_i915_private *dev_priv = dev->dev_private;
1646
1647         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1648 }
1649
1650 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1651 {
1652         struct drm_i915_private *dev_priv = dev->dev_private;
1653         u32 blt_ecoskpd;
1654
1655         /* Make sure blitter notifies FBC of writes */
1656         gen6_gt_force_wake_get(dev_priv);
1657         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1658         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1659                 GEN6_BLITTER_LOCK_SHIFT;
1660         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1661         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1662         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1663         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1664                          GEN6_BLITTER_LOCK_SHIFT);
1665         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1666         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1667         gen6_gt_force_wake_put(dev_priv);
1668 }
1669
1670 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1671 {
1672         struct drm_device *dev = crtc->dev;
1673         struct drm_i915_private *dev_priv = dev->dev_private;
1674         struct drm_framebuffer *fb = crtc->fb;
1675         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1676         struct drm_i915_gem_object *obj = intel_fb->obj;
1677         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1678         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1679         unsigned long stall_watermark = 200;
1680         u32 dpfc_ctl;
1681
1682         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1683         dpfc_ctl &= DPFC_RESERVED;
1684         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1685         /* Set persistent mode for front-buffer rendering, ala X. */
1686         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1687         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1688         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1689
1690         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1691                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1692                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1693         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1694         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1695         /* enable it... */
1696         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1697
1698         if (IS_GEN6(dev)) {
1699                 I915_WRITE(SNB_DPFC_CTL_SA,
1700                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1701                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1702                 sandybridge_blit_fbc_update(dev);
1703         }
1704
1705         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1706 }
1707
1708 static void ironlake_disable_fbc(struct drm_device *dev)
1709 {
1710         struct drm_i915_private *dev_priv = dev->dev_private;
1711         u32 dpfc_ctl;
1712
1713         /* Disable compression */
1714         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1715         if (dpfc_ctl & DPFC_CTL_EN) {
1716                 dpfc_ctl &= ~DPFC_CTL_EN;
1717                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1718
1719                 DRM_DEBUG_KMS("disabled FBC\n");
1720         }
1721 }
1722
1723 static bool ironlake_fbc_enabled(struct drm_device *dev)
1724 {
1725         struct drm_i915_private *dev_priv = dev->dev_private;
1726
1727         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1728 }
1729
1730 bool intel_fbc_enabled(struct drm_device *dev)
1731 {
1732         struct drm_i915_private *dev_priv = dev->dev_private;
1733
1734         if (!dev_priv->display.fbc_enabled)
1735                 return false;
1736
1737         return dev_priv->display.fbc_enabled(dev);
1738 }
1739
1740 static void intel_fbc_work_fn(struct work_struct *__work)
1741 {
1742         struct intel_fbc_work *work =
1743                 container_of(to_delayed_work(__work),
1744                              struct intel_fbc_work, work);
1745         struct drm_device *dev = work->crtc->dev;
1746         struct drm_i915_private *dev_priv = dev->dev_private;
1747
1748         mutex_lock(&dev->struct_mutex);
1749         if (work == dev_priv->fbc_work) {
1750                 /* Double check that we haven't switched fb without cancelling
1751                  * the prior work.
1752                  */
1753                 if (work->crtc->fb == work->fb) {
1754                         dev_priv->display.enable_fbc(work->crtc,
1755                                                      work->interval);
1756
1757                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1758                         dev_priv->cfb_fb = work->crtc->fb->base.id;
1759                         dev_priv->cfb_y = work->crtc->y;
1760                 }
1761
1762                 dev_priv->fbc_work = NULL;
1763         }
1764         mutex_unlock(&dev->struct_mutex);
1765
1766         kfree(work);
1767 }
1768
1769 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1770 {
1771         if (dev_priv->fbc_work == NULL)
1772                 return;
1773
1774         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1775
1776         /* Synchronisation is provided by struct_mutex and checking of
1777          * dev_priv->fbc_work, so we can perform the cancellation
1778          * entirely asynchronously.
1779          */
1780         if (cancel_delayed_work(&dev_priv->fbc_work->work))
1781                 /* tasklet was killed before being run, clean up */
1782                 kfree(dev_priv->fbc_work);
1783
1784         /* Mark the work as no longer wanted so that if it does
1785          * wake-up (because the work was already running and waiting
1786          * for our mutex), it will discover that is no longer
1787          * necessary to run.
1788          */
1789         dev_priv->fbc_work = NULL;
1790 }
1791
1792 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1793 {
1794         struct intel_fbc_work *work;
1795         struct drm_device *dev = crtc->dev;
1796         struct drm_i915_private *dev_priv = dev->dev_private;
1797
1798         if (!dev_priv->display.enable_fbc)
1799                 return;
1800
1801         intel_cancel_fbc_work(dev_priv);
1802
1803         work = kzalloc(sizeof *work, GFP_KERNEL);
1804         if (work == NULL) {
1805                 dev_priv->display.enable_fbc(crtc, interval);
1806                 return;
1807         }
1808
1809         work->crtc = crtc;
1810         work->fb = crtc->fb;
1811         work->interval = interval;
1812         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1813
1814         dev_priv->fbc_work = work;
1815
1816         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1817
1818         /* Delay the actual enabling to let pageflipping cease and the
1819          * display to settle before starting the compression. Note that
1820          * this delay also serves a second purpose: it allows for a
1821          * vblank to pass after disabling the FBC before we attempt
1822          * to modify the control registers.
1823          *
1824          * A more complicated solution would involve tracking vblanks
1825          * following the termination of the page-flipping sequence
1826          * and indeed performing the enable as a co-routine and not
1827          * waiting synchronously upon the vblank.
1828          */
1829         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1830 }
1831
1832 void intel_disable_fbc(struct drm_device *dev)
1833 {
1834         struct drm_i915_private *dev_priv = dev->dev_private;
1835
1836         intel_cancel_fbc_work(dev_priv);
1837
1838         if (!dev_priv->display.disable_fbc)
1839                 return;
1840
1841         dev_priv->display.disable_fbc(dev);
1842         dev_priv->cfb_plane = -1;
1843 }
1844
1845 /**
1846  * intel_update_fbc - enable/disable FBC as needed
1847  * @dev: the drm_device
1848  *
1849  * Set up the framebuffer compression hardware at mode set time.  We
1850  * enable it if possible:
1851  *   - plane A only (on pre-965)
1852  *   - no pixel mulitply/line duplication
1853  *   - no alpha buffer discard
1854  *   - no dual wide
1855  *   - framebuffer <= 2048 in width, 1536 in height
1856  *
1857  * We can't assume that any compression will take place (worst case),
1858  * so the compressed buffer has to be the same size as the uncompressed
1859  * one.  It also must reside (along with the line length buffer) in
1860  * stolen memory.
1861  *
1862  * We need to enable/disable FBC on a global basis.
1863  */
1864 static void intel_update_fbc(struct drm_device *dev)
1865 {
1866         struct drm_i915_private *dev_priv = dev->dev_private;
1867         struct drm_crtc *crtc = NULL, *tmp_crtc;
1868         struct intel_crtc *intel_crtc;
1869         struct drm_framebuffer *fb;
1870         struct intel_framebuffer *intel_fb;
1871         struct drm_i915_gem_object *obj;
1872         int enable_fbc;
1873
1874         DRM_DEBUG_KMS("\n");
1875
1876         if (!i915_powersave)
1877                 return;
1878
1879         if (!I915_HAS_FBC(dev))
1880                 return;
1881
1882         /*
1883          * If FBC is already on, we just have to verify that we can
1884          * keep it that way...
1885          * Need to disable if:
1886          *   - more than one pipe is active
1887          *   - changing FBC params (stride, fence, mode)
1888          *   - new fb is too large to fit in compressed buffer
1889          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1890          */
1891         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1892                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1893                         if (crtc) {
1894                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1895                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1896                                 goto out_disable;
1897                         }
1898                         crtc = tmp_crtc;
1899                 }
1900         }
1901
1902         if (!crtc || crtc->fb == NULL) {
1903                 DRM_DEBUG_KMS("no output, disabling\n");
1904                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1905                 goto out_disable;
1906         }
1907
1908         intel_crtc = to_intel_crtc(crtc);
1909         fb = crtc->fb;
1910         intel_fb = to_intel_framebuffer(fb);
1911         obj = intel_fb->obj;
1912
1913         enable_fbc = i915_enable_fbc;
1914         if (enable_fbc < 0) {
1915                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1916                 enable_fbc = 1;
1917                 if (INTEL_INFO(dev)->gen <= 6)
1918                         enable_fbc = 0;
1919         }
1920         if (!enable_fbc) {
1921                 DRM_DEBUG_KMS("fbc disabled per module param\n");
1922                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1923                 goto out_disable;
1924         }
1925         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1926                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1927                               "compression\n");
1928                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1929                 goto out_disable;
1930         }
1931         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1932             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1933                 DRM_DEBUG_KMS("mode incompatible with compression, "
1934                               "disabling\n");
1935                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1936                 goto out_disable;
1937         }
1938         if ((crtc->mode.hdisplay > 2048) ||
1939             (crtc->mode.vdisplay > 1536)) {
1940                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1941                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1942                 goto out_disable;
1943         }
1944         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1945                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1946                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1947                 goto out_disable;
1948         }
1949
1950         /* The use of a CPU fence is mandatory in order to detect writes
1951          * by the CPU to the scanout and trigger updates to the FBC.
1952          */
1953         if (obj->tiling_mode != I915_TILING_X ||
1954             obj->fence_reg == I915_FENCE_REG_NONE) {
1955                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1956                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1957                 goto out_disable;
1958         }
1959
1960         /* If the kernel debugger is active, always disable compression */
1961         if (in_dbg_master())
1962                 goto out_disable;
1963
1964         /* If the scanout has not changed, don't modify the FBC settings.
1965          * Note that we make the fundamental assumption that the fb->obj
1966          * cannot be unpinned (and have its GTT offset and fence revoked)
1967          * without first being decoupled from the scanout and FBC disabled.
1968          */
1969         if (dev_priv->cfb_plane == intel_crtc->plane &&
1970             dev_priv->cfb_fb == fb->base.id &&
1971             dev_priv->cfb_y == crtc->y)
1972                 return;
1973
1974         if (intel_fbc_enabled(dev)) {
1975                 /* We update FBC along two paths, after changing fb/crtc
1976                  * configuration (modeswitching) and after page-flipping
1977                  * finishes. For the latter, we know that not only did
1978                  * we disable the FBC at the start of the page-flip
1979                  * sequence, but also more than one vblank has passed.
1980                  *
1981                  * For the former case of modeswitching, it is possible
1982                  * to switch between two FBC valid configurations
1983                  * instantaneously so we do need to disable the FBC
1984                  * before we can modify its control registers. We also
1985                  * have to wait for the next vblank for that to take
1986                  * effect. However, since we delay enabling FBC we can
1987                  * assume that a vblank has passed since disabling and
1988                  * that we can safely alter the registers in the deferred
1989                  * callback.
1990                  *
1991                  * In the scenario that we go from a valid to invalid
1992                  * and then back to valid FBC configuration we have
1993                  * no strict enforcement that a vblank occurred since
1994                  * disabling the FBC. However, along all current pipe
1995                  * disabling paths we do need to wait for a vblank at
1996                  * some point. And we wait before enabling FBC anyway.
1997                  */
1998                 DRM_DEBUG_KMS("disabling active FBC for update\n");
1999                 intel_disable_fbc(dev);
2000         }
2001
2002         intel_enable_fbc(crtc, 500);
2003         return;
2004
2005 out_disable:
2006         /* Multiple disables should be harmless */
2007         if (intel_fbc_enabled(dev)) {
2008                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
2009                 intel_disable_fbc(dev);
2010         }
2011 }
2012
2013 int
2014 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2015                            struct drm_i915_gem_object *obj,
2016                            struct intel_ring_buffer *pipelined)
2017 {
2018         struct drm_i915_private *dev_priv = dev->dev_private;
2019         u32 alignment;
2020         int ret;
2021
2022         switch (obj->tiling_mode) {
2023         case I915_TILING_NONE:
2024                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2025                         alignment = 128 * 1024;
2026                 else if (INTEL_INFO(dev)->gen >= 4)
2027                         alignment = 4 * 1024;
2028                 else
2029                         alignment = 64 * 1024;
2030                 break;
2031         case I915_TILING_X:
2032                 /* pin() will align the object as required by fence */
2033                 alignment = 0;
2034                 break;
2035         case I915_TILING_Y:
2036                 /* FIXME: Is this true? */
2037                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2038                 return -EINVAL;
2039         default:
2040                 BUG();
2041         }
2042
2043         dev_priv->mm.interruptible = false;
2044         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2045         if (ret)
2046                 goto err_interruptible;
2047
2048         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2049          * fence, whereas 965+ only requires a fence if using
2050          * framebuffer compression.  For simplicity, we always install
2051          * a fence as the cost is not that onerous.
2052          */
2053         if (obj->tiling_mode != I915_TILING_NONE) {
2054                 ret = i915_gem_object_get_fence(obj, pipelined);
2055                 if (ret)
2056                         goto err_unpin;
2057
2058                 i915_gem_object_pin_fence(obj);
2059         }
2060
2061         dev_priv->mm.interruptible = true;
2062         return 0;
2063
2064 err_unpin:
2065         i915_gem_object_unpin(obj);
2066 err_interruptible:
2067         dev_priv->mm.interruptible = true;
2068         return ret;
2069 }
2070
2071 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2072 {
2073         i915_gem_object_unpin_fence(obj);
2074         i915_gem_object_unpin(obj);
2075 }
2076
2077 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2078                              int x, int y)
2079 {
2080         struct drm_device *dev = crtc->dev;
2081         struct drm_i915_private *dev_priv = dev->dev_private;
2082         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2083         struct intel_framebuffer *intel_fb;
2084         struct drm_i915_gem_object *obj;
2085         int plane = intel_crtc->plane;
2086         unsigned long Start, Offset;
2087         u32 dspcntr;
2088         u32 reg;
2089
2090         switch (plane) {
2091         case 0:
2092         case 1:
2093                 break;
2094         default:
2095                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2096                 return -EINVAL;
2097         }
2098
2099         intel_fb = to_intel_framebuffer(fb);
2100         obj = intel_fb->obj;
2101
2102         reg = DSPCNTR(plane);
2103         dspcntr = I915_READ(reg);
2104         /* Mask out pixel format bits in case we change it */
2105         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2106         switch (fb->bits_per_pixel) {
2107         case 8:
2108                 dspcntr |= DISPPLANE_8BPP;
2109                 break;
2110         case 16:
2111                 if (fb->depth == 15)
2112                         dspcntr |= DISPPLANE_15_16BPP;
2113                 else
2114                         dspcntr |= DISPPLANE_16BPP;
2115                 break;
2116         case 24:
2117         case 32:
2118                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2119                 break;
2120         default:
2121                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2122                 return -EINVAL;
2123         }
2124         if (INTEL_INFO(dev)->gen >= 4) {
2125                 if (obj->tiling_mode != I915_TILING_NONE)
2126                         dspcntr |= DISPPLANE_TILED;
2127                 else
2128                         dspcntr &= ~DISPPLANE_TILED;
2129         }
2130
2131         I915_WRITE(reg, dspcntr);
2132
2133         Start = obj->gtt_offset;
2134         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2135
2136         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2137                       Start, Offset, x, y, fb->pitches[0]);
2138         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2139         if (INTEL_INFO(dev)->gen >= 4) {
2140                 I915_WRITE(DSPSURF(plane), Start);
2141                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2142                 I915_WRITE(DSPADDR(plane), Offset);
2143         } else
2144                 I915_WRITE(DSPADDR(plane), Start + Offset);
2145         POSTING_READ(reg);
2146
2147         return 0;
2148 }
2149
2150 static int ironlake_update_plane(struct drm_crtc *crtc,
2151                                  struct drm_framebuffer *fb, int x, int y)
2152 {
2153         struct drm_device *dev = crtc->dev;
2154         struct drm_i915_private *dev_priv = dev->dev_private;
2155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2156         struct intel_framebuffer *intel_fb;
2157         struct drm_i915_gem_object *obj;
2158         int plane = intel_crtc->plane;
2159         unsigned long Start, Offset;
2160         u32 dspcntr;
2161         u32 reg;
2162
2163         switch (plane) {
2164         case 0:
2165         case 1:
2166         case 2:
2167                 break;
2168         default:
2169                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2170                 return -EINVAL;
2171         }
2172
2173         intel_fb = to_intel_framebuffer(fb);
2174         obj = intel_fb->obj;
2175
2176         reg = DSPCNTR(plane);
2177         dspcntr = I915_READ(reg);
2178         /* Mask out pixel format bits in case we change it */
2179         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2180         switch (fb->bits_per_pixel) {
2181         case 8:
2182                 dspcntr |= DISPPLANE_8BPP;
2183                 break;
2184         case 16:
2185                 if (fb->depth != 16)
2186                         return -EINVAL;
2187
2188                 dspcntr |= DISPPLANE_16BPP;
2189                 break;
2190         case 24:
2191         case 32:
2192                 if (fb->depth == 24)
2193                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2194                 else if (fb->depth == 30)
2195                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2196                 else
2197                         return -EINVAL;
2198                 break;
2199         default:
2200                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2201                 return -EINVAL;
2202         }
2203
2204         if (obj->tiling_mode != I915_TILING_NONE)
2205                 dspcntr |= DISPPLANE_TILED;
2206         else
2207                 dspcntr &= ~DISPPLANE_TILED;
2208
2209         /* must disable */
2210         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2211
2212         I915_WRITE(reg, dspcntr);
2213
2214         Start = obj->gtt_offset;
2215         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2216
2217         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2218                       Start, Offset, x, y, fb->pitches[0]);
2219         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2220         I915_WRITE(DSPSURF(plane), Start);
2221         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2222         I915_WRITE(DSPADDR(plane), Offset);
2223         POSTING_READ(reg);
2224
2225         return 0;
2226 }
2227
2228 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2229 static int
2230 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2231                            int x, int y, enum mode_set_atomic state)
2232 {
2233         struct drm_device *dev = crtc->dev;
2234         struct drm_i915_private *dev_priv = dev->dev_private;
2235         int ret;
2236
2237         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2238         if (ret)
2239                 return ret;
2240
2241         intel_update_fbc(dev);
2242         intel_increase_pllclock(crtc);
2243
2244         return 0;
2245 }
2246
2247 static int
2248 intel_finish_fb(struct drm_framebuffer *old_fb)
2249 {
2250         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2251         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2252         bool was_interruptible = dev_priv->mm.interruptible;
2253         int ret;
2254
2255         wait_event(dev_priv->pending_flip_queue,
2256                    atomic_read(&dev_priv->mm.wedged) ||
2257                    atomic_read(&obj->pending_flip) == 0);
2258
2259         /* Big Hammer, we also need to ensure that any pending
2260          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2261          * current scanout is retired before unpinning the old
2262          * framebuffer.
2263          *
2264          * This should only fail upon a hung GPU, in which case we
2265          * can safely continue.
2266          */
2267         dev_priv->mm.interruptible = false;
2268         ret = i915_gem_object_finish_gpu(obj);
2269         dev_priv->mm.interruptible = was_interruptible;
2270
2271         return ret;
2272 }
2273
2274 static int
2275 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2276                     struct drm_framebuffer *old_fb)
2277 {
2278         struct drm_device *dev = crtc->dev;
2279         struct drm_i915_master_private *master_priv;
2280         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2281         int ret;
2282
2283         /* no fb bound */
2284         if (!crtc->fb) {
2285                 DRM_ERROR("No FB bound\n");
2286                 return 0;
2287         }
2288
2289         switch (intel_crtc->plane) {
2290         case 0:
2291         case 1:
2292                 break;
2293         case 2:
2294                 if (IS_IVYBRIDGE(dev))
2295                         break;
2296                 /* fall through otherwise */
2297         default:
2298                 DRM_ERROR("no plane for crtc\n");
2299                 return -EINVAL;
2300         }
2301
2302         mutex_lock(&dev->struct_mutex);
2303         ret = intel_pin_and_fence_fb_obj(dev,
2304                                          to_intel_framebuffer(crtc->fb)->obj,
2305                                          NULL);
2306         if (ret != 0) {
2307                 mutex_unlock(&dev->struct_mutex);
2308                 DRM_ERROR("pin & fence failed\n");
2309                 return ret;
2310         }
2311
2312         if (old_fb)
2313                 intel_finish_fb(old_fb);
2314
2315         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2316                                          LEAVE_ATOMIC_MODE_SET);
2317         if (ret) {
2318                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2319                 mutex_unlock(&dev->struct_mutex);
2320                 DRM_ERROR("failed to update base address\n");
2321                 return ret;
2322         }
2323
2324         if (old_fb) {
2325                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2326                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2327         }
2328
2329         mutex_unlock(&dev->struct_mutex);
2330
2331         if (!dev->primary->master)
2332                 return 0;
2333
2334         master_priv = dev->primary->master->driver_priv;
2335         if (!master_priv->sarea_priv)
2336                 return 0;
2337
2338         if (intel_crtc->pipe) {
2339                 master_priv->sarea_priv->pipeB_x = x;
2340                 master_priv->sarea_priv->pipeB_y = y;
2341         } else {
2342                 master_priv->sarea_priv->pipeA_x = x;
2343                 master_priv->sarea_priv->pipeA_y = y;
2344         }
2345
2346         return 0;
2347 }
2348
2349 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2350 {
2351         struct drm_device *dev = crtc->dev;
2352         struct drm_i915_private *dev_priv = dev->dev_private;
2353         u32 dpa_ctl;
2354
2355         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2356         dpa_ctl = I915_READ(DP_A);
2357         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2358
2359         if (clock < 200000) {
2360                 u32 temp;
2361                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2362                 /* workaround for 160Mhz:
2363                    1) program 0x4600c bits 15:0 = 0x8124
2364                    2) program 0x46010 bit 0 = 1
2365                    3) program 0x46034 bit 24 = 1
2366                    4) program 0x64000 bit 14 = 1
2367                    */
2368                 temp = I915_READ(0x4600c);
2369                 temp &= 0xffff0000;
2370                 I915_WRITE(0x4600c, temp | 0x8124);
2371
2372                 temp = I915_READ(0x46010);
2373                 I915_WRITE(0x46010, temp | 1);
2374
2375                 temp = I915_READ(0x46034);
2376                 I915_WRITE(0x46034, temp | (1 << 24));
2377         } else {
2378                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2379         }
2380         I915_WRITE(DP_A, dpa_ctl);
2381
2382         POSTING_READ(DP_A);
2383         udelay(500);
2384 }
2385
2386 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2387 {
2388         struct drm_device *dev = crtc->dev;
2389         struct drm_i915_private *dev_priv = dev->dev_private;
2390         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2391         int pipe = intel_crtc->pipe;
2392         u32 reg, temp;
2393
2394         /* enable normal train */
2395         reg = FDI_TX_CTL(pipe);
2396         temp = I915_READ(reg);
2397         if (IS_IVYBRIDGE(dev)) {
2398                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2399                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2400         } else {
2401                 temp &= ~FDI_LINK_TRAIN_NONE;
2402                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2403         }
2404         I915_WRITE(reg, temp);
2405
2406         reg = FDI_RX_CTL(pipe);
2407         temp = I915_READ(reg);
2408         if (HAS_PCH_CPT(dev)) {
2409                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2410                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2411         } else {
2412                 temp &= ~FDI_LINK_TRAIN_NONE;
2413                 temp |= FDI_LINK_TRAIN_NONE;
2414         }
2415         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2416
2417         /* wait one idle pattern time */
2418         POSTING_READ(reg);
2419         udelay(1000);
2420
2421         /* IVB wants error correction enabled */
2422         if (IS_IVYBRIDGE(dev))
2423                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2424                            FDI_FE_ERRC_ENABLE);
2425 }
2426
2427 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2428 {
2429         struct drm_i915_private *dev_priv = dev->dev_private;
2430         u32 flags = I915_READ(SOUTH_CHICKEN1);
2431
2432         flags |= FDI_PHASE_SYNC_OVR(pipe);
2433         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2434         flags |= FDI_PHASE_SYNC_EN(pipe);
2435         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2436         POSTING_READ(SOUTH_CHICKEN1);
2437 }
2438
2439 /* The FDI link training functions for ILK/Ibexpeak. */
2440 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2441 {
2442         struct drm_device *dev = crtc->dev;
2443         struct drm_i915_private *dev_priv = dev->dev_private;
2444         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2445         int pipe = intel_crtc->pipe;
2446         int plane = intel_crtc->plane;
2447         u32 reg, temp, tries;
2448
2449         /* FDI needs bits from pipe & plane first */
2450         assert_pipe_enabled(dev_priv, pipe);
2451         assert_plane_enabled(dev_priv, plane);
2452
2453         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2454            for train result */
2455         reg = FDI_RX_IMR(pipe);
2456         temp = I915_READ(reg);
2457         temp &= ~FDI_RX_SYMBOL_LOCK;
2458         temp &= ~FDI_RX_BIT_LOCK;
2459         I915_WRITE(reg, temp);
2460         I915_READ(reg);
2461         udelay(150);
2462
2463         /* enable CPU FDI TX and PCH FDI RX */
2464         reg = FDI_TX_CTL(pipe);
2465         temp = I915_READ(reg);
2466         temp &= ~(7 << 19);
2467         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2468         temp &= ~FDI_LINK_TRAIN_NONE;
2469         temp |= FDI_LINK_TRAIN_PATTERN_1;
2470         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2471
2472         reg = FDI_RX_CTL(pipe);
2473         temp = I915_READ(reg);
2474         temp &= ~FDI_LINK_TRAIN_NONE;
2475         temp |= FDI_LINK_TRAIN_PATTERN_1;
2476         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2477
2478         POSTING_READ(reg);
2479         udelay(150);
2480
2481         /* Ironlake workaround, enable clock pointer after FDI enable*/
2482         if (HAS_PCH_IBX(dev)) {
2483                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2484                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2485                            FDI_RX_PHASE_SYNC_POINTER_EN);
2486         }
2487
2488         reg = FDI_RX_IIR(pipe);
2489         for (tries = 0; tries < 5; tries++) {
2490                 temp = I915_READ(reg);
2491                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2492
2493                 if ((temp & FDI_RX_BIT_LOCK)) {
2494                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2495                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2496                         break;
2497                 }
2498         }
2499         if (tries == 5)
2500                 DRM_ERROR("FDI train 1 fail!\n");
2501
2502         /* Train 2 */
2503         reg = FDI_TX_CTL(pipe);
2504         temp = I915_READ(reg);
2505         temp &= ~FDI_LINK_TRAIN_NONE;
2506         temp |= FDI_LINK_TRAIN_PATTERN_2;
2507         I915_WRITE(reg, temp);
2508
2509         reg = FDI_RX_CTL(pipe);
2510         temp = I915_READ(reg);
2511         temp &= ~FDI_LINK_TRAIN_NONE;
2512         temp |= FDI_LINK_TRAIN_PATTERN_2;
2513         I915_WRITE(reg, temp);
2514
2515         POSTING_READ(reg);
2516         udelay(150);
2517
2518         reg = FDI_RX_IIR(pipe);
2519         for (tries = 0; tries < 5; tries++) {
2520                 temp = I915_READ(reg);
2521                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2522
2523                 if (temp & FDI_RX_SYMBOL_LOCK) {
2524                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2525                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2526                         break;
2527                 }
2528         }
2529         if (tries == 5)
2530                 DRM_ERROR("FDI train 2 fail!\n");
2531
2532         DRM_DEBUG_KMS("FDI train done\n");
2533
2534 }
2535
2536 static const int snb_b_fdi_train_param[] = {
2537         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2538         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2539         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2540         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2541 };
2542
2543 /* The FDI link training functions for SNB/Cougarpoint. */
2544 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2545 {
2546         struct drm_device *dev = crtc->dev;
2547         struct drm_i915_private *dev_priv = dev->dev_private;
2548         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2549         int pipe = intel_crtc->pipe;
2550         u32 reg, temp, i;
2551
2552         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2553            for train result */
2554         reg = FDI_RX_IMR(pipe);
2555         temp = I915_READ(reg);
2556         temp &= ~FDI_RX_SYMBOL_LOCK;
2557         temp &= ~FDI_RX_BIT_LOCK;
2558         I915_WRITE(reg, temp);
2559
2560         POSTING_READ(reg);
2561         udelay(150);
2562
2563         /* enable CPU FDI TX and PCH FDI RX */
2564         reg = FDI_TX_CTL(pipe);
2565         temp = I915_READ(reg);
2566         temp &= ~(7 << 19);
2567         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2568         temp &= ~FDI_LINK_TRAIN_NONE;
2569         temp |= FDI_LINK_TRAIN_PATTERN_1;
2570         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2571         /* SNB-B */
2572         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2573         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2574
2575         reg = FDI_RX_CTL(pipe);
2576         temp = I915_READ(reg);
2577         if (HAS_PCH_CPT(dev)) {
2578                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2579                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2580         } else {
2581                 temp &= ~FDI_LINK_TRAIN_NONE;
2582                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2583         }
2584         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2585
2586         POSTING_READ(reg);
2587         udelay(150);
2588
2589         if (HAS_PCH_CPT(dev))
2590                 cpt_phase_pointer_enable(dev, pipe);
2591
2592         for (i = 0; i < 4; i++) {
2593                 reg = FDI_TX_CTL(pipe);
2594                 temp = I915_READ(reg);
2595                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2596                 temp |= snb_b_fdi_train_param[i];
2597                 I915_WRITE(reg, temp);
2598
2599                 POSTING_READ(reg);
2600                 udelay(500);
2601
2602                 reg = FDI_RX_IIR(pipe);
2603                 temp = I915_READ(reg);
2604                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2605
2606                 if (temp & FDI_RX_BIT_LOCK) {
2607                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2608                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2609                         break;
2610                 }
2611         }
2612         if (i == 4)
2613                 DRM_ERROR("FDI train 1 fail!\n");
2614
2615         /* Train 2 */
2616         reg = FDI_TX_CTL(pipe);
2617         temp = I915_READ(reg);
2618         temp &= ~FDI_LINK_TRAIN_NONE;
2619         temp |= FDI_LINK_TRAIN_PATTERN_2;
2620         if (IS_GEN6(dev)) {
2621                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2622                 /* SNB-B */
2623                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2624         }
2625         I915_WRITE(reg, temp);
2626
2627         reg = FDI_RX_CTL(pipe);
2628         temp = I915_READ(reg);
2629         if (HAS_PCH_CPT(dev)) {
2630                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2631                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2632         } else {
2633                 temp &= ~FDI_LINK_TRAIN_NONE;
2634                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2635         }
2636         I915_WRITE(reg, temp);
2637
2638         POSTING_READ(reg);
2639         udelay(150);
2640
2641         for (i = 0; i < 4; i++) {
2642                 reg = FDI_TX_CTL(pipe);
2643                 temp = I915_READ(reg);
2644                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2645                 temp |= snb_b_fdi_train_param[i];
2646                 I915_WRITE(reg, temp);
2647
2648                 POSTING_READ(reg);
2649                 udelay(500);
2650
2651                 reg = FDI_RX_IIR(pipe);
2652                 temp = I915_READ(reg);
2653                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2654
2655                 if (temp & FDI_RX_SYMBOL_LOCK) {
2656                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2657                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2658                         break;
2659                 }
2660         }
2661         if (i == 4)
2662                 DRM_ERROR("FDI train 2 fail!\n");
2663
2664         DRM_DEBUG_KMS("FDI train done.\n");
2665 }
2666
2667 /* Manual link training for Ivy Bridge A0 parts */
2668 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2669 {
2670         struct drm_device *dev = crtc->dev;
2671         struct drm_i915_private *dev_priv = dev->dev_private;
2672         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2673         int pipe = intel_crtc->pipe;
2674         u32 reg, temp, i;
2675
2676         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2677            for train result */
2678         reg = FDI_RX_IMR(pipe);
2679         temp = I915_READ(reg);
2680         temp &= ~FDI_RX_SYMBOL_LOCK;
2681         temp &= ~FDI_RX_BIT_LOCK;
2682         I915_WRITE(reg, temp);
2683
2684         POSTING_READ(reg);
2685         udelay(150);
2686
2687         /* enable CPU FDI TX and PCH FDI RX */
2688         reg = FDI_TX_CTL(pipe);
2689         temp = I915_READ(reg);
2690         temp &= ~(7 << 19);
2691         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2692         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2693         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2694         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2695         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2696         temp |= FDI_COMPOSITE_SYNC;
2697         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2698
2699         reg = FDI_RX_CTL(pipe);
2700         temp = I915_READ(reg);
2701         temp &= ~FDI_LINK_TRAIN_AUTO;
2702         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2703         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2704         temp |= FDI_COMPOSITE_SYNC;
2705         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2706
2707         POSTING_READ(reg);
2708         udelay(150);
2709
2710         if (HAS_PCH_CPT(dev))
2711                 cpt_phase_pointer_enable(dev, pipe);
2712
2713         for (i = 0; i < 4; i++) {
2714                 reg = FDI_TX_CTL(pipe);
2715                 temp = I915_READ(reg);
2716                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2717                 temp |= snb_b_fdi_train_param[i];
2718                 I915_WRITE(reg, temp);
2719
2720                 POSTING_READ(reg);
2721                 udelay(500);
2722
2723                 reg = FDI_RX_IIR(pipe);
2724                 temp = I915_READ(reg);
2725                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2726
2727                 if (temp & FDI_RX_BIT_LOCK ||
2728                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2729                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2730                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2731                         break;
2732                 }
2733         }
2734         if (i == 4)
2735                 DRM_ERROR("FDI train 1 fail!\n");
2736
2737         /* Train 2 */
2738         reg = FDI_TX_CTL(pipe);
2739         temp = I915_READ(reg);
2740         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2741         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2742         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2743         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2744         I915_WRITE(reg, temp);
2745
2746         reg = FDI_RX_CTL(pipe);
2747         temp = I915_READ(reg);
2748         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2749         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2750         I915_WRITE(reg, temp);
2751
2752         POSTING_READ(reg);
2753         udelay(150);
2754
2755         for (i = 0; i < 4; i++) {
2756                 reg = FDI_TX_CTL(pipe);
2757                 temp = I915_READ(reg);
2758                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2759                 temp |= snb_b_fdi_train_param[i];
2760                 I915_WRITE(reg, temp);
2761
2762                 POSTING_READ(reg);
2763                 udelay(500);
2764
2765                 reg = FDI_RX_IIR(pipe);
2766                 temp = I915_READ(reg);
2767                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2768
2769                 if (temp & FDI_RX_SYMBOL_LOCK) {
2770                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2771                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2772                         break;
2773                 }
2774         }
2775         if (i == 4)
2776                 DRM_ERROR("FDI train 2 fail!\n");
2777
2778         DRM_DEBUG_KMS("FDI train done.\n");
2779 }
2780
2781 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2782 {
2783         struct drm_device *dev = crtc->dev;
2784         struct drm_i915_private *dev_priv = dev->dev_private;
2785         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2786         int pipe = intel_crtc->pipe;
2787         u32 reg, temp;
2788
2789         /* Write the TU size bits so error detection works */
2790         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2791                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2792
2793         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2794         reg = FDI_RX_CTL(pipe);
2795         temp = I915_READ(reg);
2796         temp &= ~((0x7 << 19) | (0x7 << 16));
2797         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2798         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2799         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2800
2801         POSTING_READ(reg);
2802         udelay(200);
2803
2804         /* Switch from Rawclk to PCDclk */
2805         temp = I915_READ(reg);
2806         I915_WRITE(reg, temp | FDI_PCDCLK);
2807
2808         POSTING_READ(reg);
2809         udelay(200);
2810
2811         /* Enable CPU FDI TX PLL, always on for Ironlake */
2812         reg = FDI_TX_CTL(pipe);
2813         temp = I915_READ(reg);
2814         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2815                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2816
2817                 POSTING_READ(reg);
2818                 udelay(100);
2819         }
2820 }
2821
2822 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2823 {
2824         struct drm_i915_private *dev_priv = dev->dev_private;
2825         u32 flags = I915_READ(SOUTH_CHICKEN1);
2826
2827         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2828         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2829         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2830         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2831         POSTING_READ(SOUTH_CHICKEN1);
2832 }
2833 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2834 {
2835         struct drm_device *dev = crtc->dev;
2836         struct drm_i915_private *dev_priv = dev->dev_private;
2837         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2838         int pipe = intel_crtc->pipe;
2839         u32 reg, temp;
2840
2841         /* disable CPU FDI tx and PCH FDI rx */
2842         reg = FDI_TX_CTL(pipe);
2843         temp = I915_READ(reg);
2844         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2845         POSTING_READ(reg);
2846
2847         reg = FDI_RX_CTL(pipe);
2848         temp = I915_READ(reg);
2849         temp &= ~(0x7 << 16);
2850         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2851         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2852
2853         POSTING_READ(reg);
2854         udelay(100);
2855
2856         /* Ironlake workaround, disable clock pointer after downing FDI */
2857         if (HAS_PCH_IBX(dev)) {
2858                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2859                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2860                            I915_READ(FDI_RX_CHICKEN(pipe) &
2861                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2862         } else if (HAS_PCH_CPT(dev)) {
2863                 cpt_phase_pointer_disable(dev, pipe);
2864         }
2865
2866         /* still set train pattern 1 */
2867         reg = FDI_TX_CTL(pipe);
2868         temp = I915_READ(reg);
2869         temp &= ~FDI_LINK_TRAIN_NONE;
2870         temp |= FDI_LINK_TRAIN_PATTERN_1;
2871         I915_WRITE(reg, temp);
2872
2873         reg = FDI_RX_CTL(pipe);
2874         temp = I915_READ(reg);
2875         if (HAS_PCH_CPT(dev)) {
2876                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2877                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2878         } else {
2879                 temp &= ~FDI_LINK_TRAIN_NONE;
2880                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2881         }
2882         /* BPC in FDI rx is consistent with that in PIPECONF */
2883         temp &= ~(0x07 << 16);
2884         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2885         I915_WRITE(reg, temp);
2886
2887         POSTING_READ(reg);
2888         udelay(100);
2889 }
2890
2891 /*
2892  * When we disable a pipe, we need to clear any pending scanline wait events
2893  * to avoid hanging the ring, which we assume we are waiting on.
2894  */
2895 static void intel_clear_scanline_wait(struct drm_device *dev)
2896 {
2897         struct drm_i915_private *dev_priv = dev->dev_private;
2898         struct intel_ring_buffer *ring;
2899         u32 tmp;
2900
2901         if (IS_GEN2(dev))
2902                 /* Can't break the hang on i8xx */
2903                 return;
2904
2905         ring = LP_RING(dev_priv);
2906         tmp = I915_READ_CTL(ring);
2907         if (tmp & RING_WAIT)
2908                 I915_WRITE_CTL(ring, tmp);
2909 }
2910
2911 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2912 {
2913         struct drm_i915_gem_object *obj;
2914         struct drm_i915_private *dev_priv;
2915
2916         if (crtc->fb == NULL)
2917                 return;
2918
2919         obj = to_intel_framebuffer(crtc->fb)->obj;
2920         dev_priv = crtc->dev->dev_private;
2921         wait_event(dev_priv->pending_flip_queue,
2922                    atomic_read(&obj->pending_flip) == 0);
2923 }
2924
2925 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2926 {
2927         struct drm_device *dev = crtc->dev;
2928         struct drm_mode_config *mode_config = &dev->mode_config;
2929         struct intel_encoder *encoder;
2930
2931         /*
2932          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2933          * must be driven by its own crtc; no sharing is possible.
2934          */
2935         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2936                 if (encoder->base.crtc != crtc)
2937                         continue;
2938
2939                 switch (encoder->type) {
2940                 case INTEL_OUTPUT_EDP:
2941                         if (!intel_encoder_is_pch_edp(&encoder->base))
2942                                 return false;
2943                         continue;
2944                 }
2945         }
2946
2947         return true;
2948 }
2949
2950 /*
2951  * Enable PCH resources required for PCH ports:
2952  *   - PCH PLLs
2953  *   - FDI training & RX/TX
2954  *   - update transcoder timings
2955  *   - DP transcoding bits
2956  *   - transcoder
2957  */
2958 static void ironlake_pch_enable(struct drm_crtc *crtc)
2959 {
2960         struct drm_device *dev = crtc->dev;
2961         struct drm_i915_private *dev_priv = dev->dev_private;
2962         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2963         int pipe = intel_crtc->pipe;
2964         u32 reg, temp, transc_sel;
2965
2966         /* For PCH output, training FDI link */
2967         dev_priv->display.fdi_link_train(crtc);
2968
2969         intel_enable_pch_pll(dev_priv, pipe);
2970
2971         if (HAS_PCH_CPT(dev)) {
2972                 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2973                         TRANSC_DPLLB_SEL;
2974
2975                 /* Be sure PCH DPLL SEL is set */
2976                 temp = I915_READ(PCH_DPLL_SEL);
2977                 if (pipe == 0) {
2978                         temp &= ~(TRANSA_DPLLB_SEL);
2979                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2980                 } else if (pipe == 1) {
2981                         temp &= ~(TRANSB_DPLLB_SEL);
2982                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2983                 } else if (pipe == 2) {
2984                         temp &= ~(TRANSC_DPLLB_SEL);
2985                         temp |= (TRANSC_DPLL_ENABLE | transc_sel);
2986                 }
2987                 I915_WRITE(PCH_DPLL_SEL, temp);
2988         }
2989
2990         /* set transcoder timing, panel must allow it */
2991         assert_panel_unlocked(dev_priv, pipe);
2992         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2993         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2994         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2995
2996         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2997         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2998         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2999         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3000
3001         intel_fdi_normal_train(crtc);
3002
3003         /* For PCH DP, enable TRANS_DP_CTL */
3004         if (HAS_PCH_CPT(dev) &&
3005             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3006              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3007                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3008                 reg = TRANS_DP_CTL(pipe);
3009                 temp = I915_READ(reg);
3010                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3011                           TRANS_DP_SYNC_MASK |
3012                           TRANS_DP_BPC_MASK);
3013                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3014                          TRANS_DP_ENH_FRAMING);
3015                 temp |= bpc << 9; /* same format but at 11:9 */
3016
3017                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3018                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3019                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3020                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3021
3022                 switch (intel_trans_dp_port_sel(crtc)) {
3023                 case PCH_DP_B:
3024                         temp |= TRANS_DP_PORT_SEL_B;
3025                         break;
3026                 case PCH_DP_C:
3027                         temp |= TRANS_DP_PORT_SEL_C;
3028                         break;
3029                 case PCH_DP_D:
3030                         temp |= TRANS_DP_PORT_SEL_D;
3031                         break;
3032                 default:
3033                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3034                         temp |= TRANS_DP_PORT_SEL_B;
3035                         break;
3036                 }
3037
3038                 I915_WRITE(reg, temp);
3039         }
3040
3041         intel_enable_transcoder(dev_priv, pipe);
3042 }
3043
3044 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3045 {
3046         struct drm_i915_private *dev_priv = dev->dev_private;
3047         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3048         u32 temp;
3049
3050         temp = I915_READ(dslreg);
3051         udelay(500);
3052         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3053                 /* Without this, mode sets may fail silently on FDI */
3054                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3055                 udelay(250);
3056                 I915_WRITE(tc2reg, 0);
3057                 if (wait_for(I915_READ(dslreg) != temp, 5))
3058                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3059         }
3060 }
3061
3062 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3063 {
3064         struct drm_device *dev = crtc->dev;
3065         struct drm_i915_private *dev_priv = dev->dev_private;
3066         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3067         int pipe = intel_crtc->pipe;
3068         int plane = intel_crtc->plane;
3069         u32 temp;
3070         bool is_pch_port;
3071
3072         if (intel_crtc->active)
3073                 return;
3074
3075         intel_crtc->active = true;
3076         intel_update_watermarks(dev);
3077
3078         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3079                 temp = I915_READ(PCH_LVDS);
3080                 if ((temp & LVDS_PORT_EN) == 0)
3081                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3082         }
3083
3084         is_pch_port = intel_crtc_driving_pch(crtc);
3085
3086         if (is_pch_port)
3087                 ironlake_fdi_pll_enable(crtc);
3088         else
3089                 ironlake_fdi_disable(crtc);
3090
3091         /* Enable panel fitting for LVDS */
3092         if (dev_priv->pch_pf_size &&
3093             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3094                 /* Force use of hard-coded filter coefficients
3095                  * as some pre-programmed values are broken,
3096                  * e.g. x201.
3097                  */
3098                 if (IS_IVYBRIDGE(dev))
3099                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3100                                                  PF_PIPE_SEL_IVB(pipe));
3101                 else
3102                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3103                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3104                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3105         }
3106
3107         /*
3108          * On ILK+ LUT must be loaded before the pipe is running but with
3109          * clocks enabled
3110          */
3111         intel_crtc_load_lut(crtc);
3112
3113         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3114         intel_enable_plane(dev_priv, plane, pipe);
3115
3116         if (is_pch_port)
3117                 ironlake_pch_enable(crtc);
3118
3119         mutex_lock(&dev->struct_mutex);
3120         intel_update_fbc(dev);
3121         mutex_unlock(&dev->struct_mutex);
3122
3123         intel_crtc_update_cursor(crtc, true);
3124 }
3125
3126 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3127 {
3128         struct drm_device *dev = crtc->dev;
3129         struct drm_i915_private *dev_priv = dev->dev_private;
3130         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3131         int pipe = intel_crtc->pipe;
3132         int plane = intel_crtc->plane;
3133         u32 reg, temp;
3134
3135         if (!intel_crtc->active)
3136                 return;
3137
3138         intel_crtc_wait_for_pending_flips(crtc);
3139         drm_vblank_off(dev, pipe);
3140         intel_crtc_update_cursor(crtc, false);
3141
3142         intel_disable_plane(dev_priv, plane, pipe);
3143
3144         if (dev_priv->cfb_plane == plane)
3145                 intel_disable_fbc(dev);
3146
3147         intel_disable_pipe(dev_priv, pipe);
3148
3149         /* Disable PF */
3150         I915_WRITE(PF_CTL(pipe), 0);
3151         I915_WRITE(PF_WIN_SZ(pipe), 0);
3152
3153         ironlake_fdi_disable(crtc);
3154
3155         /* This is a horrible layering violation; we should be doing this in
3156          * the connector/encoder ->prepare instead, but we don't always have
3157          * enough information there about the config to know whether it will
3158          * actually be necessary or just cause undesired flicker.
3159          */
3160         intel_disable_pch_ports(dev_priv, pipe);
3161
3162         intel_disable_transcoder(dev_priv, pipe);
3163
3164         if (HAS_PCH_CPT(dev)) {
3165                 /* disable TRANS_DP_CTL */
3166                 reg = TRANS_DP_CTL(pipe);
3167                 temp = I915_READ(reg);
3168                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3169                 temp |= TRANS_DP_PORT_SEL_NONE;
3170                 I915_WRITE(reg, temp);
3171
3172                 /* disable DPLL_SEL */
3173                 temp = I915_READ(PCH_DPLL_SEL);
3174                 switch (pipe) {
3175                 case 0:
3176                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3177                         break;
3178                 case 1:
3179                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3180                         break;
3181                 case 2:
3182                         /* C shares PLL A or B */
3183                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3184                         break;
3185                 default:
3186                         BUG(); /* wtf */
3187                 }
3188                 I915_WRITE(PCH_DPLL_SEL, temp);
3189         }
3190
3191         /* disable PCH DPLL */
3192         if (!intel_crtc->no_pll)
3193                 intel_disable_pch_pll(dev_priv, pipe);
3194
3195         /* Switch from PCDclk to Rawclk */
3196         reg = FDI_RX_CTL(pipe);
3197         temp = I915_READ(reg);
3198         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3199
3200         /* Disable CPU FDI TX PLL */
3201         reg = FDI_TX_CTL(pipe);
3202         temp = I915_READ(reg);
3203         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3204
3205         POSTING_READ(reg);
3206         udelay(100);
3207
3208         reg = FDI_RX_CTL(pipe);
3209         temp = I915_READ(reg);
3210         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3211
3212         /* Wait for the clocks to turn off. */
3213         POSTING_READ(reg);
3214         udelay(100);
3215
3216         intel_crtc->active = false;
3217         intel_update_watermarks(dev);
3218
3219         mutex_lock(&dev->struct_mutex);
3220         intel_update_fbc(dev);
3221         intel_clear_scanline_wait(dev);
3222         mutex_unlock(&dev->struct_mutex);
3223 }
3224
3225 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3226 {
3227         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3228         int pipe = intel_crtc->pipe;
3229         int plane = intel_crtc->plane;
3230
3231         /* XXX: When our outputs are all unaware of DPMS modes other than off
3232          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3233          */
3234         switch (mode) {
3235         case DRM_MODE_DPMS_ON:
3236         case DRM_MODE_DPMS_STANDBY:
3237         case DRM_MODE_DPMS_SUSPEND:
3238                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3239                 ironlake_crtc_enable(crtc);
3240                 break;
3241
3242         case DRM_MODE_DPMS_OFF:
3243                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3244                 ironlake_crtc_disable(crtc);
3245                 break;
3246         }
3247 }
3248
3249 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3250 {
3251         if (!enable && intel_crtc->overlay) {
3252                 struct drm_device *dev = intel_crtc->base.dev;
3253                 struct drm_i915_private *dev_priv = dev->dev_private;
3254
3255                 mutex_lock(&dev->struct_mutex);
3256                 dev_priv->mm.interruptible = false;
3257                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3258                 dev_priv->mm.interruptible = true;
3259                 mutex_unlock(&dev->struct_mutex);
3260         }
3261
3262         /* Let userspace switch the overlay on again. In most cases userspace
3263          * has to recompute where to put it anyway.
3264          */
3265 }
3266
3267 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3268 {
3269         struct drm_device *dev = crtc->dev;
3270         struct drm_i915_private *dev_priv = dev->dev_private;
3271         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3272         int pipe = intel_crtc->pipe;
3273         int plane = intel_crtc->plane;
3274
3275         if (intel_crtc->active)
3276                 return;
3277
3278         intel_crtc->active = true;
3279         intel_update_watermarks(dev);
3280
3281         intel_enable_pll(dev_priv, pipe);
3282         intel_enable_pipe(dev_priv, pipe, false);
3283         intel_enable_plane(dev_priv, plane, pipe);
3284
3285         intel_crtc_load_lut(crtc);
3286         intel_update_fbc(dev);
3287
3288         /* Give the overlay scaler a chance to enable if it's on this pipe */
3289         intel_crtc_dpms_overlay(intel_crtc, true);
3290         intel_crtc_update_cursor(crtc, true);
3291 }
3292
3293 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3294 {
3295         struct drm_device *dev = crtc->dev;
3296         struct drm_i915_private *dev_priv = dev->dev_private;
3297         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3298         int pipe = intel_crtc->pipe;
3299         int plane = intel_crtc->plane;
3300
3301         if (!intel_crtc->active)
3302                 return;
3303
3304         /* Give the overlay scaler a chance to disable if it's on this pipe */
3305         intel_crtc_wait_for_pending_flips(crtc);
3306         drm_vblank_off(dev, pipe);
3307         intel_crtc_dpms_overlay(intel_crtc, false);
3308         intel_crtc_update_cursor(crtc, false);
3309
3310         if (dev_priv->cfb_plane == plane)
3311                 intel_disable_fbc(dev);
3312
3313         intel_disable_plane(dev_priv, plane, pipe);
3314         intel_disable_pipe(dev_priv, pipe);
3315         intel_disable_pll(dev_priv, pipe);
3316
3317         intel_crtc->active = false;
3318         intel_update_fbc(dev);
3319         intel_update_watermarks(dev);
3320         intel_clear_scanline_wait(dev);
3321 }
3322
3323 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3324 {
3325         /* XXX: When our outputs are all unaware of DPMS modes other than off
3326          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3327          */
3328         switch (mode) {
3329         case DRM_MODE_DPMS_ON:
3330         case DRM_MODE_DPMS_STANDBY:
3331         case DRM_MODE_DPMS_SUSPEND:
3332                 i9xx_crtc_enable(crtc);
3333                 break;
3334         case DRM_MODE_DPMS_OFF:
3335                 i9xx_crtc_disable(crtc);
3336                 break;
3337         }
3338 }
3339
3340 /**
3341  * Sets the power management mode of the pipe and plane.
3342  */
3343 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3344 {
3345         struct drm_device *dev = crtc->dev;
3346         struct drm_i915_private *dev_priv = dev->dev_private;
3347         struct drm_i915_master_private *master_priv;
3348         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3349         int pipe = intel_crtc->pipe;
3350         bool enabled;
3351
3352         if (intel_crtc->dpms_mode == mode)
3353                 return;
3354
3355         intel_crtc->dpms_mode = mode;
3356
3357         dev_priv->display.dpms(crtc, mode);
3358
3359         if (!dev->primary->master)
3360                 return;
3361
3362         master_priv = dev->primary->master->driver_priv;
3363         if (!master_priv->sarea_priv)
3364                 return;
3365
3366         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3367
3368         switch (pipe) {
3369         case 0:
3370                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3371                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3372                 break;
3373         case 1:
3374                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3375                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3376                 break;
3377         default:
3378                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3379                 break;
3380         }
3381 }
3382
3383 static void intel_crtc_disable(struct drm_crtc *crtc)
3384 {
3385         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3386         struct drm_device *dev = crtc->dev;
3387
3388         /* Flush any pending WAITs before we disable the pipe. Note that
3389          * we need to drop the struct_mutex in order to acquire it again
3390          * during the lowlevel dpms routines around a couple of the
3391          * operations. It does not look trivial nor desirable to move
3392          * that locking higher. So instead we leave a window for the
3393          * submission of further commands on the fb before we can actually
3394          * disable it. This race with userspace exists anyway, and we can
3395          * only rely on the pipe being disabled by userspace after it
3396          * receives the hotplug notification and has flushed any pending
3397          * batches.
3398          */
3399         if (crtc->fb) {
3400                 mutex_lock(&dev->struct_mutex);
3401                 intel_finish_fb(crtc->fb);
3402                 mutex_unlock(&dev->struct_mutex);
3403         }
3404
3405         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3406         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3407         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3408
3409         if (crtc->fb) {
3410                 mutex_lock(&dev->struct_mutex);
3411                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3412                 mutex_unlock(&dev->struct_mutex);
3413         }
3414 }
3415
3416 /* Prepare for a mode set.
3417  *
3418  * Note we could be a lot smarter here.  We need to figure out which outputs
3419  * will be enabled, which disabled (in short, how the config will changes)
3420  * and perform the minimum necessary steps to accomplish that, e.g. updating
3421  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3422  * panel fitting is in the proper state, etc.
3423  */
3424 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3425 {
3426         i9xx_crtc_disable(crtc);
3427 }
3428
3429 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3430 {
3431         i9xx_crtc_enable(crtc);
3432 }
3433
3434 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3435 {
3436         ironlake_crtc_disable(crtc);
3437 }
3438
3439 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3440 {
3441         ironlake_crtc_enable(crtc);
3442 }
3443
3444 void intel_encoder_prepare(struct drm_encoder *encoder)
3445 {
3446         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3447         /* lvds has its own version of prepare see intel_lvds_prepare */
3448         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3449 }
3450
3451 void intel_encoder_commit(struct drm_encoder *encoder)
3452 {
3453         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3454         struct drm_device *dev = encoder->dev;
3455         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3456         struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3457
3458         /* lvds has its own version of commit see intel_lvds_commit */
3459         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3460
3461         if (HAS_PCH_CPT(dev))
3462                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3463 }
3464
3465 void intel_encoder_destroy(struct drm_encoder *encoder)
3466 {
3467         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3468
3469         drm_encoder_cleanup(encoder);
3470         kfree(intel_encoder);
3471 }
3472
3473 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3474                                   struct drm_display_mode *mode,
3475                                   struct drm_display_mode *adjusted_mode)
3476 {
3477         struct drm_device *dev = crtc->dev;
3478
3479         if (HAS_PCH_SPLIT(dev)) {
3480                 /* FDI link clock is fixed at 2.7G */
3481                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3482                         return false;
3483         }
3484
3485         /* All interlaced capable intel hw wants timings in frames. Note though
3486          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3487          * timings, so we need to be careful not to clobber these.*/
3488         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3489                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3490
3491         return true;
3492 }
3493
3494 static int i945_get_display_clock_speed(struct drm_device *dev)
3495 {
3496         return 400000;
3497 }
3498
3499 static int i915_get_display_clock_speed(struct drm_device *dev)
3500 {
3501         return 333000;
3502 }
3503
3504 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3505 {
3506         return 200000;
3507 }
3508
3509 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3510 {
3511         u16 gcfgc = 0;
3512
3513         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3514
3515         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3516                 return 133000;
3517         else {
3518                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3519                 case GC_DISPLAY_CLOCK_333_MHZ:
3520                         return 333000;
3521                 default:
3522                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3523                         return 190000;
3524                 }
3525         }
3526 }
3527
3528 static int i865_get_display_clock_speed(struct drm_device *dev)
3529 {
3530         return 266000;
3531 }
3532
3533 static int i855_get_display_clock_speed(struct drm_device *dev)
3534 {
3535         u16 hpllcc = 0;
3536         /* Assume that the hardware is in the high speed state.  This
3537          * should be the default.
3538          */
3539         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3540         case GC_CLOCK_133_200:
3541         case GC_CLOCK_100_200:
3542                 return 200000;
3543         case GC_CLOCK_166_250:
3544                 return 250000;
3545         case GC_CLOCK_100_133:
3546                 return 133000;
3547         }
3548
3549         /* Shouldn't happen */
3550         return 0;
3551 }
3552
3553 static int i830_get_display_clock_speed(struct drm_device *dev)
3554 {
3555         return 133000;
3556 }
3557
3558 struct fdi_m_n {
3559         u32        tu;
3560         u32        gmch_m;
3561         u32        gmch_n;
3562         u32        link_m;
3563         u32        link_n;
3564 };
3565
3566 static void
3567 fdi_reduce_ratio(u32 *num, u32 *den)
3568 {
3569         while (*num > 0xffffff || *den > 0xffffff) {
3570                 *num >>= 1;
3571                 *den >>= 1;
3572         }
3573 }
3574
3575 static void
3576 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3577                      int link_clock, struct fdi_m_n *m_n)
3578 {
3579         m_n->tu = 64; /* default size */
3580
3581         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3582         m_n->gmch_m = bits_per_pixel * pixel_clock;
3583         m_n->gmch_n = link_clock * nlanes * 8;
3584         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3585
3586         m_n->link_m = pixel_clock;
3587         m_n->link_n = link_clock;
3588         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3589 }
3590
3591
3592 struct intel_watermark_params {
3593         unsigned long fifo_size;
3594         unsigned long max_wm;
3595         unsigned long default_wm;
3596         unsigned long guard_size;
3597         unsigned long cacheline_size;
3598 };
3599
3600 /* Pineview has different values for various configs */
3601 static const struct intel_watermark_params pineview_display_wm = {
3602         PINEVIEW_DISPLAY_FIFO,
3603         PINEVIEW_MAX_WM,
3604         PINEVIEW_DFT_WM,
3605         PINEVIEW_GUARD_WM,
3606         PINEVIEW_FIFO_LINE_SIZE
3607 };
3608 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3609         PINEVIEW_DISPLAY_FIFO,
3610         PINEVIEW_MAX_WM,
3611         PINEVIEW_DFT_HPLLOFF_WM,
3612         PINEVIEW_GUARD_WM,
3613         PINEVIEW_FIFO_LINE_SIZE
3614 };
3615 static const struct intel_watermark_params pineview_cursor_wm = {
3616         PINEVIEW_CURSOR_FIFO,
3617         PINEVIEW_CURSOR_MAX_WM,
3618         PINEVIEW_CURSOR_DFT_WM,
3619         PINEVIEW_CURSOR_GUARD_WM,
3620         PINEVIEW_FIFO_LINE_SIZE,
3621 };
3622 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3623         PINEVIEW_CURSOR_FIFO,
3624         PINEVIEW_CURSOR_MAX_WM,
3625         PINEVIEW_CURSOR_DFT_WM,
3626         PINEVIEW_CURSOR_GUARD_WM,
3627         PINEVIEW_FIFO_LINE_SIZE
3628 };
3629 static const struct intel_watermark_params g4x_wm_info = {
3630         G4X_FIFO_SIZE,
3631         G4X_MAX_WM,
3632         G4X_MAX_WM,
3633         2,
3634         G4X_FIFO_LINE_SIZE,
3635 };
3636 static const struct intel_watermark_params g4x_cursor_wm_info = {
3637         I965_CURSOR_FIFO,
3638         I965_CURSOR_MAX_WM,
3639         I965_CURSOR_DFT_WM,
3640         2,
3641         G4X_FIFO_LINE_SIZE,
3642 };
3643 static const struct intel_watermark_params i965_cursor_wm_info = {
3644         I965_CURSOR_FIFO,
3645         I965_CURSOR_MAX_WM,
3646         I965_CURSOR_DFT_WM,
3647         2,
3648         I915_FIFO_LINE_SIZE,
3649 };
3650 static const struct intel_watermark_params i945_wm_info = {
3651         I945_FIFO_SIZE,
3652         I915_MAX_WM,
3653         1,
3654         2,
3655         I915_FIFO_LINE_SIZE
3656 };
3657 static const struct intel_watermark_params i915_wm_info = {
3658         I915_FIFO_SIZE,
3659         I915_MAX_WM,
3660         1,
3661         2,
3662         I915_FIFO_LINE_SIZE
3663 };
3664 static const struct intel_watermark_params i855_wm_info = {
3665         I855GM_FIFO_SIZE,
3666         I915_MAX_WM,
3667         1,
3668         2,
3669         I830_FIFO_LINE_SIZE
3670 };
3671 static const struct intel_watermark_params i830_wm_info = {
3672         I830_FIFO_SIZE,
3673         I915_MAX_WM,
3674         1,
3675         2,
3676         I830_FIFO_LINE_SIZE
3677 };
3678
3679 static const struct intel_watermark_params ironlake_display_wm_info = {
3680         ILK_DISPLAY_FIFO,
3681         ILK_DISPLAY_MAXWM,
3682         ILK_DISPLAY_DFTWM,
3683         2,
3684         ILK_FIFO_LINE_SIZE
3685 };
3686 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3687         ILK_CURSOR_FIFO,
3688         ILK_CURSOR_MAXWM,
3689         ILK_CURSOR_DFTWM,
3690         2,
3691         ILK_FIFO_LINE_SIZE
3692 };
3693 static const struct intel_watermark_params ironlake_display_srwm_info = {
3694         ILK_DISPLAY_SR_FIFO,
3695         ILK_DISPLAY_MAX_SRWM,
3696         ILK_DISPLAY_DFT_SRWM,
3697         2,
3698         ILK_FIFO_LINE_SIZE
3699 };
3700 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3701         ILK_CURSOR_SR_FIFO,
3702         ILK_CURSOR_MAX_SRWM,
3703         ILK_CURSOR_DFT_SRWM,
3704         2,
3705         ILK_FIFO_LINE_SIZE
3706 };
3707
3708 static const struct intel_watermark_params sandybridge_display_wm_info = {
3709         SNB_DISPLAY_FIFO,
3710         SNB_DISPLAY_MAXWM,
3711         SNB_DISPLAY_DFTWM,
3712         2,
3713         SNB_FIFO_LINE_SIZE
3714 };
3715 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3716         SNB_CURSOR_FIFO,
3717         SNB_CURSOR_MAXWM,
3718         SNB_CURSOR_DFTWM,
3719         2,
3720         SNB_FIFO_LINE_SIZE
3721 };
3722 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3723         SNB_DISPLAY_SR_FIFO,
3724         SNB_DISPLAY_MAX_SRWM,
3725         SNB_DISPLAY_DFT_SRWM,
3726         2,
3727         SNB_FIFO_LINE_SIZE
3728 };
3729 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3730         SNB_CURSOR_SR_FIFO,
3731         SNB_CURSOR_MAX_SRWM,
3732         SNB_CURSOR_DFT_SRWM,
3733         2,
3734         SNB_FIFO_LINE_SIZE
3735 };
3736
3737
3738 /**
3739  * intel_calculate_wm - calculate watermark level
3740  * @clock_in_khz: pixel clock
3741  * @wm: chip FIFO params
3742  * @pixel_size: display pixel size
3743  * @latency_ns: memory latency for the platform
3744  *
3745  * Calculate the watermark level (the level at which the display plane will
3746  * start fetching from memory again).  Each chip has a different display
3747  * FIFO size and allocation, so the caller needs to figure that out and pass
3748  * in the correct intel_watermark_params structure.
3749  *
3750  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3751  * on the pixel size.  When it reaches the watermark level, it'll start
3752  * fetching FIFO line sized based chunks from memory until the FIFO fills
3753  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3754  * will occur, and a display engine hang could result.
3755  */
3756 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3757                                         const struct intel_watermark_params *wm,
3758                                         int fifo_size,
3759                                         int pixel_size,
3760                                         unsigned long latency_ns)
3761 {
3762         long entries_required, wm_size;
3763
3764         /*
3765          * Note: we need to make sure we don't overflow for various clock &
3766          * latency values.
3767          * clocks go from a few thousand to several hundred thousand.
3768          * latency is usually a few thousand
3769          */
3770         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3771                 1000;
3772         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3773
3774         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3775
3776         wm_size = fifo_size - (entries_required + wm->guard_size);
3777
3778         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3779
3780         /* Don't promote wm_size to unsigned... */
3781         if (wm_size > (long)wm->max_wm)
3782                 wm_size = wm->max_wm;
3783         if (wm_size <= 0)
3784                 wm_size = wm->default_wm;
3785         return wm_size;
3786 }
3787
3788 struct cxsr_latency {
3789         int is_desktop;
3790         int is_ddr3;
3791         unsigned long fsb_freq;
3792         unsigned long mem_freq;
3793         unsigned long display_sr;
3794         unsigned long display_hpll_disable;
3795         unsigned long cursor_sr;
3796         unsigned long cursor_hpll_disable;
3797 };
3798
3799 static const struct cxsr_latency cxsr_latency_table[] = {
3800         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3801         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3802         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3803         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3804         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3805
3806         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3807         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3808         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3809         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3810         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3811
3812         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3813         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3814         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3815         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3816         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3817
3818         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3819         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3820         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3821         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3822         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3823
3824         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3825         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3826         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3827         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3828         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3829
3830         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3831         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3832         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3833         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3834         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3835 };
3836
3837 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3838                                                          int is_ddr3,
3839                                                          int fsb,
3840                                                          int mem)
3841 {
3842         const struct cxsr_latency *latency;
3843         int i;
3844
3845         if (fsb == 0 || mem == 0)
3846                 return NULL;
3847
3848         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3849                 latency = &cxsr_latency_table[i];
3850                 if (is_desktop == latency->is_desktop &&
3851                     is_ddr3 == latency->is_ddr3 &&
3852                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3853                         return latency;
3854         }
3855
3856         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3857
3858         return NULL;
3859 }
3860
3861 static void pineview_disable_cxsr(struct drm_device *dev)
3862 {
3863         struct drm_i915_private *dev_priv = dev->dev_private;
3864
3865         /* deactivate cxsr */
3866         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3867 }
3868
3869 /*
3870  * Latency for FIFO fetches is dependent on several factors:
3871  *   - memory configuration (speed, channels)
3872  *   - chipset
3873  *   - current MCH state
3874  * It can be fairly high in some situations, so here we assume a fairly
3875  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3876  * set this value too high, the FIFO will fetch frequently to stay full)
3877  * and power consumption (set it too low to save power and we might see
3878  * FIFO underruns and display "flicker").
3879  *
3880  * A value of 5us seems to be a good balance; safe for very low end
3881  * platforms but not overly aggressive on lower latency configs.
3882  */
3883 static const int latency_ns = 5000;
3884
3885 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3886 {
3887         struct drm_i915_private *dev_priv = dev->dev_private;
3888         uint32_t dsparb = I915_READ(DSPARB);
3889         int size;
3890
3891         size = dsparb & 0x7f;
3892         if (plane)
3893                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3894
3895         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3896                       plane ? "B" : "A", size);
3897
3898         return size;
3899 }
3900
3901 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3902 {
3903         struct drm_i915_private *dev_priv = dev->dev_private;
3904         uint32_t dsparb = I915_READ(DSPARB);
3905         int size;
3906
3907         size = dsparb & 0x1ff;
3908         if (plane)
3909                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3910         size >>= 1; /* Convert to cachelines */
3911
3912         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3913                       plane ? "B" : "A", size);
3914
3915         return size;
3916 }
3917
3918 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3919 {
3920         struct drm_i915_private *dev_priv = dev->dev_private;
3921         uint32_t dsparb = I915_READ(DSPARB);
3922         int size;
3923
3924         size = dsparb & 0x7f;
3925         size >>= 2; /* Convert to cachelines */
3926
3927         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3928                       plane ? "B" : "A",
3929                       size);
3930
3931         return size;
3932 }
3933
3934 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3935 {
3936         struct drm_i915_private *dev_priv = dev->dev_private;
3937         uint32_t dsparb = I915_READ(DSPARB);
3938         int size;
3939
3940         size = dsparb & 0x7f;
3941         size >>= 1; /* Convert to cachelines */
3942
3943         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3944                       plane ? "B" : "A", size);
3945
3946         return size;
3947 }
3948
3949 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3950 {
3951         struct drm_crtc *crtc, *enabled = NULL;
3952
3953         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3954                 if (crtc->enabled && crtc->fb) {
3955                         if (enabled)
3956                                 return NULL;
3957                         enabled = crtc;
3958                 }
3959         }
3960
3961         return enabled;
3962 }
3963
3964 static void pineview_update_wm(struct drm_device *dev)
3965 {
3966         struct drm_i915_private *dev_priv = dev->dev_private;
3967         struct drm_crtc *crtc;
3968         const struct cxsr_latency *latency;
3969         u32 reg;
3970         unsigned long wm;
3971
3972         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3973                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3974         if (!latency) {
3975                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3976                 pineview_disable_cxsr(dev);
3977                 return;
3978         }
3979
3980         crtc = single_enabled_crtc(dev);
3981         if (crtc) {
3982                 int clock = crtc->mode.clock;
3983                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3984
3985                 /* Display SR */
3986                 wm = intel_calculate_wm(clock, &pineview_display_wm,
3987                                         pineview_display_wm.fifo_size,
3988                                         pixel_size, latency->display_sr);
3989                 reg = I915_READ(DSPFW1);
3990                 reg &= ~DSPFW_SR_MASK;
3991                 reg |= wm << DSPFW_SR_SHIFT;
3992                 I915_WRITE(DSPFW1, reg);
3993                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3994
3995                 /* cursor SR */
3996                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3997                                         pineview_display_wm.fifo_size,
3998                                         pixel_size, latency->cursor_sr);
3999                 reg = I915_READ(DSPFW3);
4000                 reg &= ~DSPFW_CURSOR_SR_MASK;
4001                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
4002                 I915_WRITE(DSPFW3, reg);
4003
4004                 /* Display HPLL off SR */
4005                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
4006                                         pineview_display_hplloff_wm.fifo_size,
4007                                         pixel_size, latency->display_hpll_disable);
4008                 reg = I915_READ(DSPFW3);
4009                 reg &= ~DSPFW_HPLL_SR_MASK;
4010                 reg |= wm & DSPFW_HPLL_SR_MASK;
4011                 I915_WRITE(DSPFW3, reg);
4012
4013                 /* cursor HPLL off SR */
4014                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
4015                                         pineview_display_hplloff_wm.fifo_size,
4016                                         pixel_size, latency->cursor_hpll_disable);
4017                 reg = I915_READ(DSPFW3);
4018                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
4019                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
4020                 I915_WRITE(DSPFW3, reg);
4021                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
4022
4023                 /* activate cxsr */
4024                 I915_WRITE(DSPFW3,
4025                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
4026                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
4027         } else {
4028                 pineview_disable_cxsr(dev);
4029                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
4030         }
4031 }
4032
4033 static bool g4x_compute_wm0(struct drm_device *dev,
4034                             int plane,
4035                             const struct intel_watermark_params *display,
4036                             int display_latency_ns,
4037                             const struct intel_watermark_params *cursor,
4038                             int cursor_latency_ns,
4039                             int *plane_wm,
4040                             int *cursor_wm)
4041 {
4042         struct drm_crtc *crtc;
4043         int htotal, hdisplay, clock, pixel_size;
4044         int line_time_us, line_count;
4045         int entries, tlb_miss;
4046
4047         crtc = intel_get_crtc_for_plane(dev, plane);
4048         if (crtc->fb == NULL || !crtc->enabled) {
4049                 *cursor_wm = cursor->guard_size;
4050                 *plane_wm = display->guard_size;
4051                 return false;
4052         }
4053
4054         htotal = crtc->mode.htotal;
4055         hdisplay = crtc->mode.hdisplay;
4056         clock = crtc->mode.clock;
4057         pixel_size = crtc->fb->bits_per_pixel / 8;
4058
4059         /* Use the small buffer method to calculate plane watermark */
4060         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4061         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4062         if (tlb_miss > 0)
4063                 entries += tlb_miss;
4064         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4065         *plane_wm = entries + display->guard_size;
4066         if (*plane_wm > (int)display->max_wm)
4067                 *plane_wm = display->max_wm;
4068
4069         /* Use the large buffer method to calculate cursor watermark */
4070         line_time_us = ((htotal * 1000) / clock);
4071         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4072         entries = line_count * 64 * pixel_size;
4073         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4074         if (tlb_miss > 0)
4075                 entries += tlb_miss;
4076         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4077         *cursor_wm = entries + cursor->guard_size;
4078         if (*cursor_wm > (int)cursor->max_wm)
4079                 *cursor_wm = (int)cursor->max_wm;
4080
4081         return true;
4082 }
4083
4084 /*
4085  * Check the wm result.
4086  *
4087  * If any calculated watermark values is larger than the maximum value that
4088  * can be programmed into the associated watermark register, that watermark
4089  * must be disabled.
4090  */
4091 static bool g4x_check_srwm(struct drm_device *dev,
4092                            int display_wm, int cursor_wm,
4093                            const struct intel_watermark_params *display,
4094                            const struct intel_watermark_params *cursor)
4095 {
4096         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4097                       display_wm, cursor_wm);
4098
4099         if (display_wm > display->max_wm) {
4100                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4101                               display_wm, display->max_wm);
4102                 return false;
4103         }
4104
4105         if (cursor_wm > cursor->max_wm) {
4106                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4107                               cursor_wm, cursor->max_wm);
4108                 return false;
4109         }
4110
4111         if (!(display_wm || cursor_wm)) {
4112                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4113                 return false;
4114         }
4115
4116         return true;
4117 }
4118
4119 static bool g4x_compute_srwm(struct drm_device *dev,
4120                              int plane,
4121                              int latency_ns,
4122                              const struct intel_watermark_params *display,
4123                              const struct intel_watermark_params *cursor,
4124                              int *display_wm, int *cursor_wm)
4125 {
4126         struct drm_crtc *crtc;
4127         int hdisplay, htotal, pixel_size, clock;
4128         unsigned long line_time_us;
4129         int line_count, line_size;
4130         int small, large;
4131         int entries;
4132
4133         if (!latency_ns) {
4134                 *display_wm = *cursor_wm = 0;
4135                 return false;
4136         }
4137
4138         crtc = intel_get_crtc_for_plane(dev, plane);
4139         hdisplay = crtc->mode.hdisplay;
4140         htotal = crtc->mode.htotal;
4141         clock = crtc->mode.clock;
4142         pixel_size = crtc->fb->bits_per_pixel / 8;
4143
4144         line_time_us = (htotal * 1000) / clock;
4145         line_count = (latency_ns / line_time_us + 1000) / 1000;
4146         line_size = hdisplay * pixel_size;
4147
4148         /* Use the minimum of the small and large buffer method for primary */
4149         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4150         large = line_count * line_size;
4151
4152         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4153         *display_wm = entries + display->guard_size;
4154
4155         /* calculate the self-refresh watermark for display cursor */
4156         entries = line_count * pixel_size * 64;
4157         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4158         *cursor_wm = entries + cursor->guard_size;
4159
4160         return g4x_check_srwm(dev,
4161                               *display_wm, *cursor_wm,
4162                               display, cursor);
4163 }
4164
4165 #define single_plane_enabled(mask) is_power_of_2(mask)
4166
4167 static void g4x_update_wm(struct drm_device *dev)
4168 {
4169         static const int sr_latency_ns = 12000;
4170         struct drm_i915_private *dev_priv = dev->dev_private;
4171         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4172         int plane_sr, cursor_sr;
4173         unsigned int enabled = 0;
4174
4175         if (g4x_compute_wm0(dev, 0,
4176                             &g4x_wm_info, latency_ns,
4177                             &g4x_cursor_wm_info, latency_ns,
4178                             &planea_wm, &cursora_wm))
4179                 enabled |= 1;
4180
4181         if (g4x_compute_wm0(dev, 1,
4182                             &g4x_wm_info, latency_ns,
4183                             &g4x_cursor_wm_info, latency_ns,
4184                             &planeb_wm, &cursorb_wm))
4185                 enabled |= 2;
4186
4187         plane_sr = cursor_sr = 0;
4188         if (single_plane_enabled(enabled) &&
4189             g4x_compute_srwm(dev, ffs(enabled) - 1,
4190                              sr_latency_ns,
4191                              &g4x_wm_info,
4192                              &g4x_cursor_wm_info,
4193                              &plane_sr, &cursor_sr))
4194                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4195         else
4196                 I915_WRITE(FW_BLC_SELF,
4197                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4198
4199         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4200                       planea_wm, cursora_wm,
4201                       planeb_wm, cursorb_wm,
4202                       plane_sr, cursor_sr);
4203
4204         I915_WRITE(DSPFW1,
4205                    (plane_sr << DSPFW_SR_SHIFT) |
4206                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4207                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
4208                    planea_wm);
4209         I915_WRITE(DSPFW2,
4210                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4211                    (cursora_wm << DSPFW_CURSORA_SHIFT));
4212         /* HPLL off in SR has some issues on G4x... disable it */
4213         I915_WRITE(DSPFW3,
4214                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4215                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4216 }
4217
4218 static void i965_update_wm(struct drm_device *dev)
4219 {
4220         struct drm_i915_private *dev_priv = dev->dev_private;
4221         struct drm_crtc *crtc;
4222         int srwm = 1;
4223         int cursor_sr = 16;
4224
4225         /* Calc sr entries for one plane configs */
4226         crtc = single_enabled_crtc(dev);
4227         if (crtc) {
4228                 /* self-refresh has much higher latency */
4229                 static const int sr_latency_ns = 12000;
4230                 int clock = crtc->mode.clock;
4231                 int htotal = crtc->mode.htotal;
4232                 int hdisplay = crtc->mode.hdisplay;
4233                 int pixel_size = crtc->fb->bits_per_pixel / 8;
4234                 unsigned long line_time_us;
4235                 int entries;
4236
4237                 line_time_us = ((htotal * 1000) / clock);
4238
4239                 /* Use ns/us then divide to preserve precision */
4240                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4241                         pixel_size * hdisplay;
4242                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4243                 srwm = I965_FIFO_SIZE - entries;
4244                 if (srwm < 0)
4245                         srwm = 1;
4246                 srwm &= 0x1ff;
4247                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4248                               entries, srwm);
4249
4250                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4251                         pixel_size * 64;
4252                 entries = DIV_ROUND_UP(entries,
4253                                           i965_cursor_wm_info.cacheline_size);
4254                 cursor_sr = i965_cursor_wm_info.fifo_size -
4255                         (entries + i965_cursor_wm_info.guard_size);
4256
4257                 if (cursor_sr > i965_cursor_wm_info.max_wm)
4258                         cursor_sr = i965_cursor_wm_info.max_wm;
4259
4260                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4261                               "cursor %d\n", srwm, cursor_sr);
4262
4263                 if (IS_CRESTLINE(dev))
4264                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4265         } else {
4266                 /* Turn off self refresh if both pipes are enabled */
4267                 if (IS_CRESTLINE(dev))
4268                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4269                                    & ~FW_BLC_SELF_EN);
4270         }
4271
4272         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4273                       srwm);
4274
4275         /* 965 has limitations... */
4276         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4277                    (8 << 16) | (8 << 8) | (8 << 0));
4278         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4279         /* update cursor SR watermark */
4280         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4281 }
4282
4283 static void i9xx_update_wm(struct drm_device *dev)
4284 {
4285         struct drm_i915_private *dev_priv = dev->dev_private;
4286         const struct intel_watermark_params *wm_info;
4287         uint32_t fwater_lo;
4288         uint32_t fwater_hi;
4289         int cwm, srwm = 1;
4290         int fifo_size;
4291         int planea_wm, planeb_wm;
4292         struct drm_crtc *crtc, *enabled = NULL;
4293
4294         if (IS_I945GM(dev))
4295                 wm_info = &i945_wm_info;
4296         else if (!IS_GEN2(dev))
4297                 wm_info = &i915_wm_info;
4298         else
4299                 wm_info = &i855_wm_info;
4300
4301         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4302         crtc = intel_get_crtc_for_plane(dev, 0);
4303         if (crtc->enabled && crtc->fb) {
4304                 planea_wm = intel_calculate_wm(crtc->mode.clock,
4305                                                wm_info, fifo_size,
4306                                                crtc->fb->bits_per_pixel / 8,
4307                                                latency_ns);
4308                 enabled = crtc;
4309         } else
4310                 planea_wm = fifo_size - wm_info->guard_size;
4311
4312         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4313         crtc = intel_get_crtc_for_plane(dev, 1);
4314         if (crtc->enabled && crtc->fb) {
4315                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4316                                                wm_info, fifo_size,
4317                                                crtc->fb->bits_per_pixel / 8,
4318                                                latency_ns);
4319                 if (enabled == NULL)
4320                         enabled = crtc;
4321                 else
4322                         enabled = NULL;
4323         } else
4324                 planeb_wm = fifo_size - wm_info->guard_size;
4325
4326         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4327
4328         /*
4329          * Overlay gets an aggressive default since video jitter is bad.
4330          */
4331         cwm = 2;
4332
4333         /* Play safe and disable self-refresh before adjusting watermarks. */
4334         if (IS_I945G(dev) || IS_I945GM(dev))
4335                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4336         else if (IS_I915GM(dev))
4337                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4338
4339         /* Calc sr entries for one plane configs */
4340         if (HAS_FW_BLC(dev) && enabled) {
4341                 /* self-refresh has much higher latency */
4342                 static const int sr_latency_ns = 6000;
4343                 int clock = enabled->mode.clock;
4344                 int htotal = enabled->mode.htotal;
4345                 int hdisplay = enabled->mode.hdisplay;
4346                 int pixel_size = enabled->fb->bits_per_pixel / 8;
4347                 unsigned long line_time_us;
4348                 int entries;
4349
4350                 line_time_us = (htotal * 1000) / clock;
4351
4352                 /* Use ns/us then divide to preserve precision */
4353                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4354                         pixel_size * hdisplay;
4355                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4356                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4357                 srwm = wm_info->fifo_size - entries;
4358                 if (srwm < 0)
4359                         srwm = 1;
4360
4361                 if (IS_I945G(dev) || IS_I945GM(dev))
4362                         I915_WRITE(FW_BLC_SELF,
4363                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4364                 else if (IS_I915GM(dev))
4365                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4366         }
4367
4368         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4369                       planea_wm, planeb_wm, cwm, srwm);
4370
4371         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4372         fwater_hi = (cwm & 0x1f);
4373
4374         /* Set request length to 8 cachelines per fetch */
4375         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4376         fwater_hi = fwater_hi | (1 << 8);
4377
4378         I915_WRITE(FW_BLC, fwater_lo);
4379         I915_WRITE(FW_BLC2, fwater_hi);
4380
4381         if (HAS_FW_BLC(dev)) {
4382                 if (enabled) {
4383                         if (IS_I945G(dev) || IS_I945GM(dev))
4384                                 I915_WRITE(FW_BLC_SELF,
4385                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4386                         else if (IS_I915GM(dev))
4387                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4388                         DRM_DEBUG_KMS("memory self refresh enabled\n");
4389                 } else
4390                         DRM_DEBUG_KMS("memory self refresh disabled\n");
4391         }
4392 }
4393
4394 static void i830_update_wm(struct drm_device *dev)
4395 {
4396         struct drm_i915_private *dev_priv = dev->dev_private;
4397         struct drm_crtc *crtc;
4398         uint32_t fwater_lo;
4399         int planea_wm;
4400
4401         crtc = single_enabled_crtc(dev);
4402         if (crtc == NULL)
4403                 return;
4404
4405         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4406                                        dev_priv->display.get_fifo_size(dev, 0),
4407                                        crtc->fb->bits_per_pixel / 8,
4408                                        latency_ns);
4409         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4410         fwater_lo |= (3<<8) | planea_wm;
4411
4412         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4413
4414         I915_WRITE(FW_BLC, fwater_lo);
4415 }
4416
4417 #define ILK_LP0_PLANE_LATENCY           700
4418 #define ILK_LP0_CURSOR_LATENCY          1300
4419
4420 /*
4421  * Check the wm result.
4422  *
4423  * If any calculated watermark values is larger than the maximum value that
4424  * can be programmed into the associated watermark register, that watermark
4425  * must be disabled.
4426  */
4427 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4428                                 int fbc_wm, int display_wm, int cursor_wm,
4429                                 const struct intel_watermark_params *display,
4430                                 const struct intel_watermark_params *cursor)
4431 {
4432         struct drm_i915_private *dev_priv = dev->dev_private;
4433
4434         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4435                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4436
4437         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4438                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4439                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4440
4441                 /* fbc has it's own way to disable FBC WM */
4442                 I915_WRITE(DISP_ARB_CTL,
4443                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4444                 return false;
4445         }
4446
4447         if (display_wm > display->max_wm) {
4448                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4449                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4450                 return false;
4451         }
4452
4453         if (cursor_wm > cursor->max_wm) {
4454                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4455                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4456                 return false;
4457         }
4458
4459         if (!(fbc_wm || display_wm || cursor_wm)) {
4460                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4461                 return false;
4462         }
4463
4464         return true;
4465 }
4466
4467 /*
4468  * Compute watermark values of WM[1-3],
4469  */
4470 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4471                                   int latency_ns,
4472                                   const struct intel_watermark_params *display,
4473                                   const struct intel_watermark_params *cursor,
4474                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4475 {
4476         struct drm_crtc *crtc;
4477         unsigned long line_time_us;
4478         int hdisplay, htotal, pixel_size, clock;
4479         int line_count, line_size;
4480         int small, large;
4481         int entries;
4482
4483         if (!latency_ns) {
4484                 *fbc_wm = *display_wm = *cursor_wm = 0;
4485                 return false;
4486         }
4487
4488         crtc = intel_get_crtc_for_plane(dev, plane);
4489         hdisplay = crtc->mode.hdisplay;
4490         htotal = crtc->mode.htotal;
4491         clock = crtc->mode.clock;
4492         pixel_size = crtc->fb->bits_per_pixel / 8;
4493
4494         line_time_us = (htotal * 1000) / clock;
4495         line_count = (latency_ns / line_time_us + 1000) / 1000;
4496         line_size = hdisplay * pixel_size;
4497
4498         /* Use the minimum of the small and large buffer method for primary */
4499         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4500         large = line_count * line_size;
4501
4502         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4503         *display_wm = entries + display->guard_size;
4504
4505         /*
4506          * Spec says:
4507          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4508          */
4509         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4510
4511         /* calculate the self-refresh watermark for display cursor */
4512         entries = line_count * pixel_size * 64;
4513         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4514         *cursor_wm = entries + cursor->guard_size;
4515
4516         return ironlake_check_srwm(dev, level,
4517                                    *fbc_wm, *display_wm, *cursor_wm,
4518                                    display, cursor);
4519 }
4520
4521 static void ironlake_update_wm(struct drm_device *dev)
4522 {
4523         struct drm_i915_private *dev_priv = dev->dev_private;
4524         int fbc_wm, plane_wm, cursor_wm;
4525         unsigned int enabled;
4526
4527         enabled = 0;
4528         if (g4x_compute_wm0(dev, 0,
4529                             &ironlake_display_wm_info,
4530                             ILK_LP0_PLANE_LATENCY,
4531                             &ironlake_cursor_wm_info,
4532                             ILK_LP0_CURSOR_LATENCY,
4533                             &plane_wm, &cursor_wm)) {
4534                 I915_WRITE(WM0_PIPEA_ILK,
4535                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4536                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4537                               " plane %d, " "cursor: %d\n",
4538                               plane_wm, cursor_wm);
4539                 enabled |= 1;
4540         }
4541
4542         if (g4x_compute_wm0(dev, 1,
4543                             &ironlake_display_wm_info,
4544                             ILK_LP0_PLANE_LATENCY,
4545                             &ironlake_cursor_wm_info,
4546                             ILK_LP0_CURSOR_LATENCY,
4547                             &plane_wm, &cursor_wm)) {
4548                 I915_WRITE(WM0_PIPEB_ILK,
4549                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4550                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4551                               " plane %d, cursor: %d\n",
4552                               plane_wm, cursor_wm);
4553                 enabled |= 2;
4554         }
4555
4556         /*
4557          * Calculate and update the self-refresh watermark only when one
4558          * display plane is used.
4559          */
4560         I915_WRITE(WM3_LP_ILK, 0);
4561         I915_WRITE(WM2_LP_ILK, 0);
4562         I915_WRITE(WM1_LP_ILK, 0);
4563
4564         if (!single_plane_enabled(enabled))
4565                 return;
4566         enabled = ffs(enabled) - 1;
4567
4568         /* WM1 */
4569         if (!ironlake_compute_srwm(dev, 1, enabled,
4570                                    ILK_READ_WM1_LATENCY() * 500,
4571                                    &ironlake_display_srwm_info,
4572                                    &ironlake_cursor_srwm_info,
4573                                    &fbc_wm, &plane_wm, &cursor_wm))
4574                 return;
4575
4576         I915_WRITE(WM1_LP_ILK,
4577                    WM1_LP_SR_EN |
4578                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4579                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4580                    (plane_wm << WM1_LP_SR_SHIFT) |
4581                    cursor_wm);
4582
4583         /* WM2 */
4584         if (!ironlake_compute_srwm(dev, 2, enabled,
4585                                    ILK_READ_WM2_LATENCY() * 500,
4586                                    &ironlake_display_srwm_info,
4587                                    &ironlake_cursor_srwm_info,
4588                                    &fbc_wm, &plane_wm, &cursor_wm))
4589                 return;
4590
4591         I915_WRITE(WM2_LP_ILK,
4592                    WM2_LP_EN |
4593                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4594                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4595                    (plane_wm << WM1_LP_SR_SHIFT) |
4596                    cursor_wm);
4597
4598         /*
4599          * WM3 is unsupported on ILK, probably because we don't have latency
4600          * data for that power state
4601          */
4602 }
4603
4604 void sandybridge_update_wm(struct drm_device *dev)
4605 {
4606         struct drm_i915_private *dev_priv = dev->dev_private;
4607         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4608         u32 val;
4609         int fbc_wm, plane_wm, cursor_wm;
4610         unsigned int enabled;
4611
4612         enabled = 0;
4613         if (g4x_compute_wm0(dev, 0,
4614                             &sandybridge_display_wm_info, latency,
4615                             &sandybridge_cursor_wm_info, latency,
4616                             &plane_wm, &cursor_wm)) {
4617                 val = I915_READ(WM0_PIPEA_ILK);
4618                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4619                 I915_WRITE(WM0_PIPEA_ILK, val |
4620                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4621                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4622                               " plane %d, " "cursor: %d\n",
4623                               plane_wm, cursor_wm);
4624                 enabled |= 1;
4625         }
4626
4627         if (g4x_compute_wm0(dev, 1,
4628                             &sandybridge_display_wm_info, latency,
4629                             &sandybridge_cursor_wm_info, latency,
4630                             &plane_wm, &cursor_wm)) {
4631                 val = I915_READ(WM0_PIPEB_ILK);
4632                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4633                 I915_WRITE(WM0_PIPEB_ILK, val |
4634                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4635                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4636                               " plane %d, cursor: %d\n",
4637                               plane_wm, cursor_wm);
4638                 enabled |= 2;
4639         }
4640
4641         /* IVB has 3 pipes */
4642         if (IS_IVYBRIDGE(dev) &&
4643             g4x_compute_wm0(dev, 2,
4644                             &sandybridge_display_wm_info, latency,
4645                             &sandybridge_cursor_wm_info, latency,
4646                             &plane_wm, &cursor_wm)) {
4647                 val = I915_READ(WM0_PIPEC_IVB);
4648                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4649                 I915_WRITE(WM0_PIPEC_IVB, val |
4650                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4651                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4652                               " plane %d, cursor: %d\n",
4653                               plane_wm, cursor_wm);
4654                 enabled |= 3;
4655         }
4656
4657         /*
4658          * Calculate and update the self-refresh watermark only when one
4659          * display plane is used.
4660          *
4661          * SNB support 3 levels of watermark.
4662          *
4663          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4664          * and disabled in the descending order
4665          *
4666          */
4667         I915_WRITE(WM3_LP_ILK, 0);
4668         I915_WRITE(WM2_LP_ILK, 0);
4669         I915_WRITE(WM1_LP_ILK, 0);
4670
4671         if (!single_plane_enabled(enabled) ||
4672             dev_priv->sprite_scaling_enabled)
4673                 return;
4674         enabled = ffs(enabled) - 1;
4675
4676         /* WM1 */
4677         if (!ironlake_compute_srwm(dev, 1, enabled,
4678                                    SNB_READ_WM1_LATENCY() * 500,
4679                                    &sandybridge_display_srwm_info,
4680                                    &sandybridge_cursor_srwm_info,
4681                                    &fbc_wm, &plane_wm, &cursor_wm))
4682                 return;
4683
4684         I915_WRITE(WM1_LP_ILK,
4685                    WM1_LP_SR_EN |
4686                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4687                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4688                    (plane_wm << WM1_LP_SR_SHIFT) |
4689                    cursor_wm);
4690
4691         /* WM2 */
4692         if (!ironlake_compute_srwm(dev, 2, enabled,
4693                                    SNB_READ_WM2_LATENCY() * 500,
4694                                    &sandybridge_display_srwm_info,
4695                                    &sandybridge_cursor_srwm_info,
4696                                    &fbc_wm, &plane_wm, &cursor_wm))
4697                 return;
4698
4699         I915_WRITE(WM2_LP_ILK,
4700                    WM2_LP_EN |
4701                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4702                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4703                    (plane_wm << WM1_LP_SR_SHIFT) |
4704                    cursor_wm);
4705
4706         /* WM3 */
4707         if (!ironlake_compute_srwm(dev, 3, enabled,
4708                                    SNB_READ_WM3_LATENCY() * 500,
4709                                    &sandybridge_display_srwm_info,
4710                                    &sandybridge_cursor_srwm_info,
4711                                    &fbc_wm, &plane_wm, &cursor_wm))
4712                 return;
4713
4714         I915_WRITE(WM3_LP_ILK,
4715                    WM3_LP_EN |
4716                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4717                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4718                    (plane_wm << WM1_LP_SR_SHIFT) |
4719                    cursor_wm);
4720 }
4721
4722 static bool
4723 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4724                               uint32_t sprite_width, int pixel_size,
4725                               const struct intel_watermark_params *display,
4726                               int display_latency_ns, int *sprite_wm)
4727 {
4728         struct drm_crtc *crtc;
4729         int clock;
4730         int entries, tlb_miss;
4731
4732         crtc = intel_get_crtc_for_plane(dev, plane);
4733         if (crtc->fb == NULL || !crtc->enabled) {
4734                 *sprite_wm = display->guard_size;
4735                 return false;
4736         }
4737
4738         clock = crtc->mode.clock;
4739
4740         /* Use the small buffer method to calculate the sprite watermark */
4741         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4742         tlb_miss = display->fifo_size*display->cacheline_size -
4743                 sprite_width * 8;
4744         if (tlb_miss > 0)
4745                 entries += tlb_miss;
4746         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4747         *sprite_wm = entries + display->guard_size;
4748         if (*sprite_wm > (int)display->max_wm)
4749                 *sprite_wm = display->max_wm;
4750
4751         return true;
4752 }
4753
4754 static bool
4755 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4756                                 uint32_t sprite_width, int pixel_size,
4757                                 const struct intel_watermark_params *display,
4758                                 int latency_ns, int *sprite_wm)
4759 {
4760         struct drm_crtc *crtc;
4761         unsigned long line_time_us;
4762         int clock;
4763         int line_count, line_size;
4764         int small, large;
4765         int entries;
4766
4767         if (!latency_ns) {
4768                 *sprite_wm = 0;
4769                 return false;
4770         }
4771
4772         crtc = intel_get_crtc_for_plane(dev, plane);
4773         clock = crtc->mode.clock;
4774         if (!clock) {
4775                 *sprite_wm = 0;
4776                 return false;
4777         }
4778
4779         line_time_us = (sprite_width * 1000) / clock;
4780         if (!line_time_us) {
4781                 *sprite_wm = 0;
4782                 return false;
4783         }
4784
4785         line_count = (latency_ns / line_time_us + 1000) / 1000;
4786         line_size = sprite_width * pixel_size;
4787
4788         /* Use the minimum of the small and large buffer method for primary */
4789         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4790         large = line_count * line_size;
4791
4792         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4793         *sprite_wm = entries + display->guard_size;
4794
4795         return *sprite_wm > 0x3ff ? false : true;
4796 }
4797
4798 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4799                                          uint32_t sprite_width, int pixel_size)
4800 {
4801         struct drm_i915_private *dev_priv = dev->dev_private;
4802         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4803         u32 val;
4804         int sprite_wm, reg;
4805         int ret;
4806
4807         switch (pipe) {
4808         case 0:
4809                 reg = WM0_PIPEA_ILK;
4810                 break;
4811         case 1:
4812                 reg = WM0_PIPEB_ILK;
4813                 break;
4814         case 2:
4815                 reg = WM0_PIPEC_IVB;
4816                 break;
4817         default:
4818                 return; /* bad pipe */
4819         }
4820
4821         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4822                                             &sandybridge_display_wm_info,
4823                                             latency, &sprite_wm);
4824         if (!ret) {
4825                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4826                               pipe);
4827                 return;
4828         }
4829
4830         val = I915_READ(reg);
4831         val &= ~WM0_PIPE_SPRITE_MASK;
4832         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
4833         DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4834
4835
4836         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4837                                               pixel_size,
4838                                               &sandybridge_display_srwm_info,
4839                                               SNB_READ_WM1_LATENCY() * 500,
4840                                               &sprite_wm);
4841         if (!ret) {
4842                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4843                               pipe);
4844                 return;
4845         }
4846         I915_WRITE(WM1S_LP_ILK, sprite_wm);
4847
4848         /* Only IVB has two more LP watermarks for sprite */
4849         if (!IS_IVYBRIDGE(dev))
4850                 return;
4851
4852         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4853                                               pixel_size,
4854                                               &sandybridge_display_srwm_info,
4855                                               SNB_READ_WM2_LATENCY() * 500,
4856                                               &sprite_wm);
4857         if (!ret) {
4858                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4859                               pipe);
4860                 return;
4861         }
4862         I915_WRITE(WM2S_LP_IVB, sprite_wm);
4863
4864         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4865                                               pixel_size,
4866                                               &sandybridge_display_srwm_info,
4867                                               SNB_READ_WM3_LATENCY() * 500,
4868                                               &sprite_wm);
4869         if (!ret) {
4870                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4871                               pipe);
4872                 return;
4873         }
4874         I915_WRITE(WM3S_LP_IVB, sprite_wm);
4875 }
4876
4877 /**
4878  * intel_update_watermarks - update FIFO watermark values based on current modes
4879  *
4880  * Calculate watermark values for the various WM regs based on current mode
4881  * and plane configuration.
4882  *
4883  * There are several cases to deal with here:
4884  *   - normal (i.e. non-self-refresh)
4885  *   - self-refresh (SR) mode
4886  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4887  *   - lines are small relative to FIFO size (buffer can hold more than 2
4888  *     lines), so need to account for TLB latency
4889  *
4890  *   The normal calculation is:
4891  *     watermark = dotclock * bytes per pixel * latency
4892  *   where latency is platform & configuration dependent (we assume pessimal
4893  *   values here).
4894  *
4895  *   The SR calculation is:
4896  *     watermark = (trunc(latency/line time)+1) * surface width *
4897  *       bytes per pixel
4898  *   where
4899  *     line time = htotal / dotclock
4900  *     surface width = hdisplay for normal plane and 64 for cursor
4901  *   and latency is assumed to be high, as above.
4902  *
4903  * The final value programmed to the register should always be rounded up,
4904  * and include an extra 2 entries to account for clock crossings.
4905  *
4906  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4907  * to set the non-SR watermarks to 8.
4908  */
4909 static void intel_update_watermarks(struct drm_device *dev)
4910 {
4911         struct drm_i915_private *dev_priv = dev->dev_private;
4912
4913         if (dev_priv->display.update_wm)
4914                 dev_priv->display.update_wm(dev);
4915 }
4916
4917 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4918                                     uint32_t sprite_width, int pixel_size)
4919 {
4920         struct drm_i915_private *dev_priv = dev->dev_private;
4921
4922         if (dev_priv->display.update_sprite_wm)
4923                 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4924                                                    pixel_size);
4925 }
4926
4927 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4928 {
4929         if (i915_panel_use_ssc >= 0)
4930                 return i915_panel_use_ssc != 0;
4931         return dev_priv->lvds_use_ssc
4932                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4933 }
4934
4935 /**
4936  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4937  * @crtc: CRTC structure
4938  * @mode: requested mode
4939  *
4940  * A pipe may be connected to one or more outputs.  Based on the depth of the
4941  * attached framebuffer, choose a good color depth to use on the pipe.
4942  *
4943  * If possible, match the pipe depth to the fb depth.  In some cases, this
4944  * isn't ideal, because the connected output supports a lesser or restricted
4945  * set of depths.  Resolve that here:
4946  *    LVDS typically supports only 6bpc, so clamp down in that case
4947  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4948  *    Displays may support a restricted set as well, check EDID and clamp as
4949  *      appropriate.
4950  *    DP may want to dither down to 6bpc to fit larger modes
4951  *
4952  * RETURNS:
4953  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4954  * true if they don't match).
4955  */
4956 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4957                                          unsigned int *pipe_bpp,
4958                                          struct drm_display_mode *mode)
4959 {
4960         struct drm_device *dev = crtc->dev;
4961         struct drm_i915_private *dev_priv = dev->dev_private;
4962         struct drm_encoder *encoder;
4963         struct drm_connector *connector;
4964         unsigned int display_bpc = UINT_MAX, bpc;
4965
4966         /* Walk the encoders & connectors on this crtc, get min bpc */
4967         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4968                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4969
4970                 if (encoder->crtc != crtc)
4971                         continue;
4972
4973                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4974                         unsigned int lvds_bpc;
4975
4976                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4977                             LVDS_A3_POWER_UP)
4978                                 lvds_bpc = 8;
4979                         else
4980                                 lvds_bpc = 6;
4981
4982                         if (lvds_bpc < display_bpc) {
4983                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4984                                 display_bpc = lvds_bpc;
4985                         }
4986                         continue;
4987                 }
4988
4989                 /* Not one of the known troublemakers, check the EDID */
4990                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4991                                     head) {
4992                         if (connector->encoder != encoder)
4993                                 continue;
4994
4995                         /* Don't use an invalid EDID bpc value */
4996                         if (connector->display_info.bpc &&
4997                             connector->display_info.bpc < display_bpc) {
4998                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4999                                 display_bpc = connector->display_info.bpc;
5000                         }
5001                 }
5002
5003                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
5004                         /* Use VBT settings if we have an eDP panel */
5005                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
5006
5007                         if (edp_bpc && edp_bpc < display_bpc) {
5008                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5009                                 display_bpc = edp_bpc;
5010                         }
5011                         continue;
5012                 }
5013
5014                 /*
5015                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
5016                  * through, clamp it down.  (Note: >12bpc will be caught below.)
5017                  */
5018                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
5019                         if (display_bpc > 8 && display_bpc < 12) {
5020                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5021                                 display_bpc = 12;
5022                         } else {
5023                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5024                                 display_bpc = 8;
5025                         }
5026                 }
5027         }
5028
5029         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5030                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
5031                 display_bpc = 6;
5032         }
5033
5034         /*
5035          * We could just drive the pipe at the highest bpc all the time and
5036          * enable dithering as needed, but that costs bandwidth.  So choose
5037          * the minimum value that expresses the full color range of the fb but
5038          * also stays within the max display bpc discovered above.
5039          */
5040
5041         switch (crtc->fb->depth) {
5042         case 8:
5043                 bpc = 8; /* since we go through a colormap */
5044                 break;
5045         case 15:
5046         case 16:
5047                 bpc = 6; /* min is 18bpp */
5048                 break;
5049         case 24:
5050                 bpc = 8;
5051                 break;
5052         case 30:
5053                 bpc = 10;
5054                 break;
5055         case 48:
5056                 bpc = 12;
5057                 break;
5058         default:
5059                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
5060                 bpc = min((unsigned int)8, display_bpc);
5061                 break;
5062         }
5063
5064         display_bpc = min(display_bpc, bpc);
5065
5066         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
5067                       bpc, display_bpc);
5068
5069         *pipe_bpp = display_bpc * 3;
5070
5071         return display_bpc != bpc;
5072 }
5073
5074 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5075 {
5076         struct drm_device *dev = crtc->dev;
5077         struct drm_i915_private *dev_priv = dev->dev_private;
5078         int refclk;
5079
5080         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5081             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5082                 refclk = dev_priv->lvds_ssc_freq * 1000;
5083                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5084                               refclk / 1000);
5085         } else if (!IS_GEN2(dev)) {
5086                 refclk = 96000;
5087         } else {
5088                 refclk = 48000;
5089         }
5090
5091         return refclk;
5092 }
5093
5094 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5095                                       intel_clock_t *clock)
5096 {
5097         /* SDVO TV has fixed PLL values depend on its clock range,
5098            this mirrors vbios setting. */
5099         if (adjusted_mode->clock >= 100000
5100             && adjusted_mode->clock < 140500) {
5101                 clock->p1 = 2;
5102                 clock->p2 = 10;
5103                 clock->n = 3;
5104                 clock->m1 = 16;
5105                 clock->m2 = 8;
5106         } else if (adjusted_mode->clock >= 140500
5107                    && adjusted_mode->clock <= 200000) {
5108                 clock->p1 = 1;
5109                 clock->p2 = 10;
5110                 clock->n = 6;
5111                 clock->m1 = 12;
5112                 clock->m2 = 8;
5113         }
5114 }
5115
5116 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5117                                      intel_clock_t *clock,
5118                                      intel_clock_t *reduced_clock)
5119 {
5120         struct drm_device *dev = crtc->dev;
5121         struct drm_i915_private *dev_priv = dev->dev_private;
5122         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5123         int pipe = intel_crtc->pipe;
5124         u32 fp, fp2 = 0;
5125
5126         if (IS_PINEVIEW(dev)) {
5127                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5128                 if (reduced_clock)
5129                         fp2 = (1 << reduced_clock->n) << 16 |
5130                                 reduced_clock->m1 << 8 | reduced_clock->m2;
5131         } else {
5132                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5133                 if (reduced_clock)
5134                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5135                                 reduced_clock->m2;
5136         }
5137
5138         I915_WRITE(FP0(pipe), fp);
5139
5140         intel_crtc->lowfreq_avail = false;
5141         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5142             reduced_clock && i915_powersave) {
5143                 I915_WRITE(FP1(pipe), fp2);
5144                 intel_crtc->lowfreq_avail = true;
5145         } else {
5146                 I915_WRITE(FP1(pipe), fp);
5147         }
5148 }
5149
5150 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5151                               struct drm_display_mode *mode,
5152                               struct drm_display_mode *adjusted_mode,
5153                               int x, int y,
5154                               struct drm_framebuffer *old_fb)
5155 {
5156         struct drm_device *dev = crtc->dev;
5157         struct drm_i915_private *dev_priv = dev->dev_private;
5158         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5159         int pipe = intel_crtc->pipe;
5160         int plane = intel_crtc->plane;
5161         int refclk, num_connectors = 0;
5162         intel_clock_t clock, reduced_clock;
5163         u32 dpll, dspcntr, pipeconf, vsyncshift;
5164         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
5165         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5166         struct drm_mode_config *mode_config = &dev->mode_config;
5167         struct intel_encoder *encoder;
5168         const intel_limit_t *limit;
5169         int ret;
5170         u32 temp;
5171         u32 lvds_sync = 0;
5172
5173         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5174                 if (encoder->base.crtc != crtc)
5175                         continue;
5176
5177                 switch (encoder->type) {
5178                 case INTEL_OUTPUT_LVDS:
5179                         is_lvds = true;
5180                         break;
5181                 case INTEL_OUTPUT_SDVO:
5182                 case INTEL_OUTPUT_HDMI:
5183                         is_sdvo = true;
5184                         if (encoder->needs_tv_clock)
5185                                 is_tv = true;
5186                         break;
5187                 case INTEL_OUTPUT_DVO:
5188                         is_dvo = true;
5189                         break;
5190                 case INTEL_OUTPUT_TVOUT:
5191                         is_tv = true;
5192                         break;
5193                 case INTEL_OUTPUT_ANALOG:
5194                         is_crt = true;
5195                         break;
5196                 case INTEL_OUTPUT_DISPLAYPORT:
5197                         is_dp = true;
5198                         break;
5199                 }
5200
5201                 num_connectors++;
5202         }
5203
5204         refclk = i9xx_get_refclk(crtc, num_connectors);
5205
5206         /*
5207          * Returns a set of divisors for the desired target clock with the given
5208          * refclk, or FALSE.  The returned values represent the clock equation:
5209          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5210          */
5211         limit = intel_limit(crtc, refclk);
5212         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5213                              &clock);
5214         if (!ok) {
5215                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5216                 return -EINVAL;
5217         }
5218
5219         /* Ensure that the cursor is valid for the new mode before changing... */
5220         intel_crtc_update_cursor(crtc, true);
5221
5222         if (is_lvds && dev_priv->lvds_downclock_avail) {
5223                 /*
5224                  * Ensure we match the reduced clock's P to the target clock.
5225                  * If the clocks don't match, we can't switch the display clock
5226                  * by using the FP0/FP1. In such case we will disable the LVDS
5227                  * downclock feature.
5228                 */
5229                 has_reduced_clock = limit->find_pll(limit, crtc,
5230                                                     dev_priv->lvds_downclock,
5231                                                     refclk,
5232                                                     &clock,
5233                                                     &reduced_clock);
5234         }
5235
5236         if (is_sdvo && is_tv)
5237                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
5238
5239         i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5240                                  &reduced_clock : NULL);
5241
5242         dpll = DPLL_VGA_MODE_DIS;
5243
5244         if (!IS_GEN2(dev)) {
5245                 if (is_lvds)
5246                         dpll |= DPLLB_MODE_LVDS;
5247                 else
5248                         dpll |= DPLLB_MODE_DAC_SERIAL;
5249                 if (is_sdvo) {
5250                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5251                         if (pixel_multiplier > 1) {
5252                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5253                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
5254                         }
5255                         dpll |= DPLL_DVO_HIGH_SPEED;
5256                 }
5257                 if (is_dp)
5258                         dpll |= DPLL_DVO_HIGH_SPEED;
5259
5260                 /* compute bitmask from p1 value */
5261                 if (IS_PINEVIEW(dev))
5262                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5263                 else {
5264                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5265                         if (IS_G4X(dev) && has_reduced_clock)
5266                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5267                 }
5268                 switch (clock.p2) {
5269                 case 5:
5270                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5271                         break;
5272                 case 7:
5273                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5274                         break;
5275                 case 10:
5276                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5277                         break;
5278                 case 14:
5279                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5280                         break;
5281                 }
5282                 if (INTEL_INFO(dev)->gen >= 4)
5283                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5284         } else {
5285                 if (is_lvds) {
5286                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5287                 } else {
5288                         if (clock.p1 == 2)
5289                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
5290                         else
5291                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5292                         if (clock.p2 == 4)
5293                                 dpll |= PLL_P2_DIVIDE_BY_4;
5294                 }
5295         }
5296
5297         if (is_sdvo && is_tv)
5298                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5299         else if (is_tv)
5300                 /* XXX: just matching BIOS for now */
5301                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5302                 dpll |= 3;
5303         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5304                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5305         else
5306                 dpll |= PLL_REF_INPUT_DREFCLK;
5307
5308         /* setup pipeconf */
5309         pipeconf = I915_READ(PIPECONF(pipe));
5310
5311         /* Set up the display plane register */
5312         dspcntr = DISPPLANE_GAMMA_ENABLE;
5313
5314         if (pipe == 0)
5315                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5316         else
5317                 dspcntr |= DISPPLANE_SEL_PIPE_B;
5318
5319         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5320                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5321                  * core speed.
5322                  *
5323                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5324                  * pipe == 0 check?
5325                  */
5326                 if (mode->clock >
5327                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5328                         pipeconf |= PIPECONF_DOUBLE_WIDE;
5329                 else
5330                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5331         }
5332
5333         /* default to 8bpc */
5334         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5335         if (is_dp) {
5336                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5337                         pipeconf |= PIPECONF_BPP_6 |
5338                                     PIPECONF_DITHER_EN |
5339                                     PIPECONF_DITHER_TYPE_SP;
5340                 }
5341         }
5342
5343         dpll |= DPLL_VCO_ENABLE;
5344
5345         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5346         drm_mode_debug_printmodeline(mode);
5347
5348         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5349
5350         POSTING_READ(DPLL(pipe));
5351         udelay(150);
5352
5353         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5354          * This is an exception to the general rule that mode_set doesn't turn
5355          * things on.
5356          */
5357         if (is_lvds) {
5358                 temp = I915_READ(LVDS);
5359                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5360                 if (pipe == 1) {
5361                         temp |= LVDS_PIPEB_SELECT;
5362                 } else {
5363                         temp &= ~LVDS_PIPEB_SELECT;
5364                 }
5365                 /* set the corresponsding LVDS_BORDER bit */
5366                 temp |= dev_priv->lvds_border_bits;
5367                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5368                  * set the DPLLs for dual-channel mode or not.
5369                  */
5370                 if (clock.p2 == 7)
5371                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5372                 else
5373                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5374
5375                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5376                  * appropriately here, but we need to look more thoroughly into how
5377                  * panels behave in the two modes.
5378                  */
5379                 /* set the dithering flag on LVDS as needed */
5380                 if (INTEL_INFO(dev)->gen >= 4) {
5381                         if (dev_priv->lvds_dither)
5382                                 temp |= LVDS_ENABLE_DITHER;
5383                         else
5384                                 temp &= ~LVDS_ENABLE_DITHER;
5385                 }
5386                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5387                         lvds_sync |= LVDS_HSYNC_POLARITY;
5388                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5389                         lvds_sync |= LVDS_VSYNC_POLARITY;
5390                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5391                     != lvds_sync) {
5392                         char flags[2] = "-+";
5393                         DRM_INFO("Changing LVDS panel from "
5394                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5395                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5396                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5397                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5398                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5399                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5400                         temp |= lvds_sync;
5401                 }
5402                 I915_WRITE(LVDS, temp);
5403         }
5404
5405         if (is_dp) {
5406                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5407         }
5408
5409         I915_WRITE(DPLL(pipe), dpll);
5410
5411         /* Wait for the clocks to stabilize. */
5412         POSTING_READ(DPLL(pipe));
5413         udelay(150);
5414
5415         if (INTEL_INFO(dev)->gen >= 4) {
5416                 temp = 0;
5417                 if (is_sdvo) {
5418                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5419                         if (temp > 1)
5420                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5421                         else
5422                                 temp = 0;
5423                 }
5424                 I915_WRITE(DPLL_MD(pipe), temp);
5425         } else {
5426                 /* The pixel multiplier can only be updated once the
5427                  * DPLL is enabled and the clocks are stable.
5428                  *
5429                  * So write it again.
5430                  */
5431                 I915_WRITE(DPLL(pipe), dpll);
5432         }
5433
5434         if (HAS_PIPE_CXSR(dev)) {
5435                 if (intel_crtc->lowfreq_avail) {
5436                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5437                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5438                 } else {
5439                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5440                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5441                 }
5442         }
5443
5444         pipeconf &= ~PIPECONF_INTERLACE_MASK;
5445         if (!IS_GEN2(dev) &&
5446             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5447                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5448                 /* the chip adds 2 halflines automatically */
5449                 adjusted_mode->crtc_vtotal -= 1;
5450                 adjusted_mode->crtc_vblank_end -= 1;
5451                 vsyncshift = adjusted_mode->crtc_hsync_start
5452                              - adjusted_mode->crtc_htotal/2;
5453         } else {
5454                 pipeconf |= PIPECONF_PROGRESSIVE;
5455                 vsyncshift = 0;
5456         }
5457
5458         if (!IS_GEN3(dev))
5459                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
5460
5461         I915_WRITE(HTOTAL(pipe),
5462                    (adjusted_mode->crtc_hdisplay - 1) |
5463                    ((adjusted_mode->crtc_htotal - 1) << 16));
5464         I915_WRITE(HBLANK(pipe),
5465                    (adjusted_mode->crtc_hblank_start - 1) |
5466                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5467         I915_WRITE(HSYNC(pipe),
5468                    (adjusted_mode->crtc_hsync_start - 1) |
5469                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5470
5471         I915_WRITE(VTOTAL(pipe),
5472                    (adjusted_mode->crtc_vdisplay - 1) |
5473                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5474         I915_WRITE(VBLANK(pipe),
5475                    (adjusted_mode->crtc_vblank_start - 1) |
5476                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5477         I915_WRITE(VSYNC(pipe),
5478                    (adjusted_mode->crtc_vsync_start - 1) |
5479                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5480
5481         /* pipesrc and dspsize control the size that is scaled from,
5482          * which should always be the user's requested size.
5483          */
5484         I915_WRITE(DSPSIZE(plane),
5485                    ((mode->vdisplay - 1) << 16) |
5486                    (mode->hdisplay - 1));
5487         I915_WRITE(DSPPOS(plane), 0);
5488         I915_WRITE(PIPESRC(pipe),
5489                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5490
5491         I915_WRITE(PIPECONF(pipe), pipeconf);
5492         POSTING_READ(PIPECONF(pipe));
5493         intel_enable_pipe(dev_priv, pipe, false);
5494
5495         intel_wait_for_vblank(dev, pipe);
5496
5497         I915_WRITE(DSPCNTR(plane), dspcntr);
5498         POSTING_READ(DSPCNTR(plane));
5499         intel_enable_plane(dev_priv, plane, pipe);
5500
5501         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5502
5503         intel_update_watermarks(dev);
5504
5505         return ret;
5506 }
5507
5508 /*
5509  * Initialize reference clocks when the driver loads
5510  */
5511 void ironlake_init_pch_refclk(struct drm_device *dev)
5512 {
5513         struct drm_i915_private *dev_priv = dev->dev_private;
5514         struct drm_mode_config *mode_config = &dev->mode_config;
5515         struct intel_encoder *encoder;
5516         u32 temp;
5517         bool has_lvds = false;
5518         bool has_cpu_edp = false;
5519         bool has_pch_edp = false;
5520         bool has_panel = false;
5521         bool has_ck505 = false;
5522         bool can_ssc = false;
5523
5524         /* We need to take the global config into account */
5525         list_for_each_entry(encoder, &mode_config->encoder_list,
5526                             base.head) {
5527                 switch (encoder->type) {
5528                 case INTEL_OUTPUT_LVDS:
5529                         has_panel = true;
5530                         has_lvds = true;
5531                         break;
5532                 case INTEL_OUTPUT_EDP:
5533                         has_panel = true;
5534                         if (intel_encoder_is_pch_edp(&encoder->base))
5535                                 has_pch_edp = true;
5536                         else
5537                                 has_cpu_edp = true;
5538                         break;
5539                 }
5540         }
5541
5542         if (HAS_PCH_IBX(dev)) {
5543                 has_ck505 = dev_priv->display_clock_mode;
5544                 can_ssc = has_ck505;
5545         } else {
5546                 has_ck505 = false;
5547                 can_ssc = true;
5548         }
5549
5550         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5551                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5552                       has_ck505);
5553
5554         /* Ironlake: try to setup display ref clock before DPLL
5555          * enabling. This is only under driver's control after
5556          * PCH B stepping, previous chipset stepping should be
5557          * ignoring this setting.
5558          */
5559         temp = I915_READ(PCH_DREF_CONTROL);
5560         /* Always enable nonspread source */
5561         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5562
5563         if (has_ck505)
5564                 temp |= DREF_NONSPREAD_CK505_ENABLE;
5565         else
5566                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5567
5568         if (has_panel) {
5569                 temp &= ~DREF_SSC_SOURCE_MASK;
5570                 temp |= DREF_SSC_SOURCE_ENABLE;
5571
5572                 /* SSC must be turned on before enabling the CPU output  */
5573                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5574                         DRM_DEBUG_KMS("Using SSC on panel\n");
5575                         temp |= DREF_SSC1_ENABLE;
5576                 } else
5577                         temp &= ~DREF_SSC1_ENABLE;
5578
5579                 /* Get SSC going before enabling the outputs */
5580                 I915_WRITE(PCH_DREF_CONTROL, temp);
5581                 POSTING_READ(PCH_DREF_CONTROL);
5582                 udelay(200);
5583
5584                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5585
5586                 /* Enable CPU source on CPU attached eDP */
5587                 if (has_cpu_edp) {
5588                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5589                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5590                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5591                         }
5592                         else
5593                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5594                 } else
5595                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5596
5597                 I915_WRITE(PCH_DREF_CONTROL, temp);
5598                 POSTING_READ(PCH_DREF_CONTROL);
5599                 udelay(200);
5600         } else {
5601                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5602
5603                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5604
5605                 /* Turn off CPU output */
5606                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5607
5608                 I915_WRITE(PCH_DREF_CONTROL, temp);
5609                 POSTING_READ(PCH_DREF_CONTROL);
5610                 udelay(200);
5611
5612                 /* Turn off the SSC source */
5613                 temp &= ~DREF_SSC_SOURCE_MASK;
5614                 temp |= DREF_SSC_SOURCE_DISABLE;
5615
5616                 /* Turn off SSC1 */
5617                 temp &= ~ DREF_SSC1_ENABLE;
5618
5619                 I915_WRITE(PCH_DREF_CONTROL, temp);
5620                 POSTING_READ(PCH_DREF_CONTROL);
5621                 udelay(200);
5622         }
5623 }
5624
5625 static int ironlake_get_refclk(struct drm_crtc *crtc)
5626 {
5627         struct drm_device *dev = crtc->dev;
5628         struct drm_i915_private *dev_priv = dev->dev_private;
5629         struct intel_encoder *encoder;
5630         struct drm_mode_config *mode_config = &dev->mode_config;
5631         struct intel_encoder *edp_encoder = NULL;
5632         int num_connectors = 0;
5633         bool is_lvds = false;
5634
5635         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5636                 if (encoder->base.crtc != crtc)
5637                         continue;
5638
5639                 switch (encoder->type) {
5640                 case INTEL_OUTPUT_LVDS:
5641                         is_lvds = true;
5642                         break;
5643                 case INTEL_OUTPUT_EDP:
5644                         edp_encoder = encoder;
5645                         break;
5646                 }
5647                 num_connectors++;
5648         }
5649
5650         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5651                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5652                               dev_priv->lvds_ssc_freq);
5653                 return dev_priv->lvds_ssc_freq * 1000;
5654         }
5655
5656         return 120000;
5657 }
5658
5659 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5660                                   struct drm_display_mode *mode,
5661                                   struct drm_display_mode *adjusted_mode,
5662                                   int x, int y,
5663                                   struct drm_framebuffer *old_fb)
5664 {
5665         struct drm_device *dev = crtc->dev;
5666         struct drm_i915_private *dev_priv = dev->dev_private;
5667         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5668         int pipe = intel_crtc->pipe;
5669         int plane = intel_crtc->plane;
5670         int refclk, num_connectors = 0;
5671         intel_clock_t clock, reduced_clock;
5672         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5673         bool ok, has_reduced_clock = false, is_sdvo = false;
5674         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5675         struct intel_encoder *has_edp_encoder = NULL;
5676         struct drm_mode_config *mode_config = &dev->mode_config;
5677         struct intel_encoder *encoder;
5678         const intel_limit_t *limit;
5679         int ret;
5680         struct fdi_m_n m_n = {0};
5681         u32 temp;
5682         u32 lvds_sync = 0;
5683         int target_clock, pixel_multiplier, lane, link_bw, factor;
5684         unsigned int pipe_bpp;
5685         bool dither;
5686
5687         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5688                 if (encoder->base.crtc != crtc)
5689                         continue;
5690
5691                 switch (encoder->type) {
5692                 case INTEL_OUTPUT_LVDS:
5693                         is_lvds = true;
5694                         break;
5695                 case INTEL_OUTPUT_SDVO:
5696                 case INTEL_OUTPUT_HDMI:
5697                         is_sdvo = true;
5698                         if (encoder->needs_tv_clock)
5699                                 is_tv = true;
5700                         break;
5701                 case INTEL_OUTPUT_TVOUT:
5702                         is_tv = true;
5703                         break;
5704                 case INTEL_OUTPUT_ANALOG:
5705                         is_crt = true;
5706                         break;
5707                 case INTEL_OUTPUT_DISPLAYPORT:
5708                         is_dp = true;
5709                         break;
5710                 case INTEL_OUTPUT_EDP:
5711                         has_edp_encoder = encoder;
5712                         break;
5713                 }
5714
5715                 num_connectors++;
5716         }
5717
5718         refclk = ironlake_get_refclk(crtc);
5719
5720         /*
5721          * Returns a set of divisors for the desired target clock with the given
5722          * refclk, or FALSE.  The returned values represent the clock equation:
5723          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5724          */
5725         limit = intel_limit(crtc, refclk);
5726         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5727                              &clock);
5728         if (!ok) {
5729                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5730                 return -EINVAL;
5731         }
5732
5733         /* Ensure that the cursor is valid for the new mode before changing... */
5734         intel_crtc_update_cursor(crtc, true);
5735
5736         if (is_lvds && dev_priv->lvds_downclock_avail) {
5737                 /*
5738                  * Ensure we match the reduced clock's P to the target clock.
5739                  * If the clocks don't match, we can't switch the display clock
5740                  * by using the FP0/FP1. In such case we will disable the LVDS
5741                  * downclock feature.
5742                 */
5743                 has_reduced_clock = limit->find_pll(limit, crtc,
5744                                                     dev_priv->lvds_downclock,
5745                                                     refclk,
5746                                                     &clock,
5747                                                     &reduced_clock);
5748         }
5749         /* SDVO TV has fixed PLL values depend on its clock range,
5750            this mirrors vbios setting. */
5751         if (is_sdvo && is_tv) {
5752                 if (adjusted_mode->clock >= 100000
5753                     && adjusted_mode->clock < 140500) {
5754                         clock.p1 = 2;
5755                         clock.p2 = 10;
5756                         clock.n = 3;
5757                         clock.m1 = 16;
5758                         clock.m2 = 8;
5759                 } else if (adjusted_mode->clock >= 140500
5760                            && adjusted_mode->clock <= 200000) {
5761                         clock.p1 = 1;
5762                         clock.p2 = 10;
5763                         clock.n = 6;
5764                         clock.m1 = 12;
5765                         clock.m2 = 8;
5766                 }
5767         }
5768
5769         /* FDI link */
5770         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5771         lane = 0;
5772         /* CPU eDP doesn't require FDI link, so just set DP M/N
5773            according to current link config */
5774         if (has_edp_encoder &&
5775             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5776                 target_clock = mode->clock;
5777                 intel_edp_link_config(has_edp_encoder,
5778                                       &lane, &link_bw);
5779         } else {
5780                 /* [e]DP over FDI requires target mode clock
5781                    instead of link clock */
5782                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5783                         target_clock = mode->clock;
5784                 else
5785                         target_clock = adjusted_mode->clock;
5786
5787                 /* FDI is a binary signal running at ~2.7GHz, encoding
5788                  * each output octet as 10 bits. The actual frequency
5789                  * is stored as a divider into a 100MHz clock, and the
5790                  * mode pixel clock is stored in units of 1KHz.
5791                  * Hence the bw of each lane in terms of the mode signal
5792                  * is:
5793                  */
5794                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5795         }
5796
5797         /* determine panel color depth */
5798         temp = I915_READ(PIPECONF(pipe));
5799         temp &= ~PIPE_BPC_MASK;
5800         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, adjusted_mode);
5801         switch (pipe_bpp) {
5802         case 18:
5803                 temp |= PIPE_6BPC;
5804                 break;
5805         case 24:
5806                 temp |= PIPE_8BPC;
5807                 break;
5808         case 30:
5809                 temp |= PIPE_10BPC;
5810                 break;
5811         case 36:
5812                 temp |= PIPE_12BPC;
5813                 break;
5814         default:
5815                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5816                         pipe_bpp);
5817                 temp |= PIPE_8BPC;
5818                 pipe_bpp = 24;
5819                 break;
5820         }
5821
5822         intel_crtc->bpp = pipe_bpp;
5823         I915_WRITE(PIPECONF(pipe), temp);
5824
5825         if (!lane) {
5826                 /*
5827                  * Account for spread spectrum to avoid
5828                  * oversubscribing the link. Max center spread
5829                  * is 2.5%; use 5% for safety's sake.
5830                  */
5831                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5832                 lane = bps / (link_bw * 8) + 1;
5833         }
5834
5835         intel_crtc->fdi_lanes = lane;
5836
5837         if (pixel_multiplier > 1)
5838                 link_bw *= pixel_multiplier;
5839         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5840                              &m_n);
5841
5842         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5843         if (has_reduced_clock)
5844                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5845                         reduced_clock.m2;
5846
5847         /* Enable autotuning of the PLL clock (if permissible) */
5848         factor = 21;
5849         if (is_lvds) {
5850                 if ((intel_panel_use_ssc(dev_priv) &&
5851                      dev_priv->lvds_ssc_freq == 100) ||
5852                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5853                         factor = 25;
5854         } else if (is_sdvo && is_tv)
5855                 factor = 20;
5856
5857         if (clock.m < factor * clock.n)
5858                 fp |= FP_CB_TUNE;
5859
5860         dpll = 0;
5861
5862         if (is_lvds)
5863                 dpll |= DPLLB_MODE_LVDS;
5864         else
5865                 dpll |= DPLLB_MODE_DAC_SERIAL;
5866         if (is_sdvo) {
5867                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5868                 if (pixel_multiplier > 1) {
5869                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5870                 }
5871                 dpll |= DPLL_DVO_HIGH_SPEED;
5872         }
5873         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5874                 dpll |= DPLL_DVO_HIGH_SPEED;
5875
5876         /* compute bitmask from p1 value */
5877         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5878         /* also FPA1 */
5879         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5880
5881         switch (clock.p2) {
5882         case 5:
5883                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5884                 break;
5885         case 7:
5886                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5887                 break;
5888         case 10:
5889                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5890                 break;
5891         case 14:
5892                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5893                 break;
5894         }
5895
5896         if (is_sdvo && is_tv)
5897                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5898         else if (is_tv)
5899                 /* XXX: just matching BIOS for now */
5900                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5901                 dpll |= 3;
5902         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5903                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5904         else
5905                 dpll |= PLL_REF_INPUT_DREFCLK;
5906
5907         /* setup pipeconf */
5908         pipeconf = I915_READ(PIPECONF(pipe));
5909
5910         /* Set up the display plane register */
5911         dspcntr = DISPPLANE_GAMMA_ENABLE;
5912
5913         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5914         drm_mode_debug_printmodeline(mode);
5915
5916         /* PCH eDP needs FDI, but CPU eDP does not */
5917         if (!intel_crtc->no_pll) {
5918                 if (!has_edp_encoder ||
5919                     intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5920                         I915_WRITE(PCH_FP0(pipe), fp);
5921                         I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5922
5923                         POSTING_READ(PCH_DPLL(pipe));
5924                         udelay(150);
5925                 }
5926         } else {
5927                 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5928                     fp == I915_READ(PCH_FP0(0))) {
5929                         intel_crtc->use_pll_a = true;
5930                         DRM_DEBUG_KMS("using pipe a dpll\n");
5931                 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5932                            fp == I915_READ(PCH_FP0(1))) {
5933                         intel_crtc->use_pll_a = false;
5934                         DRM_DEBUG_KMS("using pipe b dpll\n");
5935                 } else {
5936                         DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5937                         return -EINVAL;
5938                 }
5939         }
5940
5941         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5942          * This is an exception to the general rule that mode_set doesn't turn
5943          * things on.
5944          */
5945         if (is_lvds) {
5946                 temp = I915_READ(PCH_LVDS);
5947                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5948                 if (HAS_PCH_CPT(dev)) {
5949                         temp &= ~PORT_TRANS_SEL_MASK;
5950                         temp |= PORT_TRANS_SEL_CPT(pipe);
5951                 } else {
5952                         if (pipe == 1)
5953                                 temp |= LVDS_PIPEB_SELECT;
5954                         else
5955                                 temp &= ~LVDS_PIPEB_SELECT;
5956                 }
5957
5958                 /* set the corresponsding LVDS_BORDER bit */
5959                 temp |= dev_priv->lvds_border_bits;
5960                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5961                  * set the DPLLs for dual-channel mode or not.
5962                  */
5963                 if (clock.p2 == 7)
5964                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5965                 else
5966                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5967
5968                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5969                  * appropriately here, but we need to look more thoroughly into how
5970                  * panels behave in the two modes.
5971                  */
5972                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5973                         lvds_sync |= LVDS_HSYNC_POLARITY;
5974                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5975                         lvds_sync |= LVDS_VSYNC_POLARITY;
5976                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5977                     != lvds_sync) {
5978                         char flags[2] = "-+";
5979                         DRM_INFO("Changing LVDS panel from "
5980                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5981                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5982                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5983                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5984                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5985     &