a0a4e3bcbcf65f21592e1e787aa517ee0e4bd8d0
[linux-2.6.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *      Eric Anholt <eric@anholt.net>
25  */
26
27 #include <linux/cpufreq.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include "drmP.h"
36 #include "intel_drv.h"
37 #include "i915_drm.h"
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
43
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_update_watermarks(struct drm_device *dev);
48 static void intel_increase_pllclock(struct drm_crtc *crtc);
49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
50
51 typedef struct {
52         /* given values */
53         int n;
54         int m1, m2;
55         int p1, p2;
56         /* derived values */
57         int     dot;
58         int     vco;
59         int     m;
60         int     p;
61 } intel_clock_t;
62
63 typedef struct {
64         int     min, max;
65 } intel_range_t;
66
67 typedef struct {
68         int     dot_limit;
69         int     p2_slow, p2_fast;
70 } intel_p2_t;
71
72 #define INTEL_P2_NUM                  2
73 typedef struct intel_limit intel_limit_t;
74 struct intel_limit {
75         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
76         intel_p2_t          p2;
77         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
78                         int, int, intel_clock_t *, intel_clock_t *);
79 };
80
81 /* FDI */
82 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
83
84 static bool
85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
86                     int target, int refclk, intel_clock_t *match_clock,
87                     intel_clock_t *best_clock);
88 static bool
89 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
90                         int target, int refclk, intel_clock_t *match_clock,
91                         intel_clock_t *best_clock);
92
93 static bool
94 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
95                       int target, int refclk, intel_clock_t *match_clock,
96                       intel_clock_t *best_clock);
97 static bool
98 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
99                            int target, int refclk, intel_clock_t *match_clock,
100                            intel_clock_t *best_clock);
101
102 static inline u32 /* units of 100MHz */
103 intel_fdi_link_freq(struct drm_device *dev)
104 {
105         if (IS_GEN5(dev)) {
106                 struct drm_i915_private *dev_priv = dev->dev_private;
107                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
108         } else
109                 return 27;
110 }
111
112 static const intel_limit_t intel_limits_i8xx_dvo = {
113         .dot = { .min = 25000, .max = 350000 },
114         .vco = { .min = 930000, .max = 1400000 },
115         .n = { .min = 3, .max = 16 },
116         .m = { .min = 96, .max = 140 },
117         .m1 = { .min = 18, .max = 26 },
118         .m2 = { .min = 6, .max = 16 },
119         .p = { .min = 4, .max = 128 },
120         .p1 = { .min = 2, .max = 33 },
121         .p2 = { .dot_limit = 165000,
122                 .p2_slow = 4, .p2_fast = 2 },
123         .find_pll = intel_find_best_PLL,
124 };
125
126 static const intel_limit_t intel_limits_i8xx_lvds = {
127         .dot = { .min = 25000, .max = 350000 },
128         .vco = { .min = 930000, .max = 1400000 },
129         .n = { .min = 3, .max = 16 },
130         .m = { .min = 96, .max = 140 },
131         .m1 = { .min = 18, .max = 26 },
132         .m2 = { .min = 6, .max = 16 },
133         .p = { .min = 4, .max = 128 },
134         .p1 = { .min = 1, .max = 6 },
135         .p2 = { .dot_limit = 165000,
136                 .p2_slow = 14, .p2_fast = 7 },
137         .find_pll = intel_find_best_PLL,
138 };
139
140 static const intel_limit_t intel_limits_i9xx_sdvo = {
141         .dot = { .min = 20000, .max = 400000 },
142         .vco = { .min = 1400000, .max = 2800000 },
143         .n = { .min = 1, .max = 6 },
144         .m = { .min = 70, .max = 120 },
145         .m1 = { .min = 10, .max = 22 },
146         .m2 = { .min = 5, .max = 9 },
147         .p = { .min = 5, .max = 80 },
148         .p1 = { .min = 1, .max = 8 },
149         .p2 = { .dot_limit = 200000,
150                 .p2_slow = 10, .p2_fast = 5 },
151         .find_pll = intel_find_best_PLL,
152 };
153
154 static const intel_limit_t intel_limits_i9xx_lvds = {
155         .dot = { .min = 20000, .max = 400000 },
156         .vco = { .min = 1400000, .max = 2800000 },
157         .n = { .min = 1, .max = 6 },
158         .m = { .min = 70, .max = 120 },
159         .m1 = { .min = 10, .max = 22 },
160         .m2 = { .min = 5, .max = 9 },
161         .p = { .min = 7, .max = 98 },
162         .p1 = { .min = 1, .max = 8 },
163         .p2 = { .dot_limit = 112000,
164                 .p2_slow = 14, .p2_fast = 7 },
165         .find_pll = intel_find_best_PLL,
166 };
167
168
169 static const intel_limit_t intel_limits_g4x_sdvo = {
170         .dot = { .min = 25000, .max = 270000 },
171         .vco = { .min = 1750000, .max = 3500000},
172         .n = { .min = 1, .max = 4 },
173         .m = { .min = 104, .max = 138 },
174         .m1 = { .min = 17, .max = 23 },
175         .m2 = { .min = 5, .max = 11 },
176         .p = { .min = 10, .max = 30 },
177         .p1 = { .min = 1, .max = 3},
178         .p2 = { .dot_limit = 270000,
179                 .p2_slow = 10,
180                 .p2_fast = 10
181         },
182         .find_pll = intel_g4x_find_best_PLL,
183 };
184
185 static const intel_limit_t intel_limits_g4x_hdmi = {
186         .dot = { .min = 22000, .max = 400000 },
187         .vco = { .min = 1750000, .max = 3500000},
188         .n = { .min = 1, .max = 4 },
189         .m = { .min = 104, .max = 138 },
190         .m1 = { .min = 16, .max = 23 },
191         .m2 = { .min = 5, .max = 11 },
192         .p = { .min = 5, .max = 80 },
193         .p1 = { .min = 1, .max = 8},
194         .p2 = { .dot_limit = 165000,
195                 .p2_slow = 10, .p2_fast = 5 },
196         .find_pll = intel_g4x_find_best_PLL,
197 };
198
199 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
200         .dot = { .min = 20000, .max = 115000 },
201         .vco = { .min = 1750000, .max = 3500000 },
202         .n = { .min = 1, .max = 3 },
203         .m = { .min = 104, .max = 138 },
204         .m1 = { .min = 17, .max = 23 },
205         .m2 = { .min = 5, .max = 11 },
206         .p = { .min = 28, .max = 112 },
207         .p1 = { .min = 2, .max = 8 },
208         .p2 = { .dot_limit = 0,
209                 .p2_slow = 14, .p2_fast = 14
210         },
211         .find_pll = intel_g4x_find_best_PLL,
212 };
213
214 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
215         .dot = { .min = 80000, .max = 224000 },
216         .vco = { .min = 1750000, .max = 3500000 },
217         .n = { .min = 1, .max = 3 },
218         .m = { .min = 104, .max = 138 },
219         .m1 = { .min = 17, .max = 23 },
220         .m2 = { .min = 5, .max = 11 },
221         .p = { .min = 14, .max = 42 },
222         .p1 = { .min = 2, .max = 6 },
223         .p2 = { .dot_limit = 0,
224                 .p2_slow = 7, .p2_fast = 7
225         },
226         .find_pll = intel_g4x_find_best_PLL,
227 };
228
229 static const intel_limit_t intel_limits_g4x_display_port = {
230         .dot = { .min = 161670, .max = 227000 },
231         .vco = { .min = 1750000, .max = 3500000},
232         .n = { .min = 1, .max = 2 },
233         .m = { .min = 97, .max = 108 },
234         .m1 = { .min = 0x10, .max = 0x12 },
235         .m2 = { .min = 0x05, .max = 0x06 },
236         .p = { .min = 10, .max = 20 },
237         .p1 = { .min = 1, .max = 2},
238         .p2 = { .dot_limit = 0,
239                 .p2_slow = 10, .p2_fast = 10 },
240         .find_pll = intel_find_pll_g4x_dp,
241 };
242
243 static const intel_limit_t intel_limits_pineview_sdvo = {
244         .dot = { .min = 20000, .max = 400000},
245         .vco = { .min = 1700000, .max = 3500000 },
246         /* Pineview's Ncounter is a ring counter */
247         .n = { .min = 3, .max = 6 },
248         .m = { .min = 2, .max = 256 },
249         /* Pineview only has one combined m divider, which we treat as m2. */
250         .m1 = { .min = 0, .max = 0 },
251         .m2 = { .min = 0, .max = 254 },
252         .p = { .min = 5, .max = 80 },
253         .p1 = { .min = 1, .max = 8 },
254         .p2 = { .dot_limit = 200000,
255                 .p2_slow = 10, .p2_fast = 5 },
256         .find_pll = intel_find_best_PLL,
257 };
258
259 static const intel_limit_t intel_limits_pineview_lvds = {
260         .dot = { .min = 20000, .max = 400000 },
261         .vco = { .min = 1700000, .max = 3500000 },
262         .n = { .min = 3, .max = 6 },
263         .m = { .min = 2, .max = 256 },
264         .m1 = { .min = 0, .max = 0 },
265         .m2 = { .min = 0, .max = 254 },
266         .p = { .min = 7, .max = 112 },
267         .p1 = { .min = 1, .max = 8 },
268         .p2 = { .dot_limit = 112000,
269                 .p2_slow = 14, .p2_fast = 14 },
270         .find_pll = intel_find_best_PLL,
271 };
272
273 /* Ironlake / Sandybridge
274  *
275  * We calculate clock using (register_value + 2) for N/M1/M2, so here
276  * the range value for them is (actual_value - 2).
277  */
278 static const intel_limit_t intel_limits_ironlake_dac = {
279         .dot = { .min = 25000, .max = 350000 },
280         .vco = { .min = 1760000, .max = 3510000 },
281         .n = { .min = 1, .max = 5 },
282         .m = { .min = 79, .max = 127 },
283         .m1 = { .min = 12, .max = 22 },
284         .m2 = { .min = 5, .max = 9 },
285         .p = { .min = 5, .max = 80 },
286         .p1 = { .min = 1, .max = 8 },
287         .p2 = { .dot_limit = 225000,
288                 .p2_slow = 10, .p2_fast = 5 },
289         .find_pll = intel_g4x_find_best_PLL,
290 };
291
292 static const intel_limit_t intel_limits_ironlake_single_lvds = {
293         .dot = { .min = 25000, .max = 350000 },
294         .vco = { .min = 1760000, .max = 3510000 },
295         .n = { .min = 1, .max = 3 },
296         .m = { .min = 79, .max = 118 },
297         .m1 = { .min = 12, .max = 22 },
298         .m2 = { .min = 5, .max = 9 },
299         .p = { .min = 28, .max = 112 },
300         .p1 = { .min = 2, .max = 8 },
301         .p2 = { .dot_limit = 225000,
302                 .p2_slow = 14, .p2_fast = 14 },
303         .find_pll = intel_g4x_find_best_PLL,
304 };
305
306 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
307         .dot = { .min = 25000, .max = 350000 },
308         .vco = { .min = 1760000, .max = 3510000 },
309         .n = { .min = 1, .max = 3 },
310         .m = { .min = 79, .max = 127 },
311         .m1 = { .min = 12, .max = 22 },
312         .m2 = { .min = 5, .max = 9 },
313         .p = { .min = 14, .max = 56 },
314         .p1 = { .min = 2, .max = 8 },
315         .p2 = { .dot_limit = 225000,
316                 .p2_slow = 7, .p2_fast = 7 },
317         .find_pll = intel_g4x_find_best_PLL,
318 };
319
320 /* LVDS 100mhz refclk limits. */
321 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
322         .dot = { .min = 25000, .max = 350000 },
323         .vco = { .min = 1760000, .max = 3510000 },
324         .n = { .min = 1, .max = 2 },
325         .m = { .min = 79, .max = 126 },
326         .m1 = { .min = 12, .max = 22 },
327         .m2 = { .min = 5, .max = 9 },
328         .p = { .min = 28, .max = 112 },
329         .p1 = { .min = 2, .max = 8 },
330         .p2 = { .dot_limit = 225000,
331                 .p2_slow = 14, .p2_fast = 14 },
332         .find_pll = intel_g4x_find_best_PLL,
333 };
334
335 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
336         .dot = { .min = 25000, .max = 350000 },
337         .vco = { .min = 1760000, .max = 3510000 },
338         .n = { .min = 1, .max = 3 },
339         .m = { .min = 79, .max = 126 },
340         .m1 = { .min = 12, .max = 22 },
341         .m2 = { .min = 5, .max = 9 },
342         .p = { .min = 14, .max = 42 },
343         .p1 = { .min = 2, .max = 6 },
344         .p2 = { .dot_limit = 225000,
345                 .p2_slow = 7, .p2_fast = 7 },
346         .find_pll = intel_g4x_find_best_PLL,
347 };
348
349 static const intel_limit_t intel_limits_ironlake_display_port = {
350         .dot = { .min = 25000, .max = 350000 },
351         .vco = { .min = 1760000, .max = 3510000},
352         .n = { .min = 1, .max = 2 },
353         .m = { .min = 81, .max = 90 },
354         .m1 = { .min = 12, .max = 22 },
355         .m2 = { .min = 5, .max = 9 },
356         .p = { .min = 10, .max = 20 },
357         .p1 = { .min = 1, .max = 2},
358         .p2 = { .dot_limit = 0,
359                 .p2_slow = 10, .p2_fast = 10 },
360         .find_pll = intel_find_pll_ironlake_dp,
361 };
362
363 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
364                                                 int refclk)
365 {
366         struct drm_device *dev = crtc->dev;
367         struct drm_i915_private *dev_priv = dev->dev_private;
368         const intel_limit_t *limit;
369
370         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
371                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
372                     LVDS_CLKB_POWER_UP) {
373                         /* LVDS dual channel */
374                         if (refclk == 100000)
375                                 limit = &intel_limits_ironlake_dual_lvds_100m;
376                         else
377                                 limit = &intel_limits_ironlake_dual_lvds;
378                 } else {
379                         if (refclk == 100000)
380                                 limit = &intel_limits_ironlake_single_lvds_100m;
381                         else
382                                 limit = &intel_limits_ironlake_single_lvds;
383                 }
384         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
385                         HAS_eDP)
386                 limit = &intel_limits_ironlake_display_port;
387         else
388                 limit = &intel_limits_ironlake_dac;
389
390         return limit;
391 }
392
393 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
394 {
395         struct drm_device *dev = crtc->dev;
396         struct drm_i915_private *dev_priv = dev->dev_private;
397         const intel_limit_t *limit;
398
399         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
400                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
401                     LVDS_CLKB_POWER_UP)
402                         /* LVDS with dual channel */
403                         limit = &intel_limits_g4x_dual_channel_lvds;
404                 else
405                         /* LVDS with dual channel */
406                         limit = &intel_limits_g4x_single_channel_lvds;
407         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
408                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
409                 limit = &intel_limits_g4x_hdmi;
410         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
411                 limit = &intel_limits_g4x_sdvo;
412         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
413                 limit = &intel_limits_g4x_display_port;
414         } else /* The option is for other outputs */
415                 limit = &intel_limits_i9xx_sdvo;
416
417         return limit;
418 }
419
420 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
421 {
422         struct drm_device *dev = crtc->dev;
423         const intel_limit_t *limit;
424
425         if (HAS_PCH_SPLIT(dev))
426                 limit = intel_ironlake_limit(crtc, refclk);
427         else if (IS_G4X(dev)) {
428                 limit = intel_g4x_limit(crtc);
429         } else if (IS_PINEVIEW(dev)) {
430                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
431                         limit = &intel_limits_pineview_lvds;
432                 else
433                         limit = &intel_limits_pineview_sdvo;
434         } else if (!IS_GEN2(dev)) {
435                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
436                         limit = &intel_limits_i9xx_lvds;
437                 else
438                         limit = &intel_limits_i9xx_sdvo;
439         } else {
440                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
441                         limit = &intel_limits_i8xx_lvds;
442                 else
443                         limit = &intel_limits_i8xx_dvo;
444         }
445         return limit;
446 }
447
448 /* m1 is reserved as 0 in Pineview, n is a ring counter */
449 static void pineview_clock(int refclk, intel_clock_t *clock)
450 {
451         clock->m = clock->m2 + 2;
452         clock->p = clock->p1 * clock->p2;
453         clock->vco = refclk * clock->m / clock->n;
454         clock->dot = clock->vco / clock->p;
455 }
456
457 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
458 {
459         if (IS_PINEVIEW(dev)) {
460                 pineview_clock(refclk, clock);
461                 return;
462         }
463         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
464         clock->p = clock->p1 * clock->p2;
465         clock->vco = refclk * clock->m / (clock->n + 2);
466         clock->dot = clock->vco / clock->p;
467 }
468
469 /**
470  * Returns whether any output on the specified pipe is of the specified type
471  */
472 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
473 {
474         struct drm_device *dev = crtc->dev;
475         struct drm_mode_config *mode_config = &dev->mode_config;
476         struct intel_encoder *encoder;
477
478         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
479                 if (encoder->base.crtc == crtc && encoder->type == type)
480                         return true;
481
482         return false;
483 }
484
485 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
486 /**
487  * Returns whether the given set of divisors are valid for a given refclk with
488  * the given connectors.
489  */
490
491 static bool intel_PLL_is_valid(struct drm_device *dev,
492                                const intel_limit_t *limit,
493                                const intel_clock_t *clock)
494 {
495         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
496                 INTELPllInvalid("p1 out of range\n");
497         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
498                 INTELPllInvalid("p out of range\n");
499         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
500                 INTELPllInvalid("m2 out of range\n");
501         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
502                 INTELPllInvalid("m1 out of range\n");
503         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
504                 INTELPllInvalid("m1 <= m2\n");
505         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
506                 INTELPllInvalid("m out of range\n");
507         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
508                 INTELPllInvalid("n out of range\n");
509         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
510                 INTELPllInvalid("vco out of range\n");
511         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
512          * connector, etc., rather than just a single range.
513          */
514         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
515                 INTELPllInvalid("dot out of range\n");
516
517         return true;
518 }
519
520 static bool
521 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
522                     int target, int refclk, intel_clock_t *match_clock,
523                     intel_clock_t *best_clock)
524
525 {
526         struct drm_device *dev = crtc->dev;
527         struct drm_i915_private *dev_priv = dev->dev_private;
528         intel_clock_t clock;
529         int err = target;
530
531         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
532             (I915_READ(LVDS)) != 0) {
533                 /*
534                  * For LVDS, if the panel is on, just rely on its current
535                  * settings for dual-channel.  We haven't figured out how to
536                  * reliably set up different single/dual channel state, if we
537                  * even can.
538                  */
539                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
540                     LVDS_CLKB_POWER_UP)
541                         clock.p2 = limit->p2.p2_fast;
542                 else
543                         clock.p2 = limit->p2.p2_slow;
544         } else {
545                 if (target < limit->p2.dot_limit)
546                         clock.p2 = limit->p2.p2_slow;
547                 else
548                         clock.p2 = limit->p2.p2_fast;
549         }
550
551         memset(best_clock, 0, sizeof(*best_clock));
552
553         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
554              clock.m1++) {
555                 for (clock.m2 = limit->m2.min;
556                      clock.m2 <= limit->m2.max; clock.m2++) {
557                         /* m1 is always 0 in Pineview */
558                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
559                                 break;
560                         for (clock.n = limit->n.min;
561                              clock.n <= limit->n.max; clock.n++) {
562                                 for (clock.p1 = limit->p1.min;
563                                         clock.p1 <= limit->p1.max; clock.p1++) {
564                                         int this_err;
565
566                                         intel_clock(dev, refclk, &clock);
567                                         if (!intel_PLL_is_valid(dev, limit,
568                                                                 &clock))
569                                                 continue;
570                                         if (match_clock &&
571                                             clock.p != match_clock->p)
572                                                 continue;
573
574                                         this_err = abs(clock.dot - target);
575                                         if (this_err < err) {
576                                                 *best_clock = clock;
577                                                 err = this_err;
578                                         }
579                                 }
580                         }
581                 }
582         }
583
584         return (err != target);
585 }
586
587 static bool
588 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
589                         int target, int refclk, intel_clock_t *match_clock,
590                         intel_clock_t *best_clock)
591 {
592         struct drm_device *dev = crtc->dev;
593         struct drm_i915_private *dev_priv = dev->dev_private;
594         intel_clock_t clock;
595         int max_n;
596         bool found;
597         /* approximately equals target * 0.00585 */
598         int err_most = (target >> 8) + (target >> 9);
599         found = false;
600
601         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
602                 int lvds_reg;
603
604                 if (HAS_PCH_SPLIT(dev))
605                         lvds_reg = PCH_LVDS;
606                 else
607                         lvds_reg = LVDS;
608                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
609                     LVDS_CLKB_POWER_UP)
610                         clock.p2 = limit->p2.p2_fast;
611                 else
612                         clock.p2 = limit->p2.p2_slow;
613         } else {
614                 if (target < limit->p2.dot_limit)
615                         clock.p2 = limit->p2.p2_slow;
616                 else
617                         clock.p2 = limit->p2.p2_fast;
618         }
619
620         memset(best_clock, 0, sizeof(*best_clock));
621         max_n = limit->n.max;
622         /* based on hardware requirement, prefer smaller n to precision */
623         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
624                 /* based on hardware requirement, prefere larger m1,m2 */
625                 for (clock.m1 = limit->m1.max;
626                      clock.m1 >= limit->m1.min; clock.m1--) {
627                         for (clock.m2 = limit->m2.max;
628                              clock.m2 >= limit->m2.min; clock.m2--) {
629                                 for (clock.p1 = limit->p1.max;
630                                      clock.p1 >= limit->p1.min; clock.p1--) {
631                                         int this_err;
632
633                                         intel_clock(dev, refclk, &clock);
634                                         if (!intel_PLL_is_valid(dev, limit,
635                                                                 &clock))
636                                                 continue;
637                                         if (match_clock &&
638                                             clock.p != match_clock->p)
639                                                 continue;
640
641                                         this_err = abs(clock.dot - target);
642                                         if (this_err < err_most) {
643                                                 *best_clock = clock;
644                                                 err_most = this_err;
645                                                 max_n = clock.n;
646                                                 found = true;
647                                         }
648                                 }
649                         }
650                 }
651         }
652         return found;
653 }
654
655 static bool
656 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
657                            int target, int refclk, intel_clock_t *match_clock,
658                            intel_clock_t *best_clock)
659 {
660         struct drm_device *dev = crtc->dev;
661         intel_clock_t clock;
662
663         if (target < 200000) {
664                 clock.n = 1;
665                 clock.p1 = 2;
666                 clock.p2 = 10;
667                 clock.m1 = 12;
668                 clock.m2 = 9;
669         } else {
670                 clock.n = 2;
671                 clock.p1 = 1;
672                 clock.p2 = 10;
673                 clock.m1 = 14;
674                 clock.m2 = 8;
675         }
676         intel_clock(dev, refclk, &clock);
677         memcpy(best_clock, &clock, sizeof(intel_clock_t));
678         return true;
679 }
680
681 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
682 static bool
683 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
684                       int target, int refclk, intel_clock_t *match_clock,
685                       intel_clock_t *best_clock)
686 {
687         intel_clock_t clock;
688         if (target < 200000) {
689                 clock.p1 = 2;
690                 clock.p2 = 10;
691                 clock.n = 2;
692                 clock.m1 = 23;
693                 clock.m2 = 8;
694         } else {
695                 clock.p1 = 1;
696                 clock.p2 = 10;
697                 clock.n = 1;
698                 clock.m1 = 14;
699                 clock.m2 = 2;
700         }
701         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
702         clock.p = (clock.p1 * clock.p2);
703         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
704         clock.vco = 0;
705         memcpy(best_clock, &clock, sizeof(intel_clock_t));
706         return true;
707 }
708
709 /**
710  * intel_wait_for_vblank - wait for vblank on a given pipe
711  * @dev: drm device
712  * @pipe: pipe to wait for
713  *
714  * Wait for vblank to occur on a given pipe.  Needed for various bits of
715  * mode setting code.
716  */
717 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
718 {
719         struct drm_i915_private *dev_priv = dev->dev_private;
720         int pipestat_reg = PIPESTAT(pipe);
721
722         /* Clear existing vblank status. Note this will clear any other
723          * sticky status fields as well.
724          *
725          * This races with i915_driver_irq_handler() with the result
726          * that either function could miss a vblank event.  Here it is not
727          * fatal, as we will either wait upon the next vblank interrupt or
728          * timeout.  Generally speaking intel_wait_for_vblank() is only
729          * called during modeset at which time the GPU should be idle and
730          * should *not* be performing page flips and thus not waiting on
731          * vblanks...
732          * Currently, the result of us stealing a vblank from the irq
733          * handler is that a single frame will be skipped during swapbuffers.
734          */
735         I915_WRITE(pipestat_reg,
736                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
737
738         /* Wait for vblank interrupt bit to set */
739         if (wait_for(I915_READ(pipestat_reg) &
740                      PIPE_VBLANK_INTERRUPT_STATUS,
741                      50))
742                 DRM_DEBUG_KMS("vblank wait timed out\n");
743 }
744
745 /*
746  * intel_wait_for_pipe_off - wait for pipe to turn off
747  * @dev: drm device
748  * @pipe: pipe to wait for
749  *
750  * After disabling a pipe, we can't wait for vblank in the usual way,
751  * spinning on the vblank interrupt status bit, since we won't actually
752  * see an interrupt when the pipe is disabled.
753  *
754  * On Gen4 and above:
755  *   wait for the pipe register state bit to turn off
756  *
757  * Otherwise:
758  *   wait for the display line value to settle (it usually
759  *   ends up stopping at the start of the next frame).
760  *
761  */
762 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
763 {
764         struct drm_i915_private *dev_priv = dev->dev_private;
765
766         if (INTEL_INFO(dev)->gen >= 4) {
767                 int reg = PIPECONF(pipe);
768
769                 /* Wait for the Pipe State to go off */
770                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
771                              100))
772                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
773         } else {
774                 u32 last_line;
775                 int reg = PIPEDSL(pipe);
776                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
777
778                 /* Wait for the display line to settle */
779                 do {
780                         last_line = I915_READ(reg) & DSL_LINEMASK;
781                         mdelay(5);
782                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
783                          time_after(timeout, jiffies));
784                 if (time_after(jiffies, timeout))
785                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
786         }
787 }
788
789 static const char *state_string(bool enabled)
790 {
791         return enabled ? "on" : "off";
792 }
793
794 /* Only for pre-ILK configs */
795 static void assert_pll(struct drm_i915_private *dev_priv,
796                        enum pipe pipe, bool state)
797 {
798         int reg;
799         u32 val;
800         bool cur_state;
801
802         reg = DPLL(pipe);
803         val = I915_READ(reg);
804         cur_state = !!(val & DPLL_VCO_ENABLE);
805         WARN(cur_state != state,
806              "PLL state assertion failure (expected %s, current %s)\n",
807              state_string(state), state_string(cur_state));
808 }
809 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
810 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
811
812 /* For ILK+ */
813 static void assert_pch_pll(struct drm_i915_private *dev_priv,
814                            enum pipe pipe, bool state)
815 {
816         int reg;
817         u32 val;
818         bool cur_state;
819
820         if (HAS_PCH_CPT(dev_priv->dev)) {
821                 u32 pch_dpll;
822
823                 pch_dpll = I915_READ(PCH_DPLL_SEL);
824
825                 /* Make sure the selected PLL is enabled to the transcoder */
826                 WARN(!((pch_dpll >> (4 * pipe)) & 8),
827                      "transcoder %d PLL not enabled\n", pipe);
828
829                 /* Convert the transcoder pipe number to a pll pipe number */
830                 pipe = (pch_dpll >> (4 * pipe)) & 1;
831         }
832
833         reg = PCH_DPLL(pipe);
834         val = I915_READ(reg);
835         cur_state = !!(val & DPLL_VCO_ENABLE);
836         WARN(cur_state != state,
837              "PCH PLL state assertion failure (expected %s, current %s)\n",
838              state_string(state), state_string(cur_state));
839 }
840 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
841 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
842
843 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
844                           enum pipe pipe, bool state)
845 {
846         int reg;
847         u32 val;
848         bool cur_state;
849
850         reg = FDI_TX_CTL(pipe);
851         val = I915_READ(reg);
852         cur_state = !!(val & FDI_TX_ENABLE);
853         WARN(cur_state != state,
854              "FDI TX state assertion failure (expected %s, current %s)\n",
855              state_string(state), state_string(cur_state));
856 }
857 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
858 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
859
860 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
861                           enum pipe pipe, bool state)
862 {
863         int reg;
864         u32 val;
865         bool cur_state;
866
867         reg = FDI_RX_CTL(pipe);
868         val = I915_READ(reg);
869         cur_state = !!(val & FDI_RX_ENABLE);
870         WARN(cur_state != state,
871              "FDI RX state assertion failure (expected %s, current %s)\n",
872              state_string(state), state_string(cur_state));
873 }
874 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
875 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
876
877 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
878                                       enum pipe pipe)
879 {
880         int reg;
881         u32 val;
882
883         /* ILK FDI PLL is always enabled */
884         if (dev_priv->info->gen == 5)
885                 return;
886
887         reg = FDI_TX_CTL(pipe);
888         val = I915_READ(reg);
889         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
890 }
891
892 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
893                                       enum pipe pipe)
894 {
895         int reg;
896         u32 val;
897
898         reg = FDI_RX_CTL(pipe);
899         val = I915_READ(reg);
900         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
901 }
902
903 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
904                                   enum pipe pipe)
905 {
906         int pp_reg, lvds_reg;
907         u32 val;
908         enum pipe panel_pipe = PIPE_A;
909         bool locked = true;
910
911         if (HAS_PCH_SPLIT(dev_priv->dev)) {
912                 pp_reg = PCH_PP_CONTROL;
913                 lvds_reg = PCH_LVDS;
914         } else {
915                 pp_reg = PP_CONTROL;
916                 lvds_reg = LVDS;
917         }
918
919         val = I915_READ(pp_reg);
920         if (!(val & PANEL_POWER_ON) ||
921             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
922                 locked = false;
923
924         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
925                 panel_pipe = PIPE_B;
926
927         WARN(panel_pipe == pipe && locked,
928              "panel assertion failure, pipe %c regs locked\n",
929              pipe_name(pipe));
930 }
931
932 void assert_pipe(struct drm_i915_private *dev_priv,
933                  enum pipe pipe, bool state)
934 {
935         int reg;
936         u32 val;
937         bool cur_state;
938
939         /* if we need the pipe A quirk it must be always on */
940         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
941                 state = true;
942
943         reg = PIPECONF(pipe);
944         val = I915_READ(reg);
945         cur_state = !!(val & PIPECONF_ENABLE);
946         WARN(cur_state != state,
947              "pipe %c assertion failure (expected %s, current %s)\n",
948              pipe_name(pipe), state_string(state), state_string(cur_state));
949 }
950
951 static void assert_plane(struct drm_i915_private *dev_priv,
952                          enum plane plane, bool state)
953 {
954         int reg;
955         u32 val;
956         bool cur_state;
957
958         reg = DSPCNTR(plane);
959         val = I915_READ(reg);
960         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
961         WARN(cur_state != state,
962              "plane %c assertion failure (expected %s, current %s)\n",
963              plane_name(plane), state_string(state), state_string(cur_state));
964 }
965
966 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
967 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
968
969 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
970                                    enum pipe pipe)
971 {
972         int reg, i;
973         u32 val;
974         int cur_pipe;
975
976         /* Planes are fixed to pipes on ILK+ */
977         if (HAS_PCH_SPLIT(dev_priv->dev)) {
978                 reg = DSPCNTR(pipe);
979                 val = I915_READ(reg);
980                 WARN((val & DISPLAY_PLANE_ENABLE),
981                      "plane %c assertion failure, should be disabled but not\n",
982                      plane_name(pipe));
983                 return;
984         }
985
986         /* Need to check both planes against the pipe */
987         for (i = 0; i < 2; i++) {
988                 reg = DSPCNTR(i);
989                 val = I915_READ(reg);
990                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
991                         DISPPLANE_SEL_PIPE_SHIFT;
992                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
993                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
994                      plane_name(i), pipe_name(pipe));
995         }
996 }
997
998 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
999 {
1000         u32 val;
1001         bool enabled;
1002
1003         val = I915_READ(PCH_DREF_CONTROL);
1004         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1005                             DREF_SUPERSPREAD_SOURCE_MASK));
1006         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1007 }
1008
1009 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1010                                        enum pipe pipe)
1011 {
1012         int reg;
1013         u32 val;
1014         bool enabled;
1015
1016         reg = TRANSCONF(pipe);
1017         val = I915_READ(reg);
1018         enabled = !!(val & TRANS_ENABLE);
1019         WARN(enabled,
1020              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1021              pipe_name(pipe));
1022 }
1023
1024 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1025                             enum pipe pipe, u32 port_sel, u32 val)
1026 {
1027         if ((val & DP_PORT_EN) == 0)
1028                 return false;
1029
1030         if (HAS_PCH_CPT(dev_priv->dev)) {
1031                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1032                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1033                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1034                         return false;
1035         } else {
1036                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1037                         return false;
1038         }
1039         return true;
1040 }
1041
1042 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1043                               enum pipe pipe, u32 val)
1044 {
1045         if ((val & PORT_ENABLE) == 0)
1046                 return false;
1047
1048         if (HAS_PCH_CPT(dev_priv->dev)) {
1049                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1050                         return false;
1051         } else {
1052                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1053                         return false;
1054         }
1055         return true;
1056 }
1057
1058 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1059                               enum pipe pipe, u32 val)
1060 {
1061         if ((val & LVDS_PORT_EN) == 0)
1062                 return false;
1063
1064         if (HAS_PCH_CPT(dev_priv->dev)) {
1065                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1066                         return false;
1067         } else {
1068                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1069                         return false;
1070         }
1071         return true;
1072 }
1073
1074 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1075                               enum pipe pipe, u32 val)
1076 {
1077         if ((val & ADPA_DAC_ENABLE) == 0)
1078                 return false;
1079         if (HAS_PCH_CPT(dev_priv->dev)) {
1080                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1081                         return false;
1082         } else {
1083                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1084                         return false;
1085         }
1086         return true;
1087 }
1088
1089 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1090                                    enum pipe pipe, int reg, u32 port_sel)
1091 {
1092         u32 val = I915_READ(reg);
1093         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1094              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1095              reg, pipe_name(pipe));
1096 }
1097
1098 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1099                                      enum pipe pipe, int reg)
1100 {
1101         u32 val = I915_READ(reg);
1102         WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1103              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1104              reg, pipe_name(pipe));
1105 }
1106
1107 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1108                                       enum pipe pipe)
1109 {
1110         int reg;
1111         u32 val;
1112
1113         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1114         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1115         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1116
1117         reg = PCH_ADPA;
1118         val = I915_READ(reg);
1119         WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1120              "PCH VGA enabled on transcoder %c, should be disabled\n",
1121              pipe_name(pipe));
1122
1123         reg = PCH_LVDS;
1124         val = I915_READ(reg);
1125         WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1126              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1127              pipe_name(pipe));
1128
1129         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1130         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1131         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1132 }
1133
1134 /**
1135  * intel_enable_pll - enable a PLL
1136  * @dev_priv: i915 private structure
1137  * @pipe: pipe PLL to enable
1138  *
1139  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1140  * make sure the PLL reg is writable first though, since the panel write
1141  * protect mechanism may be enabled.
1142  *
1143  * Note!  This is for pre-ILK only.
1144  */
1145 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1146 {
1147         int reg;
1148         u32 val;
1149
1150         /* No really, not for ILK+ */
1151         BUG_ON(dev_priv->info->gen >= 5);
1152
1153         /* PLL is protected by panel, make sure we can write it */
1154         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1155                 assert_panel_unlocked(dev_priv, pipe);
1156
1157         reg = DPLL(pipe);
1158         val = I915_READ(reg);
1159         val |= DPLL_VCO_ENABLE;
1160
1161         /* We do this three times for luck */
1162         I915_WRITE(reg, val);
1163         POSTING_READ(reg);
1164         udelay(150); /* wait for warmup */
1165         I915_WRITE(reg, val);
1166         POSTING_READ(reg);
1167         udelay(150); /* wait for warmup */
1168         I915_WRITE(reg, val);
1169         POSTING_READ(reg);
1170         udelay(150); /* wait for warmup */
1171 }
1172
1173 /**
1174  * intel_disable_pll - disable a PLL
1175  * @dev_priv: i915 private structure
1176  * @pipe: pipe PLL to disable
1177  *
1178  * Disable the PLL for @pipe, making sure the pipe is off first.
1179  *
1180  * Note!  This is for pre-ILK only.
1181  */
1182 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1183 {
1184         int reg;
1185         u32 val;
1186
1187         /* Don't disable pipe A or pipe A PLLs if needed */
1188         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1189                 return;
1190
1191         /* Make sure the pipe isn't still relying on us */
1192         assert_pipe_disabled(dev_priv, pipe);
1193
1194         reg = DPLL(pipe);
1195         val = I915_READ(reg);
1196         val &= ~DPLL_VCO_ENABLE;
1197         I915_WRITE(reg, val);
1198         POSTING_READ(reg);
1199 }
1200
1201 /**
1202  * intel_enable_pch_pll - enable PCH PLL
1203  * @dev_priv: i915 private structure
1204  * @pipe: pipe PLL to enable
1205  *
1206  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1207  * drives the transcoder clock.
1208  */
1209 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1210                                  enum pipe pipe)
1211 {
1212         int reg;
1213         u32 val;
1214
1215         if (pipe > 1)
1216                 return;
1217
1218         /* PCH only available on ILK+ */
1219         BUG_ON(dev_priv->info->gen < 5);
1220
1221         /* PCH refclock must be enabled first */
1222         assert_pch_refclk_enabled(dev_priv);
1223
1224         reg = PCH_DPLL(pipe);
1225         val = I915_READ(reg);
1226         val |= DPLL_VCO_ENABLE;
1227         I915_WRITE(reg, val);
1228         POSTING_READ(reg);
1229         udelay(200);
1230 }
1231
1232 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1233                                   enum pipe pipe)
1234 {
1235         int reg;
1236         u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1237                 pll_sel = TRANSC_DPLL_ENABLE;
1238
1239         if (pipe > 1)
1240                 return;
1241
1242         /* PCH only available on ILK+ */
1243         BUG_ON(dev_priv->info->gen < 5);
1244
1245         /* Make sure transcoder isn't still depending on us */
1246         assert_transcoder_disabled(dev_priv, pipe);
1247
1248         if (pipe == 0)
1249                 pll_sel |= TRANSC_DPLLA_SEL;
1250         else if (pipe == 1)
1251                 pll_sel |= TRANSC_DPLLB_SEL;
1252
1253
1254         if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1255                 return;
1256
1257         reg = PCH_DPLL(pipe);
1258         val = I915_READ(reg);
1259         val &= ~DPLL_VCO_ENABLE;
1260         I915_WRITE(reg, val);
1261         POSTING_READ(reg);
1262         udelay(200);
1263 }
1264
1265 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1266                                     enum pipe pipe)
1267 {
1268         int reg;
1269         u32 val, pipeconf_val;
1270         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1271
1272         /* PCH only available on ILK+ */
1273         BUG_ON(dev_priv->info->gen < 5);
1274
1275         /* Make sure PCH DPLL is enabled */
1276         assert_pch_pll_enabled(dev_priv, pipe);
1277
1278         /* FDI must be feeding us bits for PCH ports */
1279         assert_fdi_tx_enabled(dev_priv, pipe);
1280         assert_fdi_rx_enabled(dev_priv, pipe);
1281
1282         reg = TRANSCONF(pipe);
1283         val = I915_READ(reg);
1284         pipeconf_val = I915_READ(PIPECONF(pipe));
1285
1286         if (HAS_PCH_IBX(dev_priv->dev)) {
1287                 /*
1288                  * make the BPC in transcoder be consistent with
1289                  * that in pipeconf reg.
1290                  */
1291                 val &= ~PIPE_BPC_MASK;
1292                 val |= pipeconf_val & PIPE_BPC_MASK;
1293         }
1294
1295         val &= ~TRANS_INTERLACE_MASK;
1296         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1297                 if (HAS_PCH_IBX(dev_priv->dev) &&
1298                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1299                         val |= TRANS_LEGACY_INTERLACED_ILK;
1300                 else
1301                         val |= TRANS_INTERLACED;
1302         else
1303                 val |= TRANS_PROGRESSIVE;
1304
1305         I915_WRITE(reg, val | TRANS_ENABLE);
1306         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1307                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1308 }
1309
1310 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1311                                      enum pipe pipe)
1312 {
1313         int reg;
1314         u32 val;
1315
1316         /* FDI relies on the transcoder */
1317         assert_fdi_tx_disabled(dev_priv, pipe);
1318         assert_fdi_rx_disabled(dev_priv, pipe);
1319
1320         /* Ports must be off as well */
1321         assert_pch_ports_disabled(dev_priv, pipe);
1322
1323         reg = TRANSCONF(pipe);
1324         val = I915_READ(reg);
1325         val &= ~TRANS_ENABLE;
1326         I915_WRITE(reg, val);
1327         /* wait for PCH transcoder off, transcoder state */
1328         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1329                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1330 }
1331
1332 /**
1333  * intel_enable_pipe - enable a pipe, asserting requirements
1334  * @dev_priv: i915 private structure
1335  * @pipe: pipe to enable
1336  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1337  *
1338  * Enable @pipe, making sure that various hardware specific requirements
1339  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1340  *
1341  * @pipe should be %PIPE_A or %PIPE_B.
1342  *
1343  * Will wait until the pipe is actually running (i.e. first vblank) before
1344  * returning.
1345  */
1346 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1347                               bool pch_port)
1348 {
1349         int reg;
1350         u32 val;
1351
1352         /*
1353          * A pipe without a PLL won't actually be able to drive bits from
1354          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1355          * need the check.
1356          */
1357         if (!HAS_PCH_SPLIT(dev_priv->dev))
1358                 assert_pll_enabled(dev_priv, pipe);
1359         else {
1360                 if (pch_port) {
1361                         /* if driving the PCH, we need FDI enabled */
1362                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1363                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1364                 }
1365                 /* FIXME: assert CPU port conditions for SNB+ */
1366         }
1367
1368         reg = PIPECONF(pipe);
1369         val = I915_READ(reg);
1370         if (val & PIPECONF_ENABLE)
1371                 return;
1372
1373         I915_WRITE(reg, val | PIPECONF_ENABLE);
1374         intel_wait_for_vblank(dev_priv->dev, pipe);
1375 }
1376
1377 /**
1378  * intel_disable_pipe - disable a pipe, asserting requirements
1379  * @dev_priv: i915 private structure
1380  * @pipe: pipe to disable
1381  *
1382  * Disable @pipe, making sure that various hardware specific requirements
1383  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1384  *
1385  * @pipe should be %PIPE_A or %PIPE_B.
1386  *
1387  * Will wait until the pipe has shut down before returning.
1388  */
1389 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1390                                enum pipe pipe)
1391 {
1392         int reg;
1393         u32 val;
1394
1395         /*
1396          * Make sure planes won't keep trying to pump pixels to us,
1397          * or we might hang the display.
1398          */
1399         assert_planes_disabled(dev_priv, pipe);
1400
1401         /* Don't disable pipe A or pipe A PLLs if needed */
1402         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1403                 return;
1404
1405         reg = PIPECONF(pipe);
1406         val = I915_READ(reg);
1407         if ((val & PIPECONF_ENABLE) == 0)
1408                 return;
1409
1410         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1411         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1412 }
1413
1414 /*
1415  * Plane regs are double buffered, going from enabled->disabled needs a
1416  * trigger in order to latch.  The display address reg provides this.
1417  */
1418 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1419                                       enum plane plane)
1420 {
1421         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1422         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1423 }
1424
1425 /**
1426  * intel_enable_plane - enable a display plane on a given pipe
1427  * @dev_priv: i915 private structure
1428  * @plane: plane to enable
1429  * @pipe: pipe being fed
1430  *
1431  * Enable @plane on @pipe, making sure that @pipe is running first.
1432  */
1433 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1434                                enum plane plane, enum pipe pipe)
1435 {
1436         int reg;
1437         u32 val;
1438
1439         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1440         assert_pipe_enabled(dev_priv, pipe);
1441
1442         reg = DSPCNTR(plane);
1443         val = I915_READ(reg);
1444         if (val & DISPLAY_PLANE_ENABLE)
1445                 return;
1446
1447         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1448         intel_flush_display_plane(dev_priv, plane);
1449         intel_wait_for_vblank(dev_priv->dev, pipe);
1450 }
1451
1452 /**
1453  * intel_disable_plane - disable a display plane
1454  * @dev_priv: i915 private structure
1455  * @plane: plane to disable
1456  * @pipe: pipe consuming the data
1457  *
1458  * Disable @plane; should be an independent operation.
1459  */
1460 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1461                                 enum plane plane, enum pipe pipe)
1462 {
1463         int reg;
1464         u32 val;
1465
1466         reg = DSPCNTR(plane);
1467         val = I915_READ(reg);
1468         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1469                 return;
1470
1471         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1472         intel_flush_display_plane(dev_priv, plane);
1473         intel_wait_for_vblank(dev_priv->dev, pipe);
1474 }
1475
1476 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1477                            enum pipe pipe, int reg, u32 port_sel)
1478 {
1479         u32 val = I915_READ(reg);
1480         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1481                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1482                 I915_WRITE(reg, val & ~DP_PORT_EN);
1483         }
1484 }
1485
1486 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1487                              enum pipe pipe, int reg)
1488 {
1489         u32 val = I915_READ(reg);
1490         if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1491                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1492                               reg, pipe);
1493                 I915_WRITE(reg, val & ~PORT_ENABLE);
1494         }
1495 }
1496
1497 /* Disable any ports connected to this transcoder */
1498 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1499                                     enum pipe pipe)
1500 {
1501         u32 reg, val;
1502
1503         val = I915_READ(PCH_PP_CONTROL);
1504         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1505
1506         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1507         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1508         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1509
1510         reg = PCH_ADPA;
1511         val = I915_READ(reg);
1512         if (adpa_pipe_enabled(dev_priv, val, pipe))
1513                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1514
1515         reg = PCH_LVDS;
1516         val = I915_READ(reg);
1517         if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1518                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1519                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1520                 POSTING_READ(reg);
1521                 udelay(100);
1522         }
1523
1524         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1525         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1526         disable_pch_hdmi(dev_priv, pipe, HDMID);
1527 }
1528
1529 static void i8xx_disable_fbc(struct drm_device *dev)
1530 {
1531         struct drm_i915_private *dev_priv = dev->dev_private;
1532         u32 fbc_ctl;
1533
1534         /* Disable compression */
1535         fbc_ctl = I915_READ(FBC_CONTROL);
1536         if ((fbc_ctl & FBC_CTL_EN) == 0)
1537                 return;
1538
1539         fbc_ctl &= ~FBC_CTL_EN;
1540         I915_WRITE(FBC_CONTROL, fbc_ctl);
1541
1542         /* Wait for compressing bit to clear */
1543         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1544                 DRM_DEBUG_KMS("FBC idle timed out\n");
1545                 return;
1546         }
1547
1548         DRM_DEBUG_KMS("disabled FBC\n");
1549 }
1550
1551 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1552 {
1553         struct drm_device *dev = crtc->dev;
1554         struct drm_i915_private *dev_priv = dev->dev_private;
1555         struct drm_framebuffer *fb = crtc->fb;
1556         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1557         struct drm_i915_gem_object *obj = intel_fb->obj;
1558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1559         int cfb_pitch;
1560         int plane, i;
1561         u32 fbc_ctl, fbc_ctl2;
1562
1563         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1564         if (fb->pitches[0] < cfb_pitch)
1565                 cfb_pitch = fb->pitches[0];
1566
1567         /* FBC_CTL wants 64B units */
1568         cfb_pitch = (cfb_pitch / 64) - 1;
1569         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1570
1571         /* Clear old tags */
1572         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1573                 I915_WRITE(FBC_TAG + (i * 4), 0);
1574
1575         /* Set it up... */
1576         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1577         fbc_ctl2 |= plane;
1578         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1579         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1580
1581         /* enable it... */
1582         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1583         if (IS_I945GM(dev))
1584                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1585         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1586         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1587         fbc_ctl |= obj->fence_reg;
1588         I915_WRITE(FBC_CONTROL, fbc_ctl);
1589
1590         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1591                       cfb_pitch, crtc->y, intel_crtc->plane);
1592 }
1593
1594 static bool i8xx_fbc_enabled(struct drm_device *dev)
1595 {
1596         struct drm_i915_private *dev_priv = dev->dev_private;
1597
1598         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1599 }
1600
1601 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1602 {
1603         struct drm_device *dev = crtc->dev;
1604         struct drm_i915_private *dev_priv = dev->dev_private;
1605         struct drm_framebuffer *fb = crtc->fb;
1606         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1607         struct drm_i915_gem_object *obj = intel_fb->obj;
1608         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1609         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1610         unsigned long stall_watermark = 200;
1611         u32 dpfc_ctl;
1612
1613         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1614         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1615         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1616
1617         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1618                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1619                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1620         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1621
1622         /* enable it... */
1623         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1624
1625         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1626 }
1627
1628 static void g4x_disable_fbc(struct drm_device *dev)
1629 {
1630         struct drm_i915_private *dev_priv = dev->dev_private;
1631         u32 dpfc_ctl;
1632
1633         /* Disable compression */
1634         dpfc_ctl = I915_READ(DPFC_CONTROL);
1635         if (dpfc_ctl & DPFC_CTL_EN) {
1636                 dpfc_ctl &= ~DPFC_CTL_EN;
1637                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1638
1639                 DRM_DEBUG_KMS("disabled FBC\n");
1640         }
1641 }
1642
1643 static bool g4x_fbc_enabled(struct drm_device *dev)
1644 {
1645         struct drm_i915_private *dev_priv = dev->dev_private;
1646
1647         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1648 }
1649
1650 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1651 {
1652         struct drm_i915_private *dev_priv = dev->dev_private;
1653         u32 blt_ecoskpd;
1654
1655         /* Make sure blitter notifies FBC of writes */
1656         gen6_gt_force_wake_get(dev_priv);
1657         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1658         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1659                 GEN6_BLITTER_LOCK_SHIFT;
1660         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1661         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1662         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1663         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1664                          GEN6_BLITTER_LOCK_SHIFT);
1665         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1666         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1667         gen6_gt_force_wake_put(dev_priv);
1668 }
1669
1670 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1671 {
1672         struct drm_device *dev = crtc->dev;
1673         struct drm_i915_private *dev_priv = dev->dev_private;
1674         struct drm_framebuffer *fb = crtc->fb;
1675         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1676         struct drm_i915_gem_object *obj = intel_fb->obj;
1677         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1678         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1679         unsigned long stall_watermark = 200;
1680         u32 dpfc_ctl;
1681
1682         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1683         dpfc_ctl &= DPFC_RESERVED;
1684         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1685         /* Set persistent mode for front-buffer rendering, ala X. */
1686         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1687         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1688         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1689
1690         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1691                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1692                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1693         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1694         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1695         /* enable it... */
1696         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1697
1698         if (IS_GEN6(dev)) {
1699                 I915_WRITE(SNB_DPFC_CTL_SA,
1700                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1701                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1702                 sandybridge_blit_fbc_update(dev);
1703         }
1704
1705         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1706 }
1707
1708 static void ironlake_disable_fbc(struct drm_device *dev)
1709 {
1710         struct drm_i915_private *dev_priv = dev->dev_private;
1711         u32 dpfc_ctl;
1712
1713         /* Disable compression */
1714         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1715         if (dpfc_ctl & DPFC_CTL_EN) {
1716                 dpfc_ctl &= ~DPFC_CTL_EN;
1717                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1718
1719                 DRM_DEBUG_KMS("disabled FBC\n");
1720         }
1721 }
1722
1723 static bool ironlake_fbc_enabled(struct drm_device *dev)
1724 {
1725         struct drm_i915_private *dev_priv = dev->dev_private;
1726
1727         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1728 }
1729
1730 bool intel_fbc_enabled(struct drm_device *dev)
1731 {
1732         struct drm_i915_private *dev_priv = dev->dev_private;
1733
1734         if (!dev_priv->display.fbc_enabled)
1735                 return false;
1736
1737         return dev_priv->display.fbc_enabled(dev);
1738 }
1739
1740 static void intel_fbc_work_fn(struct work_struct *__work)
1741 {
1742         struct intel_fbc_work *work =
1743                 container_of(to_delayed_work(__work),
1744                              struct intel_fbc_work, work);
1745         struct drm_device *dev = work->crtc->dev;
1746         struct drm_i915_private *dev_priv = dev->dev_private;
1747
1748         mutex_lock(&dev->struct_mutex);
1749         if (work == dev_priv->fbc_work) {
1750                 /* Double check that we haven't switched fb without cancelling
1751                  * the prior work.
1752                  */
1753                 if (work->crtc->fb == work->fb) {
1754                         dev_priv->display.enable_fbc(work->crtc,
1755                                                      work->interval);
1756
1757                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1758                         dev_priv->cfb_fb = work->crtc->fb->base.id;
1759                         dev_priv->cfb_y = work->crtc->y;
1760                 }
1761
1762                 dev_priv->fbc_work = NULL;
1763         }
1764         mutex_unlock(&dev->struct_mutex);
1765
1766         kfree(work);
1767 }
1768
1769 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1770 {
1771         if (dev_priv->fbc_work == NULL)
1772                 return;
1773
1774         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1775
1776         /* Synchronisation is provided by struct_mutex and checking of
1777          * dev_priv->fbc_work, so we can perform the cancellation
1778          * entirely asynchronously.
1779          */
1780         if (cancel_delayed_work(&dev_priv->fbc_work->work))
1781                 /* tasklet was killed before being run, clean up */
1782                 kfree(dev_priv->fbc_work);
1783
1784         /* Mark the work as no longer wanted so that if it does
1785          * wake-up (because the work was already running and waiting
1786          * for our mutex), it will discover that is no longer
1787          * necessary to run.
1788          */
1789         dev_priv->fbc_work = NULL;
1790 }
1791
1792 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1793 {
1794         struct intel_fbc_work *work;
1795         struct drm_device *dev = crtc->dev;
1796         struct drm_i915_private *dev_priv = dev->dev_private;
1797
1798         if (!dev_priv->display.enable_fbc)
1799                 return;
1800
1801         intel_cancel_fbc_work(dev_priv);
1802
1803         work = kzalloc(sizeof *work, GFP_KERNEL);
1804         if (work == NULL) {
1805                 dev_priv->display.enable_fbc(crtc, interval);
1806                 return;
1807         }
1808
1809         work->crtc = crtc;
1810         work->fb = crtc->fb;
1811         work->interval = interval;
1812         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1813
1814         dev_priv->fbc_work = work;
1815
1816         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1817
1818         /* Delay the actual enabling to let pageflipping cease and the
1819          * display to settle before starting the compression. Note that
1820          * this delay also serves a second purpose: it allows for a
1821          * vblank to pass after disabling the FBC before we attempt
1822          * to modify the control registers.
1823          *
1824          * A more complicated solution would involve tracking vblanks
1825          * following the termination of the page-flipping sequence
1826          * and indeed performing the enable as a co-routine and not
1827          * waiting synchronously upon the vblank.
1828          */
1829         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1830 }
1831
1832 void intel_disable_fbc(struct drm_device *dev)
1833 {
1834         struct drm_i915_private *dev_priv = dev->dev_private;
1835
1836         intel_cancel_fbc_work(dev_priv);
1837
1838         if (!dev_priv->display.disable_fbc)
1839                 return;
1840
1841         dev_priv->display.disable_fbc(dev);
1842         dev_priv->cfb_plane = -1;
1843 }
1844
1845 /**
1846  * intel_update_fbc - enable/disable FBC as needed
1847  * @dev: the drm_device
1848  *
1849  * Set up the framebuffer compression hardware at mode set time.  We
1850  * enable it if possible:
1851  *   - plane A only (on pre-965)
1852  *   - no pixel mulitply/line duplication
1853  *   - no alpha buffer discard
1854  *   - no dual wide
1855  *   - framebuffer <= 2048 in width, 1536 in height
1856  *
1857  * We can't assume that any compression will take place (worst case),
1858  * so the compressed buffer has to be the same size as the uncompressed
1859  * one.  It also must reside (along with the line length buffer) in
1860  * stolen memory.
1861  *
1862  * We need to enable/disable FBC on a global basis.
1863  */
1864 static void intel_update_fbc(struct drm_device *dev)
1865 {
1866         struct drm_i915_private *dev_priv = dev->dev_private;
1867         struct drm_crtc *crtc = NULL, *tmp_crtc;
1868         struct intel_crtc *intel_crtc;
1869         struct drm_framebuffer *fb;
1870         struct intel_framebuffer *intel_fb;
1871         struct drm_i915_gem_object *obj;
1872         int enable_fbc;
1873
1874         DRM_DEBUG_KMS("\n");
1875
1876         if (!i915_powersave)
1877                 return;
1878
1879         if (!I915_HAS_FBC(dev))
1880                 return;
1881
1882         /*
1883          * If FBC is already on, we just have to verify that we can
1884          * keep it that way...
1885          * Need to disable if:
1886          *   - more than one pipe is active
1887          *   - changing FBC params (stride, fence, mode)
1888          *   - new fb is too large to fit in compressed buffer
1889          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1890          */
1891         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1892                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1893                         if (crtc) {
1894                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1895                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1896                                 goto out_disable;
1897                         }
1898                         crtc = tmp_crtc;
1899                 }
1900         }
1901
1902         if (!crtc || crtc->fb == NULL) {
1903                 DRM_DEBUG_KMS("no output, disabling\n");
1904                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1905                 goto out_disable;
1906         }
1907
1908         intel_crtc = to_intel_crtc(crtc);
1909         fb = crtc->fb;
1910         intel_fb = to_intel_framebuffer(fb);
1911         obj = intel_fb->obj;
1912
1913         enable_fbc = i915_enable_fbc;
1914         if (enable_fbc < 0) {
1915                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1916                 enable_fbc = 1;
1917                 if (INTEL_INFO(dev)->gen <= 6)
1918                         enable_fbc = 0;
1919         }
1920         if (!enable_fbc) {
1921                 DRM_DEBUG_KMS("fbc disabled per module param\n");
1922                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1923                 goto out_disable;
1924         }
1925         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1926                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1927                               "compression\n");
1928                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1929                 goto out_disable;
1930         }
1931         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1932             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1933                 DRM_DEBUG_KMS("mode incompatible with compression, "
1934                               "disabling\n");
1935                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1936                 goto out_disable;
1937         }
1938         if ((crtc->mode.hdisplay > 2048) ||
1939             (crtc->mode.vdisplay > 1536)) {
1940                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1941                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1942                 goto out_disable;
1943         }
1944         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1945                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1946                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1947                 goto out_disable;
1948         }
1949
1950         /* The use of a CPU fence is mandatory in order to detect writes
1951          * by the CPU to the scanout and trigger updates to the FBC.
1952          */
1953         if (obj->tiling_mode != I915_TILING_X ||
1954             obj->fence_reg == I915_FENCE_REG_NONE) {
1955                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1956                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1957                 goto out_disable;
1958         }
1959
1960         /* If the kernel debugger is active, always disable compression */
1961         if (in_dbg_master())
1962                 goto out_disable;
1963
1964         /* If the scanout has not changed, don't modify the FBC settings.
1965          * Note that we make the fundamental assumption that the fb->obj
1966          * cannot be unpinned (and have its GTT offset and fence revoked)
1967          * without first being decoupled from the scanout and FBC disabled.
1968          */
1969         if (dev_priv->cfb_plane == intel_crtc->plane &&
1970             dev_priv->cfb_fb == fb->base.id &&
1971             dev_priv->cfb_y == crtc->y)
1972                 return;
1973
1974         if (intel_fbc_enabled(dev)) {
1975                 /* We update FBC along two paths, after changing fb/crtc
1976                  * configuration (modeswitching) and after page-flipping
1977                  * finishes. For the latter, we know that not only did
1978                  * we disable the FBC at the start of the page-flip
1979                  * sequence, but also more than one vblank has passed.
1980                  *
1981                  * For the former case of modeswitching, it is possible
1982                  * to switch between two FBC valid configurations
1983                  * instantaneously so we do need to disable the FBC
1984                  * before we can modify its control registers. We also
1985                  * have to wait for the next vblank for that to take
1986                  * effect. However, since we delay enabling FBC we can
1987                  * assume that a vblank has passed since disabling and
1988                  * that we can safely alter the registers in the deferred
1989                  * callback.
1990                  *
1991                  * In the scenario that we go from a valid to invalid
1992                  * and then back to valid FBC configuration we have
1993                  * no strict enforcement that a vblank occurred since
1994                  * disabling the FBC. However, along all current pipe
1995                  * disabling paths we do need to wait for a vblank at
1996                  * some point. And we wait before enabling FBC anyway.
1997                  */
1998                 DRM_DEBUG_KMS("disabling active FBC for update\n");
1999                 intel_disable_fbc(dev);
2000         }
2001
2002         intel_enable_fbc(crtc, 500);
2003         return;
2004
2005 out_disable:
2006         /* Multiple disables should be harmless */
2007         if (intel_fbc_enabled(dev)) {
2008                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
2009                 intel_disable_fbc(dev);
2010         }
2011 }
2012
2013 int
2014 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2015                            struct drm_i915_gem_object *obj,
2016                            struct intel_ring_buffer *pipelined)
2017 {
2018         struct drm_i915_private *dev_priv = dev->dev_private;
2019         u32 alignment;
2020         int ret;
2021
2022         switch (obj->tiling_mode) {
2023         case I915_TILING_NONE:
2024                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2025                         alignment = 128 * 1024;
2026                 else if (INTEL_INFO(dev)->gen >= 4)
2027                         alignment = 4 * 1024;
2028                 else
2029                         alignment = 64 * 1024;
2030                 break;
2031         case I915_TILING_X:
2032                 /* pin() will align the object as required by fence */
2033                 alignment = 0;
2034                 break;
2035         case I915_TILING_Y:
2036                 /* FIXME: Is this true? */
2037                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2038                 return -EINVAL;
2039         default:
2040                 BUG();
2041         }
2042
2043         dev_priv->mm.interruptible = false;
2044         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2045         if (ret)
2046                 goto err_interruptible;
2047
2048         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2049          * fence, whereas 965+ only requires a fence if using
2050          * framebuffer compression.  For simplicity, we always install
2051          * a fence as the cost is not that onerous.
2052          */
2053         if (obj->tiling_mode != I915_TILING_NONE) {
2054                 ret = i915_gem_object_get_fence(obj, pipelined);
2055                 if (ret)
2056                         goto err_unpin;
2057
2058                 i915_gem_object_pin_fence(obj);
2059         }
2060
2061         dev_priv->mm.interruptible = true;
2062         return 0;
2063
2064 err_unpin:
2065         i915_gem_object_unpin(obj);
2066 err_interruptible:
2067         dev_priv->mm.interruptible = true;
2068         return ret;
2069 }
2070
2071 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2072 {
2073         i915_gem_object_unpin_fence(obj);
2074         i915_gem_object_unpin(obj);
2075 }
2076
2077 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2078                              int x, int y)
2079 {
2080         struct drm_device *dev = crtc->dev;
2081         struct drm_i915_private *dev_priv = dev->dev_private;
2082         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2083         struct intel_framebuffer *intel_fb;
2084         struct drm_i915_gem_object *obj;
2085         int plane = intel_crtc->plane;
2086         unsigned long Start, Offset;
2087         u32 dspcntr;
2088         u32 reg;
2089
2090         switch (plane) {
2091         case 0:
2092         case 1:
2093                 break;
2094         default:
2095                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2096                 return -EINVAL;
2097         }
2098
2099         intel_fb = to_intel_framebuffer(fb);
2100         obj = intel_fb->obj;
2101
2102         reg = DSPCNTR(plane);
2103         dspcntr = I915_READ(reg);
2104         /* Mask out pixel format bits in case we change it */
2105         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2106         switch (fb->bits_per_pixel) {
2107         case 8:
2108                 dspcntr |= DISPPLANE_8BPP;
2109                 break;
2110         case 16:
2111                 if (fb->depth == 15)
2112                         dspcntr |= DISPPLANE_15_16BPP;
2113                 else
2114                         dspcntr |= DISPPLANE_16BPP;
2115                 break;
2116         case 24:
2117         case 32:
2118                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2119                 break;
2120         default:
2121                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2122                 return -EINVAL;
2123         }
2124         if (INTEL_INFO(dev)->gen >= 4) {
2125                 if (obj->tiling_mode != I915_TILING_NONE)
2126                         dspcntr |= DISPPLANE_TILED;
2127                 else
2128                         dspcntr &= ~DISPPLANE_TILED;
2129         }
2130
2131         I915_WRITE(reg, dspcntr);
2132
2133         Start = obj->gtt_offset;
2134         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2135
2136         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2137                       Start, Offset, x, y, fb->pitches[0]);
2138         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2139         if (INTEL_INFO(dev)->gen >= 4) {
2140                 I915_WRITE(DSPSURF(plane), Start);
2141                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2142                 I915_WRITE(DSPADDR(plane), Offset);
2143         } else
2144                 I915_WRITE(DSPADDR(plane), Start + Offset);
2145         POSTING_READ(reg);
2146
2147         return 0;
2148 }
2149
2150 static int ironlake_update_plane(struct drm_crtc *crtc,
2151                                  struct drm_framebuffer *fb, int x, int y)
2152 {
2153         struct drm_device *dev = crtc->dev;
2154         struct drm_i915_private *dev_priv = dev->dev_private;
2155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2156         struct intel_framebuffer *intel_fb;
2157         struct drm_i915_gem_object *obj;
2158         int plane = intel_crtc->plane;
2159         unsigned long Start, Offset;
2160         u32 dspcntr;
2161         u32 reg;
2162
2163         switch (plane) {
2164         case 0:
2165         case 1:
2166         case 2:
2167                 break;
2168         default:
2169                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2170                 return -EINVAL;
2171         }
2172
2173         intel_fb = to_intel_framebuffer(fb);
2174         obj = intel_fb->obj;
2175
2176         reg = DSPCNTR(plane);
2177         dspcntr = I915_READ(reg);
2178         /* Mask out pixel format bits in case we change it */
2179         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2180         switch (fb->bits_per_pixel) {
2181         case 8:
2182                 dspcntr |= DISPPLANE_8BPP;
2183                 break;
2184         case 16:
2185                 if (fb->depth != 16)
2186                         return -EINVAL;
2187
2188                 dspcntr |= DISPPLANE_16BPP;
2189                 break;
2190         case 24:
2191         case 32:
2192                 if (fb->depth == 24)
2193                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2194                 else if (fb->depth == 30)
2195                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2196                 else
2197                         return -EINVAL;
2198                 break;
2199         default:
2200                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2201                 return -EINVAL;
2202         }
2203
2204         if (obj->tiling_mode != I915_TILING_NONE)
2205                 dspcntr |= DISPPLANE_TILED;
2206         else
2207                 dspcntr &= ~DISPPLANE_TILED;
2208
2209         /* must disable */
2210         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2211
2212         I915_WRITE(reg, dspcntr);
2213
2214         Start = obj->gtt_offset;
2215         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2216
2217         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2218                       Start, Offset, x, y, fb->pitches[0]);
2219         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2220         I915_WRITE(DSPSURF(plane), Start);
2221         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2222         I915_WRITE(DSPADDR(plane), Offset);
2223         POSTING_READ(reg);
2224
2225         return 0;
2226 }
2227
2228 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2229 static int
2230 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2231                            int x, int y, enum mode_set_atomic state)
2232 {
2233         struct drm_device *dev = crtc->dev;
2234         struct drm_i915_private *dev_priv = dev->dev_private;
2235         int ret;
2236
2237         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2238         if (ret)
2239                 return ret;
2240
2241         intel_update_fbc(dev);
2242         intel_increase_pllclock(crtc);
2243
2244         return 0;
2245 }
2246
2247 static int
2248 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2249                     struct drm_framebuffer *old_fb)
2250 {
2251         struct drm_device *dev = crtc->dev;
2252         struct drm_i915_master_private *master_priv;
2253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2254         int ret;
2255
2256         /* no fb bound */
2257         if (!crtc->fb) {
2258                 DRM_ERROR("No FB bound\n");
2259                 return 0;
2260         }
2261
2262         switch (intel_crtc->plane) {
2263         case 0:
2264         case 1:
2265                 break;
2266         case 2:
2267                 if (IS_IVYBRIDGE(dev))
2268                         break;
2269                 /* fall through otherwise */
2270         default:
2271                 DRM_ERROR("no plane for crtc\n");
2272                 return -EINVAL;
2273         }
2274
2275         mutex_lock(&dev->struct_mutex);
2276         ret = intel_pin_and_fence_fb_obj(dev,
2277                                          to_intel_framebuffer(crtc->fb)->obj,
2278                                          NULL);
2279         if (ret != 0) {
2280                 mutex_unlock(&dev->struct_mutex);
2281                 DRM_ERROR("pin & fence failed\n");
2282                 return ret;
2283         }
2284
2285         if (old_fb) {
2286                 struct drm_i915_private *dev_priv = dev->dev_private;
2287                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2288
2289                 wait_event(dev_priv->pending_flip_queue,
2290                            atomic_read(&dev_priv->mm.wedged) ||
2291                            atomic_read(&obj->pending_flip) == 0);
2292
2293                 /* Big Hammer, we also need to ensure that any pending
2294                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2295                  * current scanout is retired before unpinning the old
2296                  * framebuffer.
2297                  *
2298                  * This should only fail upon a hung GPU, in which case we
2299                  * can safely continue.
2300                  */
2301                 ret = i915_gem_object_finish_gpu(obj);
2302                 (void) ret;
2303         }
2304
2305         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2306                                          LEAVE_ATOMIC_MODE_SET);
2307         if (ret) {
2308                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2309                 mutex_unlock(&dev->struct_mutex);
2310                 DRM_ERROR("failed to update base address\n");
2311                 return ret;
2312         }
2313
2314         if (old_fb) {
2315                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2316                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2317         }
2318
2319         mutex_unlock(&dev->struct_mutex);
2320
2321         if (!dev->primary->master)
2322                 return 0;
2323
2324         master_priv = dev->primary->master->driver_priv;
2325         if (!master_priv->sarea_priv)
2326                 return 0;
2327
2328         if (intel_crtc->pipe) {
2329                 master_priv->sarea_priv->pipeB_x = x;
2330                 master_priv->sarea_priv->pipeB_y = y;
2331         } else {
2332                 master_priv->sarea_priv->pipeA_x = x;
2333                 master_priv->sarea_priv->pipeA_y = y;
2334         }
2335
2336         return 0;
2337 }
2338
2339 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2340 {
2341         struct drm_device *dev = crtc->dev;
2342         struct drm_i915_private *dev_priv = dev->dev_private;
2343         u32 dpa_ctl;
2344
2345         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2346         dpa_ctl = I915_READ(DP_A);
2347         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2348
2349         if (clock < 200000) {
2350                 u32 temp;
2351                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2352                 /* workaround for 160Mhz:
2353                    1) program 0x4600c bits 15:0 = 0x8124
2354                    2) program 0x46010 bit 0 = 1
2355                    3) program 0x46034 bit 24 = 1
2356                    4) program 0x64000 bit 14 = 1
2357                    */
2358                 temp = I915_READ(0x4600c);
2359                 temp &= 0xffff0000;
2360                 I915_WRITE(0x4600c, temp | 0x8124);
2361
2362                 temp = I915_READ(0x46010);
2363                 I915_WRITE(0x46010, temp | 1);
2364
2365                 temp = I915_READ(0x46034);
2366                 I915_WRITE(0x46034, temp | (1 << 24));
2367         } else {
2368                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2369         }
2370         I915_WRITE(DP_A, dpa_ctl);
2371
2372         POSTING_READ(DP_A);
2373         udelay(500);
2374 }
2375
2376 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2377 {
2378         struct drm_device *dev = crtc->dev;
2379         struct drm_i915_private *dev_priv = dev->dev_private;
2380         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2381         int pipe = intel_crtc->pipe;
2382         u32 reg, temp;
2383
2384         /* enable normal train */
2385         reg = FDI_TX_CTL(pipe);
2386         temp = I915_READ(reg);
2387         if (IS_IVYBRIDGE(dev)) {
2388                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2389                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2390         } else {
2391                 temp &= ~FDI_LINK_TRAIN_NONE;
2392                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2393         }
2394         I915_WRITE(reg, temp);
2395
2396         reg = FDI_RX_CTL(pipe);
2397         temp = I915_READ(reg);
2398         if (HAS_PCH_CPT(dev)) {
2399                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2400                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2401         } else {
2402                 temp &= ~FDI_LINK_TRAIN_NONE;
2403                 temp |= FDI_LINK_TRAIN_NONE;
2404         }
2405         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2406
2407         /* wait one idle pattern time */
2408         POSTING_READ(reg);
2409         udelay(1000);
2410
2411         /* IVB wants error correction enabled */
2412         if (IS_IVYBRIDGE(dev))
2413                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2414                            FDI_FE_ERRC_ENABLE);
2415 }
2416
2417 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2418 {
2419         struct drm_i915_private *dev_priv = dev->dev_private;
2420         u32 flags = I915_READ(SOUTH_CHICKEN1);
2421
2422         flags |= FDI_PHASE_SYNC_OVR(pipe);
2423         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2424         flags |= FDI_PHASE_SYNC_EN(pipe);
2425         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2426         POSTING_READ(SOUTH_CHICKEN1);
2427 }
2428
2429 /* The FDI link training functions for ILK/Ibexpeak. */
2430 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2431 {
2432         struct drm_device *dev = crtc->dev;
2433         struct drm_i915_private *dev_priv = dev->dev_private;
2434         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2435         int pipe = intel_crtc->pipe;
2436         int plane = intel_crtc->plane;
2437         u32 reg, temp, tries;
2438
2439         /* FDI needs bits from pipe & plane first */
2440         assert_pipe_enabled(dev_priv, pipe);
2441         assert_plane_enabled(dev_priv, plane);
2442
2443         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2444            for train result */
2445         reg = FDI_RX_IMR(pipe);
2446         temp = I915_READ(reg);
2447         temp &= ~FDI_RX_SYMBOL_LOCK;
2448         temp &= ~FDI_RX_BIT_LOCK;
2449         I915_WRITE(reg, temp);
2450         I915_READ(reg);
2451         udelay(150);
2452
2453         /* enable CPU FDI TX and PCH FDI RX */
2454         reg = FDI_TX_CTL(pipe);
2455         temp = I915_READ(reg);
2456         temp &= ~(7 << 19);
2457         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2458         temp &= ~FDI_LINK_TRAIN_NONE;
2459         temp |= FDI_LINK_TRAIN_PATTERN_1;
2460         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2461
2462         reg = FDI_RX_CTL(pipe);
2463         temp = I915_READ(reg);
2464         temp &= ~FDI_LINK_TRAIN_NONE;
2465         temp |= FDI_LINK_TRAIN_PATTERN_1;
2466         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2467
2468         POSTING_READ(reg);
2469         udelay(150);
2470
2471         /* Ironlake workaround, enable clock pointer after FDI enable*/
2472         if (HAS_PCH_IBX(dev)) {
2473                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2474                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2475                            FDI_RX_PHASE_SYNC_POINTER_EN);
2476         }
2477
2478         reg = FDI_RX_IIR(pipe);
2479         for (tries = 0; tries < 5; tries++) {
2480                 temp = I915_READ(reg);
2481                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2482
2483                 if ((temp & FDI_RX_BIT_LOCK)) {
2484                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2485                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2486                         break;
2487                 }
2488         }
2489         if (tries == 5)
2490                 DRM_ERROR("FDI train 1 fail!\n");
2491
2492         /* Train 2 */
2493         reg = FDI_TX_CTL(pipe);
2494         temp = I915_READ(reg);
2495         temp &= ~FDI_LINK_TRAIN_NONE;
2496         temp |= FDI_LINK_TRAIN_PATTERN_2;
2497         I915_WRITE(reg, temp);
2498
2499         reg = FDI_RX_CTL(pipe);
2500         temp = I915_READ(reg);
2501         temp &= ~FDI_LINK_TRAIN_NONE;
2502         temp |= FDI_LINK_TRAIN_PATTERN_2;
2503         I915_WRITE(reg, temp);
2504
2505         POSTING_READ(reg);
2506         udelay(150);
2507
2508         reg = FDI_RX_IIR(pipe);
2509         for (tries = 0; tries < 5; tries++) {
2510                 temp = I915_READ(reg);
2511                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2512
2513                 if (temp & FDI_RX_SYMBOL_LOCK) {
2514                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2515                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2516                         break;
2517                 }
2518         }
2519         if (tries == 5)
2520                 DRM_ERROR("FDI train 2 fail!\n");
2521
2522         DRM_DEBUG_KMS("FDI train done\n");
2523
2524 }
2525
2526 static const int snb_b_fdi_train_param[] = {
2527         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2528         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2529         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2530         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2531 };
2532
2533 /* The FDI link training functions for SNB/Cougarpoint. */
2534 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2535 {
2536         struct drm_device *dev = crtc->dev;
2537         struct drm_i915_private *dev_priv = dev->dev_private;
2538         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2539         int pipe = intel_crtc->pipe;
2540         u32 reg, temp, i;
2541
2542         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2543            for train result */
2544         reg = FDI_RX_IMR(pipe);
2545         temp = I915_READ(reg);
2546         temp &= ~FDI_RX_SYMBOL_LOCK;
2547         temp &= ~FDI_RX_BIT_LOCK;
2548         I915_WRITE(reg, temp);
2549
2550         POSTING_READ(reg);
2551         udelay(150);
2552
2553         /* enable CPU FDI TX and PCH FDI RX */
2554         reg = FDI_TX_CTL(pipe);
2555         temp = I915_READ(reg);
2556         temp &= ~(7 << 19);
2557         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2558         temp &= ~FDI_LINK_TRAIN_NONE;
2559         temp |= FDI_LINK_TRAIN_PATTERN_1;
2560         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2561         /* SNB-B */
2562         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2563         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2564
2565         reg = FDI_RX_CTL(pipe);
2566         temp = I915_READ(reg);
2567         if (HAS_PCH_CPT(dev)) {
2568                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2569                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2570         } else {
2571                 temp &= ~FDI_LINK_TRAIN_NONE;
2572                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2573         }
2574         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2575
2576         POSTING_READ(reg);
2577         udelay(150);
2578
2579         if (HAS_PCH_CPT(dev))
2580                 cpt_phase_pointer_enable(dev, pipe);
2581
2582         for (i = 0; i < 4; i++) {
2583                 reg = FDI_TX_CTL(pipe);
2584                 temp = I915_READ(reg);
2585                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2586                 temp |= snb_b_fdi_train_param[i];
2587                 I915_WRITE(reg, temp);
2588
2589                 POSTING_READ(reg);
2590                 udelay(500);
2591
2592                 reg = FDI_RX_IIR(pipe);
2593                 temp = I915_READ(reg);
2594                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2595
2596                 if (temp & FDI_RX_BIT_LOCK) {
2597                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2598                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2599                         break;
2600                 }
2601         }
2602         if (i == 4)
2603                 DRM_ERROR("FDI train 1 fail!\n");
2604
2605         /* Train 2 */
2606         reg = FDI_TX_CTL(pipe);
2607         temp = I915_READ(reg);
2608         temp &= ~FDI_LINK_TRAIN_NONE;
2609         temp |= FDI_LINK_TRAIN_PATTERN_2;
2610         if (IS_GEN6(dev)) {
2611                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2612                 /* SNB-B */
2613                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2614         }
2615         I915_WRITE(reg, temp);
2616
2617         reg = FDI_RX_CTL(pipe);
2618         temp = I915_READ(reg);
2619         if (HAS_PCH_CPT(dev)) {
2620                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2621                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2622         } else {
2623                 temp &= ~FDI_LINK_TRAIN_NONE;
2624                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2625         }
2626         I915_WRITE(reg, temp);
2627
2628         POSTING_READ(reg);
2629         udelay(150);
2630
2631         for (i = 0; i < 4; i++) {
2632                 reg = FDI_TX_CTL(pipe);
2633                 temp = I915_READ(reg);
2634                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2635                 temp |= snb_b_fdi_train_param[i];
2636                 I915_WRITE(reg, temp);
2637
2638                 POSTING_READ(reg);
2639                 udelay(500);
2640
2641                 reg = FDI_RX_IIR(pipe);
2642                 temp = I915_READ(reg);
2643                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2644
2645                 if (temp & FDI_RX_SYMBOL_LOCK) {
2646                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2647                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2648                         break;
2649                 }
2650         }
2651         if (i == 4)
2652                 DRM_ERROR("FDI train 2 fail!\n");
2653
2654         DRM_DEBUG_KMS("FDI train done.\n");
2655 }
2656
2657 /* Manual link training for Ivy Bridge A0 parts */
2658 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2659 {
2660         struct drm_device *dev = crtc->dev;
2661         struct drm_i915_private *dev_priv = dev->dev_private;
2662         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2663         int pipe = intel_crtc->pipe;
2664         u32 reg, temp, i;
2665
2666         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2667            for train result */
2668         reg = FDI_RX_IMR(pipe);
2669         temp = I915_READ(reg);
2670         temp &= ~FDI_RX_SYMBOL_LOCK;
2671         temp &= ~FDI_RX_BIT_LOCK;
2672         I915_WRITE(reg, temp);
2673
2674         POSTING_READ(reg);
2675         udelay(150);
2676
2677         /* enable CPU FDI TX and PCH FDI RX */
2678         reg = FDI_TX_CTL(pipe);
2679         temp = I915_READ(reg);
2680         temp &= ~(7 << 19);
2681         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2682         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2683         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2684         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2685         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2686         temp |= FDI_COMPOSITE_SYNC;
2687         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2688
2689         reg = FDI_RX_CTL(pipe);
2690         temp = I915_READ(reg);
2691         temp &= ~FDI_LINK_TRAIN_AUTO;
2692         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2693         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2694         temp |= FDI_COMPOSITE_SYNC;
2695         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2696
2697         POSTING_READ(reg);
2698         udelay(150);
2699
2700         if (HAS_PCH_CPT(dev))
2701                 cpt_phase_pointer_enable(dev, pipe);
2702
2703         for (i = 0; i < 4; i++) {
2704                 reg = FDI_TX_CTL(pipe);
2705                 temp = I915_READ(reg);
2706                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2707                 temp |= snb_b_fdi_train_param[i];
2708                 I915_WRITE(reg, temp);
2709
2710                 POSTING_READ(reg);
2711                 udelay(500);
2712
2713                 reg = FDI_RX_IIR(pipe);
2714                 temp = I915_READ(reg);
2715                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2716
2717                 if (temp & FDI_RX_BIT_LOCK ||
2718                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2719                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2720                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2721                         break;
2722                 }
2723         }
2724         if (i == 4)
2725                 DRM_ERROR("FDI train 1 fail!\n");
2726
2727         /* Train 2 */
2728         reg = FDI_TX_CTL(pipe);
2729         temp = I915_READ(reg);
2730         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2731         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2732         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2733         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2734         I915_WRITE(reg, temp);
2735
2736         reg = FDI_RX_CTL(pipe);
2737         temp = I915_READ(reg);
2738         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2739         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2740         I915_WRITE(reg, temp);
2741
2742         POSTING_READ(reg);
2743         udelay(150);
2744
2745         for (i = 0; i < 4; i++) {
2746                 reg = FDI_TX_CTL(pipe);
2747                 temp = I915_READ(reg);
2748                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2749                 temp |= snb_b_fdi_train_param[i];
2750                 I915_WRITE(reg, temp);
2751
2752                 POSTING_READ(reg);
2753                 udelay(500);
2754
2755                 reg = FDI_RX_IIR(pipe);
2756                 temp = I915_READ(reg);
2757                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2758
2759                 if (temp & FDI_RX_SYMBOL_LOCK) {
2760                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2761                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2762                         break;
2763                 }
2764         }
2765         if (i == 4)
2766                 DRM_ERROR("FDI train 2 fail!\n");
2767
2768         DRM_DEBUG_KMS("FDI train done.\n");
2769 }
2770
2771 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2772 {
2773         struct drm_device *dev = crtc->dev;
2774         struct drm_i915_private *dev_priv = dev->dev_private;
2775         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2776         int pipe = intel_crtc->pipe;
2777         u32 reg, temp;
2778
2779         /* Write the TU size bits so error detection works */
2780         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2781                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2782
2783         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2784         reg = FDI_RX_CTL(pipe);
2785         temp = I915_READ(reg);
2786         temp &= ~((0x7 << 19) | (0x7 << 16));
2787         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2788         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2789         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2790
2791         POSTING_READ(reg);
2792         udelay(200);
2793
2794         /* Switch from Rawclk to PCDclk */
2795         temp = I915_READ(reg);
2796         I915_WRITE(reg, temp | FDI_PCDCLK);
2797
2798         POSTING_READ(reg);
2799         udelay(200);
2800
2801         /* Enable CPU FDI TX PLL, always on for Ironlake */
2802         reg = FDI_TX_CTL(pipe);
2803         temp = I915_READ(reg);
2804         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2805                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2806
2807                 POSTING_READ(reg);
2808                 udelay(100);
2809         }
2810 }
2811
2812 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2813 {
2814         struct drm_i915_private *dev_priv = dev->dev_private;
2815         u32 flags = I915_READ(SOUTH_CHICKEN1);
2816
2817         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2818         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2819         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2820         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2821         POSTING_READ(SOUTH_CHICKEN1);
2822 }
2823 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2824 {
2825         struct drm_device *dev = crtc->dev;
2826         struct drm_i915_private *dev_priv = dev->dev_private;
2827         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2828         int pipe = intel_crtc->pipe;
2829         u32 reg, temp;
2830
2831         /* disable CPU FDI tx and PCH FDI rx */
2832         reg = FDI_TX_CTL(pipe);
2833         temp = I915_READ(reg);
2834         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2835         POSTING_READ(reg);
2836
2837         reg = FDI_RX_CTL(pipe);
2838         temp = I915_READ(reg);
2839         temp &= ~(0x7 << 16);
2840         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2841         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2842
2843         POSTING_READ(reg);
2844         udelay(100);
2845
2846         /* Ironlake workaround, disable clock pointer after downing FDI */
2847         if (HAS_PCH_IBX(dev)) {
2848                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2849                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2850                            I915_READ(FDI_RX_CHICKEN(pipe) &
2851                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2852         } else if (HAS_PCH_CPT(dev)) {
2853                 cpt_phase_pointer_disable(dev, pipe);
2854         }
2855
2856         /* still set train pattern 1 */
2857         reg = FDI_TX_CTL(pipe);
2858         temp = I915_READ(reg);
2859         temp &= ~FDI_LINK_TRAIN_NONE;
2860         temp |= FDI_LINK_TRAIN_PATTERN_1;
2861         I915_WRITE(reg, temp);
2862
2863         reg = FDI_RX_CTL(pipe);
2864         temp = I915_READ(reg);
2865         if (HAS_PCH_CPT(dev)) {
2866                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2867                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2868         } else {
2869                 temp &= ~FDI_LINK_TRAIN_NONE;
2870                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2871         }
2872         /* BPC in FDI rx is consistent with that in PIPECONF */
2873         temp &= ~(0x07 << 16);
2874         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2875         I915_WRITE(reg, temp);
2876
2877         POSTING_READ(reg);
2878         udelay(100);
2879 }
2880
2881 /*
2882  * When we disable a pipe, we need to clear any pending scanline wait events
2883  * to avoid hanging the ring, which we assume we are waiting on.
2884  */
2885 static void intel_clear_scanline_wait(struct drm_device *dev)
2886 {
2887         struct drm_i915_private *dev_priv = dev->dev_private;
2888         struct intel_ring_buffer *ring;
2889         u32 tmp;
2890
2891         if (IS_GEN2(dev))
2892                 /* Can't break the hang on i8xx */
2893                 return;
2894
2895         ring = LP_RING(dev_priv);
2896         tmp = I915_READ_CTL(ring);
2897         if (tmp & RING_WAIT)
2898                 I915_WRITE_CTL(ring, tmp);
2899 }
2900
2901 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2902 {
2903         struct drm_i915_gem_object *obj;
2904         struct drm_i915_private *dev_priv;
2905
2906         if (crtc->fb == NULL)
2907                 return;
2908
2909         obj = to_intel_framebuffer(crtc->fb)->obj;
2910         dev_priv = crtc->dev->dev_private;
2911         wait_event(dev_priv->pending_flip_queue,
2912                    atomic_read(&obj->pending_flip) == 0);
2913 }
2914
2915 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2916 {
2917         struct drm_device *dev = crtc->dev;
2918         struct drm_mode_config *mode_config = &dev->mode_config;
2919         struct intel_encoder *encoder;
2920
2921         /*
2922          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2923          * must be driven by its own crtc; no sharing is possible.
2924          */
2925         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2926                 if (encoder->base.crtc != crtc)
2927                         continue;
2928
2929                 switch (encoder->type) {
2930                 case INTEL_OUTPUT_EDP:
2931                         if (!intel_encoder_is_pch_edp(&encoder->base))
2932                                 return false;
2933                         continue;
2934                 }
2935         }
2936
2937         return true;
2938 }
2939
2940 /*
2941  * Enable PCH resources required for PCH ports:
2942  *   - PCH PLLs
2943  *   - FDI training & RX/TX
2944  *   - update transcoder timings
2945  *   - DP transcoding bits
2946  *   - transcoder
2947  */
2948 static void ironlake_pch_enable(struct drm_crtc *crtc)
2949 {
2950         struct drm_device *dev = crtc->dev;
2951         struct drm_i915_private *dev_priv = dev->dev_private;
2952         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2953         int pipe = intel_crtc->pipe;
2954         u32 reg, temp, transc_sel;
2955
2956         /* For PCH output, training FDI link */
2957         dev_priv->display.fdi_link_train(crtc);
2958
2959         intel_enable_pch_pll(dev_priv, pipe);
2960
2961         if (HAS_PCH_CPT(dev)) {
2962                 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2963                         TRANSC_DPLLB_SEL;
2964
2965                 /* Be sure PCH DPLL SEL is set */
2966                 temp = I915_READ(PCH_DPLL_SEL);
2967                 if (pipe == 0) {
2968                         temp &= ~(TRANSA_DPLLB_SEL);
2969                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2970                 } else if (pipe == 1) {
2971                         temp &= ~(TRANSB_DPLLB_SEL);
2972                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2973                 } else if (pipe == 2) {
2974                         temp &= ~(TRANSC_DPLLB_SEL);
2975                         temp |= (TRANSC_DPLL_ENABLE | transc_sel);
2976                 }
2977                 I915_WRITE(PCH_DPLL_SEL, temp);
2978         }
2979
2980         /* set transcoder timing, panel must allow it */
2981         assert_panel_unlocked(dev_priv, pipe);
2982         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2983         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2984         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2985
2986         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2987         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2988         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2989         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
2990
2991         intel_fdi_normal_train(crtc);
2992
2993         /* For PCH DP, enable TRANS_DP_CTL */
2994         if (HAS_PCH_CPT(dev) &&
2995             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2996              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2997                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2998                 reg = TRANS_DP_CTL(pipe);
2999                 temp = I915_READ(reg);
3000                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3001                           TRANS_DP_SYNC_MASK |
3002                           TRANS_DP_BPC_MASK);
3003                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3004                          TRANS_DP_ENH_FRAMING);
3005                 temp |= bpc << 9; /* same format but at 11:9 */
3006
3007                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3008                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3009                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3010                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3011
3012                 switch (intel_trans_dp_port_sel(crtc)) {
3013                 case PCH_DP_B:
3014                         temp |= TRANS_DP_PORT_SEL_B;
3015                         break;
3016                 case PCH_DP_C:
3017                         temp |= TRANS_DP_PORT_SEL_C;
3018                         break;
3019                 case PCH_DP_D:
3020                         temp |= TRANS_DP_PORT_SEL_D;
3021                         break;
3022                 default:
3023                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3024                         temp |= TRANS_DP_PORT_SEL_B;
3025                         break;
3026                 }
3027
3028                 I915_WRITE(reg, temp);
3029         }
3030
3031         intel_enable_transcoder(dev_priv, pipe);
3032 }
3033
3034 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3035 {
3036         struct drm_i915_private *dev_priv = dev->dev_private;
3037         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3038         u32 temp;
3039
3040         temp = I915_READ(dslreg);
3041         udelay(500);
3042         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3043                 /* Without this, mode sets may fail silently on FDI */
3044                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3045                 udelay(250);
3046                 I915_WRITE(tc2reg, 0);
3047                 if (wait_for(I915_READ(dslreg) != temp, 5))
3048                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3049         }
3050 }
3051
3052 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3053 {
3054         struct drm_device *dev = crtc->dev;
3055         struct drm_i915_private *dev_priv = dev->dev_private;
3056         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3057         int pipe = intel_crtc->pipe;
3058         int plane = intel_crtc->plane;
3059         u32 temp;
3060         bool is_pch_port;
3061
3062         if (intel_crtc->active)
3063                 return;
3064
3065         intel_crtc->active = true;
3066         intel_update_watermarks(dev);
3067
3068         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3069                 temp = I915_READ(PCH_LVDS);
3070                 if ((temp & LVDS_PORT_EN) == 0)
3071                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3072         }
3073
3074         is_pch_port = intel_crtc_driving_pch(crtc);
3075
3076         if (is_pch_port)
3077                 ironlake_fdi_pll_enable(crtc);
3078         else
3079                 ironlake_fdi_disable(crtc);
3080
3081         /* Enable panel fitting for LVDS */
3082         if (dev_priv->pch_pf_size &&
3083             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3084                 /* Force use of hard-coded filter coefficients
3085                  * as some pre-programmed values are broken,
3086                  * e.g. x201.
3087                  */
3088                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3089                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3090                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3091         }
3092
3093         /*
3094          * On ILK+ LUT must be loaded before the pipe is running but with
3095          * clocks enabled
3096          */
3097         intel_crtc_load_lut(crtc);
3098
3099         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3100         intel_enable_plane(dev_priv, plane, pipe);
3101
3102         if (is_pch_port)
3103                 ironlake_pch_enable(crtc);
3104
3105         mutex_lock(&dev->struct_mutex);
3106         intel_update_fbc(dev);
3107         mutex_unlock(&dev->struct_mutex);
3108
3109         intel_crtc_update_cursor(crtc, true);
3110 }
3111
3112 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3113 {
3114         struct drm_device *dev = crtc->dev;
3115         struct drm_i915_private *dev_priv = dev->dev_private;
3116         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3117         int pipe = intel_crtc->pipe;
3118         int plane = intel_crtc->plane;
3119         u32 reg, temp;
3120
3121         if (!intel_crtc->active)
3122                 return;
3123
3124         intel_crtc_wait_for_pending_flips(crtc);
3125         drm_vblank_off(dev, pipe);
3126         intel_crtc_update_cursor(crtc, false);
3127
3128         intel_disable_plane(dev_priv, plane, pipe);
3129
3130         if (dev_priv->cfb_plane == plane)
3131                 intel_disable_fbc(dev);
3132
3133         intel_disable_pipe(dev_priv, pipe);
3134
3135         /* Disable PF */
3136         I915_WRITE(PF_CTL(pipe), 0);
3137         I915_WRITE(PF_WIN_SZ(pipe), 0);
3138
3139         ironlake_fdi_disable(crtc);
3140
3141         /* This is a horrible layering violation; we should be doing this in
3142          * the connector/encoder ->prepare instead, but we don't always have
3143          * enough information there about the config to know whether it will
3144          * actually be necessary or just cause undesired flicker.
3145          */
3146         intel_disable_pch_ports(dev_priv, pipe);
3147
3148         intel_disable_transcoder(dev_priv, pipe);
3149
3150         if (HAS_PCH_CPT(dev)) {
3151                 /* disable TRANS_DP_CTL */
3152                 reg = TRANS_DP_CTL(pipe);
3153                 temp = I915_READ(reg);
3154                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3155                 temp |= TRANS_DP_PORT_SEL_NONE;
3156                 I915_WRITE(reg, temp);
3157
3158                 /* disable DPLL_SEL */
3159                 temp = I915_READ(PCH_DPLL_SEL);
3160                 switch (pipe) {
3161                 case 0:
3162                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3163                         break;
3164                 case 1:
3165                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3166                         break;
3167                 case 2:
3168                         /* C shares PLL A or B */
3169                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3170                         break;
3171                 default:
3172                         BUG(); /* wtf */
3173                 }
3174                 I915_WRITE(PCH_DPLL_SEL, temp);
3175         }
3176
3177         /* disable PCH DPLL */
3178         if (!intel_crtc->no_pll)
3179                 intel_disable_pch_pll(dev_priv, pipe);
3180
3181         /* Switch from PCDclk to Rawclk */
3182         reg = FDI_RX_CTL(pipe);
3183         temp = I915_READ(reg);
3184         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3185
3186         /* Disable CPU FDI TX PLL */
3187         reg = FDI_TX_CTL(pipe);
3188         temp = I915_READ(reg);
3189         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3190
3191         POSTING_READ(reg);
3192         udelay(100);
3193
3194         reg = FDI_RX_CTL(pipe);
3195         temp = I915_READ(reg);
3196         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3197
3198         /* Wait for the clocks to turn off. */
3199         POSTING_READ(reg);
3200         udelay(100);
3201
3202         intel_crtc->active = false;
3203         intel_update_watermarks(dev);
3204
3205         mutex_lock(&dev->struct_mutex);
3206         intel_update_fbc(dev);
3207         intel_clear_scanline_wait(dev);
3208         mutex_unlock(&dev->struct_mutex);
3209 }
3210
3211 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3212 {
3213         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3214         int pipe = intel_crtc->pipe;
3215         int plane = intel_crtc->plane;
3216
3217         /* XXX: When our outputs are all unaware of DPMS modes other than off
3218          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3219          */
3220         switch (mode) {
3221         case DRM_MODE_DPMS_ON:
3222         case DRM_MODE_DPMS_STANDBY:
3223         case DRM_MODE_DPMS_SUSPEND:
3224                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3225                 ironlake_crtc_enable(crtc);
3226                 break;
3227
3228         case DRM_MODE_DPMS_OFF:
3229                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3230                 ironlake_crtc_disable(crtc);
3231                 break;
3232         }
3233 }
3234
3235 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3236 {
3237         if (!enable && intel_crtc->overlay) {
3238                 struct drm_device *dev = intel_crtc->base.dev;
3239                 struct drm_i915_private *dev_priv = dev->dev_private;
3240
3241                 mutex_lock(&dev->struct_mutex);
3242                 dev_priv->mm.interruptible = false;
3243                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3244                 dev_priv->mm.interruptible = true;
3245                 mutex_unlock(&dev->struct_mutex);
3246         }
3247
3248         /* Let userspace switch the overlay on again. In most cases userspace
3249          * has to recompute where to put it anyway.
3250          */
3251 }
3252
3253 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3254 {
3255         struct drm_device *dev = crtc->dev;
3256         struct drm_i915_private *dev_priv = dev->dev_private;
3257         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3258         int pipe = intel_crtc->pipe;
3259         int plane = intel_crtc->plane;
3260
3261         if (intel_crtc->active)
3262                 return;
3263
3264         intel_crtc->active = true;
3265         intel_update_watermarks(dev);
3266
3267         intel_enable_pll(dev_priv, pipe);
3268         intel_enable_pipe(dev_priv, pipe, false);
3269         intel_enable_plane(dev_priv, plane, pipe);
3270
3271         intel_crtc_load_lut(crtc);
3272         intel_update_fbc(dev);
3273
3274         /* Give the overlay scaler a chance to enable if it's on this pipe */
3275         intel_crtc_dpms_overlay(intel_crtc, true);
3276         intel_crtc_update_cursor(crtc, true);
3277 }
3278
3279 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3280 {
3281         struct drm_device *dev = crtc->dev;
3282         struct drm_i915_private *dev_priv = dev->dev_private;
3283         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3284         int pipe = intel_crtc->pipe;
3285         int plane = intel_crtc->plane;
3286
3287         if (!intel_crtc->active)
3288                 return;
3289
3290         /* Give the overlay scaler a chance to disable if it's on this pipe */
3291         intel_crtc_wait_for_pending_flips(crtc);
3292         drm_vblank_off(dev, pipe);
3293         intel_crtc_dpms_overlay(intel_crtc, false);
3294         intel_crtc_update_cursor(crtc, false);
3295
3296         if (dev_priv->cfb_plane == plane)
3297                 intel_disable_fbc(dev);
3298
3299         intel_disable_plane(dev_priv, plane, pipe);
3300         intel_disable_pipe(dev_priv, pipe);
3301         intel_disable_pll(dev_priv, pipe);
3302
3303         intel_crtc->active = false;
3304         intel_update_fbc(dev);
3305         intel_update_watermarks(dev);
3306         intel_clear_scanline_wait(dev);
3307 }
3308
3309 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3310 {
3311         /* XXX: When our outputs are all unaware of DPMS modes other than off
3312          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3313          */
3314         switch (mode) {
3315         case DRM_MODE_DPMS_ON:
3316         case DRM_MODE_DPMS_STANDBY:
3317         case DRM_MODE_DPMS_SUSPEND:
3318                 i9xx_crtc_enable(crtc);
3319                 break;
3320         case DRM_MODE_DPMS_OFF:
3321                 i9xx_crtc_disable(crtc);
3322                 break;
3323         }
3324 }
3325
3326 /**
3327  * Sets the power management mode of the pipe and plane.
3328  */
3329 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3330 {
3331         struct drm_device *dev = crtc->dev;
3332         struct drm_i915_private *dev_priv = dev->dev_private;
3333         struct drm_i915_master_private *master_priv;
3334         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3335         int pipe = intel_crtc->pipe;
3336         bool enabled;
3337
3338         if (intel_crtc->dpms_mode == mode)
3339                 return;
3340
3341         intel_crtc->dpms_mode = mode;
3342
3343         dev_priv->display.dpms(crtc, mode);
3344
3345         if (!dev->primary->master)
3346                 return;
3347
3348         master_priv = dev->primary->master->driver_priv;
3349         if (!master_priv->sarea_priv)
3350                 return;
3351
3352         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3353
3354         switch (pipe) {
3355         case 0:
3356                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3357                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3358                 break;
3359         case 1:
3360                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3361                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3362                 break;
3363         default:
3364                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3365                 break;
3366         }
3367 }
3368
3369 static void intel_crtc_disable(struct drm_crtc *crtc)
3370 {
3371         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3372         struct drm_device *dev = crtc->dev;
3373
3374         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3375         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3376         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3377
3378         if (crtc->fb) {
3379                 mutex_lock(&dev->struct_mutex);
3380                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3381                 mutex_unlock(&dev->struct_mutex);
3382         }
3383 }
3384
3385 /* Prepare for a mode set.
3386  *
3387  * Note we could be a lot smarter here.  We need to figure out which outputs
3388  * will be enabled, which disabled (in short, how the config will changes)
3389  * and perform the minimum necessary steps to accomplish that, e.g. updating
3390  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3391  * panel fitting is in the proper state, etc.
3392  */
3393 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3394 {
3395         i9xx_crtc_disable(crtc);
3396 }
3397
3398 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3399 {
3400         i9xx_crtc_enable(crtc);
3401 }
3402
3403 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3404 {
3405         ironlake_crtc_disable(crtc);
3406 }
3407
3408 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3409 {
3410         ironlake_crtc_enable(crtc);
3411 }
3412
3413 void intel_encoder_prepare(struct drm_encoder *encoder)
3414 {
3415         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3416         /* lvds has its own version of prepare see intel_lvds_prepare */
3417         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3418 }
3419
3420 void intel_encoder_commit(struct drm_encoder *encoder)
3421 {
3422         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3423         struct drm_device *dev = encoder->dev;
3424         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3425         struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3426
3427         /* lvds has its own version of commit see intel_lvds_commit */
3428         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3429
3430         if (HAS_PCH_CPT(dev))
3431                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3432 }
3433
3434 void intel_encoder_destroy(struct drm_encoder *encoder)
3435 {
3436         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3437
3438         drm_encoder_cleanup(encoder);
3439         kfree(intel_encoder);
3440 }
3441
3442 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3443                                   struct drm_display_mode *mode,
3444                                   struct drm_display_mode *adjusted_mode)
3445 {
3446         struct drm_device *dev = crtc->dev;
3447
3448         if (HAS_PCH_SPLIT(dev)) {
3449                 /* FDI link clock is fixed at 2.7G */
3450                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3451                         return false;
3452         }
3453
3454         /* All interlaced capable intel hw wants timings in frames. */
3455         drm_mode_set_crtcinfo(adjusted_mode, 0);
3456
3457         return true;
3458 }
3459
3460 static int i945_get_display_clock_speed(struct drm_device *dev)
3461 {
3462         return 400000;
3463 }
3464
3465 static int i915_get_display_clock_speed(struct drm_device *dev)
3466 {
3467         return 333000;
3468 }
3469
3470 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3471 {
3472         return 200000;
3473 }
3474
3475 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3476 {
3477         u16 gcfgc = 0;
3478
3479         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3480
3481         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3482                 return 133000;
3483         else {
3484                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3485                 case GC_DISPLAY_CLOCK_333_MHZ:
3486                         return 333000;
3487                 default:
3488                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3489                         return 190000;
3490                 }
3491         }
3492 }
3493
3494 static int i865_get_display_clock_speed(struct drm_device *dev)
3495 {
3496         return 266000;
3497 }
3498
3499 static int i855_get_display_clock_speed(struct drm_device *dev)
3500 {
3501         u16 hpllcc = 0;
3502         /* Assume that the hardware is in the high speed state.  This
3503          * should be the default.
3504          */
3505         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3506         case GC_CLOCK_133_200:
3507         case GC_CLOCK_100_200:
3508                 return 200000;
3509         case GC_CLOCK_166_250:
3510                 return 250000;
3511         case GC_CLOCK_100_133:
3512                 return 133000;
3513         }
3514
3515         /* Shouldn't happen */
3516         return 0;
3517 }
3518
3519 static int i830_get_display_clock_speed(struct drm_device *dev)
3520 {
3521         return 133000;
3522 }
3523
3524 struct fdi_m_n {
3525         u32        tu;
3526         u32        gmch_m;
3527         u32        gmch_n;
3528         u32        link_m;
3529         u32        link_n;
3530 };
3531
3532 static void
3533 fdi_reduce_ratio(u32 *num, u32 *den)
3534 {
3535         while (*num > 0xffffff || *den > 0xffffff) {
3536                 *num >>= 1;
3537                 *den >>= 1;
3538         }
3539 }
3540
3541 static void
3542 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3543                      int link_clock, struct fdi_m_n *m_n)
3544 {
3545         m_n->tu = 64; /* default size */
3546
3547         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3548         m_n->gmch_m = bits_per_pixel * pixel_clock;
3549         m_n->gmch_n = link_clock * nlanes * 8;
3550         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3551
3552         m_n->link_m = pixel_clock;
3553         m_n->link_n = link_clock;
3554         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3555 }
3556
3557
3558 struct intel_watermark_params {
3559         unsigned long fifo_size;
3560         unsigned long max_wm;
3561         unsigned long default_wm;
3562         unsigned long guard_size;
3563         unsigned long cacheline_size;
3564 };
3565
3566 /* Pineview has different values for various configs */
3567 static const struct intel_watermark_params pineview_display_wm = {
3568         PINEVIEW_DISPLAY_FIFO,
3569         PINEVIEW_MAX_WM,
3570         PINEVIEW_DFT_WM,
3571         PINEVIEW_GUARD_WM,
3572         PINEVIEW_FIFO_LINE_SIZE
3573 };
3574 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3575         PINEVIEW_DISPLAY_FIFO,
3576         PINEVIEW_MAX_WM,
3577         PINEVIEW_DFT_HPLLOFF_WM,
3578         PINEVIEW_GUARD_WM,
3579         PINEVIEW_FIFO_LINE_SIZE
3580 };
3581 static const struct intel_watermark_params pineview_cursor_wm = {
3582         PINEVIEW_CURSOR_FIFO,
3583         PINEVIEW_CURSOR_MAX_WM,
3584         PINEVIEW_CURSOR_DFT_WM,
3585         PINEVIEW_CURSOR_GUARD_WM,
3586         PINEVIEW_FIFO_LINE_SIZE,
3587 };
3588 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3589         PINEVIEW_CURSOR_FIFO,
3590         PINEVIEW_CURSOR_MAX_WM,
3591         PINEVIEW_CURSOR_DFT_WM,
3592         PINEVIEW_CURSOR_GUARD_WM,
3593         PINEVIEW_FIFO_LINE_SIZE
3594 };
3595 static const struct intel_watermark_params g4x_wm_info = {
3596         G4X_FIFO_SIZE,
3597         G4X_MAX_WM,
3598         G4X_MAX_WM,
3599         2,
3600         G4X_FIFO_LINE_SIZE,
3601 };
3602 static const struct intel_watermark_params g4x_cursor_wm_info = {
3603         I965_CURSOR_FIFO,
3604         I965_CURSOR_MAX_WM,
3605         I965_CURSOR_DFT_WM,
3606         2,
3607         G4X_FIFO_LINE_SIZE,
3608 };
3609 static const struct intel_watermark_params i965_cursor_wm_info = {
3610         I965_CURSOR_FIFO,
3611         I965_CURSOR_MAX_WM,
3612         I965_CURSOR_DFT_WM,
3613         2,
3614         I915_FIFO_LINE_SIZE,
3615 };
3616 static const struct intel_watermark_params i945_wm_info = {
3617         I945_FIFO_SIZE,
3618         I915_MAX_WM,
3619         1,
3620         2,
3621         I915_FIFO_LINE_SIZE
3622 };
3623 static const struct intel_watermark_params i915_wm_info = {
3624         I915_FIFO_SIZE,
3625         I915_MAX_WM,
3626         1,
3627         2,
3628         I915_FIFO_LINE_SIZE
3629 };
3630 static const struct intel_watermark_params i855_wm_info = {
3631         I855GM_FIFO_SIZE,
3632         I915_MAX_WM,
3633         1,
3634         2,
3635         I830_FIFO_LINE_SIZE
3636 };
3637 static const struct intel_watermark_params i830_wm_info = {
3638         I830_FIFO_SIZE,
3639         I915_MAX_WM,
3640         1,
3641         2,
3642         I830_FIFO_LINE_SIZE
3643 };
3644
3645 static const struct intel_watermark_params ironlake_display_wm_info = {
3646         ILK_DISPLAY_FIFO,
3647         ILK_DISPLAY_MAXWM,
3648         ILK_DISPLAY_DFTWM,
3649         2,
3650         ILK_FIFO_LINE_SIZE
3651 };
3652 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3653         ILK_CURSOR_FIFO,
3654         ILK_CURSOR_MAXWM,
3655         ILK_CURSOR_DFTWM,
3656         2,
3657         ILK_FIFO_LINE_SIZE
3658 };
3659 static const struct intel_watermark_params ironlake_display_srwm_info = {
3660         ILK_DISPLAY_SR_FIFO,
3661         ILK_DISPLAY_MAX_SRWM,
3662         ILK_DISPLAY_DFT_SRWM,
3663         2,
3664         ILK_FIFO_LINE_SIZE
3665 };
3666 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3667         ILK_CURSOR_SR_FIFO,
3668         ILK_CURSOR_MAX_SRWM,
3669         ILK_CURSOR_DFT_SRWM,
3670         2,
3671         ILK_FIFO_LINE_SIZE
3672 };
3673
3674 static const struct intel_watermark_params sandybridge_display_wm_info = {
3675         SNB_DISPLAY_FIFO,
3676         SNB_DISPLAY_MAXWM,
3677         SNB_DISPLAY_DFTWM,
3678         2,
3679         SNB_FIFO_LINE_SIZE
3680 };
3681 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3682         SNB_CURSOR_FIFO,
3683         SNB_CURSOR_MAXWM,
3684         SNB_CURSOR_DFTWM,
3685         2,
3686         SNB_FIFO_LINE_SIZE
3687 };
3688 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3689         SNB_DISPLAY_SR_FIFO,
3690         SNB_DISPLAY_MAX_SRWM,
3691         SNB_DISPLAY_DFT_SRWM,
3692         2,
3693         SNB_FIFO_LINE_SIZE
3694 };
3695 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3696         SNB_CURSOR_SR_FIFO,
3697         SNB_CURSOR_MAX_SRWM,
3698         SNB_CURSOR_DFT_SRWM,
3699         2,
3700         SNB_FIFO_LINE_SIZE
3701 };
3702
3703
3704 /**
3705  * intel_calculate_wm - calculate watermark level
3706  * @clock_in_khz: pixel clock
3707  * @wm: chip FIFO params
3708  * @pixel_size: display pixel size
3709  * @latency_ns: memory latency for the platform
3710  *
3711  * Calculate the watermark level (the level at which the display plane will
3712  * start fetching from memory again).  Each chip has a different display
3713  * FIFO size and allocation, so the caller needs to figure that out and pass
3714  * in the correct intel_watermark_params structure.
3715  *
3716  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3717  * on the pixel size.  When it reaches the watermark level, it'll start
3718  * fetching FIFO line sized based chunks from memory until the FIFO fills
3719  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3720  * will occur, and a display engine hang could result.
3721  */
3722 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3723                                         const struct intel_watermark_params *wm,
3724                                         int fifo_size,
3725                                         int pixel_size,
3726                                         unsigned long latency_ns)
3727 {
3728         long entries_required, wm_size;
3729
3730         /*
3731          * Note: we need to make sure we don't overflow for various clock &
3732          * latency values.
3733          * clocks go from a few thousand to several hundred thousand.
3734          * latency is usually a few thousand
3735          */
3736         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3737                 1000;
3738         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3739
3740         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3741
3742         wm_size = fifo_size - (entries_required + wm->guard_size);
3743
3744         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3745
3746         /* Don't promote wm_size to unsigned... */
3747         if (wm_size > (long)wm->max_wm)
3748                 wm_size = wm->max_wm;
3749         if (wm_size <= 0)
3750                 wm_size = wm->default_wm;
3751         return wm_size;
3752 }
3753
3754 struct cxsr_latency {
3755         int is_desktop;
3756         int is_ddr3;
3757         unsigned long fsb_freq;
3758         unsigned long mem_freq;
3759         unsigned long display_sr;
3760         unsigned long display_hpll_disable;
3761         unsigned long cursor_sr;
3762         unsigned long cursor_hpll_disable;
3763 };
3764
3765 static const struct cxsr_latency cxsr_latency_table[] = {
3766         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3767         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3768         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3769         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3770         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3771
3772         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3773         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3774         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3775         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3776         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3777
3778         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3779         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3780         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3781         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3782         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3783
3784         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3785         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3786         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3787         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3788         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3789
3790         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3791         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3792         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3793         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3794         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3795
3796         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3797         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3798         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3799         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3800         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3801 };
3802
3803 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3804                                                          int is_ddr3,
3805                                                          int fsb,
3806                                                          int mem)
3807 {
3808         const struct cxsr_latency *latency;
3809         int i;
3810
3811         if (fsb == 0 || mem == 0)
3812                 return NULL;
3813
3814         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3815                 latency = &cxsr_latency_table[i];
3816                 if (is_desktop == latency->is_desktop &&
3817                     is_ddr3 == latency->is_ddr3 &&
3818                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3819                         return latency;
3820         }
3821
3822         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3823
3824         return NULL;
3825 }
3826
3827 static void pineview_disable_cxsr(struct drm_device *dev)
3828 {
3829         struct drm_i915_private *dev_priv = dev->dev_private;
3830
3831         /* deactivate cxsr */
3832         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3833 }
3834
3835 /*
3836  * Latency for FIFO fetches is dependent on several factors:
3837  *   - memory configuration (speed, channels)
3838  *   - chipset
3839  *   - current MCH state
3840  * It can be fairly high in some situations, so here we assume a fairly
3841  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3842  * set this value too high, the FIFO will fetch frequently to stay full)
3843  * and power consumption (set it too low to save power and we might see
3844  * FIFO underruns and display "flicker").
3845  *
3846  * A value of 5us seems to be a good balance; safe for very low end
3847  * platforms but not overly aggressive on lower latency configs.
3848  */
3849 static const int latency_ns = 5000;
3850
3851 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3852 {
3853         struct drm_i915_private *dev_priv = dev->dev_private;
3854         uint32_t dsparb = I915_READ(DSPARB);
3855         int size;
3856
3857         size = dsparb & 0x7f;
3858         if (plane)
3859                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3860
3861         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3862                       plane ? "B" : "A", size);
3863
3864         return size;
3865 }
3866
3867 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3868 {
3869         struct drm_i915_private *dev_priv = dev->dev_private;
3870         uint32_t dsparb = I915_READ(DSPARB);
3871         int size;
3872
3873         size = dsparb & 0x1ff;
3874         if (plane)
3875                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3876         size >>= 1; /* Convert to cachelines */
3877
3878         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3879                       plane ? "B" : "A", size);
3880
3881         return size;
3882 }
3883
3884 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3885 {
3886         struct drm_i915_private *dev_priv = dev->dev_private;
3887         uint32_t dsparb = I915_READ(DSPARB);
3888         int size;
3889
3890         size = dsparb & 0x7f;
3891         size >>= 2; /* Convert to cachelines */
3892
3893         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3894                       plane ? "B" : "A",
3895                       size);
3896
3897         return size;
3898 }
3899
3900 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3901 {
3902         struct drm_i915_private *dev_priv = dev->dev_private;
3903         uint32_t dsparb = I915_READ(DSPARB);
3904         int size;
3905
3906         size = dsparb & 0x7f;
3907         size >>= 1; /* Convert to cachelines */
3908
3909         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3910                       plane ? "B" : "A", size);
3911
3912         return size;
3913 }
3914
3915 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3916 {
3917         struct drm_crtc *crtc, *enabled = NULL;
3918
3919         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3920                 if (crtc->enabled && crtc->fb) {
3921                         if (enabled)
3922                                 return NULL;
3923                         enabled = crtc;
3924                 }
3925         }
3926
3927         return enabled;
3928 }
3929
3930 static void pineview_update_wm(struct drm_device *dev)
3931 {
3932         struct drm_i915_private *dev_priv = dev->dev_private;
3933         struct drm_crtc *crtc;
3934         const struct cxsr_latency *latency;
3935         u32 reg;
3936         unsigned long wm;
3937
3938         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3939                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3940         if (!latency) {
3941                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3942                 pineview_disable_cxsr(dev);
3943                 return;
3944         }
3945
3946         crtc = single_enabled_crtc(dev);
3947         if (crtc) {
3948                 int clock = crtc->mode.clock;
3949                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3950
3951                 /* Display SR */
3952                 wm = intel_calculate_wm(clock, &pineview_display_wm,
3953                                         pineview_display_wm.fifo_size,
3954                                         pixel_size, latency->display_sr);
3955                 reg = I915_READ(DSPFW1);
3956                 reg &= ~DSPFW_SR_MASK;
3957                 reg |= wm << DSPFW_SR_SHIFT;
3958                 I915_WRITE(DSPFW1, reg);
3959                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3960
3961                 /* cursor SR */
3962                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3963                                         pineview_display_wm.fifo_size,
3964                                         pixel_size, latency->cursor_sr);
3965                 reg = I915_READ(DSPFW3);
3966                 reg &= ~DSPFW_CURSOR_SR_MASK;
3967                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3968                 I915_WRITE(DSPFW3, reg);
3969
3970                 /* Display HPLL off SR */
3971                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3972                                         pineview_display_hplloff_wm.fifo_size,
3973                                         pixel_size, latency->display_hpll_disable);
3974                 reg = I915_READ(DSPFW3);
3975                 reg &= ~DSPFW_HPLL_SR_MASK;
3976                 reg |= wm & DSPFW_HPLL_SR_MASK;
3977                 I915_WRITE(DSPFW3, reg);
3978
3979                 /* cursor HPLL off SR */
3980                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3981                                         pineview_display_hplloff_wm.fifo_size,
3982                                         pixel_size, latency->cursor_hpll_disable);
3983                 reg = I915_READ(DSPFW3);
3984                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3985                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3986                 I915_WRITE(DSPFW3, reg);
3987                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3988
3989                 /* activate cxsr */
3990                 I915_WRITE(DSPFW3,
3991                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3992                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3993         } else {
3994                 pineview_disable_cxsr(dev);
3995                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3996         }
3997 }
3998
3999 static bool g4x_compute_wm0(struct drm_device *dev,
4000                             int plane,
4001                             const struct intel_watermark_params *display,
4002                             int display_latency_ns,
4003                             const struct intel_watermark_params *cursor,
4004                             int cursor_latency_ns,
4005                             int *plane_wm,
4006                             int *cursor_wm)
4007 {
4008         struct drm_crtc *crtc;
4009         int htotal, hdisplay, clock, pixel_size;
4010         int line_time_us, line_count;
4011         int entries, tlb_miss;
4012
4013         crtc = intel_get_crtc_for_plane(dev, plane);
4014         if (crtc->fb == NULL || !crtc->enabled) {
4015                 *cursor_wm = cursor->guard_size;
4016                 *plane_wm = display->guard_size;
4017                 return false;
4018         }
4019
4020         htotal = crtc->mode.htotal;
4021         hdisplay = crtc->mode.hdisplay;
4022         clock = crtc->mode.clock;
4023         pixel_size = crtc->fb->bits_per_pixel / 8;
4024
4025         /* Use the small buffer method to calculate plane watermark */
4026         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4027         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4028         if (tlb_miss > 0)
4029                 entries += tlb_miss;
4030         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4031         *plane_wm = entries + display->guard_size;
4032         if (*plane_wm > (int)display->max_wm)
4033                 *plane_wm = display->max_wm;
4034
4035         /* Use the large buffer method to calculate cursor watermark */
4036         line_time_us = ((htotal * 1000) / clock);
4037         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4038         entries = line_count * 64 * pixel_size;
4039         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4040         if (tlb_miss > 0)
4041                 entries += tlb_miss;
4042         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4043         *cursor_wm = entries + cursor->guard_size;
4044         if (*cursor_wm > (int)cursor->max_wm)
4045                 *cursor_wm = (int)cursor->max_wm;
4046
4047         return true;
4048 }
4049
4050 /*
4051  * Check the wm result.
4052  *
4053  * If any calculated watermark values is larger than the maximum value that
4054  * can be programmed into the associated watermark register, that watermark
4055  * must be disabled.
4056  */
4057 static bool g4x_check_srwm(struct drm_device *dev,
4058                            int display_wm, int cursor_wm,
4059                            const struct intel_watermark_params *display,
4060                            const struct intel_watermark_params *cursor)
4061 {
4062         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4063                       display_wm, cursor_wm);
4064
4065         if (display_wm > display->max_wm) {
4066                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4067                               display_wm, display->max_wm);
4068                 return false;
4069         }
4070
4071         if (cursor_wm > cursor->max_wm) {
4072                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4073                               cursor_wm, cursor->max_wm);
4074                 return false;
4075         }
4076
4077         if (!(display_wm || cursor_wm)) {
4078                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4079                 return false;
4080         }
4081
4082         return true;
4083 }
4084
4085 static bool g4x_compute_srwm(struct drm_device *dev,
4086                              int plane,
4087                              int latency_ns,
4088                              const struct intel_watermark_params *display,
4089                              const struct intel_watermark_params *cursor,
4090                              int *display_wm, int *cursor_wm)
4091 {
4092         struct drm_crtc *crtc;
4093         int hdisplay, htotal, pixel_size, clock;
4094         unsigned long line_time_us;
4095         int line_count, line_size;
4096         int small, large;
4097         int entries;
4098
4099         if (!latency_ns) {
4100                 *display_wm = *cursor_wm = 0;
4101                 return false;
4102         }
4103
4104         crtc = intel_get_crtc_for_plane(dev, plane);
4105         hdisplay = crtc->mode.hdisplay;
4106         htotal = crtc->mode.htotal;
4107         clock = crtc->mode.clock;
4108         pixel_size = crtc->fb->bits_per_pixel / 8;
4109
4110         line_time_us = (htotal * 1000) / clock;
4111         line_count = (latency_ns / line_time_us + 1000) / 1000;
4112         line_size = hdisplay * pixel_size;
4113
4114         /* Use the minimum of the small and large buffer method for primary */
4115         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4116         large = line_count * line_size;
4117
4118         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4119         *display_wm = entries + display->guard_size;
4120
4121         /* calculate the self-refresh watermark for display cursor */
4122         entries = line_count * pixel_size * 64;
4123         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4124         *cursor_wm = entries + cursor->guard_size;
4125
4126         return g4x_check_srwm(dev,
4127                               *display_wm, *cursor_wm,
4128                               display, cursor);
4129 }
4130
4131 #define single_plane_enabled(mask) is_power_of_2(mask)
4132
4133 static void g4x_update_wm(struct drm_device *dev)
4134 {
4135         static const int sr_latency_ns = 12000;
4136         struct drm_i915_private *dev_priv = dev->dev_private;
4137         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4138         int plane_sr, cursor_sr;
4139         unsigned int enabled = 0;
4140
4141         if (g4x_compute_wm0(dev, 0,
4142                             &g4x_wm_info, latency_ns,
4143                             &g4x_cursor_wm_info, latency_ns,
4144                             &planea_wm, &cursora_wm))
4145                 enabled |= 1;
4146
4147         if (g4x_compute_wm0(dev, 1,
4148                             &g4x_wm_info, latency_ns,
4149                             &g4x_cursor_wm_info, latency_ns,
4150                             &planeb_wm, &cursorb_wm))
4151                 enabled |= 2;
4152
4153         plane_sr = cursor_sr = 0;
4154         if (single_plane_enabled(enabled) &&
4155             g4x_compute_srwm(dev, ffs(enabled) - 1,
4156                              sr_latency_ns,
4157                              &g4x_wm_info,
4158                              &g4x_cursor_wm_info,
4159                              &plane_sr, &cursor_sr))
4160                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4161         else
4162                 I915_WRITE(FW_BLC_SELF,
4163                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4164
4165         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4166                       planea_wm, cursora_wm,
4167                       planeb_wm, cursorb_wm,
4168                       plane_sr, cursor_sr);
4169
4170         I915_WRITE(DSPFW1,
4171                    (plane_sr << DSPFW_SR_SHIFT) |
4172                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4173                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
4174                    planea_wm);
4175         I915_WRITE(DSPFW2,
4176                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4177                    (cursora_wm << DSPFW_CURSORA_SHIFT));
4178         /* HPLL off in SR has some issues on G4x... disable it */
4179         I915_WRITE(DSPFW3,
4180                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4181                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4182 }
4183
4184 static void i965_update_wm(struct drm_device *dev)
4185 {
4186         struct drm_i915_private *dev_priv = dev->dev_private;
4187         struct drm_crtc *crtc;
4188         int srwm = 1;
4189         int cursor_sr = 16;
4190
4191         /* Calc sr entries for one plane configs */
4192         crtc = single_enabled_crtc(dev);
4193         if (crtc) {
4194                 /* self-refresh has much higher latency */
4195                 static const int sr_latency_ns = 12000;
4196                 int clock = crtc->mode.clock;
4197                 int htotal = crtc->mode.htotal;
4198                 int hdisplay = crtc->mode.hdisplay;
4199                 int pixel_size = crtc->fb->bits_per_pixel / 8;
4200                 unsigned long line_time_us;
4201                 int entries;
4202
4203                 line_time_us = ((htotal * 1000) / clock);
4204
4205                 /* Use ns/us then divide to preserve precision */
4206                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4207                         pixel_size * hdisplay;
4208                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4209                 srwm = I965_FIFO_SIZE - entries;
4210                 if (srwm < 0)
4211                         srwm = 1;
4212                 srwm &= 0x1ff;
4213                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4214                               entries, srwm);
4215
4216                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4217                         pixel_size * 64;
4218                 entries = DIV_ROUND_UP(entries,
4219                                           i965_cursor_wm_info.cacheline_size);
4220                 cursor_sr = i965_cursor_wm_info.fifo_size -
4221                         (entries + i965_cursor_wm_info.guard_size);
4222
4223                 if (cursor_sr > i965_cursor_wm_info.max_wm)
4224                         cursor_sr = i965_cursor_wm_info.max_wm;
4225
4226                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4227                               "cursor %d\n", srwm, cursor_sr);
4228
4229                 if (IS_CRESTLINE(dev))
4230                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4231         } else {
4232                 /* Turn off self refresh if both pipes are enabled */
4233                 if (IS_CRESTLINE(dev))
4234                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4235                                    & ~FW_BLC_SELF_EN);
4236         }
4237
4238         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4239                       srwm);
4240
4241         /* 965 has limitations... */
4242         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4243                    (8 << 16) | (8 << 8) | (8 << 0));
4244         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4245         /* update cursor SR watermark */
4246         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4247 }
4248
4249 static void i9xx_update_wm(struct drm_device *dev)
4250 {
4251         struct drm_i915_private *dev_priv = dev->dev_private;
4252         const struct intel_watermark_params *wm_info;
4253         uint32_t fwater_lo;
4254         uint32_t fwater_hi;
4255         int cwm, srwm = 1;
4256         int fifo_size;
4257         int planea_wm, planeb_wm;
4258         struct drm_crtc *crtc, *enabled = NULL;
4259
4260         if (IS_I945GM(dev))
4261                 wm_info = &i945_wm_info;
4262         else if (!IS_GEN2(dev))
4263                 wm_info = &i915_wm_info;
4264         else
4265                 wm_info = &i855_wm_info;
4266
4267         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4268         crtc = intel_get_crtc_for_plane(dev, 0);
4269         if (crtc->enabled && crtc->fb) {
4270                 planea_wm = intel_calculate_wm(crtc->mode.clock,
4271                                                wm_info, fifo_size,
4272                                                crtc->fb->bits_per_pixel / 8,
4273                                                latency_ns);
4274                 enabled = crtc;
4275         } else
4276                 planea_wm = fifo_size - wm_info->guard_size;
4277
4278         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4279         crtc = intel_get_crtc_for_plane(dev, 1);
4280         if (crtc->enabled && crtc->fb) {
4281                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4282                                                wm_info, fifo_size,
4283                                                crtc->fb->bits_per_pixel / 8,
4284                                                latency_ns);
4285                 if (enabled == NULL)
4286                         enabled = crtc;
4287                 else
4288                         enabled = NULL;
4289         } else
4290                 planeb_wm = fifo_size - wm_info->guard_size;
4291
4292         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4293
4294         /*
4295          * Overlay gets an aggressive default since video jitter is bad.
4296          */
4297         cwm = 2;
4298
4299         /* Play safe and disable self-refresh before adjusting watermarks. */
4300         if (IS_I945G(dev) || IS_I945GM(dev))
4301                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4302         else if (IS_I915GM(dev))
4303                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4304
4305         /* Calc sr entries for one plane configs */
4306         if (HAS_FW_BLC(dev) && enabled) {
4307                 /* self-refresh has much higher latency */
4308                 static const int sr_latency_ns = 6000;
4309                 int clock = enabled->mode.clock;
4310                 int htotal = enabled->mode.htotal;
4311                 int hdisplay = enabled->mode.hdisplay;
4312                 int pixel_size = enabled->fb->bits_per_pixel / 8;
4313                 unsigned long line_time_us;
4314                 int entries;
4315
4316                 line_time_us = (htotal * 1000) / clock;
4317
4318                 /* Use ns/us then divide to preserve precision */
4319                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4320                         pixel_size * hdisplay;
4321                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4322                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4323                 srwm = wm_info->fifo_size - entries;
4324                 if (srwm < 0)
4325                         srwm = 1;
4326
4327                 if (IS_I945G(dev) || IS_I945GM(dev))
4328                         I915_WRITE(FW_BLC_SELF,
4329                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4330                 else if (IS_I915GM(dev))
4331                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4332         }
4333
4334         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4335                       planea_wm, planeb_wm, cwm, srwm);
4336
4337         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4338         fwater_hi = (cwm & 0x1f);
4339
4340         /* Set request length to 8 cachelines per fetch */
4341         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4342         fwater_hi = fwater_hi | (1 << 8);
4343
4344         I915_WRITE(FW_BLC, fwater_lo);
4345         I915_WRITE(FW_BLC2, fwater_hi);
4346
4347         if (HAS_FW_BLC(dev)) {
4348                 if (enabled) {
4349                         if (IS_I945G(dev) || IS_I945GM(dev))
4350                                 I915_WRITE(FW_BLC_SELF,
4351                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4352                         else if (IS_I915GM(dev))
4353                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4354                         DRM_DEBUG_KMS("memory self refresh enabled\n");
4355                 } else
4356                         DRM_DEBUG_KMS("memory self refresh disabled\n");
4357         }
4358 }
4359
4360 static void i830_update_wm(struct drm_device *dev)
4361 {
4362         struct drm_i915_private *dev_priv = dev->dev_private;
4363         struct drm_crtc *crtc;
4364         uint32_t fwater_lo;
4365         int planea_wm;
4366
4367         crtc = single_enabled_crtc(dev);
4368         if (crtc == NULL)
4369                 return;
4370
4371         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4372                                        dev_priv->display.get_fifo_size(dev, 0),
4373                                        crtc->fb->bits_per_pixel / 8,
4374                                        latency_ns);
4375         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4376         fwater_lo |= (3<<8) | planea_wm;
4377
4378         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4379
4380         I915_WRITE(FW_BLC, fwater_lo);
4381 }
4382
4383 #define ILK_LP0_PLANE_LATENCY           700
4384 #define ILK_LP0_CURSOR_LATENCY          1300
4385
4386 /*
4387  * Check the wm result.
4388  *
4389  * If any calculated watermark values is larger than the maximum value that
4390  * can be programmed into the associated watermark register, that watermark
4391  * must be disabled.
4392  */
4393 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4394                                 int fbc_wm, int display_wm, int cursor_wm,
4395                                 const struct intel_watermark_params *display,
4396                                 const struct intel_watermark_params *cursor)
4397 {
4398         struct drm_i915_private *dev_priv = dev->dev_private;
4399
4400         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4401                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4402
4403         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4404                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4405                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4406
4407                 /* fbc has it's own way to disable FBC WM */
4408                 I915_WRITE(DISP_ARB_CTL,
4409                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4410                 return false;
4411         }
4412
4413         if (display_wm > display->max_wm) {
4414                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4415                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4416                 return false;
4417         }
4418
4419         if (cursor_wm > cursor->max_wm) {
4420                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4421                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4422                 return false;
4423         }
4424
4425         if (!(fbc_wm || display_wm || cursor_wm)) {
4426                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4427                 return false;
4428         }
4429
4430         return true;
4431 }
4432
4433 /*
4434  * Compute watermark values of WM[1-3],
4435  */
4436 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4437                                   int latency_ns,
4438                                   const struct intel_watermark_params *display,
4439                                   const struct intel_watermark_params *cursor,
4440                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4441 {
4442         struct drm_crtc *crtc;
4443         unsigned long line_time_us;
4444         int hdisplay, htotal, pixel_size, clock;
4445         int line_count, line_size;
4446         int small, large;
4447         int entries;
4448
4449         if (!latency_ns) {
4450                 *fbc_wm = *display_wm = *cursor_wm = 0;
4451                 return false;
4452         }
4453
4454         crtc = intel_get_crtc_for_plane(dev, plane);
4455         hdisplay = crtc->mode.hdisplay;
4456         htotal = crtc->mode.htotal;
4457         clock = crtc->mode.clock;
4458         pixel_size = crtc->fb->bits_per_pixel / 8;
4459
4460         line_time_us = (htotal * 1000) / clock;
4461         line_count = (latency_ns / line_time_us + 1000) / 1000;
4462         line_size = hdisplay * pixel_size;
4463
4464         /* Use the minimum of the small and large buffer method for primary */
4465         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4466         large = line_count * line_size;
4467
4468         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4469         *display_wm = entries + display->guard_size;
4470
4471         /*
4472          * Spec says:
4473          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4474          */
4475         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4476
4477         /* calculate the self-refresh watermark for display cursor */
4478         entries = line_count * pixel_size * 64;
4479         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4480         *cursor_wm = entries + cursor->guard_size;
4481
4482         return ironlake_check_srwm(dev, level,
4483                                    *fbc_wm, *display_wm, *cursor_wm,
4484                                    display, cursor);
4485 }
4486
4487 static void ironlake_update_wm(struct drm_device *dev)
4488 {
4489         struct drm_i915_private *dev_priv = dev->dev_private;
4490         int fbc_wm, plane_wm, cursor_wm;
4491         unsigned int enabled;
4492
4493         enabled = 0;
4494         if (g4x_compute_wm0(dev, 0,
4495                             &ironlake_display_wm_info,
4496                             ILK_LP0_PLANE_LATENCY,
4497                             &ironlake_cursor_wm_info,
4498                             ILK_LP0_CURSOR_LATENCY,
4499                             &plane_wm, &cursor_wm)) {
4500                 I915_WRITE(WM0_PIPEA_ILK,
4501                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4502                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4503                               " plane %d, " "cursor: %d\n",
4504                               plane_wm, cursor_wm);
4505                 enabled |= 1;
4506         }
4507
4508         if (g4x_compute_wm0(dev, 1,
4509                             &ironlake_display_wm_info,
4510                             ILK_LP0_PLANE_LATENCY,
4511                             &ironlake_cursor_wm_info,
4512                             ILK_LP0_CURSOR_LATENCY,
4513                             &plane_wm, &cursor_wm)) {
4514                 I915_WRITE(WM0_PIPEB_ILK,
4515                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4516                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4517                               " plane %d, cursor: %d\n",
4518                               plane_wm, cursor_wm);
4519                 enabled |= 2;
4520         }
4521
4522         /*
4523          * Calculate and update the self-refresh watermark only when one
4524          * display plane is used.
4525          */
4526         I915_WRITE(WM3_LP_ILK, 0);
4527         I915_WRITE(WM2_LP_ILK, 0);
4528         I915_WRITE(WM1_LP_ILK, 0);
4529
4530         if (!single_plane_enabled(enabled))
4531                 return;
4532         enabled = ffs(enabled) - 1;
4533
4534         /* WM1 */
4535         if (!ironlake_compute_srwm(dev, 1, enabled,
4536                                    ILK_READ_WM1_LATENCY() * 500,
4537                                    &ironlake_display_srwm_info,
4538                                    &ironlake_cursor_srwm_info,
4539                                    &fbc_wm, &plane_wm, &cursor_wm))
4540                 return;
4541
4542         I915_WRITE(WM1_LP_ILK,
4543                    WM1_LP_SR_EN |
4544                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4545                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4546                    (plane_wm << WM1_LP_SR_SHIFT) |
4547                    cursor_wm);
4548
4549         /* WM2 */
4550         if (!ironlake_compute_srwm(dev, 2, enabled,
4551                                    ILK_READ_WM2_LATENCY() * 500,
4552                                    &ironlake_display_srwm_info,
4553                                    &ironlake_cursor_srwm_info,
4554                                    &fbc_wm, &plane_wm, &cursor_wm))
4555                 return;
4556
4557         I915_WRITE(WM2_LP_ILK,
4558                    WM2_LP_EN |
4559                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4560                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4561                    (plane_wm << WM1_LP_SR_SHIFT) |
4562                    cursor_wm);
4563
4564         /*
4565          * WM3 is unsupported on ILK, probably because we don't have latency
4566          * data for that power state
4567          */
4568 }
4569
4570 void sandybridge_update_wm(struct drm_device *dev)
4571 {
4572         struct drm_i915_private *dev_priv = dev->dev_private;
4573         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4574         u32 val;
4575         int fbc_wm, plane_wm, cursor_wm;
4576         unsigned int enabled;
4577
4578         enabled = 0;
4579         if (g4x_compute_wm0(dev, 0,
4580                             &sandybridge_display_wm_info, latency,
4581                             &sandybridge_cursor_wm_info, latency,
4582                             &plane_wm, &cursor_wm)) {
4583                 val = I915_READ(WM0_PIPEA_ILK);
4584                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4585                 I915_WRITE(WM0_PIPEA_ILK, val |
4586                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4587                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4588                               " plane %d, " "cursor: %d\n",
4589                               plane_wm, cursor_wm);
4590                 enabled |= 1;
4591         }
4592
4593         if (g4x_compute_wm0(dev, 1,
4594                             &sandybridge_display_wm_info, latency,
4595                             &sandybridge_cursor_wm_info, latency,
4596                             &plane_wm, &cursor_wm)) {
4597                 val = I915_READ(WM0_PIPEB_ILK);
4598                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4599                 I915_WRITE(WM0_PIPEB_ILK, val |
4600                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4601                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4602                               " plane %d, cursor: %d\n",
4603                               plane_wm, cursor_wm);
4604                 enabled |= 2;
4605         }
4606
4607         /* IVB has 3 pipes */
4608         if (IS_IVYBRIDGE(dev) &&
4609             g4x_compute_wm0(dev, 2,
4610                             &sandybridge_display_wm_info, latency,
4611                             &sandybridge_cursor_wm_info, latency,
4612                             &plane_wm, &cursor_wm)) {
4613                 val = I915_READ(WM0_PIPEC_IVB);
4614                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4615                 I915_WRITE(WM0_PIPEC_IVB, val |
4616                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
4617                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4618                               " plane %d, cursor: %d\n",
4619                               plane_wm, cursor_wm);
4620                 enabled |= 3;
4621         }
4622
4623         /*
4624          * Calculate and update the self-refresh watermark only when one
4625          * display plane is used.
4626          *
4627          * SNB support 3 levels of watermark.
4628          *
4629          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4630          * and disabled in the descending order
4631          *
4632          */
4633         I915_WRITE(WM3_LP_ILK, 0);
4634         I915_WRITE(WM2_LP_ILK, 0);
4635         I915_WRITE(WM1_LP_ILK, 0);
4636
4637         if (!single_plane_enabled(enabled) ||
4638             dev_priv->sprite_scaling_enabled)
4639                 return;
4640         enabled = ffs(enabled) - 1;
4641
4642         /* WM1 */
4643         if (!ironlake_compute_srwm(dev, 1, enabled,
4644                                    SNB_READ_WM1_LATENCY() * 500,
4645                                    &sandybridge_display_srwm_info,
4646                                    &sandybridge_cursor_srwm_info,
4647                                    &fbc_wm, &plane_wm, &cursor_wm))
4648                 return;
4649
4650         I915_WRITE(WM1_LP_ILK,
4651                    WM1_LP_SR_EN |
4652                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4653                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4654                    (plane_wm << WM1_LP_SR_SHIFT) |
4655                    cursor_wm);
4656
4657         /* WM2 */
4658         if (!ironlake_compute_srwm(dev, 2, enabled,
4659                                    SNB_READ_WM2_LATENCY() * 500,
4660                                    &sandybridge_display_srwm_info,
4661                                    &sandybridge_cursor_srwm_info,
4662                                    &fbc_wm, &plane_wm, &cursor_wm))
4663                 return;
4664
4665         I915_WRITE(WM2_LP_ILK,
4666                    WM2_LP_EN |
4667                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4668                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4669                    (plane_wm << WM1_LP_SR_SHIFT) |
4670                    cursor_wm);
4671
4672         /* WM3 */
4673         if (!ironlake_compute_srwm(dev, 3, enabled,
4674                                    SNB_READ_WM3_LATENCY() * 500,
4675                                    &sandybridge_display_srwm_info,
4676                                    &sandybridge_cursor_srwm_info,
4677                                    &fbc_wm, &plane_wm, &cursor_wm))
4678                 return;
4679
4680         I915_WRITE(WM3_LP_ILK,
4681                    WM3_LP_EN |
4682                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4683                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4684                    (plane_wm << WM1_LP_SR_SHIFT) |
4685                    cursor_wm);
4686 }
4687
4688 static bool
4689 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4690                               uint32_t sprite_width, int pixel_size,
4691                               const struct intel_watermark_params *display,
4692                               int display_latency_ns, int *sprite_wm)
4693 {
4694         struct drm_crtc *crtc;
4695         int clock;
4696         int entries, tlb_miss;
4697
4698         crtc = intel_get_crtc_for_plane(dev, plane);
4699         if (crtc->fb == NULL || !crtc->enabled) {
4700                 *sprite_wm = display->guard_size;
4701                 return false;
4702         }
4703
4704         clock = crtc->mode.clock;
4705
4706         /* Use the small buffer method to calculate the sprite watermark */
4707         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4708         tlb_miss = display->fifo_size*display->cacheline_size -
4709                 sprite_width * 8;
4710         if (tlb_miss > 0)
4711                 entries += tlb_miss;
4712         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4713         *sprite_wm = entries + display->guard_size;
4714         if (*sprite_wm > (int)display->max_wm)
4715                 *sprite_wm = display->max_wm;
4716
4717         return true;
4718 }
4719
4720 static bool
4721 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4722                                 uint32_t sprite_width, int pixel_size,
4723                                 const struct intel_watermark_params *display,
4724                                 int latency_ns, int *sprite_wm)
4725 {
4726         struct drm_crtc *crtc;
4727         unsigned long line_time_us;
4728         int clock;
4729         int line_count, line_size;
4730         int small, large;
4731         int entries;
4732
4733         if (!latency_ns) {
4734                 *sprite_wm = 0;
4735                 return false;
4736         }
4737
4738         crtc = intel_get_crtc_for_plane(dev, plane);
4739         clock = crtc->mode.clock;
4740         if (!clock) {
4741                 *sprite_wm = 0;
4742                 return false;
4743         }
4744
4745         line_time_us = (sprite_width * 1000) / clock;
4746         if (!line_time_us) {
4747                 *sprite_wm = 0;
4748                 return false;
4749         }
4750
4751         line_count = (latency_ns / line_time_us + 1000) / 1000;
4752         line_size = sprite_width * pixel_size;
4753
4754         /* Use the minimum of the small and large buffer method for primary */
4755         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4756         large = line_count * line_size;
4757
4758         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4759         *sprite_wm = entries + display->guard_size;
4760
4761         return *sprite_wm > 0x3ff ? false : true;
4762 }
4763
4764 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4765                                          uint32_t sprite_width, int pixel_size)
4766 {
4767         struct drm_i915_private *dev_priv = dev->dev_private;
4768         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4769         u32 val;
4770         int sprite_wm, reg;
4771         int ret;
4772
4773         switch (pipe) {
4774         case 0:
4775                 reg = WM0_PIPEA_ILK;
4776                 break;
4777         case 1:
4778                 reg = WM0_PIPEB_ILK;
4779                 break;
4780         case 2:
4781                 reg = WM0_PIPEC_IVB;
4782                 break;
4783         default:
4784                 return; /* bad pipe */
4785         }
4786
4787         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4788                                             &sandybridge_display_wm_info,
4789                                             latency, &sprite_wm);
4790         if (!ret) {
4791                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4792                               pipe);
4793                 return;
4794         }
4795
4796         val = I915_READ(reg);
4797         val &= ~WM0_PIPE_SPRITE_MASK;
4798         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
4799         DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4800
4801
4802         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4803                                               pixel_size,
4804                                               &sandybridge_display_srwm_info,
4805                                               SNB_READ_WM1_LATENCY() * 500,
4806                                               &sprite_wm);
4807         if (!ret) {
4808                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4809                               pipe);
4810                 return;
4811         }
4812         I915_WRITE(WM1S_LP_ILK, sprite_wm);
4813
4814         /* Only IVB has two more LP watermarks for sprite */
4815         if (!IS_IVYBRIDGE(dev))
4816                 return;
4817
4818         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4819                                               pixel_size,
4820                                               &sandybridge_display_srwm_info,
4821                                               SNB_READ_WM2_LATENCY() * 500,
4822                                               &sprite_wm);
4823         if (!ret) {
4824                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4825                               pipe);
4826                 return;
4827         }
4828         I915_WRITE(WM2S_LP_IVB, sprite_wm);
4829
4830         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4831                                               pixel_size,
4832                                               &sandybridge_display_srwm_info,
4833                                               SNB_READ_WM3_LATENCY() * 500,
4834                                               &sprite_wm);
4835         if (!ret) {
4836                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4837                               pipe);
4838                 return;
4839         }
4840         I915_WRITE(WM3S_LP_IVB, sprite_wm);
4841 }
4842
4843 /**
4844  * intel_update_watermarks - update FIFO watermark values based on current modes
4845  *
4846  * Calculate watermark values for the various WM regs based on current mode
4847  * and plane configuration.
4848  *
4849  * There are several cases to deal with here:
4850  *   - normal (i.e. non-self-refresh)
4851  *   - self-refresh (SR) mode
4852  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4853  *   - lines are small relative to FIFO size (buffer can hold more than 2
4854  *     lines), so need to account for TLB latency
4855  *
4856  *   The normal calculation is:
4857  *     watermark = dotclock * bytes per pixel * latency
4858  *   where latency is platform & configuration dependent (we assume pessimal
4859  *   values here).
4860  *
4861  *   The SR calculation is:
4862  *     watermark = (trunc(latency/line time)+1) * surface width *
4863  *       bytes per pixel
4864  *   where
4865  *     line time = htotal / dotclock
4866  *     surface width = hdisplay for normal plane and 64 for cursor
4867  *   and latency is assumed to be high, as above.
4868  *
4869  * The final value programmed to the register should always be rounded up,
4870  * and include an extra 2 entries to account for clock crossings.
4871  *
4872  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4873  * to set the non-SR watermarks to 8.
4874  */
4875 static void intel_update_watermarks(struct drm_device *dev)
4876 {
4877         struct drm_i915_private *dev_priv = dev->dev_private;
4878
4879         if (dev_priv->display.update_wm)
4880                 dev_priv->display.update_wm(dev);
4881 }
4882
4883 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4884                                     uint32_t sprite_width, int pixel_size)
4885 {
4886         struct drm_i915_private *dev_priv = dev->dev_private;
4887
4888         if (dev_priv->display.update_sprite_wm)
4889                 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4890                                                    pixel_size);
4891 }
4892
4893 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4894 {
4895         if (i915_panel_use_ssc >= 0)
4896                 return i915_panel_use_ssc != 0;
4897         return dev_priv->lvds_use_ssc
4898                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4899 }
4900
4901 /**
4902  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4903  * @crtc: CRTC structure
4904  * @mode: requested mode
4905  *
4906  * A pipe may be connected to one or more outputs.  Based on the depth of the
4907  * attached framebuffer, choose a good color depth to use on the pipe.
4908  *
4909  * If possible, match the pipe depth to the fb depth.  In some cases, this
4910  * isn't ideal, because the connected output supports a lesser or restricted
4911  * set of depths.  Resolve that here:
4912  *    LVDS typically supports only 6bpc, so clamp down in that case
4913  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4914  *    Displays may support a restricted set as well, check EDID and clamp as
4915  *      appropriate.
4916  *    DP may want to dither down to 6bpc to fit larger modes
4917  *
4918  * RETURNS:
4919  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4920  * true if they don't match).
4921  */
4922 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4923                                          unsigned int *pipe_bpp,
4924                                          struct drm_display_mode *mode)
4925 {
4926         struct drm_device *dev = crtc->dev;
4927         struct drm_i915_private *dev_priv = dev->dev_private;
4928         struct drm_encoder *encoder;
4929         struct drm_connector *connector;
4930         unsigned int display_bpc = UINT_MAX, bpc;
4931
4932         /* Walk the encoders & connectors on this crtc, get min bpc */
4933         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4934                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4935
4936                 if (encoder->crtc != crtc)
4937                         continue;
4938
4939                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4940                         unsigned int lvds_bpc;
4941
4942                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4943                             LVDS_A3_POWER_UP)
4944                                 lvds_bpc = 8;
4945                         else
4946                                 lvds_bpc = 6;
4947
4948                         if (lvds_bpc < display_bpc) {
4949                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4950                                 display_bpc = lvds_bpc;
4951                         }
4952                         continue;
4953                 }
4954
4955                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4956                         /* Use VBT settings if we have an eDP panel */
4957                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4958
4959                         if (edp_bpc < display_bpc) {
4960                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4961                                 display_bpc = edp_bpc;
4962                         }
4963                         continue;
4964                 }
4965
4966                 /* Not one of the known troublemakers, check the EDID */
4967                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4968                                     head) {
4969                         if (connector->encoder != encoder)
4970                                 continue;
4971
4972                         /* Don't use an invalid EDID bpc value */
4973                         if (connector->display_info.bpc &&
4974                             connector->display_info.bpc < display_bpc) {
4975                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4976                                 display_bpc = connector->display_info.bpc;
4977                         }
4978                 }
4979
4980                 /*
4981                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4982                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4983                  */
4984                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4985                         if (display_bpc > 8 && display_bpc < 12) {
4986                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4987                                 display_bpc = 12;
4988                         } else {
4989                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4990                                 display_bpc = 8;
4991                         }
4992                 }
4993         }
4994
4995         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4996                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4997                 display_bpc = 6;
4998         }
4999
5000         /*
5001          * We could just drive the pipe at the highest bpc all the time and
5002          * enable dithering as needed, but that costs bandwidth.  So choose
5003          * the minimum value that expresses the full color range of the fb but
5004          * also stays within the max display bpc discovered above.
5005          */
5006
5007         switch (crtc->fb->depth) {
5008         case 8:
5009                 bpc = 8; /* since we go through a colormap */
5010                 break;
5011         case 15:
5012         case 16:
5013                 bpc = 6; /* min is 18bpp */
5014                 break;
5015         case 24:
5016                 bpc = 8;
5017                 break;
5018         case 30:
5019                 bpc = 10;
5020                 break;
5021         case 48:
5022                 bpc = 12;
5023                 break;
5024         default:
5025                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
5026                 bpc = min((unsigned int)8, display_bpc);
5027                 break;
5028         }
5029
5030         display_bpc = min(display_bpc, bpc);
5031
5032         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
5033                       bpc, display_bpc);
5034
5035         *pipe_bpp = display_bpc * 3;
5036
5037         return display_bpc != bpc;
5038 }
5039
5040 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5041 {
5042         struct drm_device *dev = crtc->dev;
5043         struct drm_i915_private *dev_priv = dev->dev_private;
5044         int refclk;
5045
5046         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5047             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5048                 refclk = dev_priv->lvds_ssc_freq * 1000;
5049                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5050                               refclk / 1000);
5051         } else if (!IS_GEN2(dev)) {
5052                 refclk = 96000;
5053         } else {
5054                 refclk = 48000;
5055         }
5056
5057         return refclk;
5058 }
5059
5060 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5061                                       intel_clock_t *clock)
5062 {
5063         /* SDVO TV has fixed PLL values depend on its clock range,
5064            this mirrors vbios setting. */
5065         if (adjusted_mode->clock >= 100000
5066             && adjusted_mode->clock < 140500) {
5067                 clock->p1 = 2;
5068                 clock->p2 = 10;
5069                 clock->n = 3;
5070                 clock->m1 = 16;
5071                 clock->m2 = 8;
5072         } else if (adjusted_mode->clock >= 140500
5073                    && adjusted_mode->clock <= 200000) {
5074                 clock->p1 = 1;
5075                 clock->p2 = 10;
5076                 clock->n = 6;
5077                 clock->m1 = 12;
5078                 clock->m2 = 8;
5079         }
5080 }
5081
5082 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5083                                      intel_clock_t *clock,
5084                                      intel_clock_t *reduced_clock)
5085 {
5086         struct drm_device *dev = crtc->dev;
5087         struct drm_i915_private *dev_priv = dev->dev_private;
5088         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5089         int pipe = intel_crtc->pipe;
5090         u32 fp, fp2 = 0;
5091
5092         if (IS_PINEVIEW(dev)) {
5093                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5094                 if (reduced_clock)
5095                         fp2 = (1 << reduced_clock->n) << 16 |
5096                                 reduced_clock->m1 << 8 | reduced_clock->m2;
5097         } else {
5098                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5099                 if (reduced_clock)
5100                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5101                                 reduced_clock->m2;
5102         }
5103
5104         I915_WRITE(FP0(pipe), fp);
5105
5106         intel_crtc->lowfreq_avail = false;
5107         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5108             reduced_clock && i915_powersave) {
5109                 I915_WRITE(FP1(pipe), fp2);
5110                 intel_crtc->lowfreq_avail = true;
5111         } else {
5112                 I915_WRITE(FP1(pipe), fp);
5113         }
5114 }
5115
5116 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5117                               struct drm_display_mode *mode,
5118                               struct drm_display_mode *adjusted_mode,
5119                               int x, int y,
5120                               struct drm_framebuffer *old_fb)
5121 {
5122         struct drm_device *dev = crtc->dev;
5123         struct drm_i915_private *dev_priv = dev->dev_private;
5124         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5125         int pipe = intel_crtc->pipe;
5126         int plane = intel_crtc->plane;
5127         int refclk, num_connectors = 0;
5128         intel_clock_t clock, reduced_clock;
5129         u32 dpll, dspcntr, pipeconf, vsyncshift;
5130         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
5131         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5132         struct drm_mode_config *mode_config = &dev->mode_config;
5133         struct intel_encoder *encoder;
5134         const intel_limit_t *limit;
5135         int ret;
5136         u32 temp;
5137         u32 lvds_sync = 0;
5138
5139         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5140                 if (encoder->base.crtc != crtc)
5141                         continue;
5142
5143                 switch (encoder->type) {
5144                 case INTEL_OUTPUT_LVDS:
5145                         is_lvds = true;
5146                         break;
5147                 case INTEL_OUTPUT_SDVO:
5148                 case INTEL_OUTPUT_HDMI:
5149                         is_sdvo = true;
5150                         if (encoder->needs_tv_clock)
5151                                 is_tv = true;
5152                         break;
5153                 case INTEL_OUTPUT_DVO:
5154                         is_dvo = true;
5155                         break;
5156                 case INTEL_OUTPUT_TVOUT:
5157                         is_tv = true;
5158                         break;
5159                 case INTEL_OUTPUT_ANALOG:
5160                         is_crt = true;
5161                         break;
5162                 case INTEL_OUTPUT_DISPLAYPORT:
5163                         is_dp = true;
5164                         break;
5165                 }
5166
5167                 num_connectors++;
5168         }
5169
5170         refclk = i9xx_get_refclk(crtc, num_connectors);
5171
5172         /*
5173          * Returns a set of divisors for the desired target clock with the given
5174          * refclk, or FALSE.  The returned values represent the clock equation:
5175          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5176          */
5177         limit = intel_limit(crtc, refclk);
5178         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5179                              &clock);
5180         if (!ok) {
5181                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5182                 return -EINVAL;
5183         }
5184
5185         /* Ensure that the cursor is valid for the new mode before changing... */
5186         intel_crtc_update_cursor(crtc, true);
5187
5188         if (is_lvds && dev_priv->lvds_downclock_avail) {
5189                 /*
5190                  * Ensure we match the reduced clock's P to the target clock.
5191                  * If the clocks don't match, we can't switch the display clock
5192                  * by using the FP0/FP1. In such case we will disable the LVDS
5193                  * downclock feature.
5194                 */
5195                 has_reduced_clock = limit->find_pll(limit, crtc,
5196                                                     dev_priv->lvds_downclock,
5197                                                     refclk,
5198                                                     &clock,
5199                                                     &reduced_clock);
5200         }
5201
5202         if (is_sdvo && is_tv)
5203                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
5204
5205         i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5206                                  &reduced_clock : NULL);
5207
5208         dpll = DPLL_VGA_MODE_DIS;
5209
5210         if (!IS_GEN2(dev)) {
5211                 if (is_lvds)
5212                         dpll |= DPLLB_MODE_LVDS;
5213                 else
5214                         dpll |= DPLLB_MODE_DAC_SERIAL;
5215                 if (is_sdvo) {
5216                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5217                         if (pixel_multiplier > 1) {
5218                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5219                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
5220                         }
5221                         dpll |= DPLL_DVO_HIGH_SPEED;
5222                 }
5223                 if (is_dp)
5224                         dpll |= DPLL_DVO_HIGH_SPEED;
5225
5226                 /* compute bitmask from p1 value */
5227                 if (IS_PINEVIEW(dev))
5228                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5229                 else {
5230                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5231                         if (IS_G4X(dev) && has_reduced_clock)
5232                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5233                 }
5234                 switch (clock.p2) {
5235                 case 5:
5236                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5237                         break;
5238                 case 7:
5239                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5240                         break;
5241                 case 10:
5242                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5243                         break;
5244                 case 14:
5245                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5246                         break;
5247                 }
5248                 if (INTEL_INFO(dev)->gen >= 4)
5249                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5250         } else {
5251                 if (is_lvds) {
5252                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5253                 } else {
5254                         if (clock.p1 == 2)
5255                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
5256                         else
5257                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5258                         if (clock.p2 == 4)
5259                                 dpll |= PLL_P2_DIVIDE_BY_4;
5260                 }
5261         }
5262
5263         if (is_sdvo && is_tv)
5264                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5265         else if (is_tv)
5266                 /* XXX: just matching BIOS for now */
5267                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5268                 dpll |= 3;
5269         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5270                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5271         else
5272                 dpll |= PLL_REF_INPUT_DREFCLK;
5273
5274         /* setup pipeconf */
5275         pipeconf = I915_READ(PIPECONF(pipe));
5276
5277         /* Set up the display plane register */
5278         dspcntr = DISPPLANE_GAMMA_ENABLE;
5279
5280         if (pipe == 0)
5281                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5282         else
5283                 dspcntr |= DISPPLANE_SEL_PIPE_B;
5284
5285         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5286                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5287                  * core speed.
5288                  *
5289                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5290                  * pipe == 0 check?
5291                  */
5292                 if (mode->clock >
5293                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5294                         pipeconf |= PIPECONF_DOUBLE_WIDE;
5295                 else
5296                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5297         }
5298
5299         /* default to 8bpc */
5300         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5301         if (is_dp) {
5302                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5303                         pipeconf |= PIPECONF_BPP_6 |
5304                                     PIPECONF_DITHER_EN |
5305                                     PIPECONF_DITHER_TYPE_SP;
5306                 }
5307         }
5308
5309         dpll |= DPLL_VCO_ENABLE;
5310
5311         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5312         drm_mode_debug_printmodeline(mode);
5313
5314         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5315
5316         POSTING_READ(DPLL(pipe));
5317         udelay(150);
5318
5319         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5320          * This is an exception to the general rule that mode_set doesn't turn
5321          * things on.
5322          */
5323         if (is_lvds) {
5324                 temp = I915_READ(LVDS);
5325                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5326                 if (pipe == 1) {
5327                         temp |= LVDS_PIPEB_SELECT;
5328                 } else {
5329                         temp &= ~LVDS_PIPEB_SELECT;
5330                 }
5331                 /* set the corresponsding LVDS_BORDER bit */
5332                 temp |= dev_priv->lvds_border_bits;
5333                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5334                  * set the DPLLs for dual-channel mode or not.
5335                  */
5336                 if (clock.p2 == 7)
5337                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5338                 else
5339                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5340
5341                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5342                  * appropriately here, but we need to look more thoroughly into how
5343                  * panels behave in the two modes.
5344                  */
5345                 /* set the dithering flag on LVDS as needed */
5346                 if (INTEL_INFO(dev)->gen >= 4) {
5347                         if (dev_priv->lvds_dither)
5348                                 temp |= LVDS_ENABLE_DITHER;
5349                         else
5350                                 temp &= ~LVDS_ENABLE_DITHER;
5351                 }
5352                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5353                         lvds_sync |= LVDS_HSYNC_POLARITY;
5354                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5355                         lvds_sync |= LVDS_VSYNC_POLARITY;
5356                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5357                     != lvds_sync) {
5358                         char flags[2] = "-+";
5359                         DRM_INFO("Changing LVDS panel from "
5360                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5361                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5362                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5363                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5364                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5365                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5366                         temp |= lvds_sync;
5367                 }
5368                 I915_WRITE(LVDS, temp);
5369         }
5370
5371         if (is_dp) {
5372                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5373         }
5374
5375         I915_WRITE(DPLL(pipe), dpll);
5376
5377         /* Wait for the clocks to stabilize. */
5378         POSTING_READ(DPLL(pipe));
5379         udelay(150);
5380
5381         if (INTEL_INFO(dev)->gen >= 4) {
5382                 temp = 0;
5383                 if (is_sdvo) {
5384                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5385                         if (temp > 1)
5386                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5387                         else
5388                                 temp = 0;
5389                 }
5390                 I915_WRITE(DPLL_MD(pipe), temp);
5391         } else {
5392                 /* The pixel multiplier can only be updated once the
5393                  * DPLL is enabled and the clocks are stable.
5394                  *
5395                  * So write it again.
5396                  */
5397                 I915_WRITE(DPLL(pipe), dpll);
5398         }
5399
5400         if (HAS_PIPE_CXSR(dev)) {
5401                 if (intel_crtc->lowfreq_avail) {
5402                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5403                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5404                 } else {
5405                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5406                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5407                 }
5408         }
5409
5410         pipeconf &= ~PIPECONF_INTERLACE_MASK;
5411         if (!IS_GEN2(dev) &&
5412             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5413                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5414                 /* the chip adds 2 halflines automatically */
5415                 adjusted_mode->crtc_vtotal -= 1;
5416                 adjusted_mode->crtc_vblank_end -= 1;
5417                 vsyncshift = adjusted_mode->crtc_hsync_start
5418                              - adjusted_mode->crtc_htotal/2;
5419         } else {
5420                 pipeconf |= PIPECONF_PROGRESSIVE;
5421                 vsyncshift = 0;
5422         }
5423
5424         if (!IS_GEN3(dev))
5425                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
5426
5427         I915_WRITE(HTOTAL(pipe),
5428                    (adjusted_mode->crtc_hdisplay - 1) |
5429                    ((adjusted_mode->crtc_htotal - 1) << 16));
5430         I915_WRITE(HBLANK(pipe),
5431                    (adjusted_mode->crtc_hblank_start - 1) |
5432                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5433         I915_WRITE(HSYNC(pipe),
5434                    (adjusted_mode->crtc_hsync_start - 1) |
5435                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5436
5437         I915_WRITE(VTOTAL(pipe),
5438                    (adjusted_mode->crtc_vdisplay - 1) |
5439                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5440         I915_WRITE(VBLANK(pipe),
5441                    (adjusted_mode->crtc_vblank_start - 1) |
5442                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5443         I915_WRITE(VSYNC(pipe),
5444                    (adjusted_mode->crtc_vsync_start - 1) |
5445                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5446
5447         /* pipesrc and dspsize control the size that is scaled from,
5448          * which should always be the user's requested size.
5449          */
5450         I915_WRITE(DSPSIZE(plane),
5451                    ((mode->vdisplay - 1) << 16) |
5452                    (mode->hdisplay - 1));
5453         I915_WRITE(DSPPOS(plane), 0);
5454         I915_WRITE(PIPESRC(pipe),
5455                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5456
5457         I915_WRITE(PIPECONF(pipe), pipeconf);
5458         POSTING_READ(PIPECONF(pipe));
5459         intel_enable_pipe(dev_priv, pipe, false);
5460
5461         intel_wait_for_vblank(dev, pipe);
5462
5463         I915_WRITE(DSPCNTR(plane), dspcntr);
5464         POSTING_READ(DSPCNTR(plane));
5465         intel_enable_plane(dev_priv, plane, pipe);
5466
5467         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5468
5469         intel_update_watermarks(dev);
5470
5471         return ret;
5472 }
5473
5474 /*
5475  * Initialize reference clocks when the driver loads
5476  */
5477 void ironlake_init_pch_refclk(struct drm_device *dev)
5478 {
5479         struct drm_i915_private *dev_priv = dev->dev_private;
5480         struct drm_mode_config *mode_config = &dev->mode_config;
5481         struct intel_encoder *encoder;
5482         u32 temp;
5483         bool has_lvds = false;
5484         bool has_cpu_edp = false;
5485         bool has_pch_edp = false;
5486         bool has_panel = false;
5487         bool has_ck505 = false;
5488         bool can_ssc = false;
5489
5490         /* We need to take the global config into account */
5491         list_for_each_entry(encoder, &mode_config->encoder_list,
5492                             base.head) {
5493                 switch (encoder->type) {
5494                 case INTEL_OUTPUT_LVDS:
5495                         has_panel = true;
5496                         has_lvds = true;
5497                         break;
5498                 case INTEL_OUTPUT_EDP:
5499                         has_panel = true;
5500                         if (intel_encoder_is_pch_edp(&encoder->base))
5501                                 has_pch_edp = true;
5502                         else
5503                                 has_cpu_edp = true;
5504                         break;
5505                 }
5506         }
5507
5508         if (HAS_PCH_IBX(dev)) {
5509                 has_ck505 = dev_priv->display_clock_mode;
5510                 can_ssc = has_ck505;
5511         } else {
5512                 has_ck505 = false;
5513                 can_ssc = true;
5514         }
5515
5516         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5517                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5518                       has_ck505);
5519
5520         /* Ironlake: try to setup display ref clock before DPLL
5521          * enabling. This is only under driver's control after
5522          * PCH B stepping, previous chipset stepping should be
5523          * ignoring this setting.
5524          */
5525         temp = I915_READ(PCH_DREF_CONTROL);
5526         /* Always enable nonspread source */
5527         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5528
5529         if (has_ck505)
5530                 temp |= DREF_NONSPREAD_CK505_ENABLE;
5531         else
5532                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5533
5534         if (has_panel) {
5535                 temp &= ~DREF_SSC_SOURCE_MASK;
5536                 temp |= DREF_SSC_SOURCE_ENABLE;
5537
5538                 /* SSC must be turned on before enabling the CPU output  */
5539                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5540                         DRM_DEBUG_KMS("Using SSC on panel\n");
5541                         temp |= DREF_SSC1_ENABLE;
5542                 }
5543
5544                 /* Get SSC going before enabling the outputs */
5545                 I915_WRITE(PCH_DREF_CONTROL, temp);
5546                 POSTING_READ(PCH_DREF_CONTROL);
5547                 udelay(200);
5548
5549                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5550
5551                 /* Enable CPU source on CPU attached eDP */
5552                 if (has_cpu_edp) {
5553                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5554                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5555                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5556                         }
5557                         else
5558                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5559                 } else
5560                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5561
5562                 I915_WRITE(PCH_DREF_CONTROL, temp);
5563                 POSTING_READ(PCH_DREF_CONTROL);
5564                 udelay(200);
5565         } else {
5566                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5567
5568                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5569
5570                 /* Turn off CPU output */
5571                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5572
5573                 I915_WRITE(PCH_DREF_CONTROL, temp);
5574                 POSTING_READ(PCH_DREF_CONTROL);
5575                 udelay(200);
5576
5577                 /* Turn off the SSC source */
5578                 temp &= ~DREF_SSC_SOURCE_MASK;
5579                 temp |= DREF_SSC_SOURCE_DISABLE;
5580
5581                 /* Turn off SSC1 */
5582                 temp &= ~ DREF_SSC1_ENABLE;
5583
5584                 I915_WRITE(PCH_DREF_CONTROL, temp);
5585                 POSTING_READ(PCH_DREF_CONTROL);
5586                 udelay(200);
5587         }
5588 }
5589
5590 static int ironlake_get_refclk(struct drm_crtc *crtc)
5591 {
5592         struct drm_device *dev = crtc->dev;
5593         struct drm_i915_private *dev_priv = dev->dev_private;
5594         struct intel_encoder *encoder;
5595         struct drm_mode_config *mode_config = &dev->mode_config;
5596         struct intel_encoder *edp_encoder = NULL;
5597         int num_connectors = 0;
5598         bool is_lvds = false;
5599
5600         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5601                 if (encoder->base.crtc != crtc)
5602                         continue;
5603
5604                 switch (encoder->type) {
5605                 case INTEL_OUTPUT_LVDS:
5606                         is_lvds = true;
5607                         break;
5608                 case INTEL_OUTPUT_EDP:
5609                         edp_encoder = encoder;
5610                         break;
5611                 }
5612                 num_connectors++;
5613         }
5614
5615         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5616                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5617                               dev_priv->lvds_ssc_freq);
5618                 return dev_priv->lvds_ssc_freq * 1000;
5619         }
5620
5621         return 120000;
5622 }
5623
5624 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5625                                   struct drm_display_mode *mode,
5626                                   struct drm_display_mode *adjusted_mode,
5627                                   int x, int y,
5628                                   struct drm_framebuffer *old_fb)
5629 {
5630         struct drm_device *dev = crtc->dev;
5631         struct drm_i915_private *dev_priv = dev->dev_private;
5632         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5633         int pipe = intel_crtc->pipe;
5634         int plane = intel_crtc->plane;
5635         int refclk, num_connectors = 0;
5636         intel_clock_t clock, reduced_clock;
5637         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5638         bool ok, has_reduced_clock = false, is_sdvo = false;
5639         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5640         struct intel_encoder *has_edp_encoder = NULL;
5641         struct drm_mode_config *mode_config = &dev->mode_config;
5642         struct intel_encoder *encoder;
5643         const intel_limit_t *limit;
5644         int ret;
5645         struct fdi_m_n m_n = {0};
5646         u32 temp;
5647         u32 lvds_sync = 0;
5648         int target_clock, pixel_multiplier, lane, link_bw, factor;
5649         unsigned int pipe_bpp;
5650         bool dither;
5651
5652         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5653                 if (encoder->base.crtc != crtc)
5654                         continue;
5655
5656                 switch (encoder->type) {
5657                 case INTEL_OUTPUT_LVDS:
5658                         is_lvds = true;
5659                         break;
5660                 case INTEL_OUTPUT_SDVO:
5661                 case INTEL_OUTPUT_HDMI:
5662                         is_sdvo = true;
5663                         if (encoder->needs_tv_clock)
5664                                 is_tv = true;
5665                         break;
5666                 case INTEL_OUTPUT_TVOUT:
5667                         is_tv = true;
5668                         break;
5669                 case INTEL_OUTPUT_ANALOG:
5670                         is_crt = true;
5671                         break;
5672                 case INTEL_OUTPUT_DISPLAYPORT:
5673                         is_dp = true;
5674                         break;
5675                 case INTEL_OUTPUT_EDP:
5676                         has_edp_encoder = encoder;
5677                         break;
5678                 }
5679
5680                 num_connectors++;
5681         }
5682
5683         refclk = ironlake_get_refclk(crtc);
5684
5685         /*
5686          * Returns a set of divisors for the desired target clock with the given
5687          * refclk, or FALSE.  The returned values represent the clock equation:
5688          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5689          */
5690         limit = intel_limit(crtc, refclk);
5691         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5692                              &clock);
5693         if (!ok) {
5694                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5695                 return -EINVAL;
5696         }
5697
5698         /* Ensure that the cursor is valid for the new mode before changing... */
5699         intel_crtc_update_cursor(crtc, true);
5700
5701         if (is_lvds && dev_priv->lvds_downclock_avail) {
5702                 /*
5703                  * Ensure we match the reduced clock's P to the target clock.
5704                  * If the clocks don't match, we can't switch the display clock
5705                  * by using the FP0/FP1. In such case we will disable the LVDS
5706                  * downclock feature.
5707                 */
5708                 has_reduced_clock = limit->find_pll(limit, crtc,
5709                                                     dev_priv->lvds_downclock,
5710                                                     refclk,
5711                                                     &clock,
5712                                                     &reduced_clock);
5713         }
5714         /* SDVO TV has fixed PLL values depend on its clock range,
5715            this mirrors vbios setting. */
5716         if (is_sdvo && is_tv) {
5717                 if (adjusted_mode->clock >= 100000
5718                     && adjusted_mode->clock < 140500) {
5719                         clock.p1 = 2;
5720                         clock.p2 = 10;
5721                         clock.n = 3;
5722                         clock.m1 = 16;
5723                         clock.m2 = 8;
5724                 } else if (adjusted_mode->clock >= 140500
5725                            && adjusted_mode->clock <= 200000) {
5726                         clock.p1 = 1;
5727                         clock.p2 = 10;
5728                         clock.n = 6;
5729                         clock.m1 = 12;
5730                         clock.m2 = 8;
5731                 }
5732         }
5733
5734         /* FDI link */
5735         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5736         lane = 0;
5737         /* CPU eDP doesn't require FDI link, so just set DP M/N
5738            according to current link config */
5739         if (has_edp_encoder &&
5740             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5741                 target_clock = mode->clock;
5742                 intel_edp_link_config(has_edp_encoder,
5743                                       &lane, &link_bw);
5744         } else {
5745                 /* [e]DP over FDI requires target mode clock
5746                    instead of link clock */
5747                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5748                         target_clock = mode->clock;
5749                 else
5750                         target_clock = adjusted_mode->clock;
5751
5752                 /* FDI is a binary signal running at ~2.7GHz, encoding
5753                  * each output octet as 10 bits. The actual frequency
5754                  * is stored as a divider into a 100MHz clock, and the
5755                  * mode pixel clock is stored in units of 1KHz.
5756                  * Hence the bw of each lane in terms of the mode signal
5757                  * is:
5758                  */
5759                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5760         }
5761
5762         /* determine panel color depth */
5763         temp = I915_READ(PIPECONF(pipe));
5764         temp &= ~PIPE_BPC_MASK;
5765         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5766         switch (pipe_bpp) {
5767         case 18:
5768                 temp |= PIPE_6BPC;
5769                 break;
5770         case 24:
5771                 temp |= PIPE_8BPC;
5772                 break;
5773         case 30:
5774                 temp |= PIPE_10BPC;
5775                 break;
5776         case 36:
5777                 temp |= PIPE_12BPC;
5778                 break;
5779         default:
5780                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5781                         pipe_bpp);
5782                 temp |= PIPE_8BPC;
5783                 pipe_bpp = 24;
5784                 break;
5785         }
5786
5787         intel_crtc->bpp = pipe_bpp;
5788         I915_WRITE(PIPECONF(pipe), temp);
5789
5790         if (!lane) {
5791                 /*
5792                  * Account for spread spectrum to avoid
5793                  * oversubscribing the link. Max center spread
5794                  * is 2.5%; use 5% for safety's sake.
5795                  */
5796                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5797                 lane = bps / (link_bw * 8) + 1;
5798         }
5799
5800         intel_crtc->fdi_lanes = lane;
5801
5802         if (pixel_multiplier > 1)
5803                 link_bw *= pixel_multiplier;
5804         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5805                              &m_n);
5806
5807         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5808         if (has_reduced_clock)
5809                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5810                         reduced_clock.m2;
5811
5812         /* Enable autotuning of the PLL clock (if permissible) */
5813         factor = 21;
5814         if (is_lvds) {
5815                 if ((intel_panel_use_ssc(dev_priv) &&
5816                      dev_priv->lvds_ssc_freq == 100) ||
5817                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5818                         factor = 25;
5819         } else if (is_sdvo && is_tv)
5820                 factor = 20;
5821
5822         if (clock.m < factor * clock.n)
5823                 fp |= FP_CB_TUNE;
5824
5825         dpll = 0;
5826
5827         if (is_lvds)
5828                 dpll |= DPLLB_MODE_LVDS;
5829         else
5830                 dpll |= DPLLB_MODE_DAC_SERIAL;
5831         if (is_sdvo) {
5832                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5833                 if (pixel_multiplier > 1) {
5834                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5835                 }
5836                 dpll |= DPLL_DVO_HIGH_SPEED;
5837         }
5838         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5839                 dpll |= DPLL_DVO_HIGH_SPEED;
5840
5841         /* compute bitmask from p1 value */
5842         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5843         /* also FPA1 */
5844         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5845
5846         switch (clock.p2) {
5847         case 5:
5848                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5849                 break;
5850         case 7:
5851                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5852                 break;
5853         case 10:
5854                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5855                 break;
5856         case 14:
5857                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5858                 break;
5859         }
5860
5861         if (is_sdvo && is_tv)
5862                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5863         else if (is_tv)
5864                 /* XXX: just matching BIOS for now */
5865                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5866                 dpll |= 3;
5867         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5868                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5869         else
5870                 dpll |= PLL_REF_INPUT_DREFCLK;
5871
5872         /* setup pipeconf */
5873         pipeconf = I915_READ(PIPECONF(pipe));
5874
5875         /* Set up the display plane register */
5876         dspcntr = DISPPLANE_GAMMA_ENABLE;
5877
5878         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5879         drm_mode_debug_printmodeline(mode);
5880
5881         /* PCH eDP needs FDI, but CPU eDP does not */
5882         if (!intel_crtc->no_pll) {
5883                 if (!has_edp_encoder ||
5884                     intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5885                         I915_WRITE(PCH_FP0(pipe), fp);
5886                         I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5887
5888                         POSTING_READ(PCH_DPLL(pipe));
5889                         udelay(150);
5890                 }
5891         } else {
5892                 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5893                     fp == I915_READ(PCH_FP0(0))) {
5894                         intel_crtc->use_pll_a = true;
5895                         DRM_DEBUG_KMS("using pipe a dpll\n");
5896                 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5897                            fp == I915_READ(PCH_FP0(1))) {
5898                         intel_crtc->use_pll_a = false;
5899                         DRM_DEBUG_KMS("using pipe b dpll\n");
5900                 } else {
5901                         DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5902                         return -EINVAL;
5903                 }
5904         }
5905
5906         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5907          * This is an exception to the general rule that mode_set doesn't turn
5908          * things on.
5909          */
5910         if (is_lvds) {
5911                 temp = I915_READ(PCH_LVDS);
5912                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5913                 if (HAS_PCH_CPT(dev)) {
5914                         temp &= ~PORT_TRANS_SEL_MASK;
5915                         temp |= PORT_TRANS_SEL_CPT(pipe);
5916                 } else {
5917                         if (pipe == 1)
5918                                 temp |= LVDS_PIPEB_SELECT;
5919                         else
5920                                 temp &= ~LVDS_PIPEB_SELECT;
5921                 }
5922
5923                 /* set the corresponsding LVDS_BORDER bit */
5924                 temp |= dev_priv->lvds_border_bits;
5925                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5926                  * set the DPLLs for dual-channel mode or not.
5927                  */
5928                 if (clock.p2 == 7)
5929                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5930                 else
5931                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5932
5933                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5934                  * appropriately here, but we need to look more thoroughly into how
5935                  * panels behave in the two modes.
5936                  */
5937                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5938                         lvds_sync |= LVDS_HSYNC_POLARITY;
5939                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5940                         lvds_sync |= LVDS_VSYNC_POLARITY;
5941                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5942                     != lvds_sync) {
5943                         char flags[2] = "-+";
5944                         DRM_INFO("Changing LVDS panel from "
5945                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5946                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5947                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5948                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5949                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5950                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5951                         temp |= lvds_sync;
5952                 }
5953                 I915_WRITE(PCH_LVDS, temp);
5954         }
5955
5956         pipeconf &= ~PIPECONF_DITHER_EN;
5957         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5958         if ((is_lvds && dev_priv->lvds_dither) || dither) {
5959                 pipeconf |= PIPECONF_DITHER_EN;
5960                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
5961         }
5962         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5963                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5964         } else {
5965                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5966                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5967                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5968                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5969                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5970         }
5971
5972         if (!intel_crtc->no_pll &&
5973             (!has_edp_encoder ||
5974              intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
5975                 I915_WRITE(PCH_DPLL(pipe), dpll);
5976
5977                 /* Wait for the clocks to stabilize. */
5978                 POSTING_READ(PCH_DPLL(pipe));
5979                 udelay(150);
5980
5981                 /* The pixel multiplier can only be updated once the
5982                  * DPLL is enabled and the clocks are stable.
5983                  *
5984                  * So write it again.
5985                  */
5986                 I915_WRITE(PCH_DPLL(pipe), dpll);
5987         }
5988
5989         intel_crtc->lowfreq_avail = false;
5990         if (!intel_crtc->no_pll) {
5991        &nb