Merge git://bedivere.hansenpartnership.com/git/scsi-rc-fixes-2.6
[linux-2.6.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *      Eric Anholt <eric@anholt.net>
25  */
26
27 #include <linux/cpufreq.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include "drmP.h"
35 #include "intel_drv.h"
36 #include "i915_drm.h"
37 #include "i915_drv.h"
38 #include "i915_trace.h"
39 #include "drm_dp_helper.h"
40
41 #include "drm_crtc_helper.h"
42
43 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
44
45 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
46 static void intel_update_watermarks(struct drm_device *dev);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
49
50 typedef struct {
51     /* given values */
52     int n;
53     int m1, m2;
54     int p1, p2;
55     /* derived values */
56     int dot;
57     int vco;
58     int m;
59     int p;
60 } intel_clock_t;
61
62 typedef struct {
63     int min, max;
64 } intel_range_t;
65
66 typedef struct {
67     int dot_limit;
68     int p2_slow, p2_fast;
69 } intel_p2_t;
70
71 #define INTEL_P2_NUM                  2
72 typedef struct intel_limit intel_limit_t;
73 struct intel_limit {
74     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
75     intel_p2_t      p2;
76     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77                       int, int, intel_clock_t *);
78 };
79
80 /* FDI */
81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
82
83 static bool
84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85                     int target, int refclk, intel_clock_t *best_clock);
86 static bool
87 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
88                         int target, int refclk, intel_clock_t *best_clock);
89
90 static bool
91 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
92                       int target, int refclk, intel_clock_t *best_clock);
93 static bool
94 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
95                            int target, int refclk, intel_clock_t *best_clock);
96
97 static inline u32 /* units of 100MHz */
98 intel_fdi_link_freq(struct drm_device *dev)
99 {
100         if (IS_GEN5(dev)) {
101                 struct drm_i915_private *dev_priv = dev->dev_private;
102                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
103         } else
104                 return 27;
105 }
106
107 static const intel_limit_t intel_limits_i8xx_dvo = {
108         .dot = { .min = 25000, .max = 350000 },
109         .vco = { .min = 930000, .max = 1400000 },
110         .n = { .min = 3, .max = 16 },
111         .m = { .min = 96, .max = 140 },
112         .m1 = { .min = 18, .max = 26 },
113         .m2 = { .min = 6, .max = 16 },
114         .p = { .min = 4, .max = 128 },
115         .p1 = { .min = 2, .max = 33 },
116         .p2 = { .dot_limit = 165000,
117                 .p2_slow = 4, .p2_fast = 2 },
118         .find_pll = intel_find_best_PLL,
119 };
120
121 static const intel_limit_t intel_limits_i8xx_lvds = {
122         .dot = { .min = 25000, .max = 350000 },
123         .vco = { .min = 930000, .max = 1400000 },
124         .n = { .min = 3, .max = 16 },
125         .m = { .min = 96, .max = 140 },
126         .m1 = { .min = 18, .max = 26 },
127         .m2 = { .min = 6, .max = 16 },
128         .p = { .min = 4, .max = 128 },
129         .p1 = { .min = 1, .max = 6 },
130         .p2 = { .dot_limit = 165000,
131                 .p2_slow = 14, .p2_fast = 7 },
132         .find_pll = intel_find_best_PLL,
133 };
134
135 static const intel_limit_t intel_limits_i9xx_sdvo = {
136         .dot = { .min = 20000, .max = 400000 },
137         .vco = { .min = 1400000, .max = 2800000 },
138         .n = { .min = 1, .max = 6 },
139         .m = { .min = 70, .max = 120 },
140         .m1 = { .min = 10, .max = 22 },
141         .m2 = { .min = 5, .max = 9 },
142         .p = { .min = 5, .max = 80 },
143         .p1 = { .min = 1, .max = 8 },
144         .p2 = { .dot_limit = 200000,
145                 .p2_slow = 10, .p2_fast = 5 },
146         .find_pll = intel_find_best_PLL,
147 };
148
149 static const intel_limit_t intel_limits_i9xx_lvds = {
150         .dot = { .min = 20000, .max = 400000 },
151         .vco = { .min = 1400000, .max = 2800000 },
152         .n = { .min = 1, .max = 6 },
153         .m = { .min = 70, .max = 120 },
154         .m1 = { .min = 10, .max = 22 },
155         .m2 = { .min = 5, .max = 9 },
156         .p = { .min = 7, .max = 98 },
157         .p1 = { .min = 1, .max = 8 },
158         .p2 = { .dot_limit = 112000,
159                 .p2_slow = 14, .p2_fast = 7 },
160         .find_pll = intel_find_best_PLL,
161 };
162
163
164 static const intel_limit_t intel_limits_g4x_sdvo = {
165         .dot = { .min = 25000, .max = 270000 },
166         .vco = { .min = 1750000, .max = 3500000},
167         .n = { .min = 1, .max = 4 },
168         .m = { .min = 104, .max = 138 },
169         .m1 = { .min = 17, .max = 23 },
170         .m2 = { .min = 5, .max = 11 },
171         .p = { .min = 10, .max = 30 },
172         .p1 = { .min = 1, .max = 3},
173         .p2 = { .dot_limit = 270000,
174                 .p2_slow = 10,
175                 .p2_fast = 10
176         },
177         .find_pll = intel_g4x_find_best_PLL,
178 };
179
180 static const intel_limit_t intel_limits_g4x_hdmi = {
181         .dot = { .min = 22000, .max = 400000 },
182         .vco = { .min = 1750000, .max = 3500000},
183         .n = { .min = 1, .max = 4 },
184         .m = { .min = 104, .max = 138 },
185         .m1 = { .min = 16, .max = 23 },
186         .m2 = { .min = 5, .max = 11 },
187         .p = { .min = 5, .max = 80 },
188         .p1 = { .min = 1, .max = 8},
189         .p2 = { .dot_limit = 165000,
190                 .p2_slow = 10, .p2_fast = 5 },
191         .find_pll = intel_g4x_find_best_PLL,
192 };
193
194 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
195         .dot = { .min = 20000, .max = 115000 },
196         .vco = { .min = 1750000, .max = 3500000 },
197         .n = { .min = 1, .max = 3 },
198         .m = { .min = 104, .max = 138 },
199         .m1 = { .min = 17, .max = 23 },
200         .m2 = { .min = 5, .max = 11 },
201         .p = { .min = 28, .max = 112 },
202         .p1 = { .min = 2, .max = 8 },
203         .p2 = { .dot_limit = 0,
204                 .p2_slow = 14, .p2_fast = 14
205         },
206         .find_pll = intel_g4x_find_best_PLL,
207 };
208
209 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
210         .dot = { .min = 80000, .max = 224000 },
211         .vco = { .min = 1750000, .max = 3500000 },
212         .n = { .min = 1, .max = 3 },
213         .m = { .min = 104, .max = 138 },
214         .m1 = { .min = 17, .max = 23 },
215         .m2 = { .min = 5, .max = 11 },
216         .p = { .min = 14, .max = 42 },
217         .p1 = { .min = 2, .max = 6 },
218         .p2 = { .dot_limit = 0,
219                 .p2_slow = 7, .p2_fast = 7
220         },
221         .find_pll = intel_g4x_find_best_PLL,
222 };
223
224 static const intel_limit_t intel_limits_g4x_display_port = {
225         .dot = { .min = 161670, .max = 227000 },
226         .vco = { .min = 1750000, .max = 3500000},
227         .n = { .min = 1, .max = 2 },
228         .m = { .min = 97, .max = 108 },
229         .m1 = { .min = 0x10, .max = 0x12 },
230         .m2 = { .min = 0x05, .max = 0x06 },
231         .p = { .min = 10, .max = 20 },
232         .p1 = { .min = 1, .max = 2},
233         .p2 = { .dot_limit = 0,
234                 .p2_slow = 10, .p2_fast = 10 },
235         .find_pll = intel_find_pll_g4x_dp,
236 };
237
238 static const intel_limit_t intel_limits_pineview_sdvo = {
239         .dot = { .min = 20000, .max = 400000},
240         .vco = { .min = 1700000, .max = 3500000 },
241         /* Pineview's Ncounter is a ring counter */
242         .n = { .min = 3, .max = 6 },
243         .m = { .min = 2, .max = 256 },
244         /* Pineview only has one combined m divider, which we treat as m2. */
245         .m1 = { .min = 0, .max = 0 },
246         .m2 = { .min = 0, .max = 254 },
247         .p = { .min = 5, .max = 80 },
248         .p1 = { .min = 1, .max = 8 },
249         .p2 = { .dot_limit = 200000,
250                 .p2_slow = 10, .p2_fast = 5 },
251         .find_pll = intel_find_best_PLL,
252 };
253
254 static const intel_limit_t intel_limits_pineview_lvds = {
255         .dot = { .min = 20000, .max = 400000 },
256         .vco = { .min = 1700000, .max = 3500000 },
257         .n = { .min = 3, .max = 6 },
258         .m = { .min = 2, .max = 256 },
259         .m1 = { .min = 0, .max = 0 },
260         .m2 = { .min = 0, .max = 254 },
261         .p = { .min = 7, .max = 112 },
262         .p1 = { .min = 1, .max = 8 },
263         .p2 = { .dot_limit = 112000,
264                 .p2_slow = 14, .p2_fast = 14 },
265         .find_pll = intel_find_best_PLL,
266 };
267
268 /* Ironlake / Sandybridge
269  *
270  * We calculate clock using (register_value + 2) for N/M1/M2, so here
271  * the range value for them is (actual_value - 2).
272  */
273 static const intel_limit_t intel_limits_ironlake_dac = {
274         .dot = { .min = 25000, .max = 350000 },
275         .vco = { .min = 1760000, .max = 3510000 },
276         .n = { .min = 1, .max = 5 },
277         .m = { .min = 79, .max = 127 },
278         .m1 = { .min = 12, .max = 22 },
279         .m2 = { .min = 5, .max = 9 },
280         .p = { .min = 5, .max = 80 },
281         .p1 = { .min = 1, .max = 8 },
282         .p2 = { .dot_limit = 225000,
283                 .p2_slow = 10, .p2_fast = 5 },
284         .find_pll = intel_g4x_find_best_PLL,
285 };
286
287 static const intel_limit_t intel_limits_ironlake_single_lvds = {
288         .dot = { .min = 25000, .max = 350000 },
289         .vco = { .min = 1760000, .max = 3510000 },
290         .n = { .min = 1, .max = 3 },
291         .m = { .min = 79, .max = 118 },
292         .m1 = { .min = 12, .max = 22 },
293         .m2 = { .min = 5, .max = 9 },
294         .p = { .min = 28, .max = 112 },
295         .p1 = { .min = 2, .max = 8 },
296         .p2 = { .dot_limit = 225000,
297                 .p2_slow = 14, .p2_fast = 14 },
298         .find_pll = intel_g4x_find_best_PLL,
299 };
300
301 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
302         .dot = { .min = 25000, .max = 350000 },
303         .vco = { .min = 1760000, .max = 3510000 },
304         .n = { .min = 1, .max = 3 },
305         .m = { .min = 79, .max = 127 },
306         .m1 = { .min = 12, .max = 22 },
307         .m2 = { .min = 5, .max = 9 },
308         .p = { .min = 14, .max = 56 },
309         .p1 = { .min = 2, .max = 8 },
310         .p2 = { .dot_limit = 225000,
311                 .p2_slow = 7, .p2_fast = 7 },
312         .find_pll = intel_g4x_find_best_PLL,
313 };
314
315 /* LVDS 100mhz refclk limits. */
316 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
317         .dot = { .min = 25000, .max = 350000 },
318         .vco = { .min = 1760000, .max = 3510000 },
319         .n = { .min = 1, .max = 2 },
320         .m = { .min = 79, .max = 126 },
321         .m1 = { .min = 12, .max = 22 },
322         .m2 = { .min = 5, .max = 9 },
323         .p = { .min = 28, .max = 112 },
324         .p1 = { .min = 2,.max = 8 },
325         .p2 = { .dot_limit = 225000,
326                 .p2_slow = 14, .p2_fast = 14 },
327         .find_pll = intel_g4x_find_best_PLL,
328 };
329
330 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
331         .dot = { .min = 25000, .max = 350000 },
332         .vco = { .min = 1760000, .max = 3510000 },
333         .n = { .min = 1, .max = 3 },
334         .m = { .min = 79, .max = 126 },
335         .m1 = { .min = 12, .max = 22 },
336         .m2 = { .min = 5, .max = 9 },
337         .p = { .min = 14, .max = 42 },
338         .p1 = { .min = 2,.max = 6 },
339         .p2 = { .dot_limit = 225000,
340                 .p2_slow = 7, .p2_fast = 7 },
341         .find_pll = intel_g4x_find_best_PLL,
342 };
343
344 static const intel_limit_t intel_limits_ironlake_display_port = {
345         .dot = { .min = 25000, .max = 350000 },
346         .vco = { .min = 1760000, .max = 3510000},
347         .n = { .min = 1, .max = 2 },
348         .m = { .min = 81, .max = 90 },
349         .m1 = { .min = 12, .max = 22 },
350         .m2 = { .min = 5, .max = 9 },
351         .p = { .min = 10, .max = 20 },
352         .p1 = { .min = 1, .max = 2},
353         .p2 = { .dot_limit = 0,
354                 .p2_slow = 10, .p2_fast = 10 },
355         .find_pll = intel_find_pll_ironlake_dp,
356 };
357
358 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
359                                                 int refclk)
360 {
361         struct drm_device *dev = crtc->dev;
362         struct drm_i915_private *dev_priv = dev->dev_private;
363         const intel_limit_t *limit;
364
365         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
366                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
367                     LVDS_CLKB_POWER_UP) {
368                         /* LVDS dual channel */
369                         if (refclk == 100000)
370                                 limit = &intel_limits_ironlake_dual_lvds_100m;
371                         else
372                                 limit = &intel_limits_ironlake_dual_lvds;
373                 } else {
374                         if (refclk == 100000)
375                                 limit = &intel_limits_ironlake_single_lvds_100m;
376                         else
377                                 limit = &intel_limits_ironlake_single_lvds;
378                 }
379         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
380                         HAS_eDP)
381                 limit = &intel_limits_ironlake_display_port;
382         else
383                 limit = &intel_limits_ironlake_dac;
384
385         return limit;
386 }
387
388 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
389 {
390         struct drm_device *dev = crtc->dev;
391         struct drm_i915_private *dev_priv = dev->dev_private;
392         const intel_limit_t *limit;
393
394         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
395                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
396                     LVDS_CLKB_POWER_UP)
397                         /* LVDS with dual channel */
398                         limit = &intel_limits_g4x_dual_channel_lvds;
399                 else
400                         /* LVDS with dual channel */
401                         limit = &intel_limits_g4x_single_channel_lvds;
402         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
403                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
404                 limit = &intel_limits_g4x_hdmi;
405         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
406                 limit = &intel_limits_g4x_sdvo;
407         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
408                 limit = &intel_limits_g4x_display_port;
409         } else /* The option is for other outputs */
410                 limit = &intel_limits_i9xx_sdvo;
411
412         return limit;
413 }
414
415 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
416 {
417         struct drm_device *dev = crtc->dev;
418         const intel_limit_t *limit;
419
420         if (HAS_PCH_SPLIT(dev))
421                 limit = intel_ironlake_limit(crtc, refclk);
422         else if (IS_G4X(dev)) {
423                 limit = intel_g4x_limit(crtc);
424         } else if (IS_PINEVIEW(dev)) {
425                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
426                         limit = &intel_limits_pineview_lvds;
427                 else
428                         limit = &intel_limits_pineview_sdvo;
429         } else if (!IS_GEN2(dev)) {
430                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
431                         limit = &intel_limits_i9xx_lvds;
432                 else
433                         limit = &intel_limits_i9xx_sdvo;
434         } else {
435                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
436                         limit = &intel_limits_i8xx_lvds;
437                 else
438                         limit = &intel_limits_i8xx_dvo;
439         }
440         return limit;
441 }
442
443 /* m1 is reserved as 0 in Pineview, n is a ring counter */
444 static void pineview_clock(int refclk, intel_clock_t *clock)
445 {
446         clock->m = clock->m2 + 2;
447         clock->p = clock->p1 * clock->p2;
448         clock->vco = refclk * clock->m / clock->n;
449         clock->dot = clock->vco / clock->p;
450 }
451
452 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
453 {
454         if (IS_PINEVIEW(dev)) {
455                 pineview_clock(refclk, clock);
456                 return;
457         }
458         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
459         clock->p = clock->p1 * clock->p2;
460         clock->vco = refclk * clock->m / (clock->n + 2);
461         clock->dot = clock->vco / clock->p;
462 }
463
464 /**
465  * Returns whether any output on the specified pipe is of the specified type
466  */
467 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
468 {
469         struct drm_device *dev = crtc->dev;
470         struct drm_mode_config *mode_config = &dev->mode_config;
471         struct intel_encoder *encoder;
472
473         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
474                 if (encoder->base.crtc == crtc && encoder->type == type)
475                         return true;
476
477         return false;
478 }
479
480 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
481 /**
482  * Returns whether the given set of divisors are valid for a given refclk with
483  * the given connectors.
484  */
485
486 static bool intel_PLL_is_valid(struct drm_device *dev,
487                                const intel_limit_t *limit,
488                                const intel_clock_t *clock)
489 {
490         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
491                 INTELPllInvalid ("p1 out of range\n");
492         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
493                 INTELPllInvalid ("p out of range\n");
494         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
495                 INTELPllInvalid ("m2 out of range\n");
496         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
497                 INTELPllInvalid ("m1 out of range\n");
498         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
499                 INTELPllInvalid ("m1 <= m2\n");
500         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
501                 INTELPllInvalid ("m out of range\n");
502         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
503                 INTELPllInvalid ("n out of range\n");
504         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
505                 INTELPllInvalid ("vco out of range\n");
506         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
507          * connector, etc., rather than just a single range.
508          */
509         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
510                 INTELPllInvalid ("dot out of range\n");
511
512         return true;
513 }
514
515 static bool
516 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
517                     int target, int refclk, intel_clock_t *best_clock)
518
519 {
520         struct drm_device *dev = crtc->dev;
521         struct drm_i915_private *dev_priv = dev->dev_private;
522         intel_clock_t clock;
523         int err = target;
524
525         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
526             (I915_READ(LVDS)) != 0) {
527                 /*
528                  * For LVDS, if the panel is on, just rely on its current
529                  * settings for dual-channel.  We haven't figured out how to
530                  * reliably set up different single/dual channel state, if we
531                  * even can.
532                  */
533                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
534                     LVDS_CLKB_POWER_UP)
535                         clock.p2 = limit->p2.p2_fast;
536                 else
537                         clock.p2 = limit->p2.p2_slow;
538         } else {
539                 if (target < limit->p2.dot_limit)
540                         clock.p2 = limit->p2.p2_slow;
541                 else
542                         clock.p2 = limit->p2.p2_fast;
543         }
544
545         memset (best_clock, 0, sizeof (*best_clock));
546
547         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
548              clock.m1++) {
549                 for (clock.m2 = limit->m2.min;
550                      clock.m2 <= limit->m2.max; clock.m2++) {
551                         /* m1 is always 0 in Pineview */
552                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
553                                 break;
554                         for (clock.n = limit->n.min;
555                              clock.n <= limit->n.max; clock.n++) {
556                                 for (clock.p1 = limit->p1.min;
557                                         clock.p1 <= limit->p1.max; clock.p1++) {
558                                         int this_err;
559
560                                         intel_clock(dev, refclk, &clock);
561                                         if (!intel_PLL_is_valid(dev, limit,
562                                                                 &clock))
563                                                 continue;
564
565                                         this_err = abs(clock.dot - target);
566                                         if (this_err < err) {
567                                                 *best_clock = clock;
568                                                 err = this_err;
569                                         }
570                                 }
571                         }
572                 }
573         }
574
575         return (err != target);
576 }
577
578 static bool
579 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
580                         int target, int refclk, intel_clock_t *best_clock)
581 {
582         struct drm_device *dev = crtc->dev;
583         struct drm_i915_private *dev_priv = dev->dev_private;
584         intel_clock_t clock;
585         int max_n;
586         bool found;
587         /* approximately equals target * 0.00585 */
588         int err_most = (target >> 8) + (target >> 9);
589         found = false;
590
591         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
592                 int lvds_reg;
593
594                 if (HAS_PCH_SPLIT(dev))
595                         lvds_reg = PCH_LVDS;
596                 else
597                         lvds_reg = LVDS;
598                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
599                     LVDS_CLKB_POWER_UP)
600                         clock.p2 = limit->p2.p2_fast;
601                 else
602                         clock.p2 = limit->p2.p2_slow;
603         } else {
604                 if (target < limit->p2.dot_limit)
605                         clock.p2 = limit->p2.p2_slow;
606                 else
607                         clock.p2 = limit->p2.p2_fast;
608         }
609
610         memset(best_clock, 0, sizeof(*best_clock));
611         max_n = limit->n.max;
612         /* based on hardware requirement, prefer smaller n to precision */
613         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
614                 /* based on hardware requirement, prefere larger m1,m2 */
615                 for (clock.m1 = limit->m1.max;
616                      clock.m1 >= limit->m1.min; clock.m1--) {
617                         for (clock.m2 = limit->m2.max;
618                              clock.m2 >= limit->m2.min; clock.m2--) {
619                                 for (clock.p1 = limit->p1.max;
620                                      clock.p1 >= limit->p1.min; clock.p1--) {
621                                         int this_err;
622
623                                         intel_clock(dev, refclk, &clock);
624                                         if (!intel_PLL_is_valid(dev, limit,
625                                                                 &clock))
626                                                 continue;
627
628                                         this_err = abs(clock.dot - target);
629                                         if (this_err < err_most) {
630                                                 *best_clock = clock;
631                                                 err_most = this_err;
632                                                 max_n = clock.n;
633                                                 found = true;
634                                         }
635                                 }
636                         }
637                 }
638         }
639         return found;
640 }
641
642 static bool
643 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
644                            int target, int refclk, intel_clock_t *best_clock)
645 {
646         struct drm_device *dev = crtc->dev;
647         intel_clock_t clock;
648
649         if (target < 200000) {
650                 clock.n = 1;
651                 clock.p1 = 2;
652                 clock.p2 = 10;
653                 clock.m1 = 12;
654                 clock.m2 = 9;
655         } else {
656                 clock.n = 2;
657                 clock.p1 = 1;
658                 clock.p2 = 10;
659                 clock.m1 = 14;
660                 clock.m2 = 8;
661         }
662         intel_clock(dev, refclk, &clock);
663         memcpy(best_clock, &clock, sizeof(intel_clock_t));
664         return true;
665 }
666
667 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
668 static bool
669 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
670                       int target, int refclk, intel_clock_t *best_clock)
671 {
672         intel_clock_t clock;
673         if (target < 200000) {
674                 clock.p1 = 2;
675                 clock.p2 = 10;
676                 clock.n = 2;
677                 clock.m1 = 23;
678                 clock.m2 = 8;
679         } else {
680                 clock.p1 = 1;
681                 clock.p2 = 10;
682                 clock.n = 1;
683                 clock.m1 = 14;
684                 clock.m2 = 2;
685         }
686         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
687         clock.p = (clock.p1 * clock.p2);
688         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
689         clock.vco = 0;
690         memcpy(best_clock, &clock, sizeof(intel_clock_t));
691         return true;
692 }
693
694 /**
695  * intel_wait_for_vblank - wait for vblank on a given pipe
696  * @dev: drm device
697  * @pipe: pipe to wait for
698  *
699  * Wait for vblank to occur on a given pipe.  Needed for various bits of
700  * mode setting code.
701  */
702 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
703 {
704         struct drm_i915_private *dev_priv = dev->dev_private;
705         int pipestat_reg = PIPESTAT(pipe);
706
707         /* Clear existing vblank status. Note this will clear any other
708          * sticky status fields as well.
709          *
710          * This races with i915_driver_irq_handler() with the result
711          * that either function could miss a vblank event.  Here it is not
712          * fatal, as we will either wait upon the next vblank interrupt or
713          * timeout.  Generally speaking intel_wait_for_vblank() is only
714          * called during modeset at which time the GPU should be idle and
715          * should *not* be performing page flips and thus not waiting on
716          * vblanks...
717          * Currently, the result of us stealing a vblank from the irq
718          * handler is that a single frame will be skipped during swapbuffers.
719          */
720         I915_WRITE(pipestat_reg,
721                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
722
723         /* Wait for vblank interrupt bit to set */
724         if (wait_for(I915_READ(pipestat_reg) &
725                      PIPE_VBLANK_INTERRUPT_STATUS,
726                      50))
727                 DRM_DEBUG_KMS("vblank wait timed out\n");
728 }
729
730 /*
731  * intel_wait_for_pipe_off - wait for pipe to turn off
732  * @dev: drm device
733  * @pipe: pipe to wait for
734  *
735  * After disabling a pipe, we can't wait for vblank in the usual way,
736  * spinning on the vblank interrupt status bit, since we won't actually
737  * see an interrupt when the pipe is disabled.
738  *
739  * On Gen4 and above:
740  *   wait for the pipe register state bit to turn off
741  *
742  * Otherwise:
743  *   wait for the display line value to settle (it usually
744  *   ends up stopping at the start of the next frame).
745  *
746  */
747 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
748 {
749         struct drm_i915_private *dev_priv = dev->dev_private;
750
751         if (INTEL_INFO(dev)->gen >= 4) {
752                 int reg = PIPECONF(pipe);
753
754                 /* Wait for the Pipe State to go off */
755                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
756                              100))
757                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
758         } else {
759                 u32 last_line;
760                 int reg = PIPEDSL(pipe);
761                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
762
763                 /* Wait for the display line to settle */
764                 do {
765                         last_line = I915_READ(reg) & DSL_LINEMASK;
766                         mdelay(5);
767                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
768                          time_after(timeout, jiffies));
769                 if (time_after(jiffies, timeout))
770                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
771         }
772 }
773
774 static const char *state_string(bool enabled)
775 {
776         return enabled ? "on" : "off";
777 }
778
779 /* Only for pre-ILK configs */
780 static void assert_pll(struct drm_i915_private *dev_priv,
781                        enum pipe pipe, bool state)
782 {
783         int reg;
784         u32 val;
785         bool cur_state;
786
787         reg = DPLL(pipe);
788         val = I915_READ(reg);
789         cur_state = !!(val & DPLL_VCO_ENABLE);
790         WARN(cur_state != state,
791              "PLL state assertion failure (expected %s, current %s)\n",
792              state_string(state), state_string(cur_state));
793 }
794 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
795 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
796
797 /* For ILK+ */
798 static void assert_pch_pll(struct drm_i915_private *dev_priv,
799                            enum pipe pipe, bool state)
800 {
801         int reg;
802         u32 val;
803         bool cur_state;
804
805         reg = PCH_DPLL(pipe);
806         val = I915_READ(reg);
807         cur_state = !!(val & DPLL_VCO_ENABLE);
808         WARN(cur_state != state,
809              "PCH PLL state assertion failure (expected %s, current %s)\n",
810              state_string(state), state_string(cur_state));
811 }
812 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
813 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
814
815 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
816                           enum pipe pipe, bool state)
817 {
818         int reg;
819         u32 val;
820         bool cur_state;
821
822         reg = FDI_TX_CTL(pipe);
823         val = I915_READ(reg);
824         cur_state = !!(val & FDI_TX_ENABLE);
825         WARN(cur_state != state,
826              "FDI TX state assertion failure (expected %s, current %s)\n",
827              state_string(state), state_string(cur_state));
828 }
829 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
830 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
831
832 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
833                           enum pipe pipe, bool state)
834 {
835         int reg;
836         u32 val;
837         bool cur_state;
838
839         reg = FDI_RX_CTL(pipe);
840         val = I915_READ(reg);
841         cur_state = !!(val & FDI_RX_ENABLE);
842         WARN(cur_state != state,
843              "FDI RX state assertion failure (expected %s, current %s)\n",
844              state_string(state), state_string(cur_state));
845 }
846 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
847 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
848
849 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
850                                       enum pipe pipe)
851 {
852         int reg;
853         u32 val;
854
855         /* ILK FDI PLL is always enabled */
856         if (dev_priv->info->gen == 5)
857                 return;
858
859         reg = FDI_TX_CTL(pipe);
860         val = I915_READ(reg);
861         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
862 }
863
864 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
865                                       enum pipe pipe)
866 {
867         int reg;
868         u32 val;
869
870         reg = FDI_RX_CTL(pipe);
871         val = I915_READ(reg);
872         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
873 }
874
875 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
876                                   enum pipe pipe)
877 {
878         int pp_reg, lvds_reg;
879         u32 val;
880         enum pipe panel_pipe = PIPE_A;
881         bool locked = true;
882
883         if (HAS_PCH_SPLIT(dev_priv->dev)) {
884                 pp_reg = PCH_PP_CONTROL;
885                 lvds_reg = PCH_LVDS;
886         } else {
887                 pp_reg = PP_CONTROL;
888                 lvds_reg = LVDS;
889         }
890
891         val = I915_READ(pp_reg);
892         if (!(val & PANEL_POWER_ON) ||
893             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
894                 locked = false;
895
896         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
897                 panel_pipe = PIPE_B;
898
899         WARN(panel_pipe == pipe && locked,
900              "panel assertion failure, pipe %c regs locked\n",
901              pipe_name(pipe));
902 }
903
904 static void assert_pipe(struct drm_i915_private *dev_priv,
905                         enum pipe pipe, bool state)
906 {
907         int reg;
908         u32 val;
909         bool cur_state;
910
911         reg = PIPECONF(pipe);
912         val = I915_READ(reg);
913         cur_state = !!(val & PIPECONF_ENABLE);
914         WARN(cur_state != state,
915              "pipe %c assertion failure (expected %s, current %s)\n",
916              pipe_name(pipe), state_string(state), state_string(cur_state));
917 }
918 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
919 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
920
921 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
922                                  enum plane plane)
923 {
924         int reg;
925         u32 val;
926
927         reg = DSPCNTR(plane);
928         val = I915_READ(reg);
929         WARN(!(val & DISPLAY_PLANE_ENABLE),
930              "plane %c assertion failure, should be active but is disabled\n",
931              plane_name(plane));
932 }
933
934 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
935                                    enum pipe pipe)
936 {
937         int reg, i;
938         u32 val;
939         int cur_pipe;
940
941         /* Planes are fixed to pipes on ILK+ */
942         if (HAS_PCH_SPLIT(dev_priv->dev))
943                 return;
944
945         /* Need to check both planes against the pipe */
946         for (i = 0; i < 2; i++) {
947                 reg = DSPCNTR(i);
948                 val = I915_READ(reg);
949                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
950                         DISPPLANE_SEL_PIPE_SHIFT;
951                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
952                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
953                      plane_name(i), pipe_name(pipe));
954         }
955 }
956
957 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
958 {
959         u32 val;
960         bool enabled;
961
962         val = I915_READ(PCH_DREF_CONTROL);
963         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
964                             DREF_SUPERSPREAD_SOURCE_MASK));
965         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
966 }
967
968 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
969                                        enum pipe pipe)
970 {
971         int reg;
972         u32 val;
973         bool enabled;
974
975         reg = TRANSCONF(pipe);
976         val = I915_READ(reg);
977         enabled = !!(val & TRANS_ENABLE);
978         WARN(enabled,
979              "transcoder assertion failed, should be off on pipe %c but is still active\n",
980              pipe_name(pipe));
981 }
982
983 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
984                             enum pipe pipe, u32 port_sel, u32 val)
985 {
986         if ((val & DP_PORT_EN) == 0)
987                 return false;
988
989         if (HAS_PCH_CPT(dev_priv->dev)) {
990                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
991                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
992                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
993                         return false;
994         } else {
995                 if ((val & DP_PIPE_MASK) != (pipe << 30))
996                         return false;
997         }
998         return true;
999 }
1000
1001 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1002                               enum pipe pipe, u32 val)
1003 {
1004         if ((val & PORT_ENABLE) == 0)
1005                 return false;
1006
1007         if (HAS_PCH_CPT(dev_priv->dev)) {
1008                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1009                         return false;
1010         } else {
1011                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1012                         return false;
1013         }
1014         return true;
1015 }
1016
1017 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1018                               enum pipe pipe, u32 val)
1019 {
1020         if ((val & LVDS_PORT_EN) == 0)
1021                 return false;
1022
1023         if (HAS_PCH_CPT(dev_priv->dev)) {
1024                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1025                         return false;
1026         } else {
1027                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1028                         return false;
1029         }
1030         return true;
1031 }
1032
1033 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1034                               enum pipe pipe, u32 val)
1035 {
1036         if ((val & ADPA_DAC_ENABLE) == 0)
1037                 return false;
1038         if (HAS_PCH_CPT(dev_priv->dev)) {
1039                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1040                         return false;
1041         } else {
1042                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1043                         return false;
1044         }
1045         return true;
1046 }
1047
1048 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1049                                    enum pipe pipe, int reg, u32 port_sel)
1050 {
1051         u32 val = I915_READ(reg);
1052         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1053              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1054              reg, pipe_name(pipe));
1055 }
1056
1057 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1058                                      enum pipe pipe, int reg)
1059 {
1060         u32 val = I915_READ(reg);
1061         WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1062              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1063              reg, pipe_name(pipe));
1064 }
1065
1066 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1067                                       enum pipe pipe)
1068 {
1069         int reg;
1070         u32 val;
1071
1072         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1073         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1074         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1075
1076         reg = PCH_ADPA;
1077         val = I915_READ(reg);
1078         WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1079              "PCH VGA enabled on transcoder %c, should be disabled\n",
1080              pipe_name(pipe));
1081
1082         reg = PCH_LVDS;
1083         val = I915_READ(reg);
1084         WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1085              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1086              pipe_name(pipe));
1087
1088         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1089         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1090         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1091 }
1092
1093 /**
1094  * intel_enable_pll - enable a PLL
1095  * @dev_priv: i915 private structure
1096  * @pipe: pipe PLL to enable
1097  *
1098  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1099  * make sure the PLL reg is writable first though, since the panel write
1100  * protect mechanism may be enabled.
1101  *
1102  * Note!  This is for pre-ILK only.
1103  */
1104 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1105 {
1106         int reg;
1107         u32 val;
1108
1109         /* No really, not for ILK+ */
1110         BUG_ON(dev_priv->info->gen >= 5);
1111
1112         /* PLL is protected by panel, make sure we can write it */
1113         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1114                 assert_panel_unlocked(dev_priv, pipe);
1115
1116         reg = DPLL(pipe);
1117         val = I915_READ(reg);
1118         val |= DPLL_VCO_ENABLE;
1119
1120         /* We do this three times for luck */
1121         I915_WRITE(reg, val);
1122         POSTING_READ(reg);
1123         udelay(150); /* wait for warmup */
1124         I915_WRITE(reg, val);
1125         POSTING_READ(reg);
1126         udelay(150); /* wait for warmup */
1127         I915_WRITE(reg, val);
1128         POSTING_READ(reg);
1129         udelay(150); /* wait for warmup */
1130 }
1131
1132 /**
1133  * intel_disable_pll - disable a PLL
1134  * @dev_priv: i915 private structure
1135  * @pipe: pipe PLL to disable
1136  *
1137  * Disable the PLL for @pipe, making sure the pipe is off first.
1138  *
1139  * Note!  This is for pre-ILK only.
1140  */
1141 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1142 {
1143         int reg;
1144         u32 val;
1145
1146         /* Don't disable pipe A or pipe A PLLs if needed */
1147         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1148                 return;
1149
1150         /* Make sure the pipe isn't still relying on us */
1151         assert_pipe_disabled(dev_priv, pipe);
1152
1153         reg = DPLL(pipe);
1154         val = I915_READ(reg);
1155         val &= ~DPLL_VCO_ENABLE;
1156         I915_WRITE(reg, val);
1157         POSTING_READ(reg);
1158 }
1159
1160 /**
1161  * intel_enable_pch_pll - enable PCH PLL
1162  * @dev_priv: i915 private structure
1163  * @pipe: pipe PLL to enable
1164  *
1165  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1166  * drives the transcoder clock.
1167  */
1168 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1169                                  enum pipe pipe)
1170 {
1171         int reg;
1172         u32 val;
1173
1174         /* PCH only available on ILK+ */
1175         BUG_ON(dev_priv->info->gen < 5);
1176
1177         /* PCH refclock must be enabled first */
1178         assert_pch_refclk_enabled(dev_priv);
1179
1180         reg = PCH_DPLL(pipe);
1181         val = I915_READ(reg);
1182         val |= DPLL_VCO_ENABLE;
1183         I915_WRITE(reg, val);
1184         POSTING_READ(reg);
1185         udelay(200);
1186 }
1187
1188 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1189                                   enum pipe pipe)
1190 {
1191         int reg;
1192         u32 val;
1193
1194         /* PCH only available on ILK+ */
1195         BUG_ON(dev_priv->info->gen < 5);
1196
1197         /* Make sure transcoder isn't still depending on us */
1198         assert_transcoder_disabled(dev_priv, pipe);
1199
1200         reg = PCH_DPLL(pipe);
1201         val = I915_READ(reg);
1202         val &= ~DPLL_VCO_ENABLE;
1203         I915_WRITE(reg, val);
1204         POSTING_READ(reg);
1205         udelay(200);
1206 }
1207
1208 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1209                                     enum pipe pipe)
1210 {
1211         int reg;
1212         u32 val;
1213
1214         /* PCH only available on ILK+ */
1215         BUG_ON(dev_priv->info->gen < 5);
1216
1217         /* Make sure PCH DPLL is enabled */
1218         assert_pch_pll_enabled(dev_priv, pipe);
1219
1220         /* FDI must be feeding us bits for PCH ports */
1221         assert_fdi_tx_enabled(dev_priv, pipe);
1222         assert_fdi_rx_enabled(dev_priv, pipe);
1223
1224         reg = TRANSCONF(pipe);
1225         val = I915_READ(reg);
1226
1227         if (HAS_PCH_IBX(dev_priv->dev)) {
1228                 /*
1229                  * make the BPC in transcoder be consistent with
1230                  * that in pipeconf reg.
1231                  */
1232                 val &= ~PIPE_BPC_MASK;
1233                 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1234         }
1235         I915_WRITE(reg, val | TRANS_ENABLE);
1236         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1237                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1238 }
1239
1240 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1241                                      enum pipe pipe)
1242 {
1243         int reg;
1244         u32 val;
1245
1246         /* FDI relies on the transcoder */
1247         assert_fdi_tx_disabled(dev_priv, pipe);
1248         assert_fdi_rx_disabled(dev_priv, pipe);
1249
1250         /* Ports must be off as well */
1251         assert_pch_ports_disabled(dev_priv, pipe);
1252
1253         reg = TRANSCONF(pipe);
1254         val = I915_READ(reg);
1255         val &= ~TRANS_ENABLE;
1256         I915_WRITE(reg, val);
1257         /* wait for PCH transcoder off, transcoder state */
1258         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1259                 DRM_ERROR("failed to disable transcoder\n");
1260 }
1261
1262 /**
1263  * intel_enable_pipe - enable a pipe, asserting requirements
1264  * @dev_priv: i915 private structure
1265  * @pipe: pipe to enable
1266  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1267  *
1268  * Enable @pipe, making sure that various hardware specific requirements
1269  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1270  *
1271  * @pipe should be %PIPE_A or %PIPE_B.
1272  *
1273  * Will wait until the pipe is actually running (i.e. first vblank) before
1274  * returning.
1275  */
1276 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1277                               bool pch_port)
1278 {
1279         int reg;
1280         u32 val;
1281
1282         /*
1283          * A pipe without a PLL won't actually be able to drive bits from
1284          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1285          * need the check.
1286          */
1287         if (!HAS_PCH_SPLIT(dev_priv->dev))
1288                 assert_pll_enabled(dev_priv, pipe);
1289         else {
1290                 if (pch_port) {
1291                         /* if driving the PCH, we need FDI enabled */
1292                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1293                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1294                 }
1295                 /* FIXME: assert CPU port conditions for SNB+ */
1296         }
1297
1298         reg = PIPECONF(pipe);
1299         val = I915_READ(reg);
1300         if (val & PIPECONF_ENABLE)
1301                 return;
1302
1303         I915_WRITE(reg, val | PIPECONF_ENABLE);
1304         intel_wait_for_vblank(dev_priv->dev, pipe);
1305 }
1306
1307 /**
1308  * intel_disable_pipe - disable a pipe, asserting requirements
1309  * @dev_priv: i915 private structure
1310  * @pipe: pipe to disable
1311  *
1312  * Disable @pipe, making sure that various hardware specific requirements
1313  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1314  *
1315  * @pipe should be %PIPE_A or %PIPE_B.
1316  *
1317  * Will wait until the pipe has shut down before returning.
1318  */
1319 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1320                                enum pipe pipe)
1321 {
1322         int reg;
1323         u32 val;
1324
1325         /*
1326          * Make sure planes won't keep trying to pump pixels to us,
1327          * or we might hang the display.
1328          */
1329         assert_planes_disabled(dev_priv, pipe);
1330
1331         /* Don't disable pipe A or pipe A PLLs if needed */
1332         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1333                 return;
1334
1335         reg = PIPECONF(pipe);
1336         val = I915_READ(reg);
1337         if ((val & PIPECONF_ENABLE) == 0)
1338                 return;
1339
1340         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1341         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1342 }
1343
1344 /*
1345  * Plane regs are double buffered, going from enabled->disabled needs a
1346  * trigger in order to latch.  The display address reg provides this.
1347  */
1348 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1349                                       enum plane plane)
1350 {
1351         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1352         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1353 }
1354
1355 /**
1356  * intel_enable_plane - enable a display plane on a given pipe
1357  * @dev_priv: i915 private structure
1358  * @plane: plane to enable
1359  * @pipe: pipe being fed
1360  *
1361  * Enable @plane on @pipe, making sure that @pipe is running first.
1362  */
1363 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1364                                enum plane plane, enum pipe pipe)
1365 {
1366         int reg;
1367         u32 val;
1368
1369         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1370         assert_pipe_enabled(dev_priv, pipe);
1371
1372         reg = DSPCNTR(plane);
1373         val = I915_READ(reg);
1374         if (val & DISPLAY_PLANE_ENABLE)
1375                 return;
1376
1377         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1378         intel_flush_display_plane(dev_priv, plane);
1379         intel_wait_for_vblank(dev_priv->dev, pipe);
1380 }
1381
1382 /**
1383  * intel_disable_plane - disable a display plane
1384  * @dev_priv: i915 private structure
1385  * @plane: plane to disable
1386  * @pipe: pipe consuming the data
1387  *
1388  * Disable @plane; should be an independent operation.
1389  */
1390 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1391                                 enum plane plane, enum pipe pipe)
1392 {
1393         int reg;
1394         u32 val;
1395
1396         reg = DSPCNTR(plane);
1397         val = I915_READ(reg);
1398         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1399                 return;
1400
1401         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1402         intel_flush_display_plane(dev_priv, plane);
1403         intel_wait_for_vblank(dev_priv->dev, pipe);
1404 }
1405
1406 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1407                            enum pipe pipe, int reg, u32 port_sel)
1408 {
1409         u32 val = I915_READ(reg);
1410         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1411                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1412                 I915_WRITE(reg, val & ~DP_PORT_EN);
1413         }
1414 }
1415
1416 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1417                              enum pipe pipe, int reg)
1418 {
1419         u32 val = I915_READ(reg);
1420         if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1421                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1422                               reg, pipe);
1423                 I915_WRITE(reg, val & ~PORT_ENABLE);
1424         }
1425 }
1426
1427 /* Disable any ports connected to this transcoder */
1428 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1429                                     enum pipe pipe)
1430 {
1431         u32 reg, val;
1432
1433         val = I915_READ(PCH_PP_CONTROL);
1434         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1435
1436         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1437         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1438         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1439
1440         reg = PCH_ADPA;
1441         val = I915_READ(reg);
1442         if (adpa_pipe_enabled(dev_priv, val, pipe))
1443                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1444
1445         reg = PCH_LVDS;
1446         val = I915_READ(reg);
1447         if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1448                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1449                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1450                 POSTING_READ(reg);
1451                 udelay(100);
1452         }
1453
1454         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1455         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1456         disable_pch_hdmi(dev_priv, pipe, HDMID);
1457 }
1458
1459 static void i8xx_disable_fbc(struct drm_device *dev)
1460 {
1461         struct drm_i915_private *dev_priv = dev->dev_private;
1462         u32 fbc_ctl;
1463
1464         /* Disable compression */
1465         fbc_ctl = I915_READ(FBC_CONTROL);
1466         if ((fbc_ctl & FBC_CTL_EN) == 0)
1467                 return;
1468
1469         fbc_ctl &= ~FBC_CTL_EN;
1470         I915_WRITE(FBC_CONTROL, fbc_ctl);
1471
1472         /* Wait for compressing bit to clear */
1473         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1474                 DRM_DEBUG_KMS("FBC idle timed out\n");
1475                 return;
1476         }
1477
1478         DRM_DEBUG_KMS("disabled FBC\n");
1479 }
1480
1481 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1482 {
1483         struct drm_device *dev = crtc->dev;
1484         struct drm_i915_private *dev_priv = dev->dev_private;
1485         struct drm_framebuffer *fb = crtc->fb;
1486         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1487         struct drm_i915_gem_object *obj = intel_fb->obj;
1488         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1489         int cfb_pitch;
1490         int plane, i;
1491         u32 fbc_ctl, fbc_ctl2;
1492
1493         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1494         if (fb->pitch < cfb_pitch)
1495                 cfb_pitch = fb->pitch;
1496
1497         /* FBC_CTL wants 64B units */
1498         cfb_pitch = (cfb_pitch / 64) - 1;
1499         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1500
1501         /* Clear old tags */
1502         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1503                 I915_WRITE(FBC_TAG + (i * 4), 0);
1504
1505         /* Set it up... */
1506         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1507         fbc_ctl2 |= plane;
1508         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1509         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1510
1511         /* enable it... */
1512         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1513         if (IS_I945GM(dev))
1514                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1515         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1516         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1517         fbc_ctl |= obj->fence_reg;
1518         I915_WRITE(FBC_CONTROL, fbc_ctl);
1519
1520         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1521                       cfb_pitch, crtc->y, intel_crtc->plane);
1522 }
1523
1524 static bool i8xx_fbc_enabled(struct drm_device *dev)
1525 {
1526         struct drm_i915_private *dev_priv = dev->dev_private;
1527
1528         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1529 }
1530
1531 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1532 {
1533         struct drm_device *dev = crtc->dev;
1534         struct drm_i915_private *dev_priv = dev->dev_private;
1535         struct drm_framebuffer *fb = crtc->fb;
1536         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1537         struct drm_i915_gem_object *obj = intel_fb->obj;
1538         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1539         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1540         unsigned long stall_watermark = 200;
1541         u32 dpfc_ctl;
1542
1543         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1544         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1545         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1546
1547         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1548                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1549                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1550         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1551
1552         /* enable it... */
1553         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1554
1555         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1556 }
1557
1558 static void g4x_disable_fbc(struct drm_device *dev)
1559 {
1560         struct drm_i915_private *dev_priv = dev->dev_private;
1561         u32 dpfc_ctl;
1562
1563         /* Disable compression */
1564         dpfc_ctl = I915_READ(DPFC_CONTROL);
1565         if (dpfc_ctl & DPFC_CTL_EN) {
1566                 dpfc_ctl &= ~DPFC_CTL_EN;
1567                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1568
1569                 DRM_DEBUG_KMS("disabled FBC\n");
1570         }
1571 }
1572
1573 static bool g4x_fbc_enabled(struct drm_device *dev)
1574 {
1575         struct drm_i915_private *dev_priv = dev->dev_private;
1576
1577         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1578 }
1579
1580 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1581 {
1582         struct drm_i915_private *dev_priv = dev->dev_private;
1583         u32 blt_ecoskpd;
1584
1585         /* Make sure blitter notifies FBC of writes */
1586         gen6_gt_force_wake_get(dev_priv);
1587         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1588         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1589                 GEN6_BLITTER_LOCK_SHIFT;
1590         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1591         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1592         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1593         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1594                          GEN6_BLITTER_LOCK_SHIFT);
1595         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1596         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1597         gen6_gt_force_wake_put(dev_priv);
1598 }
1599
1600 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1601 {
1602         struct drm_device *dev = crtc->dev;
1603         struct drm_i915_private *dev_priv = dev->dev_private;
1604         struct drm_framebuffer *fb = crtc->fb;
1605         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1606         struct drm_i915_gem_object *obj = intel_fb->obj;
1607         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1608         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1609         unsigned long stall_watermark = 200;
1610         u32 dpfc_ctl;
1611
1612         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1613         dpfc_ctl &= DPFC_RESERVED;
1614         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1615         /* Set persistent mode for front-buffer rendering, ala X. */
1616         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1617         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1618         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1619
1620         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1621                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1622                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1623         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1624         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1625         /* enable it... */
1626         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1627
1628         if (IS_GEN6(dev)) {
1629                 I915_WRITE(SNB_DPFC_CTL_SA,
1630                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1631                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1632                 sandybridge_blit_fbc_update(dev);
1633         }
1634
1635         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1636 }
1637
1638 static void ironlake_disable_fbc(struct drm_device *dev)
1639 {
1640         struct drm_i915_private *dev_priv = dev->dev_private;
1641         u32 dpfc_ctl;
1642
1643         /* Disable compression */
1644         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1645         if (dpfc_ctl & DPFC_CTL_EN) {
1646                 dpfc_ctl &= ~DPFC_CTL_EN;
1647                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1648
1649                 DRM_DEBUG_KMS("disabled FBC\n");
1650         }
1651 }
1652
1653 static bool ironlake_fbc_enabled(struct drm_device *dev)
1654 {
1655         struct drm_i915_private *dev_priv = dev->dev_private;
1656
1657         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1658 }
1659
1660 bool intel_fbc_enabled(struct drm_device *dev)
1661 {
1662         struct drm_i915_private *dev_priv = dev->dev_private;
1663
1664         if (!dev_priv->display.fbc_enabled)
1665                 return false;
1666
1667         return dev_priv->display.fbc_enabled(dev);
1668 }
1669
1670 static void intel_fbc_work_fn(struct work_struct *__work)
1671 {
1672         struct intel_fbc_work *work =
1673                 container_of(to_delayed_work(__work),
1674                              struct intel_fbc_work, work);
1675         struct drm_device *dev = work->crtc->dev;
1676         struct drm_i915_private *dev_priv = dev->dev_private;
1677
1678         mutex_lock(&dev->struct_mutex);
1679         if (work == dev_priv->fbc_work) {
1680                 /* Double check that we haven't switched fb without cancelling
1681                  * the prior work.
1682                  */
1683                 if (work->crtc->fb == work->fb) {
1684                         dev_priv->display.enable_fbc(work->crtc,
1685                                                      work->interval);
1686
1687                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1688                         dev_priv->cfb_fb = work->crtc->fb->base.id;
1689                         dev_priv->cfb_y = work->crtc->y;
1690                 }
1691
1692                 dev_priv->fbc_work = NULL;
1693         }
1694         mutex_unlock(&dev->struct_mutex);
1695
1696         kfree(work);
1697 }
1698
1699 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1700 {
1701         if (dev_priv->fbc_work == NULL)
1702                 return;
1703
1704         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1705
1706         /* Synchronisation is provided by struct_mutex and checking of
1707          * dev_priv->fbc_work, so we can perform the cancellation
1708          * entirely asynchronously.
1709          */
1710         if (cancel_delayed_work(&dev_priv->fbc_work->work))
1711                 /* tasklet was killed before being run, clean up */
1712                 kfree(dev_priv->fbc_work);
1713
1714         /* Mark the work as no longer wanted so that if it does
1715          * wake-up (because the work was already running and waiting
1716          * for our mutex), it will discover that is no longer
1717          * necessary to run.
1718          */
1719         dev_priv->fbc_work = NULL;
1720 }
1721
1722 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1723 {
1724         struct intel_fbc_work *work;
1725         struct drm_device *dev = crtc->dev;
1726         struct drm_i915_private *dev_priv = dev->dev_private;
1727
1728         if (!dev_priv->display.enable_fbc)
1729                 return;
1730
1731         intel_cancel_fbc_work(dev_priv);
1732
1733         work = kzalloc(sizeof *work, GFP_KERNEL);
1734         if (work == NULL) {
1735                 dev_priv->display.enable_fbc(crtc, interval);
1736                 return;
1737         }
1738
1739         work->crtc = crtc;
1740         work->fb = crtc->fb;
1741         work->interval = interval;
1742         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1743
1744         dev_priv->fbc_work = work;
1745
1746         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1747
1748         /* Delay the actual enabling to let pageflipping cease and the
1749          * display to settle before starting the compression. Note that
1750          * this delay also serves a second purpose: it allows for a
1751          * vblank to pass after disabling the FBC before we attempt
1752          * to modify the control registers.
1753          *
1754          * A more complicated solution would involve tracking vblanks
1755          * following the termination of the page-flipping sequence
1756          * and indeed performing the enable as a co-routine and not
1757          * waiting synchronously upon the vblank.
1758          */
1759         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1760 }
1761
1762 void intel_disable_fbc(struct drm_device *dev)
1763 {
1764         struct drm_i915_private *dev_priv = dev->dev_private;
1765
1766         intel_cancel_fbc_work(dev_priv);
1767
1768         if (!dev_priv->display.disable_fbc)
1769                 return;
1770
1771         dev_priv->display.disable_fbc(dev);
1772         dev_priv->cfb_plane = -1;
1773 }
1774
1775 /**
1776  * intel_update_fbc - enable/disable FBC as needed
1777  * @dev: the drm_device
1778  *
1779  * Set up the framebuffer compression hardware at mode set time.  We
1780  * enable it if possible:
1781  *   - plane A only (on pre-965)
1782  *   - no pixel mulitply/line duplication
1783  *   - no alpha buffer discard
1784  *   - no dual wide
1785  *   - framebuffer <= 2048 in width, 1536 in height
1786  *
1787  * We can't assume that any compression will take place (worst case),
1788  * so the compressed buffer has to be the same size as the uncompressed
1789  * one.  It also must reside (along with the line length buffer) in
1790  * stolen memory.
1791  *
1792  * We need to enable/disable FBC on a global basis.
1793  */
1794 static void intel_update_fbc(struct drm_device *dev)
1795 {
1796         struct drm_i915_private *dev_priv = dev->dev_private;
1797         struct drm_crtc *crtc = NULL, *tmp_crtc;
1798         struct intel_crtc *intel_crtc;
1799         struct drm_framebuffer *fb;
1800         struct intel_framebuffer *intel_fb;
1801         struct drm_i915_gem_object *obj;
1802
1803         DRM_DEBUG_KMS("\n");
1804
1805         if (!i915_powersave)
1806                 return;
1807
1808         if (!I915_HAS_FBC(dev))
1809                 return;
1810
1811         /*
1812          * If FBC is already on, we just have to verify that we can
1813          * keep it that way...
1814          * Need to disable if:
1815          *   - more than one pipe is active
1816          *   - changing FBC params (stride, fence, mode)
1817          *   - new fb is too large to fit in compressed buffer
1818          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1819          */
1820         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1821                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1822                         if (crtc) {
1823                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1824                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1825                                 goto out_disable;
1826                         }
1827                         crtc = tmp_crtc;
1828                 }
1829         }
1830
1831         if (!crtc || crtc->fb == NULL) {
1832                 DRM_DEBUG_KMS("no output, disabling\n");
1833                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1834                 goto out_disable;
1835         }
1836
1837         intel_crtc = to_intel_crtc(crtc);
1838         fb = crtc->fb;
1839         intel_fb = to_intel_framebuffer(fb);
1840         obj = intel_fb->obj;
1841
1842         if (!i915_enable_fbc) {
1843                 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1844                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1845                 goto out_disable;
1846         }
1847         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1848                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1849                               "compression\n");
1850                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1851                 goto out_disable;
1852         }
1853         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1854             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1855                 DRM_DEBUG_KMS("mode incompatible with compression, "
1856                               "disabling\n");
1857                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1858                 goto out_disable;
1859         }
1860         if ((crtc->mode.hdisplay > 2048) ||
1861             (crtc->mode.vdisplay > 1536)) {
1862                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1863                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1864                 goto out_disable;
1865         }
1866         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1867                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1868                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1869                 goto out_disable;
1870         }
1871
1872         /* The use of a CPU fence is mandatory in order to detect writes
1873          * by the CPU to the scanout and trigger updates to the FBC.
1874          */
1875         if (obj->tiling_mode != I915_TILING_X ||
1876             obj->fence_reg == I915_FENCE_REG_NONE) {
1877                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1878                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1879                 goto out_disable;
1880         }
1881
1882         /* If the kernel debugger is active, always disable compression */
1883         if (in_dbg_master())
1884                 goto out_disable;
1885
1886         /* If the scanout has not changed, don't modify the FBC settings.
1887          * Note that we make the fundamental assumption that the fb->obj
1888          * cannot be unpinned (and have its GTT offset and fence revoked)
1889          * without first being decoupled from the scanout and FBC disabled.
1890          */
1891         if (dev_priv->cfb_plane == intel_crtc->plane &&
1892             dev_priv->cfb_fb == fb->base.id &&
1893             dev_priv->cfb_y == crtc->y)
1894                 return;
1895
1896         if (intel_fbc_enabled(dev)) {
1897                 /* We update FBC along two paths, after changing fb/crtc
1898                  * configuration (modeswitching) and after page-flipping
1899                  * finishes. For the latter, we know that not only did
1900                  * we disable the FBC at the start of the page-flip
1901                  * sequence, but also more than one vblank has passed.
1902                  *
1903                  * For the former case of modeswitching, it is possible
1904                  * to switch between two FBC valid configurations
1905                  * instantaneously so we do need to disable the FBC
1906                  * before we can modify its control registers. We also
1907                  * have to wait for the next vblank for that to take
1908                  * effect. However, since we delay enabling FBC we can
1909                  * assume that a vblank has passed since disabling and
1910                  * that we can safely alter the registers in the deferred
1911                  * callback.
1912                  *
1913                  * In the scenario that we go from a valid to invalid
1914                  * and then back to valid FBC configuration we have
1915                  * no strict enforcement that a vblank occurred since
1916                  * disabling the FBC. However, along all current pipe
1917                  * disabling paths we do need to wait for a vblank at
1918                  * some point. And we wait before enabling FBC anyway.
1919                  */
1920                 DRM_DEBUG_KMS("disabling active FBC for update\n");
1921                 intel_disable_fbc(dev);
1922         }
1923
1924         intel_enable_fbc(crtc, 500);
1925         return;
1926
1927 out_disable:
1928         /* Multiple disables should be harmless */
1929         if (intel_fbc_enabled(dev)) {
1930                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1931                 intel_disable_fbc(dev);
1932         }
1933 }
1934
1935 int
1936 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1937                            struct drm_i915_gem_object *obj,
1938                            struct intel_ring_buffer *pipelined)
1939 {
1940         struct drm_i915_private *dev_priv = dev->dev_private;
1941         u32 alignment;
1942         int ret;
1943
1944         switch (obj->tiling_mode) {
1945         case I915_TILING_NONE:
1946                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1947                         alignment = 128 * 1024;
1948                 else if (INTEL_INFO(dev)->gen >= 4)
1949                         alignment = 4 * 1024;
1950                 else
1951                         alignment = 64 * 1024;
1952                 break;
1953         case I915_TILING_X:
1954                 /* pin() will align the object as required by fence */
1955                 alignment = 0;
1956                 break;
1957         case I915_TILING_Y:
1958                 /* FIXME: Is this true? */
1959                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1960                 return -EINVAL;
1961         default:
1962                 BUG();
1963         }
1964
1965         dev_priv->mm.interruptible = false;
1966         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1967         if (ret)
1968                 goto err_interruptible;
1969
1970         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1971          * fence, whereas 965+ only requires a fence if using
1972          * framebuffer compression.  For simplicity, we always install
1973          * a fence as the cost is not that onerous.
1974          */
1975         if (obj->tiling_mode != I915_TILING_NONE) {
1976                 ret = i915_gem_object_get_fence(obj, pipelined);
1977                 if (ret)
1978                         goto err_unpin;
1979         }
1980
1981         dev_priv->mm.interruptible = true;
1982         return 0;
1983
1984 err_unpin:
1985         i915_gem_object_unpin(obj);
1986 err_interruptible:
1987         dev_priv->mm.interruptible = true;
1988         return ret;
1989 }
1990
1991 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1992                              int x, int y)
1993 {
1994         struct drm_device *dev = crtc->dev;
1995         struct drm_i915_private *dev_priv = dev->dev_private;
1996         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1997         struct intel_framebuffer *intel_fb;
1998         struct drm_i915_gem_object *obj;
1999         int plane = intel_crtc->plane;
2000         unsigned long Start, Offset;
2001         u32 dspcntr;
2002         u32 reg;
2003
2004         switch (plane) {
2005         case 0:
2006         case 1:
2007                 break;
2008         default:
2009                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2010                 return -EINVAL;
2011         }
2012
2013         intel_fb = to_intel_framebuffer(fb);
2014         obj = intel_fb->obj;
2015
2016         reg = DSPCNTR(plane);
2017         dspcntr = I915_READ(reg);
2018         /* Mask out pixel format bits in case we change it */
2019         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2020         switch (fb->bits_per_pixel) {
2021         case 8:
2022                 dspcntr |= DISPPLANE_8BPP;
2023                 break;
2024         case 16:
2025                 if (fb->depth == 15)
2026                         dspcntr |= DISPPLANE_15_16BPP;
2027                 else
2028                         dspcntr |= DISPPLANE_16BPP;
2029                 break;
2030         case 24:
2031         case 32:
2032                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2033                 break;
2034         default:
2035                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2036                 return -EINVAL;
2037         }
2038         if (INTEL_INFO(dev)->gen >= 4) {
2039                 if (obj->tiling_mode != I915_TILING_NONE)
2040                         dspcntr |= DISPPLANE_TILED;
2041                 else
2042                         dspcntr &= ~DISPPLANE_TILED;
2043         }
2044
2045         I915_WRITE(reg, dspcntr);
2046
2047         Start = obj->gtt_offset;
2048         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2049
2050         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2051                       Start, Offset, x, y, fb->pitch);
2052         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2053         if (INTEL_INFO(dev)->gen >= 4) {
2054                 I915_WRITE(DSPSURF(plane), Start);
2055                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2056                 I915_WRITE(DSPADDR(plane), Offset);
2057         } else
2058                 I915_WRITE(DSPADDR(plane), Start + Offset);
2059         POSTING_READ(reg);
2060
2061         return 0;
2062 }
2063
2064 static int ironlake_update_plane(struct drm_crtc *crtc,
2065                                  struct drm_framebuffer *fb, int x, int y)
2066 {
2067         struct drm_device *dev = crtc->dev;
2068         struct drm_i915_private *dev_priv = dev->dev_private;
2069         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2070         struct intel_framebuffer *intel_fb;
2071         struct drm_i915_gem_object *obj;
2072         int plane = intel_crtc->plane;
2073         unsigned long Start, Offset;
2074         u32 dspcntr;
2075         u32 reg;
2076
2077         switch (plane) {
2078         case 0:
2079         case 1:
2080                 break;
2081         default:
2082                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2083                 return -EINVAL;
2084         }
2085
2086         intel_fb = to_intel_framebuffer(fb);
2087         obj = intel_fb->obj;
2088
2089         reg = DSPCNTR(plane);
2090         dspcntr = I915_READ(reg);
2091         /* Mask out pixel format bits in case we change it */
2092         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2093         switch (fb->bits_per_pixel) {
2094         case 8:
2095                 dspcntr |= DISPPLANE_8BPP;
2096                 break;
2097         case 16:
2098                 if (fb->depth != 16)
2099                         return -EINVAL;
2100
2101                 dspcntr |= DISPPLANE_16BPP;
2102                 break;
2103         case 24:
2104         case 32:
2105                 if (fb->depth == 24)
2106                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2107                 else if (fb->depth == 30)
2108                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2109                 else
2110                         return -EINVAL;
2111                 break;
2112         default:
2113                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2114                 return -EINVAL;
2115         }
2116
2117         if (obj->tiling_mode != I915_TILING_NONE)
2118                 dspcntr |= DISPPLANE_TILED;
2119         else
2120                 dspcntr &= ~DISPPLANE_TILED;
2121
2122         /* must disable */
2123         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2124
2125         I915_WRITE(reg, dspcntr);
2126
2127         Start = obj->gtt_offset;
2128         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2129
2130         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2131                       Start, Offset, x, y, fb->pitch);
2132         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2133         I915_WRITE(DSPSURF(plane), Start);
2134         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2135         I915_WRITE(DSPADDR(plane), Offset);
2136         POSTING_READ(reg);
2137
2138         return 0;
2139 }
2140
2141 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2142 static int
2143 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2144                            int x, int y, enum mode_set_atomic state)
2145 {
2146         struct drm_device *dev = crtc->dev;
2147         struct drm_i915_private *dev_priv = dev->dev_private;
2148         int ret;
2149
2150         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2151         if (ret)
2152                 return ret;
2153
2154         intel_update_fbc(dev);
2155         intel_increase_pllclock(crtc);
2156
2157         return 0;
2158 }
2159
2160 static int
2161 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2162                     struct drm_framebuffer *old_fb)
2163 {
2164         struct drm_device *dev = crtc->dev;
2165         struct drm_i915_master_private *master_priv;
2166         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2167         int ret;
2168
2169         /* no fb bound */
2170         if (!crtc->fb) {
2171                 DRM_ERROR("No FB bound\n");
2172                 return 0;
2173         }
2174
2175         switch (intel_crtc->plane) {
2176         case 0:
2177         case 1:
2178                 break;
2179         default:
2180                 DRM_ERROR("no plane for crtc\n");
2181                 return -EINVAL;
2182         }
2183
2184         mutex_lock(&dev->struct_mutex);
2185         ret = intel_pin_and_fence_fb_obj(dev,
2186                                          to_intel_framebuffer(crtc->fb)->obj,
2187                                          NULL);
2188         if (ret != 0) {
2189                 mutex_unlock(&dev->struct_mutex);
2190                 DRM_ERROR("pin & fence failed\n");
2191                 return ret;
2192         }
2193
2194         if (old_fb) {
2195                 struct drm_i915_private *dev_priv = dev->dev_private;
2196                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2197
2198                 wait_event(dev_priv->pending_flip_queue,
2199                            atomic_read(&dev_priv->mm.wedged) ||
2200                            atomic_read(&obj->pending_flip) == 0);
2201
2202                 /* Big Hammer, we also need to ensure that any pending
2203                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2204                  * current scanout is retired before unpinning the old
2205                  * framebuffer.
2206                  *
2207                  * This should only fail upon a hung GPU, in which case we
2208                  * can safely continue.
2209                  */
2210                 ret = i915_gem_object_finish_gpu(obj);
2211                 (void) ret;
2212         }
2213
2214         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2215                                          LEAVE_ATOMIC_MODE_SET);
2216         if (ret) {
2217                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2218                 mutex_unlock(&dev->struct_mutex);
2219                 DRM_ERROR("failed to update base address\n");
2220                 return ret;
2221         }
2222
2223         if (old_fb) {
2224                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2225                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2226         }
2227
2228         mutex_unlock(&dev->struct_mutex);
2229
2230         if (!dev->primary->master)
2231                 return 0;
2232
2233         master_priv = dev->primary->master->driver_priv;
2234         if (!master_priv->sarea_priv)
2235                 return 0;
2236
2237         if (intel_crtc->pipe) {
2238                 master_priv->sarea_priv->pipeB_x = x;
2239                 master_priv->sarea_priv->pipeB_y = y;
2240         } else {
2241                 master_priv->sarea_priv->pipeA_x = x;
2242                 master_priv->sarea_priv->pipeA_y = y;
2243         }
2244
2245         return 0;
2246 }
2247
2248 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2249 {
2250         struct drm_device *dev = crtc->dev;
2251         struct drm_i915_private *dev_priv = dev->dev_private;
2252         u32 dpa_ctl;
2253
2254         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2255         dpa_ctl = I915_READ(DP_A);
2256         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2257
2258         if (clock < 200000) {
2259                 u32 temp;
2260                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2261                 /* workaround for 160Mhz:
2262                    1) program 0x4600c bits 15:0 = 0x8124
2263                    2) program 0x46010 bit 0 = 1
2264                    3) program 0x46034 bit 24 = 1
2265                    4) program 0x64000 bit 14 = 1
2266                    */
2267                 temp = I915_READ(0x4600c);
2268                 temp &= 0xffff0000;
2269                 I915_WRITE(0x4600c, temp | 0x8124);
2270
2271                 temp = I915_READ(0x46010);
2272                 I915_WRITE(0x46010, temp | 1);
2273
2274                 temp = I915_READ(0x46034);
2275                 I915_WRITE(0x46034, temp | (1 << 24));
2276         } else {
2277                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2278         }
2279         I915_WRITE(DP_A, dpa_ctl);
2280
2281         POSTING_READ(DP_A);
2282         udelay(500);
2283 }
2284
2285 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2286 {
2287         struct drm_device *dev = crtc->dev;
2288         struct drm_i915_private *dev_priv = dev->dev_private;
2289         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2290         int pipe = intel_crtc->pipe;
2291         u32 reg, temp;
2292
2293         /* enable normal train */
2294         reg = FDI_TX_CTL(pipe);
2295         temp = I915_READ(reg);
2296         if (IS_IVYBRIDGE(dev)) {
2297                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2298                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2299         } else {
2300                 temp &= ~FDI_LINK_TRAIN_NONE;
2301                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2302         }
2303         I915_WRITE(reg, temp);
2304
2305         reg = FDI_RX_CTL(pipe);
2306         temp = I915_READ(reg);
2307         if (HAS_PCH_CPT(dev)) {
2308                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2309                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2310         } else {
2311                 temp &= ~FDI_LINK_TRAIN_NONE;
2312                 temp |= FDI_LINK_TRAIN_NONE;
2313         }
2314         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2315
2316         /* wait one idle pattern time */
2317         POSTING_READ(reg);
2318         udelay(1000);
2319
2320         /* IVB wants error correction enabled */
2321         if (IS_IVYBRIDGE(dev))
2322                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2323                            FDI_FE_ERRC_ENABLE);
2324 }
2325
2326 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2327 {
2328         struct drm_i915_private *dev_priv = dev->dev_private;
2329         u32 flags = I915_READ(SOUTH_CHICKEN1);
2330
2331         flags |= FDI_PHASE_SYNC_OVR(pipe);
2332         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2333         flags |= FDI_PHASE_SYNC_EN(pipe);
2334         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2335         POSTING_READ(SOUTH_CHICKEN1);
2336 }
2337
2338 /* The FDI link training functions for ILK/Ibexpeak. */
2339 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2340 {
2341         struct drm_device *dev = crtc->dev;
2342         struct drm_i915_private *dev_priv = dev->dev_private;
2343         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2344         int pipe = intel_crtc->pipe;
2345         int plane = intel_crtc->plane;
2346         u32 reg, temp, tries;
2347
2348         /* FDI needs bits from pipe & plane first */
2349         assert_pipe_enabled(dev_priv, pipe);
2350         assert_plane_enabled(dev_priv, plane);
2351
2352         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2353            for train result */
2354         reg = FDI_RX_IMR(pipe);
2355         temp = I915_READ(reg);
2356         temp &= ~FDI_RX_SYMBOL_LOCK;
2357         temp &= ~FDI_RX_BIT_LOCK;
2358         I915_WRITE(reg, temp);
2359         I915_READ(reg);
2360         udelay(150);
2361
2362         /* enable CPU FDI TX and PCH FDI RX */
2363         reg = FDI_TX_CTL(pipe);
2364         temp = I915_READ(reg);
2365         temp &= ~(7 << 19);
2366         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2367         temp &= ~FDI_LINK_TRAIN_NONE;
2368         temp |= FDI_LINK_TRAIN_PATTERN_1;
2369         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2370
2371         reg = FDI_RX_CTL(pipe);
2372         temp = I915_READ(reg);
2373         temp &= ~FDI_LINK_TRAIN_NONE;
2374         temp |= FDI_LINK_TRAIN_PATTERN_1;
2375         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2376
2377         POSTING_READ(reg);
2378         udelay(150);
2379
2380         /* Ironlake workaround, enable clock pointer after FDI enable*/
2381         if (HAS_PCH_IBX(dev)) {
2382                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2383                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2384                            FDI_RX_PHASE_SYNC_POINTER_EN);
2385         }
2386
2387         reg = FDI_RX_IIR(pipe);
2388         for (tries = 0; tries < 5; tries++) {
2389                 temp = I915_READ(reg);
2390                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2391
2392                 if ((temp & FDI_RX_BIT_LOCK)) {
2393                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2394                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2395                         break;
2396                 }
2397         }
2398         if (tries == 5)
2399                 DRM_ERROR("FDI train 1 fail!\n");
2400
2401         /* Train 2 */
2402         reg = FDI_TX_CTL(pipe);
2403         temp = I915_READ(reg);
2404         temp &= ~FDI_LINK_TRAIN_NONE;
2405         temp |= FDI_LINK_TRAIN_PATTERN_2;
2406         I915_WRITE(reg, temp);
2407
2408         reg = FDI_RX_CTL(pipe);
2409         temp = I915_READ(reg);
2410         temp &= ~FDI_LINK_TRAIN_NONE;
2411         temp |= FDI_LINK_TRAIN_PATTERN_2;
2412         I915_WRITE(reg, temp);
2413
2414         POSTING_READ(reg);
2415         udelay(150);
2416
2417         reg = FDI_RX_IIR(pipe);
2418         for (tries = 0; tries < 5; tries++) {
2419                 temp = I915_READ(reg);
2420                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2421
2422                 if (temp & FDI_RX_SYMBOL_LOCK) {
2423                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2424                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2425                         break;
2426                 }
2427         }
2428         if (tries == 5)
2429                 DRM_ERROR("FDI train 2 fail!\n");
2430
2431         DRM_DEBUG_KMS("FDI train done\n");
2432
2433 }
2434
2435 static const int snb_b_fdi_train_param [] = {
2436         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2437         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2438         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2439         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2440 };
2441
2442 /* The FDI link training functions for SNB/Cougarpoint. */
2443 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2444 {
2445         struct drm_device *dev = crtc->dev;
2446         struct drm_i915_private *dev_priv = dev->dev_private;
2447         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2448         int pipe = intel_crtc->pipe;
2449         u32 reg, temp, i;
2450
2451         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2452            for train result */
2453         reg = FDI_RX_IMR(pipe);
2454         temp = I915_READ(reg);
2455         temp &= ~FDI_RX_SYMBOL_LOCK;
2456         temp &= ~FDI_RX_BIT_LOCK;
2457         I915_WRITE(reg, temp);
2458
2459         POSTING_READ(reg);
2460         udelay(150);
2461
2462         /* enable CPU FDI TX and PCH FDI RX */
2463         reg = FDI_TX_CTL(pipe);
2464         temp = I915_READ(reg);
2465         temp &= ~(7 << 19);
2466         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2467         temp &= ~FDI_LINK_TRAIN_NONE;
2468         temp |= FDI_LINK_TRAIN_PATTERN_1;
2469         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2470         /* SNB-B */
2471         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2472         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2473
2474         reg = FDI_RX_CTL(pipe);
2475         temp = I915_READ(reg);
2476         if (HAS_PCH_CPT(dev)) {
2477                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2478                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2479         } else {
2480                 temp &= ~FDI_LINK_TRAIN_NONE;
2481                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2482         }
2483         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2484
2485         POSTING_READ(reg);
2486         udelay(150);
2487
2488         if (HAS_PCH_CPT(dev))
2489                 cpt_phase_pointer_enable(dev, pipe);
2490
2491         for (i = 0; i < 4; i++ ) {
2492                 reg = FDI_TX_CTL(pipe);
2493                 temp = I915_READ(reg);
2494                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2495                 temp |= snb_b_fdi_train_param[i];
2496                 I915_WRITE(reg, temp);
2497
2498                 POSTING_READ(reg);
2499                 udelay(500);
2500
2501                 reg = FDI_RX_IIR(pipe);
2502                 temp = I915_READ(reg);
2503                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2504
2505                 if (temp & FDI_RX_BIT_LOCK) {
2506                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2507                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2508                         break;
2509                 }
2510         }
2511         if (i == 4)
2512                 DRM_ERROR("FDI train 1 fail!\n");
2513
2514         /* Train 2 */
2515         reg = FDI_TX_CTL(pipe);
2516         temp = I915_READ(reg);
2517         temp &= ~FDI_LINK_TRAIN_NONE;
2518         temp |= FDI_LINK_TRAIN_PATTERN_2;
2519         if (IS_GEN6(dev)) {
2520                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2521                 /* SNB-B */
2522                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2523         }
2524         I915_WRITE(reg, temp);
2525
2526         reg = FDI_RX_CTL(pipe);
2527         temp = I915_READ(reg);
2528         if (HAS_PCH_CPT(dev)) {
2529                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2530                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2531         } else {
2532                 temp &= ~FDI_LINK_TRAIN_NONE;
2533                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2534         }
2535         I915_WRITE(reg, temp);
2536
2537         POSTING_READ(reg);
2538         udelay(150);
2539
2540         for (i = 0; i < 4; i++ ) {
2541                 reg = FDI_TX_CTL(pipe);
2542                 temp = I915_READ(reg);
2543                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2544                 temp |= snb_b_fdi_train_param[i];
2545                 I915_WRITE(reg, temp);
2546
2547                 POSTING_READ(reg);
2548                 udelay(500);
2549
2550                 reg = FDI_RX_IIR(pipe);
2551                 temp = I915_READ(reg);
2552                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2553
2554                 if (temp & FDI_RX_SYMBOL_LOCK) {
2555                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2556                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2557                         break;
2558                 }
2559         }
2560         if (i == 4)
2561                 DRM_ERROR("FDI train 2 fail!\n");
2562
2563         DRM_DEBUG_KMS("FDI train done.\n");
2564 }
2565
2566 /* Manual link training for Ivy Bridge A0 parts */
2567 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2568 {
2569         struct drm_device *dev = crtc->dev;
2570         struct drm_i915_private *dev_priv = dev->dev_private;
2571         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2572         int pipe = intel_crtc->pipe;
2573         u32 reg, temp, i;
2574
2575         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2576            for train result */
2577         reg = FDI_RX_IMR(pipe);
2578         temp = I915_READ(reg);
2579         temp &= ~FDI_RX_SYMBOL_LOCK;
2580         temp &= ~FDI_RX_BIT_LOCK;
2581         I915_WRITE(reg, temp);
2582
2583         POSTING_READ(reg);
2584         udelay(150);
2585
2586         /* enable CPU FDI TX and PCH FDI RX */
2587         reg = FDI_TX_CTL(pipe);
2588         temp = I915_READ(reg);
2589         temp &= ~(7 << 19);
2590         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2591         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2592         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2593         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2594         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2595         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2596
2597         reg = FDI_RX_CTL(pipe);
2598         temp = I915_READ(reg);
2599         temp &= ~FDI_LINK_TRAIN_AUTO;
2600         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2601         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2602         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2603
2604         POSTING_READ(reg);
2605         udelay(150);
2606
2607         if (HAS_PCH_CPT(dev))
2608                 cpt_phase_pointer_enable(dev, pipe);
2609
2610         for (i = 0; i < 4; i++ ) {
2611                 reg = FDI_TX_CTL(pipe);
2612                 temp = I915_READ(reg);
2613                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2614                 temp |= snb_b_fdi_train_param[i];
2615                 I915_WRITE(reg, temp);
2616
2617                 POSTING_READ(reg);
2618                 udelay(500);
2619
2620                 reg = FDI_RX_IIR(pipe);
2621                 temp = I915_READ(reg);
2622                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2623
2624                 if (temp & FDI_RX_BIT_LOCK ||
2625                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2626                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2627                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2628                         break;
2629                 }
2630         }
2631         if (i == 4)
2632                 DRM_ERROR("FDI train 1 fail!\n");
2633
2634         /* Train 2 */
2635         reg = FDI_TX_CTL(pipe);
2636         temp = I915_READ(reg);
2637         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2638         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2639         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2640         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2641         I915_WRITE(reg, temp);
2642
2643         reg = FDI_RX_CTL(pipe);
2644         temp = I915_READ(reg);
2645         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2646         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2647         I915_WRITE(reg, temp);
2648
2649         POSTING_READ(reg);
2650         udelay(150);
2651
2652         for (i = 0; i < 4; i++ ) {
2653                 reg = FDI_TX_CTL(pipe);
2654                 temp = I915_READ(reg);
2655                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2656                 temp |= snb_b_fdi_train_param[i];
2657                 I915_WRITE(reg, temp);
2658
2659                 POSTING_READ(reg);
2660                 udelay(500);
2661
2662                 reg = FDI_RX_IIR(pipe);
2663                 temp = I915_READ(reg);
2664                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2665
2666                 if (temp & FDI_RX_SYMBOL_LOCK) {
2667                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2668                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2669                         break;
2670                 }
2671         }
2672         if (i == 4)
2673                 DRM_ERROR("FDI train 2 fail!\n");
2674
2675         DRM_DEBUG_KMS("FDI train done.\n");
2676 }
2677
2678 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2679 {
2680         struct drm_device *dev = crtc->dev;
2681         struct drm_i915_private *dev_priv = dev->dev_private;
2682         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2683         int pipe = intel_crtc->pipe;
2684         u32 reg, temp;
2685
2686         /* Write the TU size bits so error detection works */
2687         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2688                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2689
2690         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2691         reg = FDI_RX_CTL(pipe);
2692         temp = I915_READ(reg);
2693         temp &= ~((0x7 << 19) | (0x7 << 16));
2694         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2695         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2696         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2697
2698         POSTING_READ(reg);
2699         udelay(200);
2700
2701         /* Switch from Rawclk to PCDclk */
2702         temp = I915_READ(reg);
2703         I915_WRITE(reg, temp | FDI_PCDCLK);
2704
2705         POSTING_READ(reg);
2706         udelay(200);
2707
2708         /* Enable CPU FDI TX PLL, always on for Ironlake */
2709         reg = FDI_TX_CTL(pipe);
2710         temp = I915_READ(reg);
2711         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2712                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2713
2714                 POSTING_READ(reg);
2715                 udelay(100);
2716         }
2717 }
2718
2719 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2720 {
2721         struct drm_i915_private *dev_priv = dev->dev_private;
2722         u32 flags = I915_READ(SOUTH_CHICKEN1);
2723
2724         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2725         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2726         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2727         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2728         POSTING_READ(SOUTH_CHICKEN1);
2729 }
2730 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2731 {
2732         struct drm_device *dev = crtc->dev;
2733         struct drm_i915_private *dev_priv = dev->dev_private;
2734         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2735         int pipe = intel_crtc->pipe;
2736         u32 reg, temp;
2737
2738         /* disable CPU FDI tx and PCH FDI rx */
2739         reg = FDI_TX_CTL(pipe);
2740         temp = I915_READ(reg);
2741         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2742         POSTING_READ(reg);
2743
2744         reg = FDI_RX_CTL(pipe);
2745         temp = I915_READ(reg);
2746         temp &= ~(0x7 << 16);
2747         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2748         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2749
2750         POSTING_READ(reg);
2751         udelay(100);
2752
2753         /* Ironlake workaround, disable clock pointer after downing FDI */
2754         if (HAS_PCH_IBX(dev)) {
2755                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2756                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2757                            I915_READ(FDI_RX_CHICKEN(pipe) &
2758                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2759         } else if (HAS_PCH_CPT(dev)) {
2760                 cpt_phase_pointer_disable(dev, pipe);
2761         }
2762
2763         /* still set train pattern 1 */
2764         reg = FDI_TX_CTL(pipe);
2765         temp = I915_READ(reg);
2766         temp &= ~FDI_LINK_TRAIN_NONE;
2767         temp |= FDI_LINK_TRAIN_PATTERN_1;
2768         I915_WRITE(reg, temp);
2769
2770         reg = FDI_RX_CTL(pipe);
2771         temp = I915_READ(reg);
2772         if (HAS_PCH_CPT(dev)) {
2773                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2774                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2775         } else {
2776                 temp &= ~FDI_LINK_TRAIN_NONE;
2777                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2778         }
2779         /* BPC in FDI rx is consistent with that in PIPECONF */
2780         temp &= ~(0x07 << 16);
2781         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2782         I915_WRITE(reg, temp);
2783
2784         POSTING_READ(reg);
2785         udelay(100);
2786 }
2787
2788 /*
2789  * When we disable a pipe, we need to clear any pending scanline wait events
2790  * to avoid hanging the ring, which we assume we are waiting on.
2791  */
2792 static void intel_clear_scanline_wait(struct drm_device *dev)
2793 {
2794         struct drm_i915_private *dev_priv = dev->dev_private;
2795         struct intel_ring_buffer *ring;
2796         u32 tmp;
2797
2798         if (IS_GEN2(dev))
2799                 /* Can't break the hang on i8xx */
2800                 return;
2801
2802         ring = LP_RING(dev_priv);
2803         tmp = I915_READ_CTL(ring);
2804         if (tmp & RING_WAIT)
2805                 I915_WRITE_CTL(ring, tmp);
2806 }
2807
2808 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2809 {
2810         struct drm_i915_gem_object *obj;
2811         struct drm_i915_private *dev_priv;
2812
2813         if (crtc->fb == NULL)
2814                 return;
2815
2816         obj = to_intel_framebuffer(crtc->fb)->obj;
2817         dev_priv = crtc->dev->dev_private;
2818         wait_event(dev_priv->pending_flip_queue,
2819                    atomic_read(&obj->pending_flip) == 0);
2820 }
2821
2822 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2823 {
2824         struct drm_device *dev = crtc->dev;
2825         struct drm_mode_config *mode_config = &dev->mode_config;
2826         struct intel_encoder *encoder;
2827
2828         /*
2829          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2830          * must be driven by its own crtc; no sharing is possible.
2831          */
2832         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2833                 if (encoder->base.crtc != crtc)
2834                         continue;
2835
2836                 switch (encoder->type) {
2837                 case INTEL_OUTPUT_EDP:
2838                         if (!intel_encoder_is_pch_edp(&encoder->base))
2839                                 return false;
2840                         continue;
2841                 }
2842         }
2843
2844         return true;
2845 }
2846
2847 /*
2848  * Enable PCH resources required for PCH ports:
2849  *   - PCH PLLs
2850  *   - FDI training & RX/TX
2851  *   - update transcoder timings
2852  *   - DP transcoding bits
2853  *   - transcoder
2854  */
2855 static void ironlake_pch_enable(struct drm_crtc *crtc)
2856 {
2857         struct drm_device *dev = crtc->dev;
2858         struct drm_i915_private *dev_priv = dev->dev_private;
2859         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2860         int pipe = intel_crtc->pipe;
2861         u32 reg, temp;
2862
2863         /* For PCH output, training FDI link */
2864         dev_priv->display.fdi_link_train(crtc);
2865
2866         intel_enable_pch_pll(dev_priv, pipe);
2867
2868         if (HAS_PCH_CPT(dev)) {
2869                 /* Be sure PCH DPLL SEL is set */
2870                 temp = I915_READ(PCH_DPLL_SEL);
2871                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2872                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2873                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2874                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2875                 I915_WRITE(PCH_DPLL_SEL, temp);
2876         }
2877
2878         /* set transcoder timing, panel must allow it */
2879         assert_panel_unlocked(dev_priv, pipe);
2880         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2881         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2882         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2883
2884         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2885         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2886         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2887
2888         intel_fdi_normal_train(crtc);
2889
2890         /* For PCH DP, enable TRANS_DP_CTL */
2891         if (HAS_PCH_CPT(dev) &&
2892             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2893                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2894                 reg = TRANS_DP_CTL(pipe);
2895                 temp = I915_READ(reg);
2896                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2897                           TRANS_DP_SYNC_MASK |
2898                           TRANS_DP_BPC_MASK);
2899                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2900                          TRANS_DP_ENH_FRAMING);
2901                 temp |= bpc << 9; /* same format but at 11:9 */
2902
2903                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2904                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2905                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2906                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2907
2908                 switch (intel_trans_dp_port_sel(crtc)) {
2909                 case PCH_DP_B:
2910                         temp |= TRANS_DP_PORT_SEL_B;
2911                         break;
2912                 case PCH_DP_C:
2913                         temp |= TRANS_DP_PORT_SEL_C;
2914                         break;
2915                 case PCH_DP_D:
2916                         temp |= TRANS_DP_PORT_SEL_D;
2917                         break;
2918                 default:
2919                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2920                         temp |= TRANS_DP_PORT_SEL_B;
2921                         break;
2922                 }
2923
2924                 I915_WRITE(reg, temp);
2925         }
2926
2927         intel_enable_transcoder(dev_priv, pipe);
2928 }
2929
2930 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2931 {
2932         struct drm_device *dev = crtc->dev;
2933         struct drm_i915_private *dev_priv = dev->dev_private;
2934         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2935         int pipe = intel_crtc->pipe;
2936         int plane = intel_crtc->plane;
2937         u32 temp;
2938         bool is_pch_port;
2939
2940         if (intel_crtc->active)
2941                 return;
2942
2943         intel_crtc->active = true;
2944         intel_update_watermarks(dev);
2945
2946         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2947                 temp = I915_READ(PCH_LVDS);
2948                 if ((temp & LVDS_PORT_EN) == 0)
2949                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2950         }
2951
2952         is_pch_port = intel_crtc_driving_pch(crtc);
2953
2954         if (is_pch_port)
2955                 ironlake_fdi_pll_enable(crtc);
2956         else
2957                 ironlake_fdi_disable(crtc);
2958
2959         /* Enable panel fitting for LVDS */
2960         if (dev_priv->pch_pf_size &&
2961             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2962                 /* Force use of hard-coded filter coefficients
2963                  * as some pre-programmed values are broken,
2964                  * e.g. x201.
2965                  */
2966                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2967                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2968                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2969         }
2970
2971         /*
2972          * On ILK+ LUT must be loaded before the pipe is running but with
2973          * clocks enabled
2974          */
2975         intel_crtc_load_lut(crtc);
2976
2977         intel_enable_pipe(dev_priv, pipe, is_pch_port);
2978         intel_enable_plane(dev_priv, plane, pipe);
2979
2980         if (is_pch_port)
2981                 ironlake_pch_enable(crtc);
2982
2983         mutex_lock(&dev->struct_mutex);
2984         intel_update_fbc(dev);
2985         mutex_unlock(&dev->struct_mutex);
2986
2987         intel_crtc_update_cursor(crtc, true);
2988 }
2989
2990 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2991 {
2992         struct drm_device *dev = crtc->dev;
2993         struct drm_i915_private *dev_priv = dev->dev_private;
2994         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2995         int pipe = intel_crtc->pipe;
2996         int plane = intel_crtc->plane;
2997         u32 reg, temp;
2998
2999         if (!intel_crtc->active)
3000                 return;
3001
3002         intel_crtc_wait_for_pending_flips(crtc);
3003         drm_vblank_off(dev, pipe);
3004         intel_crtc_update_cursor(crtc, false);
3005
3006         intel_disable_plane(dev_priv, plane, pipe);
3007
3008         if (dev_priv->cfb_plane == plane)
3009                 intel_disable_fbc(dev);
3010
3011         intel_disable_pipe(dev_priv, pipe);
3012
3013         /* Disable PF */
3014         I915_WRITE(PF_CTL(pipe), 0);
3015         I915_WRITE(PF_WIN_SZ(pipe), 0);
3016
3017         ironlake_fdi_disable(crtc);
3018
3019         /* This is a horrible layering violation; we should be doing this in
3020          * the connector/encoder ->prepare instead, but we don't always have
3021          * enough information there about the config to know whether it will
3022          * actually be necessary or just cause undesired flicker.
3023          */
3024         intel_disable_pch_ports(dev_priv, pipe);
3025
3026         intel_disable_transcoder(dev_priv, pipe);
3027
3028         if (HAS_PCH_CPT(dev)) {
3029                 /* disable TRANS_DP_CTL */
3030                 reg = TRANS_DP_CTL(pipe);
3031                 temp = I915_READ(reg);
3032                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3033                 temp |= TRANS_DP_PORT_SEL_NONE;
3034                 I915_WRITE(reg, temp);
3035
3036                 /* disable DPLL_SEL */
3037                 temp = I915_READ(PCH_DPLL_SEL);
3038                 switch (pipe) {
3039                 case 0:
3040                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3041                         break;
3042                 case 1:
3043                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3044                         break;
3045                 case 2:
3046                         /* FIXME: manage transcoder PLLs? */
3047                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3048                         break;
3049                 default:
3050                         BUG(); /* wtf */
3051                 }
3052                 I915_WRITE(PCH_DPLL_SEL, temp);
3053         }
3054
3055         /* disable PCH DPLL */
3056         intel_disable_pch_pll(dev_priv, pipe);
3057
3058         /* Switch from PCDclk to Rawclk */
3059         reg = FDI_RX_CTL(pipe);
3060         temp = I915_READ(reg);
3061         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3062
3063         /* Disable CPU FDI TX PLL */
3064         reg = FDI_TX_CTL(pipe);
3065         temp = I915_READ(reg);
3066         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3067
3068         POSTING_READ(reg);
3069         udelay(100);
3070
3071         reg = FDI_RX_CTL(pipe);
3072         temp = I915_READ(reg);
3073         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3074
3075         /* Wait for the clocks to turn off. */
3076         POSTING_READ(reg);
3077         udelay(100);
3078
3079         intel_crtc->active = false;
3080         intel_update_watermarks(dev);
3081
3082         mutex_lock(&dev->struct_mutex);
3083         intel_update_fbc(dev);
3084         intel_clear_scanline_wait(dev);
3085         mutex_unlock(&dev->struct_mutex);
3086 }
3087
3088 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3089 {
3090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3091         int pipe = intel_crtc->pipe;
3092         int plane = intel_crtc->plane;
3093
3094         /* XXX: When our outputs are all unaware of DPMS modes other than off
3095          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3096          */
3097         switch (mode) {
3098         case DRM_MODE_DPMS_ON:
3099         case DRM_MODE_DPMS_STANDBY:
3100         case DRM_MODE_DPMS_SUSPEND:
3101                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3102                 ironlake_crtc_enable(crtc);
3103                 break;
3104
3105         case DRM_MODE_DPMS_OFF:
3106                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3107                 ironlake_crtc_disable(crtc);
3108                 break;
3109         }
3110 }
3111
3112 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3113 {
3114         if (!enable && intel_crtc->overlay) {
3115                 struct drm_device *dev = intel_crtc->base.dev;
3116                 struct drm_i915_private *dev_priv = dev->dev_private;
3117
3118                 mutex_lock(&dev->struct_mutex);
3119                 dev_priv->mm.interruptible = false;
3120                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3121                 dev_priv->mm.interruptible = true;
3122                 mutex_unlock(&dev->struct_mutex);
3123         }
3124
3125         /* Let userspace switch the overlay on again. In most cases userspace
3126          * has to recompute where to put it anyway.
3127          */
3128 }
3129
3130 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3131 {
3132         struct drm_device *dev = crtc->dev;
3133         struct drm_i915_private *dev_priv = dev->dev_private;
3134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3135         int pipe = intel_crtc->pipe;
3136         int plane = intel_crtc->plane;
3137
3138         if (intel_crtc->active)
3139                 return;
3140
3141         intel_crtc->active = true;
3142         intel_update_watermarks(dev);
3143
3144         intel_enable_pll(dev_priv, pipe);
3145         intel_enable_pipe(dev_priv, pipe, false);
3146         intel_enable_plane(dev_priv, plane, pipe);
3147
3148         intel_crtc_load_lut(crtc);
3149         intel_update_fbc(dev);
3150
3151         /* Give the overlay scaler a chance to enable if it's on this pipe */
3152         intel_crtc_dpms_overlay(intel_crtc, true);
3153         intel_crtc_update_cursor(crtc, true);
3154 }
3155
3156 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3157 {
3158         struct drm_device *dev = crtc->dev;
3159         struct drm_i915_private *dev_priv = dev->dev_private;
3160         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3161         int pipe = intel_crtc->pipe;
3162         int plane = intel_crtc->plane;
3163
3164         if (!intel_crtc->active)
3165                 return;
3166
3167         /* Give the overlay scaler a chance to disable if it's on this pipe */
3168         intel_crtc_wait_for_pending_flips(crtc);
3169         drm_vblank_off(dev, pipe);
3170         intel_crtc_dpms_overlay(intel_crtc, false);
3171         intel_crtc_update_cursor(crtc, false);
3172
3173         if (dev_priv->cfb_plane == plane)
3174                 intel_disable_fbc(dev);
3175
3176         intel_disable_plane(dev_priv, plane, pipe);
3177         intel_disable_pipe(dev_priv, pipe);
3178         intel_disable_pll(dev_priv, pipe);
3179
3180         intel_crtc->active = false;
3181         intel_update_fbc(dev);
3182         intel_update_watermarks(dev);
3183         intel_clear_scanline_wait(dev);
3184 }
3185
3186 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3187 {
3188         /* XXX: When our outputs are all unaware of DPMS modes other than off
3189          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3190          */
3191         switch (mode) {
3192         case DRM_MODE_DPMS_ON:
3193         case DRM_MODE_DPMS_STANDBY:
3194         case DRM_MODE_DPMS_SUSPEND:
3195                 i9xx_crtc_enable(crtc);
3196                 break;
3197         case DRM_MODE_DPMS_OFF:
3198                 i9xx_crtc_disable(crtc);
3199                 break;
3200         }
3201 }
3202
3203 /**
3204  * Sets the power management mode of the pipe and plane.
3205  */
3206 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3207 {
3208         struct drm_device *dev = crtc->dev;
3209         struct drm_i915_private *dev_priv = dev->dev_private;
3210         struct drm_i915_master_private *master_priv;
3211         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3212         int pipe = intel_crtc->pipe;
3213         bool enabled;
3214
3215         if (intel_crtc->dpms_mode == mode)
3216                 return;
3217
3218         intel_crtc->dpms_mode = mode;
3219
3220         dev_priv->display.dpms(crtc, mode);
3221
3222         if (!dev->primary->master)
3223                 return;
3224
3225         master_priv = dev->primary->master->driver_priv;
3226         if (!master_priv->sarea_priv)
3227                 return;
3228
3229         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3230
3231         switch (pipe) {
3232         case 0:
3233                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3234                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3235                 break;
3236         case 1:
3237                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3238                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3239                 break;
3240         default:
3241                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3242                 break;
3243         }
3244 }
3245
3246 static void intel_crtc_disable(struct drm_crtc *crtc)
3247 {
3248         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3249         struct drm_device *dev = crtc->dev;
3250
3251         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3252
3253         if (crtc->fb) {
3254                 mutex_lock(&dev->struct_mutex);
3255                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3256                 mutex_unlock(&dev->struct_mutex);
3257         }
3258 }
3259
3260 /* Prepare for a mode set.
3261  *
3262  * Note we could be a lot smarter here.  We need to figure out which outputs
3263  * will be enabled, which disabled (in short, how the config will changes)
3264  * and perform the minimum necessary steps to accomplish that, e.g. updating
3265  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3266  * panel fitting is in the proper state, etc.
3267  */
3268 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3269 {
3270         i9xx_crtc_disable(crtc);
3271 }
3272
3273 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3274 {
3275         i9xx_crtc_enable(crtc);
3276 }
3277
3278 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3279 {
3280         ironlake_crtc_disable(crtc);
3281 }
3282
3283 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3284 {
3285         ironlake_crtc_enable(crtc);
3286 }
3287
3288 void intel_encoder_prepare (struct drm_encoder *encoder)
3289 {
3290         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3291         /* lvds has its own version of prepare see intel_lvds_prepare */
3292         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3293 }
3294
3295 void intel_encoder_commit (struct drm_encoder *encoder)
3296 {
3297         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3298         /* lvds has its own version of commit see intel_lvds_commit */
3299         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3300 }
3301
3302 void intel_encoder_destroy(struct drm_encoder *encoder)
3303 {
3304         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3305
3306         drm_encoder_cleanup(encoder);
3307         kfree(intel_encoder);
3308 }
3309
3310 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3311                                   struct drm_display_mode *mode,
3312                                   struct drm_display_mode *adjusted_mode)
3313 {
3314         struct drm_device *dev = crtc->dev;
3315
3316         if (HAS_PCH_SPLIT(dev)) {
3317                 /* FDI link clock is fixed at 2.7G */
3318                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3319                         return false;
3320         }
3321
3322         /* XXX some encoders set the crtcinfo, others don't.
3323          * Obviously we need some form of conflict resolution here...
3324          */
3325         if (adjusted_mode->crtc_htotal == 0)
3326                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3327
3328         return true;
3329 }
3330
3331 static int i945_get_display_clock_speed(struct drm_device *dev)
3332 {
3333         return 400000;
3334 }
3335
3336 static int i915_get_display_clock_speed(struct drm_device *dev)
3337 {
3338         return 333000;
3339 }
3340
3341 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3342 {
3343         return 200000;
3344 }
3345
3346 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3347 {
3348         u16 gcfgc = 0;
3349
3350         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3351
3352         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3353                 return 133000;
3354         else {
3355                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3356                 case GC_DISPLAY_CLOCK_333_MHZ:
3357                         return 333000;
3358                 default:
3359                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3360                         return 190000;
3361                 }
3362         }
3363 }
3364
3365 static int i865_get_display_clock_speed(struct drm_device *dev)
3366 {
3367         return 266000;
3368 }
3369
3370 static int i855_get_display_clock_speed(struct drm_device *dev)
3371 {
3372         u16 hpllcc = 0;
3373         /* Assume that the hardware is in the high speed state.  This
3374          * should be the default.
3375          */
3376         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3377         case GC_CLOCK_133_200:
3378         case GC_CLOCK_100_200:
3379                 return 200000;
3380         case GC_CLOCK_166_250:
3381                 return 250000;
3382         case GC_CLOCK_100_133:
3383                 return 133000;
3384         }
3385
3386         /* Shouldn't happen */
3387         return 0;
3388 }
3389
3390 static int i830_get_display_clock_speed(struct drm_device *dev)
3391 {
3392         return 133000;
3393 }
3394
3395 struct fdi_m_n {
3396         u32        tu;
3397         u32        gmch_m;
3398         u32        gmch_n;
3399         u32        link_m;
3400         u32        link_n;
3401 };
3402
3403 static void
3404 fdi_reduce_ratio(u32 *num, u32 *den)
3405 {
3406         while (*num > 0xffffff || *den > 0xffffff) {
3407                 *num >>= 1;
3408                 *den >>= 1;
3409         }
3410 }
3411
3412 static void
3413 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3414                      int link_clock, struct fdi_m_n *m_n)
3415 {
3416         m_n->tu = 64; /* default size */
3417
3418         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3419         m_n->gmch_m = bits_per_pixel * pixel_clock;
3420         m_n->gmch_n = link_clock * nlanes * 8;
3421         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3422
3423         m_n->link_m = pixel_clock;
3424         m_n->link_n = link_clock;
3425         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3426 }
3427
3428
3429 struct intel_watermark_params {
3430         unsigned long fifo_size;
3431         unsigned long max_wm;
3432         unsigned long default_wm;
3433         unsigned long guard_size;
3434         unsigned long cacheline_size;
3435 };
3436
3437 /* Pineview has different values for various configs */
3438 static const struct intel_watermark_params pineview_display_wm = {
3439         PINEVIEW_DISPLAY_FIFO,
3440         PINEVIEW_MAX_WM,
3441         PINEVIEW_DFT_WM,
3442         PINEVIEW_GUARD_WM,
3443         PINEVIEW_FIFO_LINE_SIZE
3444 };
3445 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3446         PINEVIEW_DISPLAY_FIFO,
3447         PINEVIEW_MAX_WM,
3448         PINEVIEW_DFT_HPLLOFF_WM,
3449         PINEVIEW_GUARD_WM,
3450         PINEVIEW_FIFO_LINE_SIZE
3451 };
3452 static const struct intel_watermark_params pineview_cursor_wm = {
3453         PINEVIEW_CURSOR_FIFO,
3454         PINEVIEW_CURSOR_MAX_WM,
3455         PINEVIEW_CURSOR_DFT_WM,
3456         PINEVIEW_CURSOR_GUARD_WM,
3457         PINEVIEW_FIFO_LINE_SIZE,
3458 };
3459 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3460         PINEVIEW_CURSOR_FIFO,
3461         PINEVIEW_CURSOR_MAX_WM,
3462         PINEVIEW_CURSOR_DFT_WM,
3463         PINEVIEW_CURSOR_GUARD_WM,
3464         PINEVIEW_FIFO_LINE_SIZE
3465 };
3466 static const struct intel_watermark_params g4x_wm_info = {
3467         G4X_FIFO_SIZE,
3468         G4X_MAX_WM,
3469         G4X_MAX_WM,
3470         2,
3471         G4X_FIFO_LINE_SIZE,
3472 };
3473 static const struct intel_watermark_params g4x_cursor_wm_info = {
3474         I965_CURSOR_FIFO,
3475         I965_CURSOR_MAX_WM,
3476         I965_CURSOR_DFT_WM,
3477         2,
3478         G4X_FIFO_LINE_SIZE,
3479 };
3480 static const struct intel_watermark_params i965_cursor_wm_info = {
3481         I965_CURSOR_FIFO,
3482         I965_CURSOR_MAX_WM,
3483         I965_CURSOR_DFT_WM,
3484         2,
3485         I915_FIFO_LINE_SIZE,
3486 };
3487 static const struct intel_watermark_params i945_wm_info = {
3488         I945_FIFO_SIZE,
3489         I915_MAX_WM,
3490         1,
3491         2,
3492         I915_FIFO_LINE_SIZE
3493 };
3494 static const struct intel_watermark_params i915_wm_info = {
3495         I915_FIFO_SIZE,
3496         I915_MAX_WM,
3497         1,
3498         2,
3499         I915_FIFO_LINE_SIZE
3500 };
3501 static const struct intel_watermark_params i855_wm_info = {
3502         I855GM_FIFO_SIZE,
3503         I915_MAX_WM,
3504         1,
3505         2,
3506         I830_FIFO_LINE_SIZE
3507 };
3508 static const struct intel_watermark_params i830_wm_info = {
3509         I830_FIFO_SIZE,
3510         I915_MAX_WM,
3511         1,
3512         2,
3513         I830_FIFO_LINE_SIZE
3514 };
3515
3516 static const struct intel_watermark_params ironlake_display_wm_info = {
3517         ILK_DISPLAY_FIFO,
3518         ILK_DISPLAY_MAXWM,
3519         ILK_DISPLAY_DFTWM,
3520         2,
3521         ILK_FIFO_LINE_SIZE
3522 };
3523 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3524         ILK_CURSOR_FIFO,
3525         ILK_CURSOR_MAXWM,
3526         ILK_CURSOR_DFTWM,
3527         2,
3528         ILK_FIFO_LINE_SIZE
3529 };
3530 static const struct intel_watermark_params ironlake_display_srwm_info = {
3531         ILK_DISPLAY_SR_FIFO,
3532         ILK_DISPLAY_MAX_SRWM,
3533         ILK_DISPLAY_DFT_SRWM,
3534         2,
3535         ILK_FIFO_LINE_SIZE
3536 };
3537 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3538         ILK_CURSOR_SR_FIFO,
3539         ILK_CURSOR_MAX_SRWM,
3540         ILK_CURSOR_DFT_SRWM,
3541         2,
3542         ILK_FIFO_LINE_SIZE
3543 };
3544
3545 static const struct intel_watermark_params sandybridge_display_wm_info = {
3546         SNB_DISPLAY_FIFO,
3547         SNB_DISPLAY_MAXWM,
3548         SNB_DISPLAY_DFTWM,
3549         2,
3550         SNB_FIFO_LINE_SIZE
3551 };
3552 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3553         SNB_CURSOR_FIFO,
3554         SNB_CURSOR_MAXWM,
3555         SNB_CURSOR_DFTWM,
3556         2,
3557         SNB_FIFO_LINE_SIZE
3558 };
3559 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3560         SNB_DISPLAY_SR_FIFO,
3561         SNB_DISPLAY_MAX_SRWM,
3562         SNB_DISPLAY_DFT_SRWM,
3563         2,
3564         SNB_FIFO_LINE_SIZE
3565 };
3566 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3567         SNB_CURSOR_SR_FIFO,
3568         SNB_CURSOR_MAX_SRWM,
3569         SNB_CURSOR_DFT_SRWM,
3570         2,
3571         SNB_FIFO_LINE_SIZE
3572 };
3573
3574
3575 /**
3576  * intel_calculate_wm - calculate watermark level
3577  * @clock_in_khz: pixel clock
3578  * @wm: chip FIFO params
3579  * @pixel_size: display pixel size
3580  * @latency_ns: memory latency for the platform
3581  *
3582  * Calculate the watermark level (the level at which the display plane will
3583  * start fetching from memory again).  Each chip has a different display
3584  * FIFO size and allocation, so the caller needs to figure that out and pass
3585  * in the correct intel_watermark_params structure.
3586  *
3587  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3588  * on the pixel size.  When it reaches the watermark level, it'll start
3589  * fetching FIFO line sized based chunks from memory until the FIFO fills
3590  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3591  * will occur, and a display engine hang could result.
3592  */
3593 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3594                                         const struct intel_watermark_params *wm,
3595                                         int fifo_size,
3596                                         int pixel_size,
3597                                         unsigned long latency_ns)
3598 {
3599         long entries_required, wm_size;
3600
3601         /*
3602          * Note: we need to make sure we don't overflow for various clock &
3603          * latency values.
3604          * clocks go from a few thousand to several hundred thousand.
3605          * latency is usually a few thousand
3606          */
3607         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3608                 1000;
3609         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3610
3611         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3612
3613         wm_size = fifo_size - (entries_required + wm->guard_size);
3614
3615         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3616
3617         /* Don't promote wm_size to unsigned... */
3618         if (wm_size > (long)wm->max_wm)
3619                 wm_size = wm->max_wm;
3620         if (wm_size <= 0)
3621                 wm_size = wm->default_wm;
3622         return wm_size;
3623 }
3624
3625 struct cxsr_latency {
3626         int is_desktop;
3627         int is_ddr3;
3628         unsigned long fsb_freq;
3629         unsigned long mem_freq;
3630         unsigned long display_sr;
3631         unsigned long display_hpll_disable;
3632         unsigned long cursor_sr;
3633         unsigned long cursor_hpll_disable;
3634 };
3635
3636 static const struct cxsr_latency cxsr_latency_table[] = {
3637         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3638         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3639         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3640         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3641         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3642
3643         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3644         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3645         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3646         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3647         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3648
3649         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3650         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3651         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3652         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3653         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3654
3655         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3656         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3657         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3658         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3659         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3660
3661         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3662         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3663         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3664         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3665         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3666
3667         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3668         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3669         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3670         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3671         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3672 };
3673
3674 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3675                                                          int is_ddr3,
3676                                                          int fsb,
3677                                                          int mem)
3678 {
3679         const struct cxsr_latency *latency;
3680         int i;
3681
3682         if (fsb == 0 || mem == 0)
3683                 return NULL;
3684
3685         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3686                 latency = &cxsr_latency_table[i];
3687                 if (is_desktop == latency->is_desktop &&
3688                     is_ddr3 == latency->is_ddr3 &&
3689                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3690                         return latency;
3691         }
3692
3693         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3694
3695         return NULL;
3696 }
3697
3698 static void pineview_disable_cxsr(struct drm_device *dev)
3699 {
3700         struct drm_i915_private *dev_priv = dev->dev_private;
3701
3702         /* deactivate cxsr */
3703         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3704 }
3705
3706 /*
3707  * Latency for FIFO fetches is dependent on several factors:
3708  *   - memory configuration (speed, channels)
3709  *   - chipset
3710  *   - current MCH state
3711  * It can be fairly high in some situations, so here we assume a fairly
3712  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3713  * set this value too high, the FIFO will fetch frequently to stay full)
3714  * and power consumption (set it too low to save power and we might see
3715  * FIFO underruns and display "flicker").
3716  *
3717  * A value of 5us seems to be a good balance; safe for very low end
3718  * platforms but not overly aggressive on lower latency configs.
3719  */
3720 static const int latency_ns = 5000;
3721
3722 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3723 {
3724         struct drm_i915_private *dev_priv = dev->dev_private;
3725         uint32_t dsparb = I915_READ(DSPARB);
3726         int size;
3727
3728         size = dsparb & 0x7f;
3729         if (plane)
3730                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3731
3732         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3733                       plane ? "B" : "A", size);
3734
3735         return size;
3736 }
3737
3738 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3739 {
3740         struct drm_i915_private *dev_priv = dev->dev_private;
3741         uint32_t dsparb = I915_READ(DSPARB);
3742         int size;
3743
3744         size = dsparb & 0x1ff;
3745         if (plane)
3746                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3747         size >>= 1; /* Convert to cachelines */
3748
3749         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3750                       plane ? "B" : "A", size);
3751
3752         return size;
3753 }
3754
3755 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3756 {
3757         struct drm_i915_private *dev_priv = dev->dev_private;
3758         uint32_t dsparb = I915_READ(DSPARB);
3759         int size;
3760
3761         size = dsparb & 0x7f;
3762         size >>= 2; /* Convert to cachelines */
3763
3764         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3765                       plane ? "B" : "A",
3766                       size);
3767
3768         return size;
3769 }
3770
3771 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3772 {
3773         struct drm_i915_private *dev_priv = dev->dev_private;
3774         uint32_t dsparb = I915_READ(DSPARB);
3775         int size;
3776
3777         size = dsparb & 0x7f;
3778         size >>= 1; /* Convert to cachelines */
3779
3780         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3781                       plane ? "B" : "A", size);
3782
3783         return size;
3784 }
3785
3786 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3787 {
3788         struct drm_crtc *crtc, *enabled = NULL;
3789
3790         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3791                 if (crtc->enabled && crtc->fb) {
3792                         if (enabled)
3793                                 return NULL;
3794                         enabled = crtc;
3795                 }
3796         }
3797
3798         return enabled;
3799 }
3800
3801 static void pineview_update_wm(struct drm_device *dev)
3802 {
3803         struct drm_i915_private *dev_priv = dev->dev_private;
3804         struct drm_crtc *crtc;
3805         const struct cxsr_latency *latency;
3806         u32 reg;
3807         unsigned long wm;
3808
3809         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3810                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3811         if (!latency) {
3812                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3813                 pineview_disable_cxsr(dev);
3814                 return;
3815         }
3816
3817         crtc = single_enabled_crtc(dev);
3818         if (crtc) {
3819                 int clock = crtc->mode.clock;
3820                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3821
3822                 /* Display SR */
3823                 wm = intel_calculate_wm(clock, &pineview_display_wm,
3824                                         pineview_display_wm.fifo_size,
3825                                         pixel_size, latency->display_sr);
3826                 reg = I915_READ(DSPFW1);
3827                 reg &= ~DSPFW_SR_MASK;
3828                 reg |= wm << DSPFW_SR_SHIFT;
3829                 I915_WRITE(DSPFW1, reg);
3830                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3831
3832                 /* cursor SR */
3833                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3834                                         pineview_display_wm.fifo_size,
3835                                         pixel_size, latency->cursor_sr);
3836                 reg = I915_READ(DSPFW3);
3837                 reg &= ~DSPFW_CURSOR_SR_MASK;
3838                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3839                 I915_WRITE(DSPFW3, reg);
3840
3841                 /* Display HPLL off SR */
3842                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3843                                         pineview_display_hplloff_wm.fifo_size,
3844                                         pixel_size, latency->display_hpll_disable);
3845                 reg = I915_READ(DSPFW3);
3846                 reg &= ~DSPFW_HPLL_SR_MASK;
3847                 reg |= wm & DSPFW_HPLL_SR_MASK;
3848                 I915_WRITE(DSPFW3, reg);
3849
3850                 /* cursor HPLL off SR */
3851                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3852                                         pineview_display_hplloff_wm.fifo_size,
3853                                         pixel_size, latency->cursor_hpll_disable);
3854                 reg = I915_READ(DSPFW3);
3855                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3856                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3857                 I915_WRITE(DSPFW3, reg);
3858                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3859
3860                 /* activate cxsr */
3861                 I915_WRITE(DSPFW3,
3862                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3863                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3864         } else {
3865                 pineview_disable_cxsr(dev);
3866                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3867         }
3868 }
3869
3870 static bool g4x_compute_wm0(struct drm_device *dev,
3871                             int plane,
3872                             const struct intel_watermark_params *display,
3873                             int display_latency_ns,
3874                             const struct intel_watermark_params *cursor,
3875                             int cursor_latency_ns,
3876                             int *plane_wm,
3877                             int *cursor_wm)
3878 {
3879         struct drm_crtc *crtc;
3880         int htotal, hdisplay, clock, pixel_size;
3881         int line_time_us, line_count;
3882         int entries, tlb_miss;
3883
3884         crtc = intel_get_crtc_for_plane(dev, plane);
3885         if (crtc->fb == NULL || !crtc->enabled) {
3886                 *cursor_wm = cursor->guard_size;
3887                 *plane_wm = display->guard_size;
3888                 return false;
3889         }
3890
3891         htotal = crtc->mode.htotal;
3892         hdisplay = crtc->mode.hdisplay;
3893         clock = crtc->mode.clock;
3894         pixel_size = crtc->fb->bits_per_pixel / 8;
3895
3896         /* Use the small buffer method to calculate plane watermark */
3897         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3898         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3899         if (tlb_miss > 0)
3900                 entries += tlb_miss;
3901         entries = DIV_ROUND_UP(entries, display->cacheline_size);
3902         *plane_wm = entries + display->guard_size;
3903         if (*plane_wm > (int)display->max_wm)
3904                 *plane_wm = display->max_wm;
3905
3906         /* Use the large buffer method to calculate cursor watermark */
3907         line_time_us = ((htotal * 1000) / clock);
3908         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3909         entries = line_count * 64 * pixel_size;
3910         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3911         if (tlb_miss > 0)
3912                 entries += tlb_miss;
3913         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3914         *cursor_wm = entries + cursor->guard_size;
3915         if (*cursor_wm > (int)cursor->max_wm)
3916                 *cursor_wm = (int)cursor->max_wm;
3917
3918         return true;
3919 }
3920
3921 /*
3922  * Check the wm result.
3923  *
3924  * If any calculated watermark values is larger than the maximum value that
3925  * can be programmed into the associated watermark register, that watermark
3926  * must be disabled.
3927  */
3928 static bool g4x_check_srwm(struct drm_device *dev,
3929                            int display_wm, int cursor_wm,
3930                            const struct intel_watermark_params *display,
3931                            const struct intel_watermark_params *cursor)
3932 {
3933         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3934                       display_wm, cursor_wm);
3935
3936         if (display_wm > display->max_wm) {
3937                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
3938                               display_wm, display->max_wm);
3939                 return false;
3940         }
3941
3942         if (cursor_wm > cursor->max_wm) {
3943                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
3944                               cursor_wm, cursor->max_wm);
3945                 return false;
3946         }
3947
3948         if (!(display_wm || cursor_wm)) {
3949                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3950                 return false;
3951         }
3952
3953         return true;
3954 }
3955
3956 static bool g4x_compute_srwm(struct drm_device *dev,
3957                              int plane,
3958                              int latency_ns,
3959                              const struct intel_watermark_params *display,
3960                              const struct intel_watermark_params *cursor,
3961                              int *display_wm, int *cursor_wm)
3962 {
3963         struct drm_crtc *crtc;
3964         int hdisplay, htotal, pixel_size, clock;
3965         unsigned long line_time_us;
3966         int line_count, line_size;
3967         int small, large;
3968         int entries;
3969
3970         if (!latency_ns) {
3971                 *display_wm = *cursor_wm = 0;
3972                 return false;
3973         }
3974
3975         crtc = intel_get_crtc_for_plane(dev, plane);
3976         hdisplay = crtc->mode.hdisplay;
3977         htotal = crtc->mode.htotal;
3978         clock = crtc->mode.clock;
3979         pixel_size = crtc->fb->bits_per_pixel / 8;
3980
3981         line_time_us = (htotal * 1000) / clock;
3982         line_count = (latency_ns / line_time_us + 1000) / 1000;
3983         line_size = hdisplay * pixel_size;
3984
3985         /* Use the minimum of the small and large buffer method for primary */
3986         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3987         large = line_count * line_size;
3988
3989         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3990         *display_wm = entries + display->guard_size;
3991
3992         /* calculate the self-refresh watermark for display cursor */
3993         entries = line_count * pixel_size * 64;
3994         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3995         *cursor_wm = entries + cursor->guard_size;
3996
3997         return g4x_check_srwm(dev,
3998                               *display_wm, *cursor_wm,
3999                               display, cursor);
4000 }
4001
4002 #define single_plane_enabled(mask) is_power_of_2(mask)
4003
4004 static void g4x_update_wm(struct drm_device *dev)
4005 {
4006         static const int sr_latency_ns = 12000;
4007         struct drm_i915_private *dev_priv = dev->dev_private;
4008         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4009         int plane_sr, cursor_sr;
4010         unsigned int enabled = 0;
4011
4012         if (g4x_compute_wm0(dev, 0,
4013                             &g4x_wm_info, latency_ns,
4014                             &g4x_cursor_wm_info, latency_ns,
4015                             &planea_wm, &cursora_wm))
4016                 enabled |= 1;
4017
4018         if (g4x_compute_wm0(dev, 1,
4019                             &g4x_wm_info, latency_ns,
4020                             &g4x_cursor_wm_info, latency_ns,
4021                             &planeb_wm, &cursorb_wm))
4022                 enabled |= 2;
4023
4024         plane_sr = cursor_sr = 0;
4025         if (single_plane_enabled(enabled) &&
4026             g4x_compute_srwm(dev, ffs(enabled) - 1,
4027                              sr_latency_ns,
4028                              &g4x_wm_info,
4029                              &g4x_cursor_wm_info,
4030                              &plane_sr, &cursor_sr))
4031                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4032         else
4033                 I915_WRITE(FW_BLC_SELF,
4034                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4035
4036         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4037                       planea_wm, cursora_wm,
4038                       planeb_wm, cursorb_wm,
4039                       plane_sr, cursor_sr);
4040
4041         I915_WRITE(DSPFW1,
4042                    (plane_sr << DSPFW_SR_SHIFT) |
4043                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4044                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
4045                    planea_wm);
4046         I915_WRITE(DSPFW2,
4047                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4048                    (cursora_wm << DSPFW_CURSORA_SHIFT));
4049         /* HPLL off in SR has some issues on G4x... disable it */
4050         I915_WRITE(DSPFW3,
4051                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4052                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4053 }
4054
4055 static void i965_update_wm(struct drm_device *dev)
4056 {
4057         struct drm_i915_private *dev_priv = dev->dev_private;
4058         struct drm_crtc *crtc;
4059         int srwm = 1;
4060         int cursor_sr = 16;
4061
4062         /* Calc sr entries for one plane configs */
4063         crtc = single_enabled_crtc(dev);
4064         if (crtc) {
4065                 /* self-refresh has much higher latency */
4066                 static const int sr_latency_ns = 12000;
4067                 int clock = crtc->mode.clock;
4068                 int htotal = crtc->mode.htotal;
4069                 int hdisplay = crtc->mode.hdisplay;
4070                 int pixel_size = crtc->fb->bits_per_pixel / 8;
4071                 unsigned long line_time_us;
4072                 int entries;
4073
4074                 line_time_us = ((htotal * 1000) / clock);
4075
4076                 /* Use ns/us then divide to preserve precision */
4077                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4078                         pixel_size * hdisplay;
4079                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4080                 srwm = I965_FIFO_SIZE - entries;
4081                 if (srwm < 0)
4082                         srwm = 1;
4083                 srwm &= 0x1ff;
4084                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4085                               entries, srwm);
4086
4087                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4088                         pixel_size * 64;
4089                 entries = DIV_ROUND_UP(entries,
4090                                           i965_cursor_wm_info.cacheline_size);
4091                 cursor_sr = i965_cursor_wm_info.fifo_size -
4092                         (entries + i965_cursor_wm_info.guard_size);
4093
4094                 if (cursor_sr > i965_cursor_wm_info.max_wm)
4095                         cursor_sr = i965_cursor_wm_info.max_wm;
4096
4097                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4098                               "cursor %d\n", srwm, cursor_sr);
4099
4100                 if (IS_CRESTLINE(dev))
4101                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4102         } else {
4103                 /* Turn off self refresh if both pipes are enabled */
4104                 if (IS_CRESTLINE(dev))
4105                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4106                                    & ~FW_BLC_SELF_EN);
4107         }
4108
4109         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4110                       srwm);
4111
4112         /* 965 has limitations... */
4113         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4114                    (8 << 16) | (8 << 8) | (8 << 0));
4115         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4116         /* update cursor SR watermark */
4117         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4118 }
4119
4120 static void i9xx_update_wm(struct drm_device *dev)
4121 {
4122         struct drm_i915_private *dev_priv = dev->dev_private;
4123         const struct intel_watermark_params *wm_info;
4124         uint32_t fwater_lo;
4125         uint32_t fwater_hi;
4126         int cwm, srwm = 1;
4127         int fifo_size;
4128         int planea_wm, planeb_wm;
4129         struct drm_crtc *crtc, *enabled = NULL;
4130
4131         if (IS_I945GM(dev))
4132                 wm_info = &i945_wm_info;
4133         else if (!IS_GEN2(dev))
4134                 wm_info = &i915_wm_info;
4135         else
4136                 wm_info = &i855_wm_info;
4137
4138         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4139         crtc = intel_get_crtc_for_plane(dev, 0);
4140         if (crtc->enabled && crtc->fb) {
4141                 planea_wm = intel_calculate_wm(crtc->mode.clock,
4142                                                wm_info, fifo_size,
4143                                                crtc->fb->bits_per_pixel / 8,
4144                                                latency_ns);
4145                 enabled = crtc;
4146         } else
4147                 planea_wm = fifo_size - wm_info->guard_size;
4148
4149         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4150         crtc = intel_get_crtc_for_plane(dev, 1);
4151         if (crtc->enabled && crtc->fb) {
4152                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4153                                                wm_info, fifo_size,
4154                                                crtc->fb->bits_per_pixel / 8,
4155                                                latency_ns);
4156                 if (enabled == NULL)
4157                         enabled = crtc;
4158                 else
4159                         enabled = NULL;
4160         } else
4161                 planeb_wm = fifo_size - wm_info->guard_size;
4162
4163         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4164
4165         /*
4166          * Overlay gets an aggressive default since video jitter is bad.
4167          */
4168         cwm = 2;
4169
4170         /* Play safe and disable self-refresh before adjusting watermarks. */
4171         if (IS_I945G(dev) || IS_I945GM(dev))
4172                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4173         else if (IS_I915GM(dev))
4174                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4175
4176         /* Calc sr entries for one plane configs */
4177         if (HAS_FW_BLC(dev) && enabled) {
4178                 /* self-refresh has much higher latency */
4179                 static const int sr_latency_ns = 6000;
4180                 int clock = enabled->mode.clock;
4181                 int htotal = enabled->mode.htotal;
4182                 int hdisplay = enabled->mode.hdisplay;
4183                 int pixel_size = enabled->fb->bits_per_pixel / 8;
4184                 unsigned long line_time_us;
4185                 int entries;
4186
4187                 line_time_us = (htotal * 1000) / clock;
4188
4189                 /* Use ns/us then divide to preserve precision */
4190                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4191                         pixel_size * hdisplay;
4192                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4193                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4194                 srwm = wm_info->fifo_size - entries;
4195                 if (srwm < 0)
4196                         srwm = 1;
4197
4198                 if (IS_I945G(dev) || IS_I945GM(dev))
4199                         I915_WRITE(FW_BLC_SELF,
4200                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4201                 else if (IS_I915GM(dev))
4202                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4203         }
4204
4205         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4206                       planea_wm, planeb_wm, cwm, srwm);
4207
4208         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4209         fwater_hi = (cwm & 0x1f);
4210
4211         /* Set request length to 8 cachelines per fetch */
4212         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4213         fwater_hi = fwater_hi | (1 << 8);
4214
4215         I915_WRITE(FW_BLC, fwater_lo);
4216         I915_WRITE(FW_BLC2, fwater_hi);
4217
4218         if (HAS_FW_BLC(dev)) {
4219                 if (enabled) {
4220                         if (IS_I945G(dev) || IS_I945GM(dev))
4221                                 I915_WRITE(FW_BLC_SELF,
4222                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4223                         else if (IS_I915GM(dev))
4224                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4225                         DRM_DEBUG_KMS("memory self refresh enabled\n");
4226                 } else
4227                         DRM_DEBUG_KMS("memory self refresh disabled\n");
4228         }
4229 }
4230
4231 static void i830_update_wm(struct drm_device *dev)
4232 {
4233         struct drm_i915_private *dev_priv = dev->dev_private;
4234         struct drm_crtc *crtc;
4235         uint32_t fwater_lo;
4236         int planea_wm;
4237
4238         crtc = single_enabled_crtc(dev);
4239         if (crtc == NULL)
4240                 return;
4241
4242         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4243                                        dev_priv->display.get_fifo_size(dev, 0),
4244                                        crtc->fb->bits_per_pixel / 8,
4245                                        latency_ns);
4246         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4247         fwater_lo |= (3<<8) | planea_wm;
4248
4249         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4250
4251         I915_WRITE(FW_BLC, fwater_lo);
4252 }
4253
4254 #define ILK_LP0_PLANE_LATENCY           700
4255 #define ILK_LP0_CURSOR_LATENCY          1300
4256
4257 /*
4258  * Check the wm result.
4259  *
4260  * If any calculated watermark values is larger than the maximum value that
4261  * can be programmed into the associated watermark register, that watermark
4262  * must be disabled.
4263  */
4264 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4265                                 int fbc_wm, int display_wm, int cursor_wm,
4266                                 const struct intel_watermark_params *display,
4267                                 const struct intel_watermark_params *cursor)
4268 {
4269         struct drm_i915_private *dev_priv = dev->dev_private;
4270
4271         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4272                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4273
4274         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4275                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4276                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4277
4278                 /* fbc has it's own way to disable FBC WM */
4279                 I915_WRITE(DISP_ARB_CTL,
4280                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4281                 return false;
4282         }
4283
4284         if (display_wm > display->max_wm) {
4285                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4286                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4287                 return false;
4288         }
4289
4290         if (cursor_wm > cursor->max_wm) {
4291                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4292                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4293                 return false;
4294         }
4295
4296         if (!(fbc_wm || display_wm || cursor_wm)) {
4297                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4298                 return false;
4299         }
4300
4301         return true;
4302 }
4303
4304 /*
4305  * Compute watermark values of WM[1-3],
4306  */
4307 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4308                                   int latency_ns,
4309                                   const struct intel_watermark_params *display,
4310                                   const struct intel_watermark_params *cursor,
4311                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4312 {
4313         struct drm_crtc *crtc;
4314         unsigned long line_time_us;
4315         int hdisplay, htotal, pixel_size, clock;
4316         int line_count, line_size;
4317         int small, large;
4318         int entries;
4319
4320         if (!latency_ns) {
4321                 *fbc_wm = *display_wm = *cursor_wm = 0;
4322                 return false;
4323         }
4324
4325         crtc = intel_get_crtc_for_plane(dev, plane);
4326         hdisplay = crtc->mode.hdisplay;
4327         htotal = crtc->mode.htotal;
4328         clock = crtc->mode.clock;
4329         pixel_size = crtc->fb->bits_per_pixel / 8;
4330
4331         line_time_us = (htotal * 1000) / clock;
4332         line_count = (latency_ns / line_time_us + 1000) / 1000;
4333         line_size = hdisplay * pixel_size;
4334
4335         /* Use the minimum of the small and large buffer method for primary */
4336         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4337         large = line_count * line_size;
4338
4339         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4340         *display_wm = entries + display->guard_size;
4341
4342         /*
4343          * Spec says:
4344          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4345          */
4346         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4347
4348         /* calculate the self-refresh watermark for display cursor */
4349         entries = line_count * pixel_size * 64;
4350         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4351         *cursor_wm = entries + cursor->guard_size;
4352
4353         return ironlake_check_srwm(dev, level,
4354                                    *fbc_wm, *display_wm, *cursor_wm,
4355                                    display, cursor);
4356 }
4357
4358 static void ironlake_update_wm(struct drm_device *dev)
4359 {
4360         struct drm_i915_private *dev_priv = dev->dev_private;
4361         int fbc_wm, plane_wm, cursor_wm;
4362         unsigned int enabled;
4363
4364         enabled = 0;
4365         if (g4x_compute_wm0(dev, 0,
4366                             &ironlake_display_wm_info,
4367                             ILK_LP0_PLANE_LATENCY,
4368                             &ironlake_cursor_wm_info,
4369                             ILK_LP0_CURSOR_LATENCY,
4370                             &plane_wm, &cursor_wm)) {
4371                 I915_WRITE(WM0_PIPEA_ILK,
4372                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4373                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4374                               " plane %d, " "cursor: %d\n",
4375                               plane_wm, cursor_wm);
4376                 enabled |= 1;
4377         }
4378
4379         if (g4x_compute_wm0(dev, 1,
4380                             &ironlake_display_wm_info,
4381                             ILK_LP0_PLANE_LATENCY,
4382                             &ironlake_cursor_wm_info,
4383                             ILK_LP0_CURSOR_LATENCY,
4384                             &plane_wm, &cursor_wm)) {
4385                 I915_WRITE(WM0_PIPEB_ILK,
4386                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4387                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4388                               " plane %d, cursor: %d\n",
4389                               plane_wm, cursor_wm);
4390                 enabled |= 2;
4391         }
4392
4393         /*
4394          * Calculate and update the self-refresh watermark only when one
4395          * display plane is used.
4396          */
4397         I915_WRITE(WM3_LP_ILK, 0);
4398         I915_WRITE(WM2_LP_ILK, 0);
4399         I915_WRITE(WM1_LP_ILK, 0);
4400
4401         if (!single_plane_enabled(enabled))
4402                 return;
4403         enabled = ffs(enabled) - 1;
4404
4405         /* WM1 */
4406         if (!ironlake_compute_srwm(dev, 1, enabled,
4407                                    ILK_READ_WM1_LATENCY() * 500,
4408                                    &ironlake_display_srwm_info,
4409                                    &ironlake_cursor_srwm_info,
4410                                    &fbc_wm, &plane_wm, &cursor_wm))
4411                 return;
4412
4413         I915_WRITE(WM1_LP_ILK,
4414                    WM1_LP_SR_EN |
4415                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4416                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4417                    (plane_wm << WM1_LP_SR_SHIFT) |
4418                    cursor_wm);
4419
4420         /* WM2 */
4421         if (!ironlake_compute_srwm(dev, 2, enabled,
4422                                    ILK_READ_WM2_LATENCY() * 500,
4423                                    &ironlake_display_srwm_info,
4424                                    &ironlake_cursor_srwm_info,
4425                                    &fbc_wm, &plane_wm, &cursor_wm))
4426                 return;
4427
4428         I915_WRITE(WM2_LP_ILK,
4429                    WM2_LP_EN |
4430                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4431                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4432                    (plane_wm << WM1_LP_SR_SHIFT) |
4433                    cursor_wm);
4434
4435         /*
4436          * WM3 is unsupported on ILK, probably because we don't have latency
4437          * data for that power state
4438          */
4439 }
4440
4441 static void sandybridge_update_wm(struct drm_device *dev)
4442 {
4443         struct drm_i915_private *dev_priv = dev->dev_private;
4444         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4445         int fbc_wm, plane_wm, cursor_wm;
4446         unsigned int enabled;
4447
4448         enabled = 0;
4449         if (g4x_compute_wm0(dev, 0,
4450                             &sandybridge_display_wm_info, latency,
4451                             &sandybridge_cursor_wm_info, latency,
4452                             &plane_wm, &cursor_wm)) {
4453                 I915_WRITE(WM0_PIPEA_ILK,
4454                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4455                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4456                               " plane %d, " "cursor: %d\n",
4457                               plane_wm, cursor_wm);
4458                 enabled |= 1;
4459         }
4460
4461         if (g4x_compute_wm0(dev, 1,
4462                             &sandybridge_display_wm_info, latency,
4463                             &sandybridge_cursor_wm_info, latency,
4464                             &plane_wm, &cursor_wm)) {
4465                 I915_WRITE(WM0_PIPEB_ILK,
4466                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4467                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4468                               " plane %d, cursor: %d\n",
4469                               plane_wm, cursor_wm);
4470                 enabled |= 2;
4471         }
4472
4473         /*
4474          * Calculate and update the self-refresh watermark only when one
4475          * display plane is used.
4476          *
4477          * SNB support 3 levels of watermark.
4478          *
4479          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4480          * and disabled in the descending order
4481          *
4482          */
4483         I915_WRITE(WM3_LP_ILK, 0);
4484         I915_WRITE(WM2_LP_ILK, 0);
4485         I915_WRITE(WM1_LP_ILK, 0);
4486
4487         if (!single_plane_enabled(enabled))
4488                 return;
4489         enabled = ffs(enabled) - 1;
4490
4491         /* WM1 */
4492         if (!ironlake_compute_srwm(dev, 1, enabled,
4493                                    SNB_READ_WM1_LATENCY() * 500,
4494                                    &sandybridge_display_srwm_info,
4495                                    &sandybridge_cursor_srwm_info,
4496                                    &fbc_wm, &plane_wm, &cursor_wm))
4497                 return;
4498
4499         I915_WRITE(WM1_LP_ILK,
4500                    WM1_LP_SR_EN |
4501                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4502                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4503                    (plane_wm << WM1_LP_SR_SHIFT) |
4504                    cursor_wm);
4505
4506         /* WM2 */
4507         if (!ironlake_compute_srwm(dev, 2, enabled,
4508                                    SNB_READ_WM2_LATENCY() * 500,
4509                                    &sandybridge_display_srwm_info,
4510                                    &sandybridge_cursor_srwm_info,
4511                                    &fbc_wm, &plane_wm, &cursor_wm))
4512                 return;
4513
4514         I915_WRITE(WM2_LP_ILK,
4515                    WM2_LP_EN |
4516                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4517                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4518                    (plane_wm << WM1_LP_SR_SHIFT) |
4519                    cursor_wm);
4520
4521         /* WM3 */
4522         if (!ironlake_compute_srwm(dev, 3, enabled,
4523                                    SNB_READ_WM3_LATENCY() * 500,
4524                                    &sandybridge_display_srwm_info,
4525                                    &sandybridge_cursor_srwm_info,
4526                                    &fbc_wm, &plane_wm, &cursor_wm))
4527                 return;
4528
4529         I915_WRITE(WM3_LP_ILK,
4530                    WM3_LP_EN |
4531                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4532                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4533                    (plane_wm << WM1_LP_SR_SHIFT) |
4534                    cursor_wm);
4535 }
4536
4537 /**
4538  * intel_update_watermarks - update FIFO watermark values based on current modes
4539  *
4540  * Calculate watermark values for the various WM regs based on current mode
4541  * and plane configuration.
4542  *
4543  * There are several cases to deal with here:
4544  *   - normal (i.e. non-self-refresh)
4545  *   - self-refresh (SR) mode
4546  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4547  *   - lines are small relative to FIFO size (buffer can hold more than 2
4548  *     lines), so need to account for TLB latency
4549  *
4550  *   The normal calculation is:
4551  *     watermark = dotclock * bytes per pixel * latency
4552  *   where latency is platform & configuration dependent (we assume pessimal
4553  *   values here).
4554  *
4555  *   The SR calculation is:
4556  *     watermark = (trunc(latency/line time)+1) * surface width *
4557  *       bytes per pixel
4558  *   where
4559  *     line time = htotal / dotclock
4560  *     surface width = hdisplay for normal plane and 64 for cursor
4561  *   and latency is assumed to be high, as above.
4562  *
4563  * The final value programmed to the register should always be rounded up,
4564  * and include an extra 2 entries to account for clock crossings.
4565  *
4566  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4567  * to set the non-SR watermarks to 8.
4568  */
4569 static void intel_update_watermarks(struct drm_device *dev)
4570 {
4571         struct drm_i915_private *dev_priv = dev->dev_private;
4572
4573         if (dev_priv->display.update_wm)
4574                 dev_priv->display.update_wm(dev);
4575 }
4576
4577 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4578 {
4579         return dev_priv->lvds_use_ssc && i915_panel_use_ssc
4580                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4581 }
4582
4583 /**
4584  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4585  * @crtc: CRTC structure
4586  *
4587  * A pipe may be connected to one or more outputs.  Based on the depth of the
4588  * attached framebuffer, choose a good color depth to use on the pipe.
4589  *
4590  * If possible, match the pipe depth to the fb depth.  In some cases, this
4591  * isn't ideal, because the connected output supports a lesser or restricted
4592  * set of depths.  Resolve that here:
4593  *    LVDS typically supports only 6bpc, so clamp down in that case
4594  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4595  *    Displays may support a restricted set as well, check EDID and clamp as
4596  *      appropriate.
4597  *
4598  * RETURNS:
4599  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4600  * true if they don't match).
4601  */
4602 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4603                                          unsigned int *pipe_bpp)
4604 {
4605         struct drm_device *dev = crtc->dev;
4606         struct drm_i915_private *dev_priv = dev->dev_private;
4607         struct drm_encoder *encoder;
4608         struct drm_connector *connector;
4609         unsigned int display_bpc = UINT_MAX, bpc;
4610
4611         /* Walk the encoders & connectors on this crtc, get min bpc */
4612         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4613                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4614
4615                 if (encoder->crtc != crtc)
4616                         continue;
4617
4618                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4619                         unsigned int lvds_bpc;
4620
4621                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4622                             LVDS_A3_POWER_UP)
4623                                 lvds_bpc = 8;
4624                         else
4625                                 lvds_bpc = 6;
4626
4627                         if (lvds_bpc < display_bpc) {
4628                                 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4629                                 display_bpc = lvds_bpc;
4630                         }
4631                         continue;
4632                 }
4633
4634                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4635                         /* Use VBT settings if we have an eDP panel */
4636                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4637
4638                         if (edp_bpc < display_bpc) {
4639                                 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4640                                 display_bpc = edp_bpc;
4641                         }
4642                         continue;
4643                 }
4644
4645                 /* Not one of the known troublemakers, check the EDID */
4646                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4647                                     head) {
4648                         if (connector->encoder != encoder)
4649                                 continue;
4650
4651                         /* Don't use an invalid EDID bpc value */
4652                         if (connector->display_info.bpc &&
4653                             connector->display_info.bpc < display_bpc) {
4654                                 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4655                                 display_bpc = connector->display_info.bpc;
4656                         }
4657                 }
4658
4659                 /*
4660                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4661                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4662                  */
4663                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4664                         if (display_bpc > 8 && display_bpc < 12) {
4665                                 DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n");
4666                                 display_bpc = 12;
4667                         } else {
4668                                 DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n");
4669                                 display_bpc = 8;
4670                         }
4671                 }
4672         }
4673
4674         /*
4675          * We could just drive the pipe at the highest bpc all the time and
4676          * enable dithering as needed, but that costs bandwidth.  So choose
4677          * the minimum value that expresses the full color range of the fb but
4678          * also stays within the max display bpc discovered above.
4679          */
4680
4681         switch (crtc->fb->depth) {
4682         case 8:
4683                 bpc = 8; /* since we go through a colormap */
4684                 break;
4685         case 15:
4686         case 16:
4687                 bpc = 6; /* min is 18bpp */
4688                 break;
4689         case 24:
4690                 bpc = min((unsigned int)8, display_bpc);
4691                 break;
4692         case 30:
4693                 bpc = min((unsigned int)10, display_bpc);
4694                 break;
4695         case 48:
4696                 bpc = min((unsigned int)12, display_bpc);
4697                 break;
4698         default:
4699                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4700                 bpc = min((unsigned int)8, display_bpc);
4701                 break;
4702         }
4703
4704         DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
4705                          bpc, display_bpc);
4706
4707         *pipe_bpp = bpc * 3;
4708
4709         return display_bpc != bpc;
4710 }
4711
4712 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4713                               struct drm_display_mode *mode,
4714                               struct drm_display_mode *adjusted_mode,
4715                               int x, int y,
4716                               struct drm_framebuffer *old_fb)
4717 {
4718         struct drm_device *dev = crtc->dev;
4719         struct drm_i915_private *dev_priv = dev->dev_private;
4720         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4721         int pipe = intel_crtc->pipe;
4722         int plane = intel_crtc->plane;
4723         int refclk, num_connectors = 0;
4724         intel_clock_t clock, reduced_clock;
4725         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4726         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4727         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4728         struct drm_mode_config *mode_config = &dev->mode_config;
4729         struct intel_encoder *encoder;
4730         const intel_limit_t *limit;
4731         int ret;
4732         u32 temp;
4733         u32 lvds_sync = 0;
4734
4735         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4736                 if (encoder->base.crtc != crtc)
4737                         continue;
4738
4739                 switch (encoder->type) {
4740                 case INTEL_OUTPUT_LVDS:
4741                         is_lvds = true;
4742                         break;
4743                 case INTEL_OUTPUT_SDVO:
4744                 case INTEL_OUTPUT_HDMI:
4745                         is_sdvo = true;
4746                         if (encoder->needs_tv_clock)
4747                                 is_tv = true;
4748                         break;
4749                 case INTEL_OUTPUT_DVO:
4750                         is_dvo = true;
4751                         break;
4752                 case INTEL_OUTPUT_TVOUT:
4753                         is_tv = true;
4754                         break;
4755                 case INTEL_OUTPUT_ANALOG:
4756                         is_crt = true;
4757                         break;
4758                 case INTEL_OUTPUT_DISPLAYPORT:
4759                         is_dp = true;
4760                         break;
4761                 }
4762
4763                 num_connectors++;
4764         }
4765
4766         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4767                 refclk = dev_priv->lvds_ssc_freq * 1000;
4768                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4769                               refclk / 1000);
4770         } else if (!IS_GEN2(dev)) {
4771                 refclk = 96000;
4772         } else {
4773                 refclk = 48000;
4774         }
4775
4776         /*
4777          * Returns a set of divisors for the desired target clock with the given
4778          * refclk, or FALSE.  The returned values represent the clock equation:
4779          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4780          */
4781         limit = intel_limit(crtc, refclk);
4782         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4783         if (!ok) {
4784                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4785                 return -EINVAL;
4786         }
4787
4788         /* Ensure that the cursor is valid for the new mode before changing... */
4789         intel_crtc_update_cursor(crtc, true);
4790
4791         if (is_lvds && dev_priv->lvds_downclock_avail) {
4792                 has_reduced_clock = limit->find_pll(limit, crtc,
4793                                                     dev_priv->lvds_downclock,
4794                                                     refclk,
4795                                                     &reduced_clock);
4796                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4797                         /*
4798                          * If the different P is found, it means that we can't
4799                          * switch the display clock by using the FP0/FP1.
4800                          * In such case we will disable the LVDS downclock
4801                          * feature.
4802                          */
4803                         DRM_DEBUG_KMS("Different P is found for "
4804                                       "LVDS clock/downclock\n");
4805                         has_reduced_clock = 0;
4806                 }
4807         }
4808         /* SDVO TV has fixed PLL values depend on its clock range,
4809            this mirrors vbios setting. */
4810         if (is_sdvo && is_tv) {
4811                 if (adjusted_mode->clock >= 100000
4812                     && adjusted_mode->clock < 140500) {
4813                         clock.p1 = 2;
4814                         clock.p2 = 10;
4815                         clock.n = 3;
4816                         clock.m1 = 16;
4817                         clock.m2 = 8;
4818                 } else if (adjusted_mode->clock >= 140500
4819                            && adjusted_mode->clock <= 200000) {
4820                         clock.p1 = 1;
4821                         clock.p2 = 10;
4822                         clock.n = 6;
4823                         clock.m1 = 12;
4824                         clock.m2 = 8;
4825                 }
4826         }
4827
4828         if (IS_PINEVIEW(dev)) {
4829                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4830                 if (has_reduced_clock)
4831                         fp2 = (1 << reduced_clock.n) << 16 |
4832                                 reduced_clock.m1 << 8 | reduced_clock.m2;
4833         } else {
4834                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4835                 if (has_reduced_clock)
4836                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4837                                 reduced_clock.m2;
4838         }
4839
4840         dpll = DPLL_VGA_MODE_DIS;
4841
4842         if (!IS_GEN2(dev)) {
4843                 if (is_lvds)
4844                         dpll |= DPLLB_MODE_LVDS;
4845                 else
4846                         dpll |= DPLLB_MODE_DAC_SERIAL;
4847                 if (is_sdvo) {
4848                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4849                         if (pixel_multiplier > 1) {
4850                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4851                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4852                         }
4853                         dpll |= DPLL_DVO_HIGH_SPEED;
4854                 }
4855                 if (is_dp)
4856                         dpll |= DPLL_DVO_HIGH_SPEED;
4857
4858                 /* compute bitmask from p1 value */
4859                 if (IS_PINEVIEW(dev))
4860                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4861                 else {
4862                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4863                         if (IS_G4X(dev) && has_reduced_clock)
4864                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4865                 }
4866                 switch (clock.p2) {
4867                 case 5:
4868                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4869                         break;
4870                 case 7:
4871                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4872                         break;
4873                 case 10:
4874                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4875                         break;
4876                 case 14:
4877                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4878                         break;
4879                 }
4880                 if (INTEL_INFO(dev)->gen >= 4)
4881                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4882         } else {
4883                 if (is_lvds) {
4884                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4885                 } else {
4886                         if (clock.p1 == 2)
4887                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
4888                         else
4889                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4890                         if (clock.p2 == 4)
4891                                 dpll |= PLL_P2_DIVIDE_BY_4;
4892                 }
4893         }
4894
4895         if (is_sdvo && is_tv)
4896                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4897         else if (is_tv)
4898                 /* XXX: just matching BIOS for now */
4899                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4900                 dpll |= 3;
4901         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4902                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4903         else
4904                 dpll |= PLL_REF_INPUT_DREFCLK;
4905
4906         /* setup pipeconf */
4907         pipeconf = I915_READ(PIPECONF(pipe));
4908
4909         /* Set up the display plane register */
4910         dspcntr = DISPPLANE_GAMMA_ENABLE;
4911
4912         /* Ironlake's plane is forced to pipe, bit 24 is to
4913            enable color space conversion */
4914         if (pipe == 0)
4915                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4916         else
4917                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4918
4919         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4920                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4921                  * core speed.
4922                  *
4923                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4924                  * pipe == 0 check?
4925                  */
4926                 if (mode->clock >
4927                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4928                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4929                 else
4930                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4931         }
4932
4933         dpll |= DPLL_VCO_ENABLE;
4934
4935         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4936         drm_mode_debug_printmodeline(mode);
4937
4938         I915_WRITE(FP0(pipe), fp);
4939         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4940
4941         POSTING_READ(DPLL(pipe));
4942         udelay(150);
4943
4944         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4945          * This is an exception to the general rule that mode_set doesn't turn
4946          * things on.
4947          */
4948         if (is_lvds) {
4949                 temp = I915_READ(LVDS);
4950                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4951                 if (pipe == 1) {
4952                         temp |= LVDS_PIPEB_SELECT;
4953                 } else {
4954                         temp &= ~LVDS_PIPEB_SELECT;
4955                 }
4956                 /* set the corresponsding LVDS_BORDER bit */
4957                 temp |= dev_priv->lvds_border_bits;
4958                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4959                  * set the DPLLs for dual-channel mode or not.
4960                  */
4961                 if (clock.p2 == 7)
4962                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4963                 else
4964                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4965
4966                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4967                  * appropriately here, but we need to look more thoroughly into how
4968                  * panels behave in the two modes.
4969                  */
4970                 /* set the dithering flag on LVDS as needed */
4971                 if (INTEL_INFO(dev)->gen >= 4) {
4972                         if (dev_priv->lvds_dither)
4973                                 temp |= LVDS_ENABLE_DITHER;
4974                         else
4975                                 temp &= ~LVDS_ENABLE_DITHER;
4976                 }
4977                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4978                         lvds_sync |= LVDS_HSYNC_POLARITY;
4979                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4980                         lvds_sync |= LVDS_VSYNC_POLARITY;
4981                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4982                     != lvds_sync) {
4983                         char flags[2] = "-+";
4984                         DRM_INFO("Changing LVDS panel from "
4985                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4986                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
4987                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
4988                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4989                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4990                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4991                         temp |= lvds_sync;
4992                 }
4993                 I915_WRITE(LVDS, temp);
4994         }
4995
4996         if (is_dp) {
4997                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4998         }
4999
5000         I915_WRITE(DPLL(pipe), dpll);
5001
5002         /* Wait for the clocks to stabilize. */
5003         POSTING_READ(DPLL(pipe));
5004         udelay(150);
5005
5006         if (INTEL_INFO(dev)->gen >= 4) {
5007                 temp = 0;
5008                 if (is_sdvo) {
5009                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5010                         if (temp > 1)
5011                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5012                         else
5013                                 temp = 0;
5014                 }
5015                 I915_WRITE(DPLL_MD(pipe), temp);
5016         } else {
5017                 /* The pixel multiplier can only be updated once the
5018                  * DPLL is enabled and the clocks are stable.
5019                  *
5020                  * So write it again.
5021                  */
5022                 I915_WRITE(DPLL(pipe), dpll);
5023         }
5024
5025         intel_crtc->lowfreq_avail = false;
5026         if (is_lvds && has_reduced_clock && i915_powersave) {
5027                 I915_WRITE(FP1(pipe), fp2);
5028                 intel_crtc->lowfreq_avail = true;
5029                 if (HAS_PIPE_CXSR(dev)) {
5030                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5031                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5032                 }
5033         } else {
5034                 I915_WRITE(FP1(pipe), fp);
5035                 if (HAS_PIPE_CXSR(dev)) {
5036                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5037                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5038                 }
5039         }
5040
5041         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5042                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5043                 /* the chip adds 2 halflines automatically */
5044                 adjusted_mode->crtc_vdisplay -= 1;
5045                 adjusted_mode->crtc_vtotal -= 1;
5046                 adjusted_mode->crtc_vblank_start -= 1;
5047                 adjusted_mode->crtc_vblank_end -= 1;
5048                 adjusted_mode->crtc_vsync_end -= 1;
5049                 adjusted_mode->crtc_vsync_start -= 1;
5050         } else
5051                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5052
5053         I915_WRITE(HTOTAL(pipe),
5054                    (adjusted_mode->crtc_hdisplay - 1) |
5055                    ((adjusted_mode->crtc_htotal - 1) << 16));
5056         I915_WRITE(HBLANK(pipe),
5057                    (adjusted_mode->crtc_hblank_start - 1) |
5058                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5059         I915_WRITE(HSYNC(pipe),
5060                    (adjusted_mode->crtc_hsync_start - 1) |
5061                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5062
5063         I915_WRITE(VTOTAL(pipe),
5064                    (adjusted_mode->crtc_vdisplay - 1) |
5065                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5066         I915_WRITE(VBLANK(pipe),
5067                    (adjusted_mode->crtc_vblank_start - 1) |
5068                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5069         I915_WRITE(VSYNC(pipe),
5070                    (adjusted_mode->crtc_vsync_start - 1) |
5071                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5072
5073         /* pipesrc and dspsize control the size that is scaled from,
5074          * which should always be the user's requested size.
5075          */
5076         I915_WRITE(DSPSIZE(plane),
5077                    ((mode->vdisplay - 1) << 16) |
5078                    (mode->hdisplay - 1));
5079         I915_WRITE(DSPPOS(plane), 0);
5080         I915_WRITE(PIPESRC(pipe),
5081                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5082
5083         I915_WRITE(PIPECONF(pipe), pipeconf);
5084         POSTING_READ(PIPECONF(pipe));
5085         intel_enable_pipe(dev_priv, pipe, false);
5086
5087         intel_wait_for_vblank(dev, pipe);
5088
5089         I915_WRITE(DSPCNTR(plane), dspcntr);
5090         POSTING_READ(DSPCNTR(plane));
5091         intel_enable_plane(dev_priv, plane, pipe);
5092
5093         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5094
5095         intel_update_watermarks(dev);
5096
5097         return ret;
5098 }
5099
5100 static void ironlake_update_pch_refclk(struct drm_device *dev)
5101 {
5102         struct drm_i915_private *dev_priv = dev->dev_private;
5103         struct drm_mode_config *mode_config = &dev->mode_config;
5104         struct drm_crtc *crtc;
5105         struct intel_encoder *encoder;
5106         struct intel_encoder *has_edp_encoder = NULL;
5107         u32 temp;
5108         bool has_lvds = false;
5109
5110         /* We need to take the global config into account */
5111         list_for_each_entry(crtc, &mode_config->crtc_list, head) {
5112                 if (!crtc->enabled)
5113                         continue;
5114
5115                 list_for_each_entry(encoder, &mode_config->encoder_list,
5116                                     base.head) {
5117                         if (encoder->base.crtc != crtc)
5118                                 continue;
5119
5120                         switch (encoder->type) {
5121                         case INTEL_OUTPUT_LVDS:
5122                                 has_lvds = true;
5123                         case INTEL_OUTPUT_EDP:
5124                                 has_edp_encoder = encoder;
5125                                 break;
5126                         }
5127                 }
5128         }
5129
5130         /* Ironlake: try to setup display ref clock before DPLL
5131          * enabling. This is only under driver's control after
5132          * PCH B stepping, previous chipset stepping should be
5133          * ignoring this setting.
5134          */
5135         temp = I915_READ(PCH_DREF_CONTROL);
5136         /* Always enable nonspread source */
5137         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5138         temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5139         temp &= ~DREF_SSC_SOURCE_MASK;
5140         temp |= DREF_SSC_SOURCE_ENABLE;
5141         I915_WRITE(PCH_DREF_CONTROL, temp);
5142
5143         POSTING_READ(PCH_DREF_CONTROL);
5144         udelay(200);
5145
5146         if (has_edp_encoder) {
5147                 if (intel_panel_use_ssc(dev_priv)) {
5148                         temp |= DREF_SSC1_ENABLE;
5149                         I915_WRITE(PCH_DREF_CONTROL, temp);
5150
5151                         POSTING_READ(PCH_DREF_CONTROL);
5152                         udelay(200);
5153                 }
5154                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5155
5156                 /* Enable CPU source on CPU attached eDP */
5157                 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5158                         if (intel_panel_use_ssc(dev_priv))
5159                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5160                         else
5161                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5162                 } else {
5163                         /* Enable SSC on PCH eDP if needed */
5164                         if (intel_panel_use_ssc(dev_priv)) {
5165                                 DRM_ERROR("enabling SSC on PCH\n");
5166                                 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
5167                         }
5168                 }
5169                 I915_WRITE(PCH_DREF_CONTROL, temp);
5170                 POSTING_READ(PCH_DREF_CONTROL);
5171                 udelay(200);
5172         }
5173 }
5174
5175 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5176                                   struct drm_display_mode *mode,
5177                                   struct drm_display_mode *adjusted_mode,
5178                                   int x, int y,
5179                                   struct drm_framebuffer *old_fb)
5180 {
5181         struct drm_device *dev = crtc->dev;
5182         struct drm_i915_private *dev_priv = dev->dev_private;
5183         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5184         int pipe = intel_crtc->pipe;
5185         int plane = intel_crtc->plane;
5186         int refclk, num_connectors = 0;
5187         intel_clock_t clock, reduced_clock;
5188         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5189         bool ok, has_reduced_clock = false, is_sdvo = false;
5190         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5191         struct intel_encoder *has_edp_encoder = NULL;
5192         struct drm_mode_config *mode_config = &dev->mode_config;
5193         struct intel_encoder *encoder;
5194         const intel_limit_t *limit;
5195         int ret;
5196         struct fdi_m_n m_n = {0};
5197         u32 temp;
5198         u32 lvds_sync = 0;
5199         int target_clock, pixel_multiplier, lane, link_bw, factor;
5200         unsigned int pipe_bpp;
5201         bool dither;
5202
5203         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5204                 if (encoder->base.crtc != crtc)
5205                         continue;
5206
5207                 switch (encoder->type) {
5208                 case INTEL_OUTPUT_LVDS:
5209                         is_lvds = true;
5210                         break;
5211                 case INTEL_OUTPUT_SDVO:
5212                 case INTEL_OUTPUT_HDMI:
5213                         is_sdvo = true;
5214                         if (encoder->needs_tv_clock)
5215                                 is_tv = true;
5216                         break;
5217                 case INTEL_OUTPUT_TVOUT:
5218                         is_tv = true;
5219                         break;
5220                 case INTEL_OUTPUT_ANALOG:
5221                         is_crt = true;
5222                         break;
5223                 case INTEL_OUTPUT_DISPLAYPORT:
5224                         is_dp = true;
5225                         break;
5226                 case INTEL_OUTPUT_EDP:
5227                         has_edp_encoder = encoder;
5228                         break;
5229                 }
5230
5231                 num_connectors++;
5232         }
5233
5234         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5235                 refclk = dev_priv->lvds_ssc_freq * 1000;
5236                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5237                               refclk / 1000);
5238         } else {
5239                 refclk = 96000;
5240                 if (!has_edp_encoder ||
5241                     intel_encoder_is_pch_edp(&has_edp_encoder->base))
5242                         refclk = 120000; /* 120Mhz refclk */
5243         }
5244
5245         /*
5246          * Returns a set of divisors for the desired target clock with the given
5247          * refclk, or FALSE.  The returned values represent the clock equation:
5248          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5249          */
5250         limit = intel_limit(crtc, refclk);
5251         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5252         if (!ok) {
5253                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5254                 return -EINVAL;
5255         }
5256
5257         /* Ensure that the cursor is valid for the new mode before changing... */
5258         intel_crtc_update_cursor(crtc, true);
5259
5260         if (is_lvds && dev_priv->lvds_downclock_avail) {
5261                 has_reduced_clock = limit->find_pll(limit, crtc,
5262                                                     dev_priv->lvds_downclock,
5263                                                     refclk,
5264                                                     &reduced_clock);
5265                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5266                         /*
5267                          * If the different P is found, it means that we can't
5268                          * switch the display clock by using the FP0/FP1.
5269                          * In such case we will disable the LVDS downclock
5270                          * feature.
5271                          */
5272                         DRM_DEBUG_KMS("Different P is found for "
5273                                       "LVDS clock/downclock\n");
5274                         has_reduced_clock = 0;
5275                 }
5276         }
5277         /* SDVO TV has fixed PLL values depend on its clock range,
5278            this mirrors vbios setting. */
5279         if (is_sdvo && is_tv) {
5280                 if (adjusted_mode->clock >= 100000
5281                     && adjusted_mode->clock < 140500) {
5282                         clock.p1 = 2;
5283                         clock.p2 = 10;
5284                         clock.n = 3;
5285                         clock.m1 = 16;
5286                         clock.m2 = 8;
5287                 } else if (adjusted_mode->clock >= 140500
5288                            && adjusted_mode->clock <= 200000) {
5289                         clock.p1 = 1;
5290                         clock.p2 = 10;
5291                         clock.n = 6;
5292                         clock.m1 = 12;
5293                         clock.m2 = 8;
5294                 }
5295         }
5296
5297         /* FDI link */
5298         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5299         lane = 0;
5300         /* CPU eDP doesn't require FDI link, so just set DP M/N
5301            according to current link config */
5302         if (has_edp_encoder &&
5303             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5304                 target_clock = mode->clock;
5305                 intel_edp_link_config(has_edp_encoder,
5306                                       &lane, &link_bw);
5307         } else {
5308                 /* [e]DP over FDI requires target mode clock
5309                    instead of link clock */
5310                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5311                         target_clock = mode->clock;
5312                 else
5313                         target_clock = adjusted_mode->clock;
5314
5315                 /* FDI is a binary signal running at ~2.7GHz, encoding
5316                  * each output octet as 10 bits. The actual frequency
5317                  * is stored as a divider into a 100MHz clock, and the
5318                  * mode pixel clock is stored in units of 1KHz.
5319                  * Hence the bw of each lane in terms of the mode signal
5320                  * is:
5321                  */
5322                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5323         }
5324
5325         /* determine panel color depth */
5326         temp = I915_READ(PIPECONF(pipe));
5327         temp &= ~PIPE_BPC_MASK;
5328         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
5329         switch (pipe_bpp) {
5330         case 18:
5331                 temp |= PIPE_6BPC;
5332                 break;
5333         case 24:
5334                 temp |= PIPE_8BPC;
5335                 break;
5336         case 30:
5337                 temp |= PIPE_10BPC;
5338                 break;
5339         case 36:
5340                 temp |= PIPE_12BPC;
5341                 break;
5342         default:
5343                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5344                         pipe_bpp);
5345                 temp |= PIPE_8BPC;
5346                 pipe_bpp = 24;
5347                 break;
5348         }
5349
5350         intel_crtc->bpp = pipe_bpp;
5351         I915_WRITE(PIPECONF(pipe), temp);
5352
5353         if (!lane) {
5354                 /*
5355                  * Account for spread spectrum to avoid
5356                  * oversubscribing the link. Max center spread
5357                  * is 2.5%; use 5% for safety's sake.
5358                  */
5359                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5360                 lane = bps / (link_bw * 8) + 1;
5361         }
5362
5363         intel_crtc->fdi_lanes = lane;
5364
5365         if (pixel_multiplier > 1)
5366                 link_bw *= pixel_multiplier;
5367         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5368                              &m_n);
5369
5370         ironlake_update_pch_refclk(dev);
5371
5372         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5373         if (has_reduced_clock)
5374                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5375                         reduced_clock.m2;
5376
5377         /* Enable autotuning of the PLL clock (if permissible) */
5378         factor = 21;
5379         if (is_lvds) {
5380                 if ((intel_panel_use_ssc(dev_priv) &&
5381                      dev_priv->lvds_ssc_freq == 100) ||
5382                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5383                         factor = 25;
5384         } else if (is_sdvo && is_tv)
5385                 factor = 20;
5386
5387         if (clock.m < factor * clock.n)
5388                 fp |= FP_CB_TUNE;
5389
5390         dpll = 0;
5391
5392         if (is_lvds)
5393                 dpll |= DPLLB_MODE_LVDS;
5394         else
5395                 dpll |= DPLLB_MODE_DAC_SERIAL;
5396         if (is_sdvo) {
5397                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5398                 if (pixel_multiplier > 1) {
5399                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5400                 }
5401                 dpll |= DPLL_DVO_HIGH_SPEED;
5402         }
5403         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5404                 dpll |= DPLL_DVO_HIGH_SPEED;
5405
5406         /* compute bitmask from p1 value */
5407         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5408         /* also FPA1 */
5409         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5410
5411         switch (clock.p2) {
5412         case 5:
5413                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5414                 break;
5415         case 7:
5416                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5417                 break;
5418         case 10:
5419                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5420                 break;
5421         case 14:
5422                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5423                 break;
5424         }
5425
5426         if (is_sdvo && is_tv)
5427                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5428         else if (is_tv)
5429                 /* XXX: just matching BIOS for now */
5430                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5431                 dpll |= 3;
5432         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5433                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5434         else
5435                 dpll |= PLL_REF_INPUT_DREFCLK;
5436
5437         /* setup pipeconf */
5438         pipeconf = I915_READ(PIPECONF(pipe));
5439
5440         /* Set up the display plane register */
5441         dspcntr = DISPPLANE_GAMMA_ENABLE;
5442
5443         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5444         drm_mode_debug_printmodeline(mode);
5445
5446         /* PCH eDP needs FDI, but CPU eDP does not */
5447         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5448                 I915_WRITE(PCH_FP0(pipe), fp);
5449                 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5450
5451                 POSTING_READ(PCH_DPLL(pipe));
5452                 udelay(150);
5453         }
5454
5455         /* enable transcoder DPLL */
5456         if (HAS_PCH_CPT(dev)) {
5457                 temp = I915_READ(PCH_DPLL_SEL);
5458                 switch (pipe) {
5459                 case 0:
5460                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
5461                         break;
5462                 case 1:
5463                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
5464                         break;
5465                 case 2:
5466                         /* FIXME: manage transcoder PLLs? */
5467                         temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5468                         break;
5469                 default:
5470                         BUG();
5471                 }
5472                 I915_WRITE(PCH_DPLL_SEL, temp);
5473
5474                 POSTING_READ(PCH_DPLL_SEL);
5475                 udelay(150);
5476         }
5477
5478         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5479          * This is an exception to the general rule that mode_set doesn't turn
5480          * things on.
5481          */
5482         if (is_lvds) {
5483                 temp = I915_READ(PCH_LVDS);
5484                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5485                 if (pipe == 1) {
5486                         if (HAS_PCH_CPT(dev))
5487                                 temp |= PORT_TRANS_B_SEL_CPT;
5488                         else
5489                                 temp |= LVDS_PIPEB_SELECT;
5490                 } else {
5491                         if (HAS_PCH_CPT(dev))
5492                                 temp &= ~PORT_TRANS_SEL_MASK;
5493                         else
5494                                 temp &= ~LVDS_PIPEB_SELECT;
5495                 }
5496                 /* set the corresponsding LVDS_BORDER bit */
5497                 temp |= dev_priv->lvds_border_bits;
5498                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5499                  * set the DPLLs for dual-channel mode or not.
5500                  */
5501                 if (clock.p2 == 7)
5502                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5503                 else
5504                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5505
5506                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5507                  * appropriately here, but we need to look more thoroughly into how
5508                  * panels behave in the two modes.
5509                  */
5510                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5511                         lvds_sync |= LVDS_HSYNC_POLARITY;
5512                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5513                         lvds_sync |= LVDS_VSYNC_POLARITY;
5514                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5515                     != lvds_sync) {
5516                         char flags[2] = "-+";
5517                         DRM_INFO("Changing LVDS panel from "
5518                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5519                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5520                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5521                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5522                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5523                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5524                         temp |= lvds_sync;
5525                 }
5526                 I915_WRITE(PCH_LVDS, temp);
5527         }
5528
5529         pipeconf &= ~PIPECONF_DITHER_EN;
5530         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5531         if ((is_lvds && dev_priv->lvds_dither) || dither) {
5532                 pipeconf |= PIPECONF_DITHER_EN;
5533                 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
5534         }
5535         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5536                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5537         } else {
5538                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5539                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5540                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5541                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5542                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5543         }
5544
5545         if (!has_edp_encoder ||
5546             intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5547                 I915_WRITE(PCH_DPLL(pipe), dpll);
5548
5549                 /* Wait for the clocks to stabilize. */
5550                 POSTING_READ(PCH_DPLL(pipe));
5551                 udelay(150);
5552
5553                 /* The pixel multiplier can only be updated once the
5554                  * DPLL is enabled and the clocks are stable.
5555                  *
5556                  * So write it again.
5557                  */
5558                 I915_WRITE(PCH_DPLL(pipe), dpll);
5559         }
5560
5561         intel_crtc->lowfreq_avail = false;
5562         if (is_lvds && has_reduced_clock && i915_powersave) {
5563                 I915_WRITE(PCH_FP1(pipe), fp2);
5564                 intel_crtc->lowfreq_avail = true;
5565                 if (HAS_PIPE_CXSR(dev)) {
5566                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5567                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5568                 }
5569         } else {
5570                 I915_WRITE(PCH_FP1(pipe), fp);
5571                 if (HAS_PIPE_CXSR(dev)) {
5572                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5573                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5574                 }
5575         }
5576
5577         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5578                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5579                 /* the chip adds 2 halflines automatically */
5580                 adjusted_mode->crtc_vdisplay -= 1;
5581                 adjusted_mode->crtc_vtotal -= 1;
5582                 adjusted_mode->crtc_vblank_start -= 1;
5583                 adjusted_mode->crtc_vblank_end -= 1;
5584                 adjusted_mode->crtc_vsync_end -= 1;
5585                 adjusted_mode->crtc_vsync_start -= 1;
5586         } else
5587                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5588
5589         I915_WRITE(HTOTAL(pipe),
5590                    (adjusted_mode->crtc_hdisplay - 1) |
5591                    ((adjusted_mode->crtc_htotal - 1) << 16));
5592         I915_WRITE(HBLANK(pipe),
5593                    (adjusted_mode->crtc_hblank_start - 1) |
5594                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5595         I915_WRITE(HSYNC(pipe),
5596                    (adjusted_mode->crtc_hsync_start - 1) |
5597                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5598
5599         I915_WRITE(VTOTAL(pipe),
5600                    (adjusted_mode->crtc_vdisplay - 1) |
5601                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5602         I915_WRITE(VBLANK(pipe),
5603                    (adjusted_mode->crtc_vblank_start - 1) |
5604                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5605         I915_WRITE(VSYNC(pipe),
5606                    (adjusted_mode->crtc_vsync_start - 1) |
5607                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5608
5609         /* pipesrc controls the size that is scaled from, which should
5610          * always be the user's requested size.
5611          */
5612         I915_WRITE(PIPESRC(pipe),
5613                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5614
5615         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5616         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5617         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5618         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5619
5620         if (has_edp_encoder &&
5621             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5622                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5623         }
5624
5625         I915_WRITE(PIPECONF(pipe), pipeconf);
5626         POSTING_READ(PIPECONF(pipe));
5627
5628         intel_wait_for_vblank(dev, pipe);
5629
5630         if (IS_GEN5(dev)) {
5631                 /* enable address swizzle for tiling buffer */
5632                 temp = I915_READ(DISP_ARB_CTL);
5633                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5634         }
5635
5636         I915_WRITE(DSPCNTR(plane), dspcntr);
5637         POSTING_READ(DSPCNTR(plane));
5638
5639         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5640
5641         intel_update_watermarks(dev);
5642
5643         return ret;
5644 }
5645
5646 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5647                                struct drm_display_mode *mode,
5648                                struct drm_display_mode *adjusted_mode,
5649                                int x, int y,
5650                                struct drm_framebuffer *old_fb)
5651 {
5652         struct drm_device *dev = crtc->dev;
5653         struct drm_i915_private *dev_priv = dev->dev_private;
5654         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5655         int pipe = intel_crtc->pipe;
5656         int ret;
5657
5658         drm_vblank_pre_modeset(dev, pipe);
5659
5660         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5661                                               x, y, old_fb);
5662
5663         drm_vblank_post_modeset(dev, pipe);
5664
5665         intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5666
5667         return ret;
5668 }
5669
5670 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5671 void intel_crtc_load_lut(struct drm_crtc *crtc)
5672 {
5673         struct drm_device *dev = crtc->dev;
5674         struct drm_i915_private *dev_priv = dev->dev_private;
5675         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5676         int palreg = PALETTE(intel_crtc->pipe);
5677         int i;
5678
5679         /* The clocks have to be on to load the palette. */
5680         if (!crtc->enabled)
5681                 return;
5682
5683         /* use legacy palette for Ironlake */
5684         if (HAS_PCH_SPLIT(dev))
5685                 palreg = LGC_PALETTE(intel_crtc->pipe);
5686
5687         for (i = 0; i < 256; i++) {
5688                 I915_WRITE(palreg + 4 * i,
5689                            (intel_crtc->lut_r[i] << 16) |
5690                            (intel_crtc->lut_g[i] << 8) |
5691                            intel_crtc->lut_b[i]);
5692         }
5693 }
5694
5695 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5696 {
5697         struct drm_device *dev = crtc->dev;
5698         struct drm_i915_private *dev_priv = dev->dev_private;
5699         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5700         bool visible = base != 0;
5701         u32 cntl;
5702
5703         if (intel_crtc->cursor_visible == visible)
5704                 return;
5705
5706         cntl = I915_READ(_CURACNTR);
5707         if (visible) {
5708                 /* On these chipsets we can only modify the base whilst
5709                  * the cursor is disabled.
5710                  */
5711                 I915_WRITE(_CURABASE, base);
5712
5713                 cntl &= ~(CURSOR_FORMAT_MASK);
5714                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5715                 cntl |= CURSOR_ENABLE |
5716                         CURSOR_GAMMA_ENABLE |
5717                         CURSOR_FORMAT_ARGB;
5718         } else
5719                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5720         I915_WRITE(_CURACNTR, cntl);
5721
5722         intel_crtc->cursor_visible = visible;
5723 }
5724
5725 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5726 {
5727         struct drm_device *dev = crtc->dev;
5728         struct drm_i915_private *dev_priv = dev->dev_private;
5729         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5730         int pipe = intel_crtc->pipe;
5731         bool visible = base != 0;
5732
5733         if (intel_crtc->cursor_visible != visible) {
5734                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5735                 if (base) {
5736                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5737                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5738                         cntl |= pipe << 28; /* Connect to correct pipe */
5739                 } else {
5740                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5741                         cntl |= CURSOR_MODE_DISABLE;
5742                 }
5743                 I915_WRITE(CURCNTR(pipe), cntl);
5744
5745                 intel_crtc->cursor_visible = visible;
5746         }
5747         /* and commit changes on next vblank */
5748         I915_WRITE(CURBASE(pipe), base);
5749 }
5750
5751 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5752 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5753                                      bool on)
5754 {
5755         struct drm_device *dev = crtc->dev;
5756         struct drm_i915_private *dev_priv = dev->dev_private;
5757         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5758         int pipe = intel_crtc->pipe;
5759         int x = intel_crtc->cursor_x;
5760         int y = intel_crtc->cursor_y;
5761         u32 base, pos;
5762         bool visible;
5763
5764         pos = 0;
5765
5766         if (on && crtc->enabled && crtc->fb) {
5767                 base = intel_crtc->cursor_addr;
5768                 if (x > (int) crtc->fb->width)
5769                         base = 0;
5770
5771                 if (y > (int) crtc->fb->height)
5772                         base = 0;
5773         } else
5774                 base = 0;
5775
5776         if (x < 0) {
5777                 if (x + intel_crtc->cursor_width < 0)
5778                         base = 0;
5779
5780                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5781                 x = -x;
5782         }
5783         pos |= x << CURSOR_X_SHIFT;
5784
5785         if (y < 0) {
5786                 if (y + intel_crtc->cursor_height < 0)
5787                         base = 0;
5788
5789                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5790                 y = -y;
5791         }
5792         pos |= y << CURSOR_Y_SHIFT;
5793
5794         visible = base != 0;
5795         if (!visible && !intel_crtc->cursor_visible)
5796                 return;
5797
5798         I915_WRITE(CURPOS(pipe), pos);
5799         if (IS_845G(dev) || IS_I865G(dev))
5800                 i845_update_cursor(crtc, base);
5801         else
5802                 i9xx_update_cursor(crtc, base);
5803
5804         if (visible)
5805                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5806 }
5807
5808 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5809                                  struct drm_file *file,
5810                                  uint32_t handle,
5811                                  uint32_t width, uint32_t height)
5812 {
5813         struct drm_device *dev = crtc->dev;
5814         struct drm_i915_private *dev_priv = dev->dev_private;
5815         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5816         struct drm_i915_gem_object *obj;
5817         uint32_t addr;
5818         int ret;
5819
5820         DRM_DEBUG_KMS("\n");
5821
5822         /* if we want to turn off the cursor ignore width and height */
5823         if (!handle) {
5824                 DRM_DEBUG_KMS("cursor off\n");
5825                 addr = 0;
5826                 obj = NULL;
5827                 mutex_lock(&dev->struct_mutex);
5828                 goto finish;
5829         }
5830
5831         /* Currently we only support 64x64 cursors */
5832         if (width != 64 || height != 64) {
5833                 DRM_ERROR("we currently only support 64x64 cursors\n");
5834                 return -EINVAL;
5835         }
5836
5837         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5838         if (&obj->base == NULL)
5839                 return -ENOENT;
5840
5841         if (obj->base.size < width * height * 4) {
5842                 DRM_ERROR("buffer is to small\n");
5843                 ret = -ENOMEM;
5844                 goto fail;
5845         }
5846
5847         /* we only need to pin inside GTT if cursor is non-phy */
5848         mutex_lock(&dev->struct_mutex);
5849         if (!dev_priv->info->cursor_needs_physical) {
5850                 if (obj->tiling_mode) {
5851                         DRM_ERROR("cursor cannot be tiled\n");
5852                         ret = -EINVAL;
5853                         goto fail_locked;
5854                 }
5855
5856                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5857                 if (ret) {
5858                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5859                         goto fail_locked;
5860                 }
5861
5862                 ret = i915_gem_object_put_fence(obj);
5863                 if (ret) {
5864                         DRM_ERROR("failed to release fence for cursor");
5865                         goto fail_unpin;
5866                 }
5867
5868                 addr = obj->gtt_offset;
5869         } else {
5870                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5871                 ret = i915_gem_attach_phys_object(dev, obj,
5872                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5873                                                   align);
5874                 if (ret) {
5875                         DRM_ERROR("failed to attach phys object\n");
5876                         goto fail_locked;
5877                 }
5878                 addr = obj->phys_obj->handle->busaddr;
5879         }
5880
5881         if (IS_GEN2(dev))
5882                 I915_WRITE(CURSIZE, (height << 12) | width);
5883
5884  finish:
5885         if (intel_crtc->cursor_bo) {
5886                 if (dev_priv->info->cursor_needs_physical) {
5887                         if (intel_crtc->cursor_bo != obj)
5888                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5889                 } else
5890                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5891                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5892         }
5893
5894         mutex_unlock(&dev->struct_mutex);
5895
5896         intel_crtc->cursor_addr = addr;
5897         intel_crtc->cursor_bo = obj;
5898         intel_crtc->cursor_width = width;
5899         intel_crtc->cursor_height = height;
5900
5901         intel_crtc_update_cursor(crtc, true);
5902
5903         return 0;
5904 fail_unpin:
5905         i915_gem_object_unpin(obj);
5906 fail_locked:
5907         mutex_unlock(&dev->struct_mutex);
5908 fail:
5909         drm_gem_object_unreference_unlocked(&obj->base);
5910         return ret;
5911 }
5912
5913 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5914 {
5915         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5916
5917         intel_crtc->cursor_x = x;
5918         intel_crtc->cursor_y = y;
5919
5920         intel_crtc_update_cursor(crtc, true);
5921
5922         return 0;
5923 }
5924
5925 /** Sets the color ramps on behalf of RandR */
5926 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5927                                  u16 blue, int regno)
5928 {
5929         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5930
5931         intel_crtc->lut_r[regno] = red >> 8;
5932         intel_crtc->lut_g[regno] = green >> 8;
5933         intel_crtc->lut_b[regno] = blue >> 8;
5934 }
5935
5936 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5937                              u16 *blue, int regno)
5938 {
5939         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5940
5941         *red = intel_crtc->lut_r[regno] << 8;
5942         *green = intel_crtc->lut_g[regno] << 8;
5943         *blue = intel_crtc->lut_b[regno] << 8;
5944 }
5945
5946 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5947                                  u16 *blue, uint32_t start, uint32_t size)
5948 {
5949         int end = (start + size > 256) ? 256 : start + size, i;
5950         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5951
5952         for (i = start; i < end; i++) {
5953                 intel_crtc->lut_r[i] = red[i] >> 8;
5954                 intel_crtc->lut_g[i] = green[i] >> 8;
5955                 intel_crtc->lut_b[i] = blue[i] >> 8;
5956         }
5957
5958         intel_crtc_load_lut(crtc);
5959 }
5960
5961 /**
5962  * Get a pipe with a simple mode set on it for doing load-based monitor
5963  * detection.
5964  *
5965  * It will be up to the load-detect code to adjust the pipe as appropriate for
5966  * its requirements.  The pipe will be connected to no other encoders.
5967  *
5968  * Currently this code will only succeed if there is a pipe with no encoders
5969  * configured for it.  In the future, it could choose to temporarily disable
5970  * some outputs to free up a pipe for its use.
5971  *
5972  * \return crtc, or NULL if no pipes are available.
5973  */
5974
5975 /* VESA 640x480x72Hz mode to set on the pipe */
5976 static struct drm_display_mode load_detect_mode = {
5977         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5978                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5979 };
5980
5981 static struct drm_framebuffer *
5982 intel_framebuffer_create(struct drm_device *dev,
5983                          struct drm_mode_fb_cmd *mode_cmd,
5984                          struct drm_i915_gem_object *obj)
5985 {
5986         struct intel_framebuffer *intel_fb;
5987         int ret;
5988
5989         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5990         if (!intel_fb) {
5991                 drm_gem_object_unreference_unlocked(&obj->base);
5992                 return ERR_PTR(-ENOMEM);
5993         }
5994
5995         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5996         if (ret) {
5997                 drm_gem_object_unreference_unlocked(&obj->base);
5998                 kfree(intel_fb);
5999                 return ERR_PTR(ret);
6000         }
6001
6002         return &intel_fb->base;
6003 }
6004
6005 static u32