Merge branch 'drm-core-next' of git://people.freedesktop.org/~airlied/linux
[linux-2.6.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *      Eric Anholt <eric@anholt.net>
25  */
26
27 #include <linux/cpufreq.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include "drmP.h"
36 #include "intel_drv.h"
37 #include "i915_drm.h"
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
43
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_update_watermarks(struct drm_device *dev);
48 static void intel_increase_pllclock(struct drm_crtc *crtc);
49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
50
51 typedef struct {
52         /* given values */
53         int n;
54         int m1, m2;
55         int p1, p2;
56         /* derived values */
57         int     dot;
58         int     vco;
59         int     m;
60         int     p;
61 } intel_clock_t;
62
63 typedef struct {
64         int     min, max;
65 } intel_range_t;
66
67 typedef struct {
68         int     dot_limit;
69         int     p2_slow, p2_fast;
70 } intel_p2_t;
71
72 #define INTEL_P2_NUM                  2
73 typedef struct intel_limit intel_limit_t;
74 struct intel_limit {
75         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
76         intel_p2_t          p2;
77         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
78                         int, int, intel_clock_t *);
79 };
80
81 /* FDI */
82 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
83
84 static bool
85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
86                     int target, int refclk, intel_clock_t *best_clock);
87 static bool
88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89                         int target, int refclk, intel_clock_t *best_clock);
90
91 static bool
92 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
93                       int target, int refclk, intel_clock_t *best_clock);
94 static bool
95 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
96                            int target, int refclk, intel_clock_t *best_clock);
97
98 static inline u32 /* units of 100MHz */
99 intel_fdi_link_freq(struct drm_device *dev)
100 {
101         if (IS_GEN5(dev)) {
102                 struct drm_i915_private *dev_priv = dev->dev_private;
103                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
104         } else
105                 return 27;
106 }
107
108 static const intel_limit_t intel_limits_i8xx_dvo = {
109         .dot = { .min = 25000, .max = 350000 },
110         .vco = { .min = 930000, .max = 1400000 },
111         .n = { .min = 3, .max = 16 },
112         .m = { .min = 96, .max = 140 },
113         .m1 = { .min = 18, .max = 26 },
114         .m2 = { .min = 6, .max = 16 },
115         .p = { .min = 4, .max = 128 },
116         .p1 = { .min = 2, .max = 33 },
117         .p2 = { .dot_limit = 165000,
118                 .p2_slow = 4, .p2_fast = 2 },
119         .find_pll = intel_find_best_PLL,
120 };
121
122 static const intel_limit_t intel_limits_i8xx_lvds = {
123         .dot = { .min = 25000, .max = 350000 },
124         .vco = { .min = 930000, .max = 1400000 },
125         .n = { .min = 3, .max = 16 },
126         .m = { .min = 96, .max = 140 },
127         .m1 = { .min = 18, .max = 26 },
128         .m2 = { .min = 6, .max = 16 },
129         .p = { .min = 4, .max = 128 },
130         .p1 = { .min = 1, .max = 6 },
131         .p2 = { .dot_limit = 165000,
132                 .p2_slow = 14, .p2_fast = 7 },
133         .find_pll = intel_find_best_PLL,
134 };
135
136 static const intel_limit_t intel_limits_i9xx_sdvo = {
137         .dot = { .min = 20000, .max = 400000 },
138         .vco = { .min = 1400000, .max = 2800000 },
139         .n = { .min = 1, .max = 6 },
140         .m = { .min = 70, .max = 120 },
141         .m1 = { .min = 10, .max = 22 },
142         .m2 = { .min = 5, .max = 9 },
143         .p = { .min = 5, .max = 80 },
144         .p1 = { .min = 1, .max = 8 },
145         .p2 = { .dot_limit = 200000,
146                 .p2_slow = 10, .p2_fast = 5 },
147         .find_pll = intel_find_best_PLL,
148 };
149
150 static const intel_limit_t intel_limits_i9xx_lvds = {
151         .dot = { .min = 20000, .max = 400000 },
152         .vco = { .min = 1400000, .max = 2800000 },
153         .n = { .min = 1, .max = 6 },
154         .m = { .min = 70, .max = 120 },
155         .m1 = { .min = 10, .max = 22 },
156         .m2 = { .min = 5, .max = 9 },
157         .p = { .min = 7, .max = 98 },
158         .p1 = { .min = 1, .max = 8 },
159         .p2 = { .dot_limit = 112000,
160                 .p2_slow = 14, .p2_fast = 7 },
161         .find_pll = intel_find_best_PLL,
162 };
163
164
165 static const intel_limit_t intel_limits_g4x_sdvo = {
166         .dot = { .min = 25000, .max = 270000 },
167         .vco = { .min = 1750000, .max = 3500000},
168         .n = { .min = 1, .max = 4 },
169         .m = { .min = 104, .max = 138 },
170         .m1 = { .min = 17, .max = 23 },
171         .m2 = { .min = 5, .max = 11 },
172         .p = { .min = 10, .max = 30 },
173         .p1 = { .min = 1, .max = 3},
174         .p2 = { .dot_limit = 270000,
175                 .p2_slow = 10,
176                 .p2_fast = 10
177         },
178         .find_pll = intel_g4x_find_best_PLL,
179 };
180
181 static const intel_limit_t intel_limits_g4x_hdmi = {
182         .dot = { .min = 22000, .max = 400000 },
183         .vco = { .min = 1750000, .max = 3500000},
184         .n = { .min = 1, .max = 4 },
185         .m = { .min = 104, .max = 138 },
186         .m1 = { .min = 16, .max = 23 },
187         .m2 = { .min = 5, .max = 11 },
188         .p = { .min = 5, .max = 80 },
189         .p1 = { .min = 1, .max = 8},
190         .p2 = { .dot_limit = 165000,
191                 .p2_slow = 10, .p2_fast = 5 },
192         .find_pll = intel_g4x_find_best_PLL,
193 };
194
195 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
196         .dot = { .min = 20000, .max = 115000 },
197         .vco = { .min = 1750000, .max = 3500000 },
198         .n = { .min = 1, .max = 3 },
199         .m = { .min = 104, .max = 138 },
200         .m1 = { .min = 17, .max = 23 },
201         .m2 = { .min = 5, .max = 11 },
202         .p = { .min = 28, .max = 112 },
203         .p1 = { .min = 2, .max = 8 },
204         .p2 = { .dot_limit = 0,
205                 .p2_slow = 14, .p2_fast = 14
206         },
207         .find_pll = intel_g4x_find_best_PLL,
208 };
209
210 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
211         .dot = { .min = 80000, .max = 224000 },
212         .vco = { .min = 1750000, .max = 3500000 },
213         .n = { .min = 1, .max = 3 },
214         .m = { .min = 104, .max = 138 },
215         .m1 = { .min = 17, .max = 23 },
216         .m2 = { .min = 5, .max = 11 },
217         .p = { .min = 14, .max = 42 },
218         .p1 = { .min = 2, .max = 6 },
219         .p2 = { .dot_limit = 0,
220                 .p2_slow = 7, .p2_fast = 7
221         },
222         .find_pll = intel_g4x_find_best_PLL,
223 };
224
225 static const intel_limit_t intel_limits_g4x_display_port = {
226         .dot = { .min = 161670, .max = 227000 },
227         .vco = { .min = 1750000, .max = 3500000},
228         .n = { .min = 1, .max = 2 },
229         .m = { .min = 97, .max = 108 },
230         .m1 = { .min = 0x10, .max = 0x12 },
231         .m2 = { .min = 0x05, .max = 0x06 },
232         .p = { .min = 10, .max = 20 },
233         .p1 = { .min = 1, .max = 2},
234         .p2 = { .dot_limit = 0,
235                 .p2_slow = 10, .p2_fast = 10 },
236         .find_pll = intel_find_pll_g4x_dp,
237 };
238
239 static const intel_limit_t intel_limits_pineview_sdvo = {
240         .dot = { .min = 20000, .max = 400000},
241         .vco = { .min = 1700000, .max = 3500000 },
242         /* Pineview's Ncounter is a ring counter */
243         .n = { .min = 3, .max = 6 },
244         .m = { .min = 2, .max = 256 },
245         /* Pineview only has one combined m divider, which we treat as m2. */
246         .m1 = { .min = 0, .max = 0 },
247         .m2 = { .min = 0, .max = 254 },
248         .p = { .min = 5, .max = 80 },
249         .p1 = { .min = 1, .max = 8 },
250         .p2 = { .dot_limit = 200000,
251                 .p2_slow = 10, .p2_fast = 5 },
252         .find_pll = intel_find_best_PLL,
253 };
254
255 static const intel_limit_t intel_limits_pineview_lvds = {
256         .dot = { .min = 20000, .max = 400000 },
257         .vco = { .min = 1700000, .max = 3500000 },
258         .n = { .min = 3, .max = 6 },
259         .m = { .min = 2, .max = 256 },
260         .m1 = { .min = 0, .max = 0 },
261         .m2 = { .min = 0, .max = 254 },
262         .p = { .min = 7, .max = 112 },
263         .p1 = { .min = 1, .max = 8 },
264         .p2 = { .dot_limit = 112000,
265                 .p2_slow = 14, .p2_fast = 14 },
266         .find_pll = intel_find_best_PLL,
267 };
268
269 /* Ironlake / Sandybridge
270  *
271  * We calculate clock using (register_value + 2) for N/M1/M2, so here
272  * the range value for them is (actual_value - 2).
273  */
274 static const intel_limit_t intel_limits_ironlake_dac = {
275         .dot = { .min = 25000, .max = 350000 },
276         .vco = { .min = 1760000, .max = 3510000 },
277         .n = { .min = 1, .max = 5 },
278         .m = { .min = 79, .max = 127 },
279         .m1 = { .min = 12, .max = 22 },
280         .m2 = { .min = 5, .max = 9 },
281         .p = { .min = 5, .max = 80 },
282         .p1 = { .min = 1, .max = 8 },
283         .p2 = { .dot_limit = 225000,
284                 .p2_slow = 10, .p2_fast = 5 },
285         .find_pll = intel_g4x_find_best_PLL,
286 };
287
288 static const intel_limit_t intel_limits_ironlake_single_lvds = {
289         .dot = { .min = 25000, .max = 350000 },
290         .vco = { .min = 1760000, .max = 3510000 },
291         .n = { .min = 1, .max = 3 },
292         .m = { .min = 79, .max = 118 },
293         .m1 = { .min = 12, .max = 22 },
294         .m2 = { .min = 5, .max = 9 },
295         .p = { .min = 28, .max = 112 },
296         .p1 = { .min = 2, .max = 8 },
297         .p2 = { .dot_limit = 225000,
298                 .p2_slow = 14, .p2_fast = 14 },
299         .find_pll = intel_g4x_find_best_PLL,
300 };
301
302 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
303         .dot = { .min = 25000, .max = 350000 },
304         .vco = { .min = 1760000, .max = 3510000 },
305         .n = { .min = 1, .max = 3 },
306         .m = { .min = 79, .max = 127 },
307         .m1 = { .min = 12, .max = 22 },
308         .m2 = { .min = 5, .max = 9 },
309         .p = { .min = 14, .max = 56 },
310         .p1 = { .min = 2, .max = 8 },
311         .p2 = { .dot_limit = 225000,
312                 .p2_slow = 7, .p2_fast = 7 },
313         .find_pll = intel_g4x_find_best_PLL,
314 };
315
316 /* LVDS 100mhz refclk limits. */
317 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
318         .dot = { .min = 25000, .max = 350000 },
319         .vco = { .min = 1760000, .max = 3510000 },
320         .n = { .min = 1, .max = 2 },
321         .m = { .min = 79, .max = 126 },
322         .m1 = { .min = 12, .max = 22 },
323         .m2 = { .min = 5, .max = 9 },
324         .p = { .min = 28, .max = 112 },
325         .p1 = { .min = 2, .max = 8 },
326         .p2 = { .dot_limit = 225000,
327                 .p2_slow = 14, .p2_fast = 14 },
328         .find_pll = intel_g4x_find_best_PLL,
329 };
330
331 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
332         .dot = { .min = 25000, .max = 350000 },
333         .vco = { .min = 1760000, .max = 3510000 },
334         .n = { .min = 1, .max = 3 },
335         .m = { .min = 79, .max = 126 },
336         .m1 = { .min = 12, .max = 22 },
337         .m2 = { .min = 5, .max = 9 },
338         .p = { .min = 14, .max = 42 },
339         .p1 = { .min = 2, .max = 6 },
340         .p2 = { .dot_limit = 225000,
341                 .p2_slow = 7, .p2_fast = 7 },
342         .find_pll = intel_g4x_find_best_PLL,
343 };
344
345 static const intel_limit_t intel_limits_ironlake_display_port = {
346         .dot = { .min = 25000, .max = 350000 },
347         .vco = { .min = 1760000, .max = 3510000},
348         .n = { .min = 1, .max = 2 },
349         .m = { .min = 81, .max = 90 },
350         .m1 = { .min = 12, .max = 22 },
351         .m2 = { .min = 5, .max = 9 },
352         .p = { .min = 10, .max = 20 },
353         .p1 = { .min = 1, .max = 2},
354         .p2 = { .dot_limit = 0,
355                 .p2_slow = 10, .p2_fast = 10 },
356         .find_pll = intel_find_pll_ironlake_dp,
357 };
358
359 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
360                                                 int refclk)
361 {
362         struct drm_device *dev = crtc->dev;
363         struct drm_i915_private *dev_priv = dev->dev_private;
364         const intel_limit_t *limit;
365
366         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
367                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
368                     LVDS_CLKB_POWER_UP) {
369                         /* LVDS dual channel */
370                         if (refclk == 100000)
371                                 limit = &intel_limits_ironlake_dual_lvds_100m;
372                         else
373                                 limit = &intel_limits_ironlake_dual_lvds;
374                 } else {
375                         if (refclk == 100000)
376                                 limit = &intel_limits_ironlake_single_lvds_100m;
377                         else
378                                 limit = &intel_limits_ironlake_single_lvds;
379                 }
380         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
381                         HAS_eDP)
382                 limit = &intel_limits_ironlake_display_port;
383         else
384                 limit = &intel_limits_ironlake_dac;
385
386         return limit;
387 }
388
389 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
390 {
391         struct drm_device *dev = crtc->dev;
392         struct drm_i915_private *dev_priv = dev->dev_private;
393         const intel_limit_t *limit;
394
395         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
396                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
397                     LVDS_CLKB_POWER_UP)
398                         /* LVDS with dual channel */
399                         limit = &intel_limits_g4x_dual_channel_lvds;
400                 else
401                         /* LVDS with dual channel */
402                         limit = &intel_limits_g4x_single_channel_lvds;
403         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
404                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
405                 limit = &intel_limits_g4x_hdmi;
406         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
407                 limit = &intel_limits_g4x_sdvo;
408         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
409                 limit = &intel_limits_g4x_display_port;
410         } else /* The option is for other outputs */
411                 limit = &intel_limits_i9xx_sdvo;
412
413         return limit;
414 }
415
416 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
417 {
418         struct drm_device *dev = crtc->dev;
419         const intel_limit_t *limit;
420
421         if (HAS_PCH_SPLIT(dev))
422                 limit = intel_ironlake_limit(crtc, refclk);
423         else if (IS_G4X(dev)) {
424                 limit = intel_g4x_limit(crtc);
425         } else if (IS_PINEVIEW(dev)) {
426                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
427                         limit = &intel_limits_pineview_lvds;
428                 else
429                         limit = &intel_limits_pineview_sdvo;
430         } else if (!IS_GEN2(dev)) {
431                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
432                         limit = &intel_limits_i9xx_lvds;
433                 else
434                         limit = &intel_limits_i9xx_sdvo;
435         } else {
436                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
437                         limit = &intel_limits_i8xx_lvds;
438                 else
439                         limit = &intel_limits_i8xx_dvo;
440         }
441         return limit;
442 }
443
444 /* m1 is reserved as 0 in Pineview, n is a ring counter */
445 static void pineview_clock(int refclk, intel_clock_t *clock)
446 {
447         clock->m = clock->m2 + 2;
448         clock->p = clock->p1 * clock->p2;
449         clock->vco = refclk * clock->m / clock->n;
450         clock->dot = clock->vco / clock->p;
451 }
452
453 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
454 {
455         if (IS_PINEVIEW(dev)) {
456                 pineview_clock(refclk, clock);
457                 return;
458         }
459         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
460         clock->p = clock->p1 * clock->p2;
461         clock->vco = refclk * clock->m / (clock->n + 2);
462         clock->dot = clock->vco / clock->p;
463 }
464
465 /**
466  * Returns whether any output on the specified pipe is of the specified type
467  */
468 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
469 {
470         struct drm_device *dev = crtc->dev;
471         struct drm_mode_config *mode_config = &dev->mode_config;
472         struct intel_encoder *encoder;
473
474         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
475                 if (encoder->base.crtc == crtc && encoder->type == type)
476                         return true;
477
478         return false;
479 }
480
481 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
482 /**
483  * Returns whether the given set of divisors are valid for a given refclk with
484  * the given connectors.
485  */
486
487 static bool intel_PLL_is_valid(struct drm_device *dev,
488                                const intel_limit_t *limit,
489                                const intel_clock_t *clock)
490 {
491         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
492                 INTELPllInvalid("p1 out of range\n");
493         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
494                 INTELPllInvalid("p out of range\n");
495         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
496                 INTELPllInvalid("m2 out of range\n");
497         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
498                 INTELPllInvalid("m1 out of range\n");
499         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
500                 INTELPllInvalid("m1 <= m2\n");
501         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
502                 INTELPllInvalid("m out of range\n");
503         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
504                 INTELPllInvalid("n out of range\n");
505         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
506                 INTELPllInvalid("vco out of range\n");
507         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
508          * connector, etc., rather than just a single range.
509          */
510         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
511                 INTELPllInvalid("dot out of range\n");
512
513         return true;
514 }
515
516 static bool
517 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
518                     int target, int refclk, intel_clock_t *best_clock)
519
520 {
521         struct drm_device *dev = crtc->dev;
522         struct drm_i915_private *dev_priv = dev->dev_private;
523         intel_clock_t clock;
524         int err = target;
525
526         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
527             (I915_READ(LVDS)) != 0) {
528                 /*
529                  * For LVDS, if the panel is on, just rely on its current
530                  * settings for dual-channel.  We haven't figured out how to
531                  * reliably set up different single/dual channel state, if we
532                  * even can.
533                  */
534                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
535                     LVDS_CLKB_POWER_UP)
536                         clock.p2 = limit->p2.p2_fast;
537                 else
538                         clock.p2 = limit->p2.p2_slow;
539         } else {
540                 if (target < limit->p2.dot_limit)
541                         clock.p2 = limit->p2.p2_slow;
542                 else
543                         clock.p2 = limit->p2.p2_fast;
544         }
545
546         memset(best_clock, 0, sizeof(*best_clock));
547
548         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
549              clock.m1++) {
550                 for (clock.m2 = limit->m2.min;
551                      clock.m2 <= limit->m2.max; clock.m2++) {
552                         /* m1 is always 0 in Pineview */
553                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
554                                 break;
555                         for (clock.n = limit->n.min;
556                              clock.n <= limit->n.max; clock.n++) {
557                                 for (clock.p1 = limit->p1.min;
558                                         clock.p1 <= limit->p1.max; clock.p1++) {
559                                         int this_err;
560
561                                         intel_clock(dev, refclk, &clock);
562                                         if (!intel_PLL_is_valid(dev, limit,
563                                                                 &clock))
564                                                 continue;
565
566                                         this_err = abs(clock.dot - target);
567                                         if (this_err < err) {
568                                                 *best_clock = clock;
569                                                 err = this_err;
570                                         }
571                                 }
572                         }
573                 }
574         }
575
576         return (err != target);
577 }
578
579 static bool
580 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
581                         int target, int refclk, intel_clock_t *best_clock)
582 {
583         struct drm_device *dev = crtc->dev;
584         struct drm_i915_private *dev_priv = dev->dev_private;
585         intel_clock_t clock;
586         int max_n;
587         bool found;
588         /* approximately equals target * 0.00585 */
589         int err_most = (target >> 8) + (target >> 9);
590         found = false;
591
592         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
593                 int lvds_reg;
594
595                 if (HAS_PCH_SPLIT(dev))
596                         lvds_reg = PCH_LVDS;
597                 else
598                         lvds_reg = LVDS;
599                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
600                     LVDS_CLKB_POWER_UP)
601                         clock.p2 = limit->p2.p2_fast;
602                 else
603                         clock.p2 = limit->p2.p2_slow;
604         } else {
605                 if (target < limit->p2.dot_limit)
606                         clock.p2 = limit->p2.p2_slow;
607                 else
608                         clock.p2 = limit->p2.p2_fast;
609         }
610
611         memset(best_clock, 0, sizeof(*best_clock));
612         max_n = limit->n.max;
613         /* based on hardware requirement, prefer smaller n to precision */
614         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
615                 /* based on hardware requirement, prefere larger m1,m2 */
616                 for (clock.m1 = limit->m1.max;
617                      clock.m1 >= limit->m1.min; clock.m1--) {
618                         for (clock.m2 = limit->m2.max;
619                              clock.m2 >= limit->m2.min; clock.m2--) {
620                                 for (clock.p1 = limit->p1.max;
621                                      clock.p1 >= limit->p1.min; clock.p1--) {
622                                         int this_err;
623
624                                         intel_clock(dev, refclk, &clock);
625                                         if (!intel_PLL_is_valid(dev, limit,
626                                                                 &clock))
627                                                 continue;
628
629                                         this_err = abs(clock.dot - target);
630                                         if (this_err < err_most) {
631                                                 *best_clock = clock;
632                                                 err_most = this_err;
633                                                 max_n = clock.n;
634                                                 found = true;
635                                         }
636                                 }
637                         }
638                 }
639         }
640         return found;
641 }
642
643 static bool
644 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
645                            int target, int refclk, intel_clock_t *best_clock)
646 {
647         struct drm_device *dev = crtc->dev;
648         intel_clock_t clock;
649
650         if (target < 200000) {
651                 clock.n = 1;
652                 clock.p1 = 2;
653                 clock.p2 = 10;
654                 clock.m1 = 12;
655                 clock.m2 = 9;
656         } else {
657                 clock.n = 2;
658                 clock.p1 = 1;
659                 clock.p2 = 10;
660                 clock.m1 = 14;
661                 clock.m2 = 8;
662         }
663         intel_clock(dev, refclk, &clock);
664         memcpy(best_clock, &clock, sizeof(intel_clock_t));
665         return true;
666 }
667
668 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
669 static bool
670 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
671                       int target, int refclk, intel_clock_t *best_clock)
672 {
673         intel_clock_t clock;
674         if (target < 200000) {
675                 clock.p1 = 2;
676                 clock.p2 = 10;
677                 clock.n = 2;
678                 clock.m1 = 23;
679                 clock.m2 = 8;
680         } else {
681                 clock.p1 = 1;
682                 clock.p2 = 10;
683                 clock.n = 1;
684                 clock.m1 = 14;
685                 clock.m2 = 2;
686         }
687         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
688         clock.p = (clock.p1 * clock.p2);
689         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
690         clock.vco = 0;
691         memcpy(best_clock, &clock, sizeof(intel_clock_t));
692         return true;
693 }
694
695 /**
696  * intel_wait_for_vblank - wait for vblank on a given pipe
697  * @dev: drm device
698  * @pipe: pipe to wait for
699  *
700  * Wait for vblank to occur on a given pipe.  Needed for various bits of
701  * mode setting code.
702  */
703 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
704 {
705         struct drm_i915_private *dev_priv = dev->dev_private;
706         int pipestat_reg = PIPESTAT(pipe);
707
708         /* Clear existing vblank status. Note this will clear any other
709          * sticky status fields as well.
710          *
711          * This races with i915_driver_irq_handler() with the result
712          * that either function could miss a vblank event.  Here it is not
713          * fatal, as we will either wait upon the next vblank interrupt or
714          * timeout.  Generally speaking intel_wait_for_vblank() is only
715          * called during modeset at which time the GPU should be idle and
716          * should *not* be performing page flips and thus not waiting on
717          * vblanks...
718          * Currently, the result of us stealing a vblank from the irq
719          * handler is that a single frame will be skipped during swapbuffers.
720          */
721         I915_WRITE(pipestat_reg,
722                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
723
724         /* Wait for vblank interrupt bit to set */
725         if (wait_for(I915_READ(pipestat_reg) &
726                      PIPE_VBLANK_INTERRUPT_STATUS,
727                      50))
728                 DRM_DEBUG_KMS("vblank wait timed out\n");
729 }
730
731 /*
732  * intel_wait_for_pipe_off - wait for pipe to turn off
733  * @dev: drm device
734  * @pipe: pipe to wait for
735  *
736  * After disabling a pipe, we can't wait for vblank in the usual way,
737  * spinning on the vblank interrupt status bit, since we won't actually
738  * see an interrupt when the pipe is disabled.
739  *
740  * On Gen4 and above:
741  *   wait for the pipe register state bit to turn off
742  *
743  * Otherwise:
744  *   wait for the display line value to settle (it usually
745  *   ends up stopping at the start of the next frame).
746  *
747  */
748 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
749 {
750         struct drm_i915_private *dev_priv = dev->dev_private;
751
752         if (INTEL_INFO(dev)->gen >= 4) {
753                 int reg = PIPECONF(pipe);
754
755                 /* Wait for the Pipe State to go off */
756                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
757                              100))
758                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
759         } else {
760                 u32 last_line;
761                 int reg = PIPEDSL(pipe);
762                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
763
764                 /* Wait for the display line to settle */
765                 do {
766                         last_line = I915_READ(reg) & DSL_LINEMASK;
767                         mdelay(5);
768                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
769                          time_after(timeout, jiffies));
770                 if (time_after(jiffies, timeout))
771                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
772         }
773 }
774
775 static const char *state_string(bool enabled)
776 {
777         return enabled ? "on" : "off";
778 }
779
780 /* Only for pre-ILK configs */
781 static void assert_pll(struct drm_i915_private *dev_priv,
782                        enum pipe pipe, bool state)
783 {
784         int reg;
785         u32 val;
786         bool cur_state;
787
788         reg = DPLL(pipe);
789         val = I915_READ(reg);
790         cur_state = !!(val & DPLL_VCO_ENABLE);
791         WARN(cur_state != state,
792              "PLL state assertion failure (expected %s, current %s)\n",
793              state_string(state), state_string(cur_state));
794 }
795 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
796 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
797
798 /* For ILK+ */
799 static void assert_pch_pll(struct drm_i915_private *dev_priv,
800                            enum pipe pipe, bool state)
801 {
802         int reg;
803         u32 val;
804         bool cur_state;
805
806         if (HAS_PCH_CPT(dev_priv->dev)) {
807                 u32 pch_dpll;
808
809                 pch_dpll = I915_READ(PCH_DPLL_SEL);
810
811                 /* Make sure the selected PLL is enabled to the transcoder */
812                 WARN(!((pch_dpll >> (4 * pipe)) & 8),
813                      "transcoder %d PLL not enabled\n", pipe);
814
815                 /* Convert the transcoder pipe number to a pll pipe number */
816                 pipe = (pch_dpll >> (4 * pipe)) & 1;
817         }
818
819         reg = PCH_DPLL(pipe);
820         val = I915_READ(reg);
821         cur_state = !!(val & DPLL_VCO_ENABLE);
822         WARN(cur_state != state,
823              "PCH PLL state assertion failure (expected %s, current %s)\n",
824              state_string(state), state_string(cur_state));
825 }
826 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
827 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
828
829 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
830                           enum pipe pipe, bool state)
831 {
832         int reg;
833         u32 val;
834         bool cur_state;
835
836         reg = FDI_TX_CTL(pipe);
837         val = I915_READ(reg);
838         cur_state = !!(val & FDI_TX_ENABLE);
839         WARN(cur_state != state,
840              "FDI TX state assertion failure (expected %s, current %s)\n",
841              state_string(state), state_string(cur_state));
842 }
843 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
844 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
845
846 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
847                           enum pipe pipe, bool state)
848 {
849         int reg;
850         u32 val;
851         bool cur_state;
852
853         reg = FDI_RX_CTL(pipe);
854         val = I915_READ(reg);
855         cur_state = !!(val & FDI_RX_ENABLE);
856         WARN(cur_state != state,
857              "FDI RX state assertion failure (expected %s, current %s)\n",
858              state_string(state), state_string(cur_state));
859 }
860 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
861 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
862
863 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
864                                       enum pipe pipe)
865 {
866         int reg;
867         u32 val;
868
869         /* ILK FDI PLL is always enabled */
870         if (dev_priv->info->gen == 5)
871                 return;
872
873         reg = FDI_TX_CTL(pipe);
874         val = I915_READ(reg);
875         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
876 }
877
878 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
879                                       enum pipe pipe)
880 {
881         int reg;
882         u32 val;
883
884         reg = FDI_RX_CTL(pipe);
885         val = I915_READ(reg);
886         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
887 }
888
889 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
890                                   enum pipe pipe)
891 {
892         int pp_reg, lvds_reg;
893         u32 val;
894         enum pipe panel_pipe = PIPE_A;
895         bool locked = true;
896
897         if (HAS_PCH_SPLIT(dev_priv->dev)) {
898                 pp_reg = PCH_PP_CONTROL;
899                 lvds_reg = PCH_LVDS;
900         } else {
901                 pp_reg = PP_CONTROL;
902                 lvds_reg = LVDS;
903         }
904
905         val = I915_READ(pp_reg);
906         if (!(val & PANEL_POWER_ON) ||
907             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
908                 locked = false;
909
910         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
911                 panel_pipe = PIPE_B;
912
913         WARN(panel_pipe == pipe && locked,
914              "panel assertion failure, pipe %c regs locked\n",
915              pipe_name(pipe));
916 }
917
918 void assert_pipe(struct drm_i915_private *dev_priv,
919                  enum pipe pipe, bool state)
920 {
921         int reg;
922         u32 val;
923         bool cur_state;
924
925         reg = PIPECONF(pipe);
926         val = I915_READ(reg);
927         cur_state = !!(val & PIPECONF_ENABLE);
928         WARN(cur_state != state,
929              "pipe %c assertion failure (expected %s, current %s)\n",
930              pipe_name(pipe), state_string(state), state_string(cur_state));
931 }
932
933 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
934                                  enum plane plane)
935 {
936         int reg;
937         u32 val;
938
939         reg = DSPCNTR(plane);
940         val = I915_READ(reg);
941         WARN(!(val & DISPLAY_PLANE_ENABLE),
942              "plane %c assertion failure, should be active but is disabled\n",
943              plane_name(plane));
944 }
945
946 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
947                                    enum pipe pipe)
948 {
949         int reg, i;
950         u32 val;
951         int cur_pipe;
952
953         /* Planes are fixed to pipes on ILK+ */
954         if (HAS_PCH_SPLIT(dev_priv->dev))
955                 return;
956
957         /* Need to check both planes against the pipe */
958         for (i = 0; i < 2; i++) {
959                 reg = DSPCNTR(i);
960                 val = I915_READ(reg);
961                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
962                         DISPPLANE_SEL_PIPE_SHIFT;
963                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
964                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
965                      plane_name(i), pipe_name(pipe));
966         }
967 }
968
969 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
970 {
971         u32 val;
972         bool enabled;
973
974         val = I915_READ(PCH_DREF_CONTROL);
975         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
976                             DREF_SUPERSPREAD_SOURCE_MASK));
977         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
978 }
979
980 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
981                                        enum pipe pipe)
982 {
983         int reg;
984         u32 val;
985         bool enabled;
986
987         reg = TRANSCONF(pipe);
988         val = I915_READ(reg);
989         enabled = !!(val & TRANS_ENABLE);
990         WARN(enabled,
991              "transcoder assertion failed, should be off on pipe %c but is still active\n",
992              pipe_name(pipe));
993 }
994
995 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
996                             enum pipe pipe, u32 port_sel, u32 val)
997 {
998         if ((val & DP_PORT_EN) == 0)
999                 return false;
1000
1001         if (HAS_PCH_CPT(dev_priv->dev)) {
1002                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1003                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1004                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1005                         return false;
1006         } else {
1007                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1008                         return false;
1009         }
1010         return true;
1011 }
1012
1013 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1014                               enum pipe pipe, u32 val)
1015 {
1016         if ((val & PORT_ENABLE) == 0)
1017                 return false;
1018
1019         if (HAS_PCH_CPT(dev_priv->dev)) {
1020                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1021                         return false;
1022         } else {
1023                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1024                         return false;
1025         }
1026         return true;
1027 }
1028
1029 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1030                               enum pipe pipe, u32 val)
1031 {
1032         if ((val & LVDS_PORT_EN) == 0)
1033                 return false;
1034
1035         if (HAS_PCH_CPT(dev_priv->dev)) {
1036                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1037                         return false;
1038         } else {
1039                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1040                         return false;
1041         }
1042         return true;
1043 }
1044
1045 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1046                               enum pipe pipe, u32 val)
1047 {
1048         if ((val & ADPA_DAC_ENABLE) == 0)
1049                 return false;
1050         if (HAS_PCH_CPT(dev_priv->dev)) {
1051                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1052                         return false;
1053         } else {
1054                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1055                         return false;
1056         }
1057         return true;
1058 }
1059
1060 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1061                                    enum pipe pipe, int reg, u32 port_sel)
1062 {
1063         u32 val = I915_READ(reg);
1064         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1065              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1066              reg, pipe_name(pipe));
1067 }
1068
1069 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1070                                      enum pipe pipe, int reg)
1071 {
1072         u32 val = I915_READ(reg);
1073         WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1074              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1075              reg, pipe_name(pipe));
1076 }
1077
1078 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1079                                       enum pipe pipe)
1080 {
1081         int reg;
1082         u32 val;
1083
1084         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1085         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1086         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1087
1088         reg = PCH_ADPA;
1089         val = I915_READ(reg);
1090         WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1091              "PCH VGA enabled on transcoder %c, should be disabled\n",
1092              pipe_name(pipe));
1093
1094         reg = PCH_LVDS;
1095         val = I915_READ(reg);
1096         WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1097              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1098              pipe_name(pipe));
1099
1100         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1101         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1102         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1103 }
1104
1105 /**
1106  * intel_enable_pll - enable a PLL
1107  * @dev_priv: i915 private structure
1108  * @pipe: pipe PLL to enable
1109  *
1110  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1111  * make sure the PLL reg is writable first though, since the panel write
1112  * protect mechanism may be enabled.
1113  *
1114  * Note!  This is for pre-ILK only.
1115  */
1116 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1117 {
1118         int reg;
1119         u32 val;
1120
1121         /* No really, not for ILK+ */
1122         BUG_ON(dev_priv->info->gen >= 5);
1123
1124         /* PLL is protected by panel, make sure we can write it */
1125         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1126                 assert_panel_unlocked(dev_priv, pipe);
1127
1128         reg = DPLL(pipe);
1129         val = I915_READ(reg);
1130         val |= DPLL_VCO_ENABLE;
1131
1132         /* We do this three times for luck */
1133         I915_WRITE(reg, val);
1134         POSTING_READ(reg);
1135         udelay(150); /* wait for warmup */
1136         I915_WRITE(reg, val);
1137         POSTING_READ(reg);
1138         udelay(150); /* wait for warmup */
1139         I915_WRITE(reg, val);
1140         POSTING_READ(reg);
1141         udelay(150); /* wait for warmup */
1142 }
1143
1144 /**
1145  * intel_disable_pll - disable a PLL
1146  * @dev_priv: i915 private structure
1147  * @pipe: pipe PLL to disable
1148  *
1149  * Disable the PLL for @pipe, making sure the pipe is off first.
1150  *
1151  * Note!  This is for pre-ILK only.
1152  */
1153 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1154 {
1155         int reg;
1156         u32 val;
1157
1158         /* Don't disable pipe A or pipe A PLLs if needed */
1159         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1160                 return;
1161
1162         /* Make sure the pipe isn't still relying on us */
1163         assert_pipe_disabled(dev_priv, pipe);
1164
1165         reg = DPLL(pipe);
1166         val = I915_READ(reg);
1167         val &= ~DPLL_VCO_ENABLE;
1168         I915_WRITE(reg, val);
1169         POSTING_READ(reg);
1170 }
1171
1172 /**
1173  * intel_enable_pch_pll - enable PCH PLL
1174  * @dev_priv: i915 private structure
1175  * @pipe: pipe PLL to enable
1176  *
1177  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1178  * drives the transcoder clock.
1179  */
1180 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1181                                  enum pipe pipe)
1182 {
1183         int reg;
1184         u32 val;
1185
1186         if (pipe > 1)
1187                 return;
1188
1189         /* PCH only available on ILK+ */
1190         BUG_ON(dev_priv->info->gen < 5);
1191
1192         /* PCH refclock must be enabled first */
1193         assert_pch_refclk_enabled(dev_priv);
1194
1195         reg = PCH_DPLL(pipe);
1196         val = I915_READ(reg);
1197         val |= DPLL_VCO_ENABLE;
1198         I915_WRITE(reg, val);
1199         POSTING_READ(reg);
1200         udelay(200);
1201 }
1202
1203 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1204                                   enum pipe pipe)
1205 {
1206         int reg;
1207         u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1208                 pll_sel = TRANSC_DPLL_ENABLE;
1209
1210         if (pipe > 1)
1211                 return;
1212
1213         /* PCH only available on ILK+ */
1214         BUG_ON(dev_priv->info->gen < 5);
1215
1216         /* Make sure transcoder isn't still depending on us */
1217         assert_transcoder_disabled(dev_priv, pipe);
1218
1219         if (pipe == 0)
1220                 pll_sel |= TRANSC_DPLLA_SEL;
1221         else if (pipe == 1)
1222                 pll_sel |= TRANSC_DPLLB_SEL;
1223
1224
1225         if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1226                 return;
1227
1228         reg = PCH_DPLL(pipe);
1229         val = I915_READ(reg);
1230         val &= ~DPLL_VCO_ENABLE;
1231         I915_WRITE(reg, val);
1232         POSTING_READ(reg);
1233         udelay(200);
1234 }
1235
1236 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1237                                     enum pipe pipe)
1238 {
1239         int reg;
1240         u32 val;
1241
1242         /* PCH only available on ILK+ */
1243         BUG_ON(dev_priv->info->gen < 5);
1244
1245         /* Make sure PCH DPLL is enabled */
1246         assert_pch_pll_enabled(dev_priv, pipe);
1247
1248         /* FDI must be feeding us bits for PCH ports */
1249         assert_fdi_tx_enabled(dev_priv, pipe);
1250         assert_fdi_rx_enabled(dev_priv, pipe);
1251
1252         reg = TRANSCONF(pipe);
1253         val = I915_READ(reg);
1254
1255         if (HAS_PCH_IBX(dev_priv->dev)) {
1256                 /*
1257                  * make the BPC in transcoder be consistent with
1258                  * that in pipeconf reg.
1259                  */
1260                 val &= ~PIPE_BPC_MASK;
1261                 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1262         }
1263         I915_WRITE(reg, val | TRANS_ENABLE);
1264         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1265                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1266 }
1267
1268 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1269                                      enum pipe pipe)
1270 {
1271         int reg;
1272         u32 val;
1273
1274         /* FDI relies on the transcoder */
1275         assert_fdi_tx_disabled(dev_priv, pipe);
1276         assert_fdi_rx_disabled(dev_priv, pipe);
1277
1278         /* Ports must be off as well */
1279         assert_pch_ports_disabled(dev_priv, pipe);
1280
1281         reg = TRANSCONF(pipe);
1282         val = I915_READ(reg);
1283         val &= ~TRANS_ENABLE;
1284         I915_WRITE(reg, val);
1285         /* wait for PCH transcoder off, transcoder state */
1286         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1287                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1288 }
1289
1290 /**
1291  * intel_enable_pipe - enable a pipe, asserting requirements
1292  * @dev_priv: i915 private structure
1293  * @pipe: pipe to enable
1294  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1295  *
1296  * Enable @pipe, making sure that various hardware specific requirements
1297  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1298  *
1299  * @pipe should be %PIPE_A or %PIPE_B.
1300  *
1301  * Will wait until the pipe is actually running (i.e. first vblank) before
1302  * returning.
1303  */
1304 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1305                               bool pch_port)
1306 {
1307         int reg;
1308         u32 val;
1309
1310         /*
1311          * A pipe without a PLL won't actually be able to drive bits from
1312          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1313          * need the check.
1314          */
1315         if (!HAS_PCH_SPLIT(dev_priv->dev))
1316                 assert_pll_enabled(dev_priv, pipe);
1317         else {
1318                 if (pch_port) {
1319                         /* if driving the PCH, we need FDI enabled */
1320                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1321                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1322                 }
1323                 /* FIXME: assert CPU port conditions for SNB+ */
1324         }
1325
1326         reg = PIPECONF(pipe);
1327         val = I915_READ(reg);
1328         if (val & PIPECONF_ENABLE)
1329                 return;
1330
1331         I915_WRITE(reg, val | PIPECONF_ENABLE);
1332         intel_wait_for_vblank(dev_priv->dev, pipe);
1333 }
1334
1335 /**
1336  * intel_disable_pipe - disable a pipe, asserting requirements
1337  * @dev_priv: i915 private structure
1338  * @pipe: pipe to disable
1339  *
1340  * Disable @pipe, making sure that various hardware specific requirements
1341  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1342  *
1343  * @pipe should be %PIPE_A or %PIPE_B.
1344  *
1345  * Will wait until the pipe has shut down before returning.
1346  */
1347 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1348                                enum pipe pipe)
1349 {
1350         int reg;
1351         u32 val;
1352
1353         /*
1354          * Make sure planes won't keep trying to pump pixels to us,
1355          * or we might hang the display.
1356          */
1357         assert_planes_disabled(dev_priv, pipe);
1358
1359         /* Don't disable pipe A or pipe A PLLs if needed */
1360         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1361                 return;
1362
1363         reg = PIPECONF(pipe);
1364         val = I915_READ(reg);
1365         if ((val & PIPECONF_ENABLE) == 0)
1366                 return;
1367
1368         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1369         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1370 }
1371
1372 /*
1373  * Plane regs are double buffered, going from enabled->disabled needs a
1374  * trigger in order to latch.  The display address reg provides this.
1375  */
1376 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1377                                       enum plane plane)
1378 {
1379         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1380         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1381 }
1382
1383 /**
1384  * intel_enable_plane - enable a display plane on a given pipe
1385  * @dev_priv: i915 private structure
1386  * @plane: plane to enable
1387  * @pipe: pipe being fed
1388  *
1389  * Enable @plane on @pipe, making sure that @pipe is running first.
1390  */
1391 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1392                                enum plane plane, enum pipe pipe)
1393 {
1394         int reg;
1395         u32 val;
1396
1397         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1398         assert_pipe_enabled(dev_priv, pipe);
1399
1400         reg = DSPCNTR(plane);
1401         val = I915_READ(reg);
1402         if (val & DISPLAY_PLANE_ENABLE)
1403                 return;
1404
1405         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1406         intel_flush_display_plane(dev_priv, plane);
1407         intel_wait_for_vblank(dev_priv->dev, pipe);
1408 }
1409
1410 /**
1411  * intel_disable_plane - disable a display plane
1412  * @dev_priv: i915 private structure
1413  * @plane: plane to disable
1414  * @pipe: pipe consuming the data
1415  *
1416  * Disable @plane; should be an independent operation.
1417  */
1418 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1419                                 enum plane plane, enum pipe pipe)
1420 {
1421         int reg;
1422         u32 val;
1423
1424         reg = DSPCNTR(plane);
1425         val = I915_READ(reg);
1426         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1427                 return;
1428
1429         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1430         intel_flush_display_plane(dev_priv, plane);
1431         intel_wait_for_vblank(dev_priv->dev, pipe);
1432 }
1433
1434 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1435                            enum pipe pipe, int reg, u32 port_sel)
1436 {
1437         u32 val = I915_READ(reg);
1438         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1439                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1440                 I915_WRITE(reg, val & ~DP_PORT_EN);
1441         }
1442 }
1443
1444 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1445                              enum pipe pipe, int reg)
1446 {
1447         u32 val = I915_READ(reg);
1448         if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1449                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1450                               reg, pipe);
1451                 I915_WRITE(reg, val & ~PORT_ENABLE);
1452         }
1453 }
1454
1455 /* Disable any ports connected to this transcoder */
1456 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1457                                     enum pipe pipe)
1458 {
1459         u32 reg, val;
1460
1461         val = I915_READ(PCH_PP_CONTROL);
1462         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1463
1464         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1465         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1466         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1467
1468         reg = PCH_ADPA;
1469         val = I915_READ(reg);
1470         if (adpa_pipe_enabled(dev_priv, val, pipe))
1471                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1472
1473         reg = PCH_LVDS;
1474         val = I915_READ(reg);
1475         if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1476                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1477                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1478                 POSTING_READ(reg);
1479                 udelay(100);
1480         }
1481
1482         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1483         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1484         disable_pch_hdmi(dev_priv, pipe, HDMID);
1485 }
1486
1487 static void i8xx_disable_fbc(struct drm_device *dev)
1488 {
1489         struct drm_i915_private *dev_priv = dev->dev_private;
1490         u32 fbc_ctl;
1491
1492         /* Disable compression */
1493         fbc_ctl = I915_READ(FBC_CONTROL);
1494         if ((fbc_ctl & FBC_CTL_EN) == 0)
1495                 return;
1496
1497         fbc_ctl &= ~FBC_CTL_EN;
1498         I915_WRITE(FBC_CONTROL, fbc_ctl);
1499
1500         /* Wait for compressing bit to clear */
1501         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1502                 DRM_DEBUG_KMS("FBC idle timed out\n");
1503                 return;
1504         }
1505
1506         DRM_DEBUG_KMS("disabled FBC\n");
1507 }
1508
1509 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1510 {
1511         struct drm_device *dev = crtc->dev;
1512         struct drm_i915_private *dev_priv = dev->dev_private;
1513         struct drm_framebuffer *fb = crtc->fb;
1514         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1515         struct drm_i915_gem_object *obj = intel_fb->obj;
1516         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1517         int cfb_pitch;
1518         int plane, i;
1519         u32 fbc_ctl, fbc_ctl2;
1520
1521         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1522         if (fb->pitches[0] < cfb_pitch)
1523                 cfb_pitch = fb->pitches[0];
1524
1525         /* FBC_CTL wants 64B units */
1526         cfb_pitch = (cfb_pitch / 64) - 1;
1527         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1528
1529         /* Clear old tags */
1530         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1531                 I915_WRITE(FBC_TAG + (i * 4), 0);
1532
1533         /* Set it up... */
1534         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1535         fbc_ctl2 |= plane;
1536         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1537         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1538
1539         /* enable it... */
1540         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1541         if (IS_I945GM(dev))
1542                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1543         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1544         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1545         fbc_ctl |= obj->fence_reg;
1546         I915_WRITE(FBC_CONTROL, fbc_ctl);
1547
1548         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1549                       cfb_pitch, crtc->y, intel_crtc->plane);
1550 }
1551
1552 static bool i8xx_fbc_enabled(struct drm_device *dev)
1553 {
1554         struct drm_i915_private *dev_priv = dev->dev_private;
1555
1556         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1557 }
1558
1559 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1560 {
1561         struct drm_device *dev = crtc->dev;
1562         struct drm_i915_private *dev_priv = dev->dev_private;
1563         struct drm_framebuffer *fb = crtc->fb;
1564         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1565         struct drm_i915_gem_object *obj = intel_fb->obj;
1566         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1567         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1568         unsigned long stall_watermark = 200;
1569         u32 dpfc_ctl;
1570
1571         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1572         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1573         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1574
1575         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1576                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1577                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1578         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1579
1580         /* enable it... */
1581         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1582
1583         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1584 }
1585
1586 static void g4x_disable_fbc(struct drm_device *dev)
1587 {
1588         struct drm_i915_private *dev_priv = dev->dev_private;
1589         u32 dpfc_ctl;
1590
1591         /* Disable compression */
1592         dpfc_ctl = I915_READ(DPFC_CONTROL);
1593         if (dpfc_ctl & DPFC_CTL_EN) {
1594                 dpfc_ctl &= ~DPFC_CTL_EN;
1595                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1596
1597                 DRM_DEBUG_KMS("disabled FBC\n");
1598         }
1599 }
1600
1601 static bool g4x_fbc_enabled(struct drm_device *dev)
1602 {
1603         struct drm_i915_private *dev_priv = dev->dev_private;
1604
1605         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1606 }
1607
1608 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1609 {
1610         struct drm_i915_private *dev_priv = dev->dev_private;
1611         u32 blt_ecoskpd;
1612
1613         /* Make sure blitter notifies FBC of writes */
1614         gen6_gt_force_wake_get(dev_priv);
1615         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1616         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1617                 GEN6_BLITTER_LOCK_SHIFT;
1618         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1619         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1620         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1621         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1622                          GEN6_BLITTER_LOCK_SHIFT);
1623         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1624         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1625         gen6_gt_force_wake_put(dev_priv);
1626 }
1627
1628 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1629 {
1630         struct drm_device *dev = crtc->dev;
1631         struct drm_i915_private *dev_priv = dev->dev_private;
1632         struct drm_framebuffer *fb = crtc->fb;
1633         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1634         struct drm_i915_gem_object *obj = intel_fb->obj;
1635         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1636         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1637         unsigned long stall_watermark = 200;
1638         u32 dpfc_ctl;
1639
1640         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1641         dpfc_ctl &= DPFC_RESERVED;
1642         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1643         /* Set persistent mode for front-buffer rendering, ala X. */
1644         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1645         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1646         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1647
1648         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1649                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1650                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1651         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1652         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1653         /* enable it... */
1654         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1655
1656         if (IS_GEN6(dev)) {
1657                 I915_WRITE(SNB_DPFC_CTL_SA,
1658                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1659                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1660                 sandybridge_blit_fbc_update(dev);
1661         }
1662
1663         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1664 }
1665
1666 static void ironlake_disable_fbc(struct drm_device *dev)
1667 {
1668         struct drm_i915_private *dev_priv = dev->dev_private;
1669         u32 dpfc_ctl;
1670
1671         /* Disable compression */
1672         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1673         if (dpfc_ctl & DPFC_CTL_EN) {
1674                 dpfc_ctl &= ~DPFC_CTL_EN;
1675                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1676
1677                 DRM_DEBUG_KMS("disabled FBC\n");
1678         }
1679 }
1680
1681 static bool ironlake_fbc_enabled(struct drm_device *dev)
1682 {
1683         struct drm_i915_private *dev_priv = dev->dev_private;
1684
1685         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1686 }
1687
1688 bool intel_fbc_enabled(struct drm_device *dev)
1689 {
1690         struct drm_i915_private *dev_priv = dev->dev_private;
1691
1692         if (!dev_priv->display.fbc_enabled)
1693                 return false;
1694
1695         return dev_priv->display.fbc_enabled(dev);
1696 }
1697
1698 static void intel_fbc_work_fn(struct work_struct *__work)
1699 {
1700         struct intel_fbc_work *work =
1701                 container_of(to_delayed_work(__work),
1702                              struct intel_fbc_work, work);
1703         struct drm_device *dev = work->crtc->dev;
1704         struct drm_i915_private *dev_priv = dev->dev_private;
1705
1706         mutex_lock(&dev->struct_mutex);
1707         if (work == dev_priv->fbc_work) {
1708                 /* Double check that we haven't switched fb without cancelling
1709                  * the prior work.
1710                  */
1711                 if (work->crtc->fb == work->fb) {
1712                         dev_priv->display.enable_fbc(work->crtc,
1713                                                      work->interval);
1714
1715                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1716                         dev_priv->cfb_fb = work->crtc->fb->base.id;
1717                         dev_priv->cfb_y = work->crtc->y;
1718                 }
1719
1720                 dev_priv->fbc_work = NULL;
1721         }
1722         mutex_unlock(&dev->struct_mutex);
1723
1724         kfree(work);
1725 }
1726
1727 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1728 {
1729         if (dev_priv->fbc_work == NULL)
1730                 return;
1731
1732         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1733
1734         /* Synchronisation is provided by struct_mutex and checking of
1735          * dev_priv->fbc_work, so we can perform the cancellation
1736          * entirely asynchronously.
1737          */
1738         if (cancel_delayed_work(&dev_priv->fbc_work->work))
1739                 /* tasklet was killed before being run, clean up */
1740                 kfree(dev_priv->fbc_work);
1741
1742         /* Mark the work as no longer wanted so that if it does
1743          * wake-up (because the work was already running and waiting
1744          * for our mutex), it will discover that is no longer
1745          * necessary to run.
1746          */
1747         dev_priv->fbc_work = NULL;
1748 }
1749
1750 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1751 {
1752         struct intel_fbc_work *work;
1753         struct drm_device *dev = crtc->dev;
1754         struct drm_i915_private *dev_priv = dev->dev_private;
1755
1756         if (!dev_priv->display.enable_fbc)
1757                 return;
1758
1759         intel_cancel_fbc_work(dev_priv);
1760
1761         work = kzalloc(sizeof *work, GFP_KERNEL);
1762         if (work == NULL) {
1763                 dev_priv->display.enable_fbc(crtc, interval);
1764                 return;
1765         }
1766
1767         work->crtc = crtc;
1768         work->fb = crtc->fb;
1769         work->interval = interval;
1770         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1771
1772         dev_priv->fbc_work = work;
1773
1774         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1775
1776         /* Delay the actual enabling to let pageflipping cease and the
1777          * display to settle before starting the compression. Note that
1778          * this delay also serves a second purpose: it allows for a
1779          * vblank to pass after disabling the FBC before we attempt
1780          * to modify the control registers.
1781          *
1782          * A more complicated solution would involve tracking vblanks
1783          * following the termination of the page-flipping sequence
1784          * and indeed performing the enable as a co-routine and not
1785          * waiting synchronously upon the vblank.
1786          */
1787         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1788 }
1789
1790 void intel_disable_fbc(struct drm_device *dev)
1791 {
1792         struct drm_i915_private *dev_priv = dev->dev_private;
1793
1794         intel_cancel_fbc_work(dev_priv);
1795
1796         if (!dev_priv->display.disable_fbc)
1797                 return;
1798
1799         dev_priv->display.disable_fbc(dev);
1800         dev_priv->cfb_plane = -1;
1801 }
1802
1803 /**
1804  * intel_update_fbc - enable/disable FBC as needed
1805  * @dev: the drm_device
1806  *
1807  * Set up the framebuffer compression hardware at mode set time.  We
1808  * enable it if possible:
1809  *   - plane A only (on pre-965)
1810  *   - no pixel mulitply/line duplication
1811  *   - no alpha buffer discard
1812  *   - no dual wide
1813  *   - framebuffer <= 2048 in width, 1536 in height
1814  *
1815  * We can't assume that any compression will take place (worst case),
1816  * so the compressed buffer has to be the same size as the uncompressed
1817  * one.  It also must reside (along with the line length buffer) in
1818  * stolen memory.
1819  *
1820  * We need to enable/disable FBC on a global basis.
1821  */
1822 static void intel_update_fbc(struct drm_device *dev)
1823 {
1824         struct drm_i915_private *dev_priv = dev->dev_private;
1825         struct drm_crtc *crtc = NULL, *tmp_crtc;
1826         struct intel_crtc *intel_crtc;
1827         struct drm_framebuffer *fb;
1828         struct intel_framebuffer *intel_fb;
1829         struct drm_i915_gem_object *obj;
1830         int enable_fbc;
1831
1832         DRM_DEBUG_KMS("\n");
1833
1834         if (!i915_powersave)
1835                 return;
1836
1837         if (!I915_HAS_FBC(dev))
1838                 return;
1839
1840         /*
1841          * If FBC is already on, we just have to verify that we can
1842          * keep it that way...
1843          * Need to disable if:
1844          *   - more than one pipe is active
1845          *   - changing FBC params (stride, fence, mode)
1846          *   - new fb is too large to fit in compressed buffer
1847          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1848          */
1849         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1850                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1851                         if (crtc) {
1852                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1853                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1854                                 goto out_disable;
1855                         }
1856                         crtc = tmp_crtc;
1857                 }
1858         }
1859
1860         if (!crtc || crtc->fb == NULL) {
1861                 DRM_DEBUG_KMS("no output, disabling\n");
1862                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1863                 goto out_disable;
1864         }
1865
1866         intel_crtc = to_intel_crtc(crtc);
1867         fb = crtc->fb;
1868         intel_fb = to_intel_framebuffer(fb);
1869         obj = intel_fb->obj;
1870
1871         enable_fbc = i915_enable_fbc;
1872         if (enable_fbc < 0) {
1873                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1874                 enable_fbc = 1;
1875                 if (INTEL_INFO(dev)->gen <= 5)
1876                         enable_fbc = 0;
1877         }
1878         if (!enable_fbc) {
1879                 DRM_DEBUG_KMS("fbc disabled per module param\n");
1880                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1881                 goto out_disable;
1882         }
1883         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1884                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1885                               "compression\n");
1886                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1887                 goto out_disable;
1888         }
1889         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1890             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1891                 DRM_DEBUG_KMS("mode incompatible with compression, "
1892                               "disabling\n");
1893                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1894                 goto out_disable;
1895         }
1896         if ((crtc->mode.hdisplay > 2048) ||
1897             (crtc->mode.vdisplay > 1536)) {
1898                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1899                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1900                 goto out_disable;
1901         }
1902         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1903                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1904                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1905                 goto out_disable;
1906         }
1907
1908         /* The use of a CPU fence is mandatory in order to detect writes
1909          * by the CPU to the scanout and trigger updates to the FBC.
1910          */
1911         if (obj->tiling_mode != I915_TILING_X ||
1912             obj->fence_reg == I915_FENCE_REG_NONE) {
1913                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1914                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1915                 goto out_disable;
1916         }
1917
1918         /* If the kernel debugger is active, always disable compression */
1919         if (in_dbg_master())
1920                 goto out_disable;
1921
1922         /* If the scanout has not changed, don't modify the FBC settings.
1923          * Note that we make the fundamental assumption that the fb->obj
1924          * cannot be unpinned (and have its GTT offset and fence revoked)
1925          * without first being decoupled from the scanout and FBC disabled.
1926          */
1927         if (dev_priv->cfb_plane == intel_crtc->plane &&
1928             dev_priv->cfb_fb == fb->base.id &&
1929             dev_priv->cfb_y == crtc->y)
1930                 return;
1931
1932         if (intel_fbc_enabled(dev)) {
1933                 /* We update FBC along two paths, after changing fb/crtc
1934                  * configuration (modeswitching) and after page-flipping
1935                  * finishes. For the latter, we know that not only did
1936                  * we disable the FBC at the start of the page-flip
1937                  * sequence, but also more than one vblank has passed.
1938                  *
1939                  * For the former case of modeswitching, it is possible
1940                  * to switch between two FBC valid configurations
1941                  * instantaneously so we do need to disable the FBC
1942                  * before we can modify its control registers. We also
1943                  * have to wait for the next vblank for that to take
1944                  * effect. However, since we delay enabling FBC we can
1945                  * assume that a vblank has passed since disabling and
1946                  * that we can safely alter the registers in the deferred
1947                  * callback.
1948                  *
1949                  * In the scenario that we go from a valid to invalid
1950                  * and then back to valid FBC configuration we have
1951                  * no strict enforcement that a vblank occurred since
1952                  * disabling the FBC. However, along all current pipe
1953                  * disabling paths we do need to wait for a vblank at
1954                  * some point. And we wait before enabling FBC anyway.
1955                  */
1956                 DRM_DEBUG_KMS("disabling active FBC for update\n");
1957                 intel_disable_fbc(dev);
1958         }
1959
1960         intel_enable_fbc(crtc, 500);
1961         return;
1962
1963 out_disable:
1964         /* Multiple disables should be harmless */
1965         if (intel_fbc_enabled(dev)) {
1966                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1967                 intel_disable_fbc(dev);
1968         }
1969 }
1970
1971 int
1972 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1973                            struct drm_i915_gem_object *obj,
1974                            struct intel_ring_buffer *pipelined)
1975 {
1976         struct drm_i915_private *dev_priv = dev->dev_private;
1977         u32 alignment;
1978         int ret;
1979
1980         switch (obj->tiling_mode) {
1981         case I915_TILING_NONE:
1982                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1983                         alignment = 128 * 1024;
1984                 else if (INTEL_INFO(dev)->gen >= 4)
1985                         alignment = 4 * 1024;
1986                 else
1987                         alignment = 64 * 1024;
1988                 break;
1989         case I915_TILING_X:
1990                 /* pin() will align the object as required by fence */
1991                 alignment = 0;
1992                 break;
1993         case I915_TILING_Y:
1994                 /* FIXME: Is this true? */
1995                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1996                 return -EINVAL;
1997         default:
1998                 BUG();
1999         }
2000
2001         dev_priv->mm.interruptible = false;
2002         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2003         if (ret)
2004                 goto err_interruptible;
2005
2006         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2007          * fence, whereas 965+ only requires a fence if using
2008          * framebuffer compression.  For simplicity, we always install
2009          * a fence as the cost is not that onerous.
2010          */
2011         if (obj->tiling_mode != I915_TILING_NONE) {
2012                 ret = i915_gem_object_get_fence(obj, pipelined);
2013                 if (ret)
2014                         goto err_unpin;
2015         }
2016
2017         dev_priv->mm.interruptible = true;
2018         return 0;
2019
2020 err_unpin:
2021         i915_gem_object_unpin(obj);
2022 err_interruptible:
2023         dev_priv->mm.interruptible = true;
2024         return ret;
2025 }
2026
2027 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2028                              int x, int y)
2029 {
2030         struct drm_device *dev = crtc->dev;
2031         struct drm_i915_private *dev_priv = dev->dev_private;
2032         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2033         struct intel_framebuffer *intel_fb;
2034         struct drm_i915_gem_object *obj;
2035         int plane = intel_crtc->plane;
2036         unsigned long Start, Offset;
2037         u32 dspcntr;
2038         u32 reg;
2039
2040         switch (plane) {
2041         case 0:
2042         case 1:
2043                 break;
2044         default:
2045                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2046                 return -EINVAL;
2047         }
2048
2049         intel_fb = to_intel_framebuffer(fb);
2050         obj = intel_fb->obj;
2051
2052         reg = DSPCNTR(plane);
2053         dspcntr = I915_READ(reg);
2054         /* Mask out pixel format bits in case we change it */
2055         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2056         switch (fb->bits_per_pixel) {
2057         case 8:
2058                 dspcntr |= DISPPLANE_8BPP;
2059                 break;
2060         case 16:
2061                 if (fb->depth == 15)
2062                         dspcntr |= DISPPLANE_15_16BPP;
2063                 else
2064                         dspcntr |= DISPPLANE_16BPP;
2065                 break;
2066         case 24:
2067         case 32:
2068                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2069                 break;
2070         default:
2071                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2072                 return -EINVAL;
2073         }
2074         if (INTEL_INFO(dev)->gen >= 4) {
2075                 if (obj->tiling_mode != I915_TILING_NONE)
2076                         dspcntr |= DISPPLANE_TILED;
2077                 else
2078                         dspcntr &= ~DISPPLANE_TILED;
2079         }
2080
2081         I915_WRITE(reg, dspcntr);
2082
2083         Start = obj->gtt_offset;
2084         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2085
2086         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2087                       Start, Offset, x, y, fb->pitches[0]);
2088         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2089         if (INTEL_INFO(dev)->gen >= 4) {
2090                 I915_WRITE(DSPSURF(plane), Start);
2091                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2092                 I915_WRITE(DSPADDR(plane), Offset);
2093         } else
2094                 I915_WRITE(DSPADDR(plane), Start + Offset);
2095         POSTING_READ(reg);
2096
2097         return 0;
2098 }
2099
2100 static int ironlake_update_plane(struct drm_crtc *crtc,
2101                                  struct drm_framebuffer *fb, int x, int y)
2102 {
2103         struct drm_device *dev = crtc->dev;
2104         struct drm_i915_private *dev_priv = dev->dev_private;
2105         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2106         struct intel_framebuffer *intel_fb;
2107         struct drm_i915_gem_object *obj;
2108         int plane = intel_crtc->plane;
2109         unsigned long Start, Offset;
2110         u32 dspcntr;
2111         u32 reg;
2112
2113         switch (plane) {
2114         case 0:
2115         case 1:
2116         case 2:
2117                 break;
2118         default:
2119                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2120                 return -EINVAL;
2121         }
2122
2123         intel_fb = to_intel_framebuffer(fb);
2124         obj = intel_fb->obj;
2125
2126         reg = DSPCNTR(plane);
2127         dspcntr = I915_READ(reg);
2128         /* Mask out pixel format bits in case we change it */
2129         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2130         switch (fb->bits_per_pixel) {
2131         case 8:
2132                 dspcntr |= DISPPLANE_8BPP;
2133                 break;
2134         case 16:
2135                 if (fb->depth != 16)
2136                         return -EINVAL;
2137
2138                 dspcntr |= DISPPLANE_16BPP;
2139                 break;
2140         case 24:
2141         case 32:
2142                 if (fb->depth == 24)
2143                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2144                 else if (fb->depth == 30)
2145                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2146                 else
2147                         return -EINVAL;
2148                 break;
2149         default:
2150                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2151                 return -EINVAL;
2152         }
2153
2154         if (obj->tiling_mode != I915_TILING_NONE)
2155                 dspcntr |= DISPPLANE_TILED;
2156         else
2157                 dspcntr &= ~DISPPLANE_TILED;
2158
2159         /* must disable */
2160         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2161
2162         I915_WRITE(reg, dspcntr);
2163
2164         Start = obj->gtt_offset;
2165         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2166
2167         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2168                       Start, Offset, x, y, fb->pitches[0]);
2169         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2170         I915_WRITE(DSPSURF(plane), Start);
2171         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2172         I915_WRITE(DSPADDR(plane), Offset);
2173         POSTING_READ(reg);
2174
2175         return 0;
2176 }
2177
2178 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2179 static int
2180 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2181                            int x, int y, enum mode_set_atomic state)
2182 {
2183         struct drm_device *dev = crtc->dev;
2184         struct drm_i915_private *dev_priv = dev->dev_private;
2185         int ret;
2186
2187         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2188         if (ret)
2189                 return ret;
2190
2191         intel_update_fbc(dev);
2192         intel_increase_pllclock(crtc);
2193
2194         return 0;
2195 }
2196
2197 static int
2198 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2199                     struct drm_framebuffer *old_fb)
2200 {
2201         struct drm_device *dev = crtc->dev;
2202         struct drm_i915_master_private *master_priv;
2203         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2204         int ret;
2205
2206         /* no fb bound */
2207         if (!crtc->fb) {
2208                 DRM_ERROR("No FB bound\n");
2209                 return 0;
2210         }
2211
2212         switch (intel_crtc->plane) {
2213         case 0:
2214         case 1:
2215                 break;
2216         case 2:
2217                 if (IS_IVYBRIDGE(dev))
2218                         break;
2219                 /* fall through otherwise */
2220         default:
2221                 DRM_ERROR("no plane for crtc\n");
2222                 return -EINVAL;
2223         }
2224
2225         mutex_lock(&dev->struct_mutex);
2226         ret = intel_pin_and_fence_fb_obj(dev,
2227                                          to_intel_framebuffer(crtc->fb)->obj,
2228                                          NULL);
2229         if (ret != 0) {
2230                 mutex_unlock(&dev->struct_mutex);
2231                 DRM_ERROR("pin & fence failed\n");
2232                 return ret;
2233         }
2234
2235         if (old_fb) {
2236                 struct drm_i915_private *dev_priv = dev->dev_private;
2237                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2238
2239                 wait_event(dev_priv->pending_flip_queue,
2240                            atomic_read(&dev_priv->mm.wedged) ||
2241                            atomic_read(&obj->pending_flip) == 0);
2242
2243                 /* Big Hammer, we also need to ensure that any pending
2244                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2245                  * current scanout is retired before unpinning the old
2246                  * framebuffer.
2247                  *
2248                  * This should only fail upon a hung GPU, in which case we
2249                  * can safely continue.
2250                  */
2251                 ret = i915_gem_object_finish_gpu(obj);
2252                 (void) ret;
2253         }
2254
2255         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2256                                          LEAVE_ATOMIC_MODE_SET);
2257         if (ret) {
2258                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2259                 mutex_unlock(&dev->struct_mutex);
2260                 DRM_ERROR("failed to update base address\n");
2261                 return ret;
2262         }
2263
2264         if (old_fb) {
2265                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2266                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2267         }
2268
2269         mutex_unlock(&dev->struct_mutex);
2270
2271         if (!dev->primary->master)
2272                 return 0;
2273
2274         master_priv = dev->primary->master->driver_priv;
2275         if (!master_priv->sarea_priv)
2276                 return 0;
2277
2278         if (intel_crtc->pipe) {
2279                 master_priv->sarea_priv->pipeB_x = x;
2280                 master_priv->sarea_priv->pipeB_y = y;
2281         } else {
2282                 master_priv->sarea_priv->pipeA_x = x;
2283                 master_priv->sarea_priv->pipeA_y = y;
2284         }
2285
2286         return 0;
2287 }
2288
2289 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2290 {
2291         struct drm_device *dev = crtc->dev;
2292         struct drm_i915_private *dev_priv = dev->dev_private;
2293         u32 dpa_ctl;
2294
2295         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2296         dpa_ctl = I915_READ(DP_A);
2297         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2298
2299         if (clock < 200000) {
2300                 u32 temp;
2301                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2302                 /* workaround for 160Mhz:
2303                    1) program 0x4600c bits 15:0 = 0x8124
2304                    2) program 0x46010 bit 0 = 1
2305                    3) program 0x46034 bit 24 = 1
2306                    4) program 0x64000 bit 14 = 1
2307                    */
2308                 temp = I915_READ(0x4600c);
2309                 temp &= 0xffff0000;
2310                 I915_WRITE(0x4600c, temp | 0x8124);
2311
2312                 temp = I915_READ(0x46010);
2313                 I915_WRITE(0x46010, temp | 1);
2314
2315                 temp = I915_READ(0x46034);
2316                 I915_WRITE(0x46034, temp | (1 << 24));
2317         } else {
2318                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2319         }
2320         I915_WRITE(DP_A, dpa_ctl);
2321
2322         POSTING_READ(DP_A);
2323         udelay(500);
2324 }
2325
2326 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2327 {
2328         struct drm_device *dev = crtc->dev;
2329         struct drm_i915_private *dev_priv = dev->dev_private;
2330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2331         int pipe = intel_crtc->pipe;
2332         u32 reg, temp;
2333
2334         /* enable normal train */
2335         reg = FDI_TX_CTL(pipe);
2336         temp = I915_READ(reg);
2337         if (IS_IVYBRIDGE(dev)) {
2338                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2339                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2340         } else {
2341                 temp &= ~FDI_LINK_TRAIN_NONE;
2342                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2343         }
2344         I915_WRITE(reg, temp);
2345
2346         reg = FDI_RX_CTL(pipe);
2347         temp = I915_READ(reg);
2348         if (HAS_PCH_CPT(dev)) {
2349                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2350                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2351         } else {
2352                 temp &= ~FDI_LINK_TRAIN_NONE;
2353                 temp |= FDI_LINK_TRAIN_NONE;
2354         }
2355         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2356
2357         /* wait one idle pattern time */
2358         POSTING_READ(reg);
2359         udelay(1000);
2360
2361         /* IVB wants error correction enabled */
2362         if (IS_IVYBRIDGE(dev))
2363                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2364                            FDI_FE_ERRC_ENABLE);
2365 }
2366
2367 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2368 {
2369         struct drm_i915_private *dev_priv = dev->dev_private;
2370         u32 flags = I915_READ(SOUTH_CHICKEN1);
2371
2372         flags |= FDI_PHASE_SYNC_OVR(pipe);
2373         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2374         flags |= FDI_PHASE_SYNC_EN(pipe);
2375         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2376         POSTING_READ(SOUTH_CHICKEN1);
2377 }
2378
2379 /* The FDI link training functions for ILK/Ibexpeak. */
2380 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2381 {
2382         struct drm_device *dev = crtc->dev;
2383         struct drm_i915_private *dev_priv = dev->dev_private;
2384         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2385         int pipe = intel_crtc->pipe;
2386         int plane = intel_crtc->plane;
2387         u32 reg, temp, tries;
2388
2389         /* FDI needs bits from pipe & plane first */
2390         assert_pipe_enabled(dev_priv, pipe);
2391         assert_plane_enabled(dev_priv, plane);
2392
2393         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2394            for train result */
2395         reg = FDI_RX_IMR(pipe);
2396         temp = I915_READ(reg);
2397         temp &= ~FDI_RX_SYMBOL_LOCK;
2398         temp &= ~FDI_RX_BIT_LOCK;
2399         I915_WRITE(reg, temp);
2400         I915_READ(reg);
2401         udelay(150);
2402
2403         /* enable CPU FDI TX and PCH FDI RX */
2404         reg = FDI_TX_CTL(pipe);
2405         temp = I915_READ(reg);
2406         temp &= ~(7 << 19);
2407         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2408         temp &= ~FDI_LINK_TRAIN_NONE;
2409         temp |= FDI_LINK_TRAIN_PATTERN_1;
2410         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2411
2412         reg = FDI_RX_CTL(pipe);
2413         temp = I915_READ(reg);
2414         temp &= ~FDI_LINK_TRAIN_NONE;
2415         temp |= FDI_LINK_TRAIN_PATTERN_1;
2416         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2417
2418         POSTING_READ(reg);
2419         udelay(150);
2420
2421         /* Ironlake workaround, enable clock pointer after FDI enable*/
2422         if (HAS_PCH_IBX(dev)) {
2423                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2424                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2425                            FDI_RX_PHASE_SYNC_POINTER_EN);
2426         }
2427
2428         reg = FDI_RX_IIR(pipe);
2429         for (tries = 0; tries < 5; tries++) {
2430                 temp = I915_READ(reg);
2431                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2432
2433                 if ((temp & FDI_RX_BIT_LOCK)) {
2434                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2435                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2436                         break;
2437                 }
2438         }
2439         if (tries == 5)
2440                 DRM_ERROR("FDI train 1 fail!\n");
2441
2442         /* Train 2 */
2443         reg = FDI_TX_CTL(pipe);
2444         temp = I915_READ(reg);
2445         temp &= ~FDI_LINK_TRAIN_NONE;
2446         temp |= FDI_LINK_TRAIN_PATTERN_2;
2447         I915_WRITE(reg, temp);
2448
2449         reg = FDI_RX_CTL(pipe);
2450         temp = I915_READ(reg);
2451         temp &= ~FDI_LINK_TRAIN_NONE;
2452         temp |= FDI_LINK_TRAIN_PATTERN_2;
2453         I915_WRITE(reg, temp);
2454
2455         POSTING_READ(reg);
2456         udelay(150);
2457
2458         reg = FDI_RX_IIR(pipe);
2459         for (tries = 0; tries < 5; tries++) {
2460                 temp = I915_READ(reg);
2461                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2462
2463                 if (temp & FDI_RX_SYMBOL_LOCK) {
2464                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2465                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2466                         break;
2467                 }
2468         }
2469         if (tries == 5)
2470                 DRM_ERROR("FDI train 2 fail!\n");
2471
2472         DRM_DEBUG_KMS("FDI train done\n");
2473
2474 }
2475
2476 static const int snb_b_fdi_train_param[] = {
2477         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2478         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2479         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2480         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2481 };
2482
2483 /* The FDI link training functions for SNB/Cougarpoint. */
2484 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2485 {
2486         struct drm_device *dev = crtc->dev;
2487         struct drm_i915_private *dev_priv = dev->dev_private;
2488         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2489         int pipe = intel_crtc->pipe;
2490         u32 reg, temp, i;
2491
2492         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2493            for train result */
2494         reg = FDI_RX_IMR(pipe);
2495         temp = I915_READ(reg);
2496         temp &= ~FDI_RX_SYMBOL_LOCK;
2497         temp &= ~FDI_RX_BIT_LOCK;
2498         I915_WRITE(reg, temp);
2499
2500         POSTING_READ(reg);
2501         udelay(150);
2502
2503         /* enable CPU FDI TX and PCH FDI RX */
2504         reg = FDI_TX_CTL(pipe);
2505         temp = I915_READ(reg);
2506         temp &= ~(7 << 19);
2507         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2508         temp &= ~FDI_LINK_TRAIN_NONE;
2509         temp |= FDI_LINK_TRAIN_PATTERN_1;
2510         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2511         /* SNB-B */
2512         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2513         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2514
2515         reg = FDI_RX_CTL(pipe);
2516         temp = I915_READ(reg);
2517         if (HAS_PCH_CPT(dev)) {
2518                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2519                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2520         } else {
2521                 temp &= ~FDI_LINK_TRAIN_NONE;
2522                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2523         }
2524         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2525
2526         POSTING_READ(reg);
2527         udelay(150);
2528
2529         if (HAS_PCH_CPT(dev))
2530                 cpt_phase_pointer_enable(dev, pipe);
2531
2532         for (i = 0; i < 4; i++) {
2533                 reg = FDI_TX_CTL(pipe);
2534                 temp = I915_READ(reg);
2535                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2536                 temp |= snb_b_fdi_train_param[i];
2537                 I915_WRITE(reg, temp);
2538
2539                 POSTING_READ(reg);
2540                 udelay(500);
2541
2542                 reg = FDI_RX_IIR(pipe);
2543                 temp = I915_READ(reg);
2544                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2545
2546                 if (temp & FDI_RX_BIT_LOCK) {
2547                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2548                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2549                         break;
2550                 }
2551         }
2552         if (i == 4)
2553                 DRM_ERROR("FDI train 1 fail!\n");
2554
2555         /* Train 2 */
2556         reg = FDI_TX_CTL(pipe);
2557         temp = I915_READ(reg);
2558         temp &= ~FDI_LINK_TRAIN_NONE;
2559         temp |= FDI_LINK_TRAIN_PATTERN_2;
2560         if (IS_GEN6(dev)) {
2561                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2562                 /* SNB-B */
2563                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2564         }
2565         I915_WRITE(reg, temp);
2566
2567         reg = FDI_RX_CTL(pipe);
2568         temp = I915_READ(reg);
2569         if (HAS_PCH_CPT(dev)) {
2570                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2571                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2572         } else {
2573                 temp &= ~FDI_LINK_TRAIN_NONE;
2574                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2575         }
2576         I915_WRITE(reg, temp);
2577
2578         POSTING_READ(reg);
2579         udelay(150);
2580
2581         for (i = 0; i < 4; i++) {
2582                 reg = FDI_TX_CTL(pipe);
2583                 temp = I915_READ(reg);
2584                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2585                 temp |= snb_b_fdi_train_param[i];
2586                 I915_WRITE(reg, temp);
2587
2588                 POSTING_READ(reg);
2589                 udelay(500);
2590
2591                 reg = FDI_RX_IIR(pipe);
2592                 temp = I915_READ(reg);
2593                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2594
2595                 if (temp & FDI_RX_SYMBOL_LOCK) {
2596                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2597                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2598                         break;
2599                 }
2600         }
2601         if (i == 4)
2602                 DRM_ERROR("FDI train 2 fail!\n");
2603
2604         DRM_DEBUG_KMS("FDI train done.\n");
2605 }
2606
2607 /* Manual link training for Ivy Bridge A0 parts */
2608 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2609 {
2610         struct drm_device *dev = crtc->dev;
2611         struct drm_i915_private *dev_priv = dev->dev_private;
2612         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2613         int pipe = intel_crtc->pipe;
2614         u32 reg, temp, i;
2615
2616         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2617            for train result */
2618         reg = FDI_RX_IMR(pipe);
2619         temp = I915_READ(reg);
2620         temp &= ~FDI_RX_SYMBOL_LOCK;
2621         temp &= ~FDI_RX_BIT_LOCK;
2622         I915_WRITE(reg, temp);
2623
2624         POSTING_READ(reg);
2625         udelay(150);
2626
2627         /* enable CPU FDI TX and PCH FDI RX */
2628         reg = FDI_TX_CTL(pipe);
2629         temp = I915_READ(reg);
2630         temp &= ~(7 << 19);
2631         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2632         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2633         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2634         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2635         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2636         temp |= FDI_COMPOSITE_SYNC;
2637         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2638
2639         reg = FDI_RX_CTL(pipe);
2640         temp = I915_READ(reg);
2641         temp &= ~FDI_LINK_TRAIN_AUTO;
2642         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2643         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2644         temp |= FDI_COMPOSITE_SYNC;
2645         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2646
2647         POSTING_READ(reg);
2648         udelay(150);
2649
2650         if (HAS_PCH_CPT(dev))
2651                 cpt_phase_pointer_enable(dev, pipe);
2652
2653         for (i = 0; i < 4; i++) {
2654                 reg = FDI_TX_CTL(pipe);
2655                 temp = I915_READ(reg);
2656                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2657                 temp |= snb_b_fdi_train_param[i];
2658                 I915_WRITE(reg, temp);
2659
2660                 POSTING_READ(reg);
2661                 udelay(500);
2662
2663                 reg = FDI_RX_IIR(pipe);
2664                 temp = I915_READ(reg);
2665                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2666
2667                 if (temp & FDI_RX_BIT_LOCK ||
2668                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2669                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2670                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2671                         break;
2672                 }
2673         }
2674         if (i == 4)
2675                 DRM_ERROR("FDI train 1 fail!\n");
2676
2677         /* Train 2 */
2678         reg = FDI_TX_CTL(pipe);
2679         temp = I915_READ(reg);
2680         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2681         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2682         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2683         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2684         I915_WRITE(reg, temp);
2685
2686         reg = FDI_RX_CTL(pipe);
2687         temp = I915_READ(reg);
2688         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2689         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2690         I915_WRITE(reg, temp);
2691
2692         POSTING_READ(reg);
2693         udelay(150);
2694
2695         for (i = 0; i < 4; i++) {
2696                 reg = FDI_TX_CTL(pipe);
2697                 temp = I915_READ(reg);
2698                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2699                 temp |= snb_b_fdi_train_param[i];
2700                 I915_WRITE(reg, temp);
2701
2702                 POSTING_READ(reg);
2703                 udelay(500);
2704
2705                 reg = FDI_RX_IIR(pipe);
2706                 temp = I915_READ(reg);
2707                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2708
2709                 if (temp & FDI_RX_SYMBOL_LOCK) {
2710                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2711                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2712                         break;
2713                 }
2714         }
2715         if (i == 4)
2716                 DRM_ERROR("FDI train 2 fail!\n");
2717
2718         DRM_DEBUG_KMS("FDI train done.\n");
2719 }
2720
2721 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2722 {
2723         struct drm_device *dev = crtc->dev;
2724         struct drm_i915_private *dev_priv = dev->dev_private;
2725         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2726         int pipe = intel_crtc->pipe;
2727         u32 reg, temp;
2728
2729         /* Write the TU size bits so error detection works */
2730         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2731                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2732
2733         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2734         reg = FDI_RX_CTL(pipe);
2735         temp = I915_READ(reg);
2736         temp &= ~((0x7 << 19) | (0x7 << 16));
2737         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2738         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2739         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2740
2741         POSTING_READ(reg);
2742         udelay(200);
2743
2744         /* Switch from Rawclk to PCDclk */
2745         temp = I915_READ(reg);
2746         I915_WRITE(reg, temp | FDI_PCDCLK);
2747
2748         POSTING_READ(reg);
2749         udelay(200);
2750
2751         /* Enable CPU FDI TX PLL, always on for Ironlake */
2752         reg = FDI_TX_CTL(pipe);
2753         temp = I915_READ(reg);
2754         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2755                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2756
2757                 POSTING_READ(reg);
2758                 udelay(100);
2759         }
2760 }
2761
2762 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2763 {
2764         struct drm_i915_private *dev_priv = dev->dev_private;
2765         u32 flags = I915_READ(SOUTH_CHICKEN1);
2766
2767         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2768         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2769         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2770         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2771         POSTING_READ(SOUTH_CHICKEN1);
2772 }
2773 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2774 {
2775         struct drm_device *dev = crtc->dev;
2776         struct drm_i915_private *dev_priv = dev->dev_private;
2777         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2778         int pipe = intel_crtc->pipe;
2779         u32 reg, temp;
2780
2781         /* disable CPU FDI tx and PCH FDI rx */
2782         reg = FDI_TX_CTL(pipe);
2783         temp = I915_READ(reg);
2784         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2785         POSTING_READ(reg);
2786
2787         reg = FDI_RX_CTL(pipe);
2788         temp = I915_READ(reg);
2789         temp &= ~(0x7 << 16);
2790         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2791         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2792
2793         POSTING_READ(reg);
2794         udelay(100);
2795
2796         /* Ironlake workaround, disable clock pointer after downing FDI */
2797         if (HAS_PCH_IBX(dev)) {
2798                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2799                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2800                            I915_READ(FDI_RX_CHICKEN(pipe) &
2801                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2802         } else if (HAS_PCH_CPT(dev)) {
2803                 cpt_phase_pointer_disable(dev, pipe);
2804         }
2805
2806         /* still set train pattern 1 */
2807         reg = FDI_TX_CTL(pipe);
2808         temp = I915_READ(reg);
2809         temp &= ~FDI_LINK_TRAIN_NONE;
2810         temp |= FDI_LINK_TRAIN_PATTERN_1;
2811         I915_WRITE(reg, temp);
2812
2813         reg = FDI_RX_CTL(pipe);
2814         temp = I915_READ(reg);
2815         if (HAS_PCH_CPT(dev)) {
2816                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2817                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2818         } else {
2819                 temp &= ~FDI_LINK_TRAIN_NONE;
2820                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2821         }
2822         /* BPC in FDI rx is consistent with that in PIPECONF */
2823         temp &= ~(0x07 << 16);
2824         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2825         I915_WRITE(reg, temp);
2826
2827         POSTING_READ(reg);
2828         udelay(100);
2829 }
2830
2831 /*
2832  * When we disable a pipe, we need to clear any pending scanline wait events
2833  * to avoid hanging the ring, which we assume we are waiting on.
2834  */
2835 static void intel_clear_scanline_wait(struct drm_device *dev)
2836 {
2837         struct drm_i915_private *dev_priv = dev->dev_private;
2838         struct intel_ring_buffer *ring;
2839         u32 tmp;
2840
2841         if (IS_GEN2(dev))
2842                 /* Can't break the hang on i8xx */
2843                 return;
2844
2845         ring = LP_RING(dev_priv);
2846         tmp = I915_READ_CTL(ring);
2847         if (tmp & RING_WAIT)
2848                 I915_WRITE_CTL(ring, tmp);
2849 }
2850
2851 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2852 {
2853         struct drm_i915_gem_object *obj;
2854         struct drm_i915_private *dev_priv;
2855
2856         if (crtc->fb == NULL)
2857                 return;
2858
2859         obj = to_intel_framebuffer(crtc->fb)->obj;
2860         dev_priv = crtc->dev->dev_private;
2861         wait_event(dev_priv->pending_flip_queue,
2862                    atomic_read(&obj->pending_flip) == 0);
2863 }
2864
2865 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2866 {
2867         struct drm_device *dev = crtc->dev;
2868         struct drm_mode_config *mode_config = &dev->mode_config;
2869         struct intel_encoder *encoder;
2870
2871         /*
2872          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2873          * must be driven by its own crtc; no sharing is possible.
2874          */
2875         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2876                 if (encoder->base.crtc != crtc)
2877                         continue;
2878
2879                 switch (encoder->type) {
2880                 case INTEL_OUTPUT_EDP:
2881                         if (!intel_encoder_is_pch_edp(&encoder->base))
2882                                 return false;
2883                         continue;
2884                 }
2885         }
2886
2887         return true;
2888 }
2889
2890 /*
2891  * Enable PCH resources required for PCH ports:
2892  *   - PCH PLLs
2893  *   - FDI training & RX/TX
2894  *   - update transcoder timings
2895  *   - DP transcoding bits
2896  *   - transcoder
2897  */
2898 static void ironlake_pch_enable(struct drm_crtc *crtc)
2899 {
2900         struct drm_device *dev = crtc->dev;
2901         struct drm_i915_private *dev_priv = dev->dev_private;
2902         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2903         int pipe = intel_crtc->pipe;
2904         u32 reg, temp, transc_sel;
2905
2906         /* For PCH output, training FDI link */
2907         dev_priv->display.fdi_link_train(crtc);
2908
2909         intel_enable_pch_pll(dev_priv, pipe);
2910
2911         if (HAS_PCH_CPT(dev)) {
2912                 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2913                         TRANSC_DPLLB_SEL;
2914
2915                 /* Be sure PCH DPLL SEL is set */
2916                 temp = I915_READ(PCH_DPLL_SEL);
2917                 if (pipe == 0) {
2918                         temp &= ~(TRANSA_DPLLB_SEL);
2919                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2920                 } else if (pipe == 1) {
2921                         temp &= ~(TRANSB_DPLLB_SEL);
2922                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2923                 } else if (pipe == 2) {
2924                         temp &= ~(TRANSC_DPLLB_SEL);
2925                         temp |= (TRANSC_DPLL_ENABLE | transc_sel);
2926                 }
2927                 I915_WRITE(PCH_DPLL_SEL, temp);
2928         }
2929
2930         /* set transcoder timing, panel must allow it */
2931         assert_panel_unlocked(dev_priv, pipe);
2932         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2933         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2934         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2935
2936         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2937         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2938         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2939
2940         intel_fdi_normal_train(crtc);
2941
2942         /* For PCH DP, enable TRANS_DP_CTL */
2943         if (HAS_PCH_CPT(dev) &&
2944             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2945              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2946                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2947                 reg = TRANS_DP_CTL(pipe);
2948                 temp = I915_READ(reg);
2949                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2950                           TRANS_DP_SYNC_MASK |
2951                           TRANS_DP_BPC_MASK);
2952                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2953                          TRANS_DP_ENH_FRAMING);
2954                 temp |= bpc << 9; /* same format but at 11:9 */
2955
2956                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2957                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2958                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2959                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2960
2961                 switch (intel_trans_dp_port_sel(crtc)) {
2962                 case PCH_DP_B:
2963                         temp |= TRANS_DP_PORT_SEL_B;
2964                         break;
2965                 case PCH_DP_C:
2966                         temp |= TRANS_DP_PORT_SEL_C;
2967                         break;
2968                 case PCH_DP_D:
2969                         temp |= TRANS_DP_PORT_SEL_D;
2970                         break;
2971                 default:
2972                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2973                         temp |= TRANS_DP_PORT_SEL_B;
2974                         break;
2975                 }
2976
2977                 I915_WRITE(reg, temp);
2978         }
2979
2980         intel_enable_transcoder(dev_priv, pipe);
2981 }
2982
2983 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2984 {
2985         struct drm_i915_private *dev_priv = dev->dev_private;
2986         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2987         u32 temp;
2988
2989         temp = I915_READ(dslreg);
2990         udelay(500);
2991         if (wait_for(I915_READ(dslreg) != temp, 5)) {
2992                 /* Without this, mode sets may fail silently on FDI */
2993                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2994                 udelay(250);
2995                 I915_WRITE(tc2reg, 0);
2996                 if (wait_for(I915_READ(dslreg) != temp, 5))
2997                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2998         }
2999 }
3000
3001 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3002 {
3003         struct drm_device *dev = crtc->dev;
3004         struct drm_i915_private *dev_priv = dev->dev_private;
3005         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3006         int pipe = intel_crtc->pipe;
3007         int plane = intel_crtc->plane;
3008         u32 temp;
3009         bool is_pch_port;
3010
3011         if (intel_crtc->active)
3012                 return;
3013
3014         intel_crtc->active = true;
3015         intel_update_watermarks(dev);
3016
3017         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3018                 temp = I915_READ(PCH_LVDS);
3019                 if ((temp & LVDS_PORT_EN) == 0)
3020                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3021         }
3022
3023         is_pch_port = intel_crtc_driving_pch(crtc);
3024
3025         if (is_pch_port)
3026                 ironlake_fdi_pll_enable(crtc);
3027         else
3028                 ironlake_fdi_disable(crtc);
3029
3030         /* Enable panel fitting for LVDS */
3031         if (dev_priv->pch_pf_size &&
3032             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3033                 /* Force use of hard-coded filter coefficients
3034                  * as some pre-programmed values are broken,
3035                  * e.g. x201.
3036                  */
3037                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3038                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3039                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3040         }
3041
3042         /*
3043          * On ILK+ LUT must be loaded before the pipe is running but with
3044          * clocks enabled
3045          */
3046         intel_crtc_load_lut(crtc);
3047
3048         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3049         intel_enable_plane(dev_priv, plane, pipe);
3050
3051         if (is_pch_port)
3052                 ironlake_pch_enable(crtc);
3053
3054         mutex_lock(&dev->struct_mutex);
3055         intel_update_fbc(dev);
3056         mutex_unlock(&dev->struct_mutex);
3057
3058         intel_crtc_update_cursor(crtc, true);
3059 }
3060
3061 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3062 {
3063         struct drm_device *dev = crtc->dev;
3064         struct drm_i915_private *dev_priv = dev->dev_private;
3065         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3066         int pipe = intel_crtc->pipe;
3067         int plane = intel_crtc->plane;
3068         u32 reg, temp;
3069
3070         if (!intel_crtc->active)
3071                 return;
3072
3073         intel_crtc_wait_for_pending_flips(crtc);
3074         drm_vblank_off(dev, pipe);
3075         intel_crtc_update_cursor(crtc, false);
3076
3077         intel_disable_plane(dev_priv, plane, pipe);
3078
3079         if (dev_priv->cfb_plane == plane)
3080                 intel_disable_fbc(dev);
3081
3082         intel_disable_pipe(dev_priv, pipe);
3083
3084         /* Disable PF */
3085         I915_WRITE(PF_CTL(pipe), 0);
3086         I915_WRITE(PF_WIN_SZ(pipe), 0);
3087
3088         ironlake_fdi_disable(crtc);
3089
3090         /* This is a horrible layering violation; we should be doing this in
3091          * the connector/encoder ->prepare instead, but we don't always have
3092          * enough information there about the config to know whether it will
3093          * actually be necessary or just cause undesired flicker.
3094          */
3095         intel_disable_pch_ports(dev_priv, pipe);
3096
3097         intel_disable_transcoder(dev_priv, pipe);
3098
3099         if (HAS_PCH_CPT(dev)) {
3100                 /* disable TRANS_DP_CTL */
3101                 reg = TRANS_DP_CTL(pipe);
3102                 temp = I915_READ(reg);
3103                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3104                 temp |= TRANS_DP_PORT_SEL_NONE;
3105                 I915_WRITE(reg, temp);
3106
3107                 /* disable DPLL_SEL */
3108                 temp = I915_READ(PCH_DPLL_SEL);
3109                 switch (pipe) {
3110                 case 0:
3111                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3112                         break;
3113                 case 1:
3114                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3115                         break;
3116                 case 2:
3117                         /* C shares PLL A or B */
3118                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3119                         break;
3120                 default:
3121                         BUG(); /* wtf */
3122                 }
3123                 I915_WRITE(PCH_DPLL_SEL, temp);
3124         }
3125
3126         /* disable PCH DPLL */
3127         if (!intel_crtc->no_pll)
3128                 intel_disable_pch_pll(dev_priv, pipe);
3129
3130         /* Switch from PCDclk to Rawclk */
3131         reg = FDI_RX_CTL(pipe);
3132         temp = I915_READ(reg);
3133         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3134
3135         /* Disable CPU FDI TX PLL */
3136         reg = FDI_TX_CTL(pipe);
3137         temp = I915_READ(reg);
3138         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3139
3140         POSTING_READ(reg);
3141         udelay(100);
3142
3143         reg = FDI_RX_CTL(pipe);
3144         temp = I915_READ(reg);
3145         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3146
3147         /* Wait for the clocks to turn off. */
3148         POSTING_READ(reg);
3149         udelay(100);
3150
3151         intel_crtc->active = false;
3152         intel_update_watermarks(dev);
3153
3154         mutex_lock(&dev->struct_mutex);
3155         intel_update_fbc(dev);
3156         intel_clear_scanline_wait(dev);
3157         mutex_unlock(&dev->struct_mutex);
3158 }
3159
3160 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3161 {
3162         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3163         int pipe = intel_crtc->pipe;
3164         int plane = intel_crtc->plane;
3165
3166         /* XXX: When our outputs are all unaware of DPMS modes other than off
3167          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3168          */
3169         switch (mode) {
3170         case DRM_MODE_DPMS_ON:
3171         case DRM_MODE_DPMS_STANDBY:
3172         case DRM_MODE_DPMS_SUSPEND:
3173                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3174                 ironlake_crtc_enable(crtc);
3175                 break;
3176
3177         case DRM_MODE_DPMS_OFF:
3178                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3179                 ironlake_crtc_disable(crtc);
3180                 break;
3181         }
3182 }
3183
3184 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3185 {
3186         if (!enable && intel_crtc->overlay) {
3187                 struct drm_device *dev = intel_crtc->base.dev;
3188                 struct drm_i915_private *dev_priv = dev->dev_private;
3189
3190                 mutex_lock(&dev->struct_mutex);
3191                 dev_priv->mm.interruptible = false;
3192                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3193                 dev_priv->mm.interruptible = true;
3194                 mutex_unlock(&dev->struct_mutex);
3195         }
3196
3197         /* Let userspace switch the overlay on again. In most cases userspace
3198          * has to recompute where to put it anyway.
3199          */
3200 }
3201
3202 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3203 {
3204         struct drm_device *dev = crtc->dev;
3205         struct drm_i915_private *dev_priv = dev->dev_private;
3206         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3207         int pipe = intel_crtc->pipe;
3208         int plane = intel_crtc->plane;
3209
3210         if (intel_crtc->active)
3211                 return;
3212
3213         intel_crtc->active = true;
3214         intel_update_watermarks(dev);
3215
3216         intel_enable_pll(dev_priv, pipe);
3217         intel_enable_pipe(dev_priv, pipe, false);
3218         intel_enable_plane(dev_priv, plane, pipe);
3219
3220         intel_crtc_load_lut(crtc);
3221         intel_update_fbc(dev);
3222
3223         /* Give the overlay scaler a chance to enable if it's on this pipe */
3224         intel_crtc_dpms_overlay(intel_crtc, true);
3225         intel_crtc_update_cursor(crtc, true);
3226 }
3227
3228 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3229 {
3230         struct drm_device *dev = crtc->dev;
3231         struct drm_i915_private *dev_priv = dev->dev_private;
3232         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3233         int pipe = intel_crtc->pipe;
3234         int plane = intel_crtc->plane;
3235
3236         if (!intel_crtc->active)
3237                 return;
3238
3239         /* Give the overlay scaler a chance to disable if it's on this pipe */
3240         intel_crtc_wait_for_pending_flips(crtc);
3241         drm_vblank_off(dev, pipe);
3242         intel_crtc_dpms_overlay(intel_crtc, false);
3243         intel_crtc_update_cursor(crtc, false);
3244
3245         if (dev_priv->cfb_plane == plane)
3246                 intel_disable_fbc(dev);
3247
3248         intel_disable_plane(dev_priv, plane, pipe);
3249         intel_disable_pipe(dev_priv, pipe);
3250         intel_disable_pll(dev_priv, pipe);
3251
3252         intel_crtc->active = false;
3253         intel_update_fbc(dev);
3254         intel_update_watermarks(dev);
3255         intel_clear_scanline_wait(dev);
3256 }
3257
3258 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3259 {
3260         /* XXX: When our outputs are all unaware of DPMS modes other than off
3261          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3262          */
3263         switch (mode) {
3264         case DRM_MODE_DPMS_ON:
3265         case DRM_MODE_DPMS_STANDBY:
3266         case DRM_MODE_DPMS_SUSPEND:
3267                 i9xx_crtc_enable(crtc);
3268                 break;
3269         case DRM_MODE_DPMS_OFF:
3270                 i9xx_crtc_disable(crtc);
3271                 break;
3272         }
3273 }
3274
3275 /**
3276  * Sets the power management mode of the pipe and plane.
3277  */
3278 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3279 {
3280         struct drm_device *dev = crtc->dev;
3281         struct drm_i915_private *dev_priv = dev->dev_private;
3282         struct drm_i915_master_private *master_priv;
3283         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3284         int pipe = intel_crtc->pipe;
3285         bool enabled;
3286
3287         if (intel_crtc->dpms_mode == mode)
3288                 return;
3289
3290         intel_crtc->dpms_mode = mode;
3291
3292         dev_priv->display.dpms(crtc, mode);
3293
3294         if (!dev->primary->master)
3295                 return;
3296
3297         master_priv = dev->primary->master->driver_priv;
3298         if (!master_priv->sarea_priv)
3299                 return;
3300
3301         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3302
3303         switch (pipe) {
3304         case 0:
3305                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3306                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3307                 break;
3308         case 1:
3309                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3310                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3311                 break;
3312         default:
3313                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3314                 break;
3315         }
3316 }
3317
3318 static void intel_crtc_disable(struct drm_crtc *crtc)
3319 {
3320         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3321         struct drm_device *dev = crtc->dev;
3322
3323         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3324
3325         if (crtc->fb) {
3326                 mutex_lock(&dev->struct_mutex);
3327                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3328                 mutex_unlock(&dev->struct_mutex);
3329         }
3330 }
3331
3332 /* Prepare for a mode set.
3333  *
3334  * Note we could be a lot smarter here.  We need to figure out which outputs
3335  * will be enabled, which disabled (in short, how the config will changes)
3336  * and perform the minimum necessary steps to accomplish that, e.g. updating
3337  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3338  * panel fitting is in the proper state, etc.
3339  */
3340 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3341 {
3342         i9xx_crtc_disable(crtc);
3343 }
3344
3345 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3346 {
3347         i9xx_crtc_enable(crtc);
3348 }
3349
3350 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3351 {
3352         ironlake_crtc_disable(crtc);
3353 }
3354
3355 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3356 {
3357         ironlake_crtc_enable(crtc);
3358 }
3359
3360 void intel_encoder_prepare(struct drm_encoder *encoder)
3361 {
3362         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3363         /* lvds has its own version of prepare see intel_lvds_prepare */
3364         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3365 }
3366
3367 void intel_encoder_commit(struct drm_encoder *encoder)
3368 {
3369         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3370         struct drm_device *dev = encoder->dev;
3371         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3372         struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3373
3374         /* lvds has its own version of commit see intel_lvds_commit */
3375         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3376
3377         if (HAS_PCH_CPT(dev))
3378                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3379 }
3380
3381 void intel_encoder_destroy(struct drm_encoder *encoder)
3382 {
3383         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3384
3385         drm_encoder_cleanup(encoder);
3386         kfree(intel_encoder);
3387 }
3388
3389 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3390                                   struct drm_display_mode *mode,
3391                                   struct drm_display_mode *adjusted_mode)
3392 {
3393         struct drm_device *dev = crtc->dev;
3394
3395         if (HAS_PCH_SPLIT(dev)) {
3396                 /* FDI link clock is fixed at 2.7G */
3397                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3398                         return false;
3399         }
3400
3401         /* XXX some encoders set the crtcinfo, others don't.
3402          * Obviously we need some form of conflict resolution here...
3403          */
3404         if (adjusted_mode->crtc_htotal == 0)
3405                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3406
3407         return true;
3408 }
3409
3410 static int i945_get_display_clock_speed(struct drm_device *dev)
3411 {
3412         return 400000;
3413 }
3414
3415 static int i915_get_display_clock_speed(struct drm_device *dev)
3416 {
3417         return 333000;
3418 }
3419
3420 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3421 {
3422         return 200000;
3423 }
3424
3425 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3426 {
3427         u16 gcfgc = 0;
3428
3429         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3430
3431         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3432                 return 133000;
3433         else {
3434                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3435                 case GC_DISPLAY_CLOCK_333_MHZ:
3436                         return 333000;
3437                 default:
3438                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3439                         return 190000;
3440                 }
3441         }
3442 }
3443
3444 static int i865_get_display_clock_speed(struct drm_device *dev)
3445 {
3446         return 266000;
3447 }
3448
3449 static int i855_get_display_clock_speed(struct drm_device *dev)
3450 {
3451         u16 hpllcc = 0;
3452         /* Assume that the hardware is in the high speed state.  This
3453          * should be the default.
3454          */
3455         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3456         case GC_CLOCK_133_200:
3457         case GC_CLOCK_100_200:
3458                 return 200000;
3459         case GC_CLOCK_166_250:
3460                 return 250000;
3461         case GC_CLOCK_100_133:
3462                 return 133000;
3463         }
3464
3465         /* Shouldn't happen */
3466         return 0;
3467 }
3468
3469 static int i830_get_display_clock_speed(struct drm_device *dev)
3470 {
3471         return 133000;
3472 }
3473
3474 struct fdi_m_n {
3475         u32        tu;
3476         u32        gmch_m;
3477         u32        gmch_n;
3478         u32        link_m;
3479         u32        link_n;
3480 };
3481
3482 static void
3483 fdi_reduce_ratio(u32 *num, u32 *den)
3484 {
3485         while (*num > 0xffffff || *den > 0xffffff) {
3486                 *num >>= 1;
3487                 *den >>= 1;
3488         }
3489 }
3490
3491 static void
3492 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3493                      int link_clock, struct fdi_m_n *m_n)
3494 {
3495         m_n->tu = 64; /* default size */
3496
3497         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3498         m_n->gmch_m = bits_per_pixel * pixel_clock;
3499         m_n->gmch_n = link_clock * nlanes * 8;
3500         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3501
3502         m_n->link_m = pixel_clock;
3503         m_n->link_n = link_clock;
3504         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3505 }
3506
3507
3508 struct intel_watermark_params {
3509         unsigned long fifo_size;
3510         unsigned long max_wm;
3511         unsigned long default_wm;
3512         unsigned long guard_size;
3513         unsigned long cacheline_size;
3514 };
3515
3516 /* Pineview has different values for various configs */
3517 static const struct intel_watermark_params pineview_display_wm = {
3518         PINEVIEW_DISPLAY_FIFO,
3519         PINEVIEW_MAX_WM,
3520         PINEVIEW_DFT_WM,
3521         PINEVIEW_GUARD_WM,
3522         PINEVIEW_FIFO_LINE_SIZE
3523 };
3524 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3525         PINEVIEW_DISPLAY_FIFO,
3526         PINEVIEW_MAX_WM,
3527         PINEVIEW_DFT_HPLLOFF_WM,
3528         PINEVIEW_GUARD_WM,
3529         PINEVIEW_FIFO_LINE_SIZE
3530 };
3531 static const struct intel_watermark_params pineview_cursor_wm = {
3532         PINEVIEW_CURSOR_FIFO,
3533         PINEVIEW_CURSOR_MAX_WM,
3534         PINEVIEW_CURSOR_DFT_WM,
3535         PINEVIEW_CURSOR_GUARD_WM,
3536         PINEVIEW_FIFO_LINE_SIZE,
3537 };
3538 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3539         PINEVIEW_CURSOR_FIFO,
3540         PINEVIEW_CURSOR_MAX_WM,
3541         PINEVIEW_CURSOR_DFT_WM,
3542         PINEVIEW_CURSOR_GUARD_WM,
3543         PINEVIEW_FIFO_LINE_SIZE
3544 };
3545 static const struct intel_watermark_params g4x_wm_info = {
3546         G4X_FIFO_SIZE,
3547         G4X_MAX_WM,
3548         G4X_MAX_WM,
3549         2,
3550         G4X_FIFO_LINE_SIZE,
3551 };
3552 static const struct intel_watermark_params g4x_cursor_wm_info = {
3553         I965_CURSOR_FIFO,
3554         I965_CURSOR_MAX_WM,
3555         I965_CURSOR_DFT_WM,
3556         2,
3557         G4X_FIFO_LINE_SIZE,
3558 };
3559 static const struct intel_watermark_params i965_cursor_wm_info = {
3560         I965_CURSOR_FIFO,
3561         I965_CURSOR_MAX_WM,
3562         I965_CURSOR_DFT_WM,
3563         2,
3564         I915_FIFO_LINE_SIZE,
3565 };
3566 static const struct intel_watermark_params i945_wm_info = {
3567         I945_FIFO_SIZE,
3568         I915_MAX_WM,
3569         1,
3570         2,
3571         I915_FIFO_LINE_SIZE
3572 };
3573 static const struct intel_watermark_params i915_wm_info = {
3574         I915_FIFO_SIZE,
3575         I915_MAX_WM,
3576         1,
3577         2,
3578         I915_FIFO_LINE_SIZE
3579 };
3580 static const struct intel_watermark_params i855_wm_info = {
3581         I855GM_FIFO_SIZE,
3582         I915_MAX_WM,
3583         1,
3584         2,
3585         I830_FIFO_LINE_SIZE
3586 };
3587 static const struct intel_watermark_params i830_wm_info = {
3588         I830_FIFO_SIZE,
3589         I915_MAX_WM,
3590         1,
3591         2,
3592         I830_FIFO_LINE_SIZE
3593 };
3594
3595 static const struct intel_watermark_params ironlake_display_wm_info = {
3596         ILK_DISPLAY_FIFO,
3597         ILK_DISPLAY_MAXWM,
3598         ILK_DISPLAY_DFTWM,
3599         2,
3600         ILK_FIFO_LINE_SIZE
3601 };
3602 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3603         ILK_CURSOR_FIFO,
3604         ILK_CURSOR_MAXWM,
3605         ILK_CURSOR_DFTWM,
3606         2,
3607         ILK_FIFO_LINE_SIZE
3608 };
3609 static const struct intel_watermark_params ironlake_display_srwm_info = {
3610         ILK_DISPLAY_SR_FIFO,
3611         ILK_DISPLAY_MAX_SRWM,
3612         ILK_DISPLAY_DFT_SRWM,
3613         2,
3614         ILK_FIFO_LINE_SIZE
3615 };
3616 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3617         ILK_CURSOR_SR_FIFO,
3618         ILK_CURSOR_MAX_SRWM,
3619         ILK_CURSOR_DFT_SRWM,
3620         2,
3621         ILK_FIFO_LINE_SIZE
3622 };
3623
3624 static const struct intel_watermark_params sandybridge_display_wm_info = {
3625         SNB_DISPLAY_FIFO,
3626         SNB_DISPLAY_MAXWM,
3627         SNB_DISPLAY_DFTWM,
3628         2,
3629         SNB_FIFO_LINE_SIZE
3630 };
3631 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3632         SNB_CURSOR_FIFO,
3633         SNB_CURSOR_MAXWM,
3634         SNB_CURSOR_DFTWM,
3635         2,
3636         SNB_FIFO_LINE_SIZE
3637 };
3638 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3639         SNB_DISPLAY_SR_FIFO,
3640         SNB_DISPLAY_MAX_SRWM,
3641         SNB_DISPLAY_DFT_SRWM,
3642         2,
3643         SNB_FIFO_LINE_SIZE
3644 };
3645 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3646         SNB_CURSOR_SR_FIFO,
3647         SNB_CURSOR_MAX_SRWM,
3648         SNB_CURSOR_DFT_SRWM,
3649         2,
3650         SNB_FIFO_LINE_SIZE
3651 };
3652
3653
3654 /**
3655  * intel_calculate_wm - calculate watermark level
3656  * @clock_in_khz: pixel clock
3657  * @wm: chip FIFO params
3658  * @pixel_size: display pixel size
3659  * @latency_ns: memory latency for the platform
3660  *
3661  * Calculate the watermark level (the level at which the display plane will
3662  * start fetching from memory again).  Each chip has a different display
3663  * FIFO size and allocation, so the caller needs to figure that out and pass
3664  * in the correct intel_watermark_params structure.
3665  *
3666  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3667  * on the pixel size.  When it reaches the watermark level, it'll start
3668  * fetching FIFO line sized based chunks from memory until the FIFO fills
3669  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3670  * will occur, and a display engine hang could result.
3671  */
3672 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3673                                         const struct intel_watermark_params *wm,
3674                                         int fifo_size,
3675                                         int pixel_size,
3676                                         unsigned long latency_ns)
3677 {
3678         long entries_required, wm_size;
3679
3680         /*
3681          * Note: we need to make sure we don't overflow for various clock &
3682          * latency values.
3683          * clocks go from a few thousand to several hundred thousand.
3684          * latency is usually a few thousand
3685          */
3686         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3687                 1000;
3688         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3689
3690         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3691
3692         wm_size = fifo_size - (entries_required + wm->guard_size);
3693
3694         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3695
3696         /* Don't promote wm_size to unsigned... */
3697         if (wm_size > (long)wm->max_wm)
3698                 wm_size = wm->max_wm;
3699         if (wm_size <= 0)
3700                 wm_size = wm->default_wm;
3701         return wm_size;
3702 }
3703
3704 struct cxsr_latency {
3705         int is_desktop;
3706         int is_ddr3;
3707         unsigned long fsb_freq;
3708         unsigned long mem_freq;
3709         unsigned long display_sr;
3710         unsigned long display_hpll_disable;
3711         unsigned long cursor_sr;
3712         unsigned long cursor_hpll_disable;
3713 };
3714
3715 static const struct cxsr_latency cxsr_latency_table[] = {
3716         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3717         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3718         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3719         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3720         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3721
3722         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3723         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3724         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3725         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3726         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3727
3728         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3729         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3730         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3731         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3732         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3733
3734         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3735         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3736         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3737         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3738         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3739
3740         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3741         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3742         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3743         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3744         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3745
3746         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3747         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3748         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3749         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3750         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3751 };
3752
3753 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3754                                                          int is_ddr3,
3755                                                          int fsb,
3756                                                          int mem)
3757 {
3758         const struct cxsr_latency *latency;
3759         int i;
3760
3761         if (fsb == 0 || mem == 0)
3762                 return NULL;
3763
3764         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3765                 latency = &cxsr_latency_table[i];
3766                 if (is_desktop == latency->is_desktop &&
3767                     is_ddr3 == latency->is_ddr3 &&
3768                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3769                         return latency;
3770         }
3771
3772         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3773
3774         return NULL;
3775 }
3776
3777 static void pineview_disable_cxsr(struct drm_device *dev)
3778 {
3779         struct drm_i915_private *dev_priv = dev->dev_private;
3780
3781         /* deactivate cxsr */
3782         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3783 }
3784
3785 /*
3786  * Latency for FIFO fetches is dependent on several factors:
3787  *   - memory configuration (speed, channels)
3788  *   - chipset
3789  *   - current MCH state
3790  * It can be fairly high in some situations, so here we assume a fairly
3791  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3792  * set this value too high, the FIFO will fetch frequently to stay full)
3793  * and power consumption (set it too low to save power and we might see
3794  * FIFO underruns and display "flicker").
3795  *
3796  * A value of 5us seems to be a good balance; safe for very low end
3797  * platforms but not overly aggressive on lower latency configs.
3798  */
3799 static const int latency_ns = 5000;
3800
3801 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3802 {
3803         struct drm_i915_private *dev_priv = dev->dev_private;
3804         uint32_t dsparb = I915_READ(DSPARB);
3805         int size;
3806
3807         size = dsparb & 0x7f;
3808         if (plane)
3809                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3810
3811         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3812                       plane ? "B" : "A", size);
3813
3814         return size;
3815 }
3816
3817 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3818 {
3819         struct drm_i915_private *dev_priv = dev->dev_private;
3820         uint32_t dsparb = I915_READ(DSPARB);
3821         int size;
3822
3823         size = dsparb & 0x1ff;
3824         if (plane)
3825                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3826         size >>= 1; /* Convert to cachelines */
3827
3828         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3829                       plane ? "B" : "A", size);
3830
3831         return size;
3832 }
3833
3834 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3835 {
3836         struct drm_i915_private *dev_priv = dev->dev_private;
3837         uint32_t dsparb = I915_READ(DSPARB);
3838         int size;
3839
3840         size = dsparb & 0x7f;
3841         size >>= 2; /* Convert to cachelines */
3842
3843         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3844                       plane ? "B" : "A",
3845                       size);
3846
3847         return size;
3848 }
3849
3850 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3851 {
3852         struct drm_i915_private *dev_priv = dev->dev_private;
3853         uint32_t dsparb = I915_READ(DSPARB);
3854         int size;
3855
3856         size = dsparb & 0x7f;
3857         size >>= 1; /* Convert to cachelines */
3858
3859         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3860                       plane ? "B" : "A", size);
3861
3862         return size;
3863 }
3864
3865 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3866 {
3867         struct drm_crtc *crtc, *enabled = NULL;
3868
3869         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3870                 if (crtc->enabled && crtc->fb) {
3871                         if (enabled)
3872                                 return NULL;
3873                         enabled = crtc;
3874                 }
3875         }
3876
3877         return enabled;
3878 }
3879
3880 static void pineview_update_wm(struct drm_device *dev)
3881 {
3882         struct drm_i915_private *dev_priv = dev->dev_private;
3883         struct drm_crtc *crtc;
3884         const struct cxsr_latency *latency;
3885         u32 reg;
3886         unsigned long wm;
3887
3888         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3889                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3890         if (!latency) {
3891                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3892                 pineview_disable_cxsr(dev);
3893                 return;
3894         }
3895
3896         crtc = single_enabled_crtc(dev);
3897         if (crtc) {
3898                 int clock = crtc->mode.clock;
3899                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3900
3901                 /* Display SR */
3902                 wm = intel_calculate_wm(clock, &pineview_display_wm,
3903                                         pineview_display_wm.fifo_size,
3904                                         pixel_size, latency->display_sr);
3905                 reg = I915_READ(DSPFW1);
3906                 reg &= ~DSPFW_SR_MASK;
3907                 reg |= wm << DSPFW_SR_SHIFT;
3908                 I915_WRITE(DSPFW1, reg);
3909                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3910
3911                 /* cursor SR */
3912                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3913                                         pineview_display_wm.fifo_size,
3914                                         pixel_size, latency->cursor_sr);
3915                 reg = I915_READ(DSPFW3);
3916                 reg &= ~DSPFW_CURSOR_SR_MASK;
3917                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3918                 I915_WRITE(DSPFW3, reg);
3919
3920                 /* Display HPLL off SR */
3921                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3922                                         pineview_display_hplloff_wm.fifo_size,
3923                                         pixel_size, latency->display_hpll_disable);
3924                 reg = I915_READ(DSPFW3);
3925                 reg &= ~DSPFW_HPLL_SR_MASK;
3926                 reg |= wm & DSPFW_HPLL_SR_MASK;
3927                 I915_WRITE(DSPFW3, reg);
3928
3929                 /* cursor HPLL off SR */
3930                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3931                                         pineview_display_hplloff_wm.fifo_size,
3932                                         pixel_size, latency->cursor_hpll_disable);
3933                 reg = I915_READ(DSPFW3);
3934                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3935                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3936                 I915_WRITE(DSPFW3, reg);
3937                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3938
3939                 /* activate cxsr */
3940                 I915_WRITE(DSPFW3,
3941                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3942                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3943         } else {
3944                 pineview_disable_cxsr(dev);
3945                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3946         }
3947 }
3948
3949 static bool g4x_compute_wm0(struct drm_device *dev,
3950                             int plane,
3951                             const struct intel_watermark_params *display,
3952                             int display_latency_ns,
3953                             const struct intel_watermark_params *cursor,
3954                             int cursor_latency_ns,
3955                             int *plane_wm,
3956                             int *cursor_wm)
3957 {
3958         struct drm_crtc *crtc;
3959         int htotal, hdisplay, clock, pixel_size;
3960         int line_time_us, line_count;
3961         int entries, tlb_miss;
3962
3963         crtc = intel_get_crtc_for_plane(dev, plane);
3964         if (crtc->fb == NULL || !crtc->enabled) {
3965                 *cursor_wm = cursor->guard_size;
3966                 *plane_wm = display->guard_size;
3967                 return false;
3968         }
3969
3970         htotal = crtc->mode.htotal;
3971         hdisplay = crtc->mode.hdisplay;
3972         clock = crtc->mode.clock;
3973         pixel_size = crtc->fb->bits_per_pixel / 8;
3974
3975         /* Use the small buffer method to calculate plane watermark */
3976         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3977         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3978         if (tlb_miss > 0)
3979                 entries += tlb_miss;
3980         entries = DIV_ROUND_UP(entries, display->cacheline_size);
3981         *plane_wm = entries + display->guard_size;
3982         if (*plane_wm > (int)display->max_wm)
3983                 *plane_wm = display->max_wm;
3984
3985         /* Use the large buffer method to calculate cursor watermark */
3986         line_time_us = ((htotal * 1000) / clock);
3987         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3988         entries = line_count * 64 * pixel_size;
3989         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3990         if (tlb_miss > 0)
3991                 entries += tlb_miss;
3992         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3993         *cursor_wm = entries + cursor->guard_size;
3994         if (*cursor_wm > (int)cursor->max_wm)
3995                 *cursor_wm = (int)cursor->max_wm;
3996
3997         return true;
3998 }
3999
4000 /*
4001  * Check the wm result.
4002  *
4003  * If any calculated watermark values is larger than the maximum value that
4004  * can be programmed into the associated watermark register, that watermark
4005  * must be disabled.
4006  */
4007 static bool g4x_check_srwm(struct drm_device *dev,
4008                            int display_wm, int cursor_wm,
4009                            const struct intel_watermark_params *display,
4010                            const struct intel_watermark_params *cursor)
4011 {
4012         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4013                       display_wm, cursor_wm);
4014
4015         if (display_wm > display->max_wm) {
4016                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4017                               display_wm, display->max_wm);
4018                 return false;
4019         }
4020
4021         if (cursor_wm > cursor->max_wm) {
4022                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4023                               cursor_wm, cursor->max_wm);
4024                 return false;
4025         }
4026
4027         if (!(display_wm || cursor_wm)) {
4028                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4029                 return false;
4030         }
4031
4032         return true;
4033 }
4034
4035 static bool g4x_compute_srwm(struct drm_device *dev,
4036                              int plane,
4037                              int latency_ns,
4038                              const struct intel_watermark_params *display,
4039                              const struct intel_watermark_params *cursor,
4040                              int *display_wm, int *cursor_wm)
4041 {
4042         struct drm_crtc *crtc;
4043         int hdisplay, htotal, pixel_size, clock;
4044         unsigned long line_time_us;
4045         int line_count, line_size;
4046         int small, large;
4047         int entries;
4048
4049         if (!latency_ns) {
4050                 *display_wm = *cursor_wm = 0;
4051                 return false;
4052         }
4053
4054         crtc = intel_get_crtc_for_plane(dev, plane);
4055         hdisplay = crtc->mode.hdisplay;
4056         htotal = crtc->mode.htotal;
4057         clock = crtc->mode.clock;
4058         pixel_size = crtc->fb->bits_per_pixel / 8;
4059
4060         line_time_us = (htotal * 1000) / clock;
4061         line_count = (latency_ns / line_time_us + 1000) / 1000;
4062         line_size = hdisplay * pixel_size;
4063
4064         /* Use the minimum of the small and large buffer method for primary */
4065         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4066         large = line_count * line_size;
4067
4068         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4069         *display_wm = entries + display->guard_size;
4070
4071         /* calculate the self-refresh watermark for display cursor */
4072         entries = line_count * pixel_size * 64;
4073         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4074         *cursor_wm = entries + cursor->guard_size;
4075
4076         return g4x_check_srwm(dev,
4077                               *display_wm, *cursor_wm,
4078                               display, cursor);
4079 }
4080
4081 #define single_plane_enabled(mask) is_power_of_2(mask)
4082
4083 static void g4x_update_wm(struct drm_device *dev)
4084 {
4085         static const int sr_latency_ns = 12000;
4086         struct drm_i915_private *dev_priv = dev->dev_private;
4087         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4088         int plane_sr, cursor_sr;
4089         unsigned int enabled = 0;
4090
4091         if (g4x_compute_wm0(dev, 0,
4092                             &g4x_wm_info, latency_ns,
4093                             &g4x_cursor_wm_info, latency_ns,
4094                             &planea_wm, &cursora_wm))
4095                 enabled |= 1;
4096
4097         if (g4x_compute_wm0(dev, 1,
4098                             &g4x_wm_info, latency_ns,
4099                             &g4x_cursor_wm_info, latency_ns,
4100                             &planeb_wm, &cursorb_wm))
4101                 enabled |= 2;
4102
4103         plane_sr = cursor_sr = 0;
4104         if (single_plane_enabled(enabled) &&
4105             g4x_compute_srwm(dev, ffs(enabled) - 1,
4106                              sr_latency_ns,
4107                              &g4x_wm_info,
4108                              &g4x_cursor_wm_info,
4109                              &plane_sr, &cursor_sr))
4110                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4111         else
4112                 I915_WRITE(FW_BLC_SELF,
4113                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4114
4115         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4116                       planea_wm, cursora_wm,
4117                       planeb_wm, cursorb_wm,
4118                       plane_sr, cursor_sr);
4119
4120         I915_WRITE(DSPFW1,
4121                    (plane_sr << DSPFW_SR_SHIFT) |
4122                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4123                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
4124                    planea_wm);
4125         I915_WRITE(DSPFW2,
4126                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4127                    (cursora_wm << DSPFW_CURSORA_SHIFT));
4128         /* HPLL off in SR has some issues on G4x... disable it */
4129         I915_WRITE(DSPFW3,
4130                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4131                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4132 }
4133
4134 static void i965_update_wm(struct drm_device *dev)
4135 {
4136         struct drm_i915_private *dev_priv = dev->dev_private;
4137         struct drm_crtc *crtc;
4138         int srwm = 1;
4139         int cursor_sr = 16;
4140
4141         /* Calc sr entries for one plane configs */
4142         crtc = single_enabled_crtc(dev);
4143         if (crtc) {
4144                 /* self-refresh has much higher latency */
4145                 static const int sr_latency_ns = 12000;
4146                 int clock = crtc->mode.clock;
4147                 int htotal = crtc->mode.htotal;
4148                 int hdisplay = crtc->mode.hdisplay;
4149                 int pixel_size = crtc->fb->bits_per_pixel / 8;
4150                 unsigned long line_time_us;
4151                 int entries;
4152
4153                 line_time_us = ((htotal * 1000) / clock);
4154
4155                 /* Use ns/us then divide to preserve precision */
4156                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4157                         pixel_size * hdisplay;
4158                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4159                 srwm = I965_FIFO_SIZE - entries;
4160                 if (srwm < 0)
4161                         srwm = 1;
4162                 srwm &= 0x1ff;
4163                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4164                               entries, srwm);
4165
4166                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4167                         pixel_size * 64;
4168                 entries = DIV_ROUND_UP(entries,
4169                                           i965_cursor_wm_info.cacheline_size);
4170                 cursor_sr = i965_cursor_wm_info.fifo_size -
4171                         (entries + i965_cursor_wm_info.guard_size);
4172
4173                 if (cursor_sr > i965_cursor_wm_info.max_wm)
4174                         cursor_sr = i965_cursor_wm_info.max_wm;
4175
4176                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4177                               "cursor %d\n", srwm, cursor_sr);
4178
4179                 if (IS_CRESTLINE(dev))
4180                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4181         } else {
4182                 /* Turn off self refresh if both pipes are enabled */
4183                 if (IS_CRESTLINE(dev))
4184                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4185                                    & ~FW_BLC_SELF_EN);
4186         }
4187
4188         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4189                       srwm);
4190
4191         /* 965 has limitations... */
4192         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4193                    (8 << 16) | (8 << 8) | (8 << 0));
4194         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4195         /* update cursor SR watermark */
4196         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4197 }
4198
4199 static void i9xx_update_wm(struct drm_device *dev)
4200 {
4201         struct drm_i915_private *dev_priv = dev->dev_private;
4202         const struct intel_watermark_params *wm_info;
4203         uint32_t fwater_lo;
4204         uint32_t fwater_hi;
4205         int cwm, srwm = 1;
4206         int fifo_size;
4207         int planea_wm, planeb_wm;
4208         struct drm_crtc *crtc, *enabled = NULL;
4209
4210         if (IS_I945GM(dev))
4211                 wm_info = &i945_wm_info;
4212         else if (!IS_GEN2(dev))
4213                 wm_info = &i915_wm_info;
4214         else
4215                 wm_info = &i855_wm_info;
4216
4217         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4218         crtc = intel_get_crtc_for_plane(dev, 0);
4219         if (crtc->enabled && crtc->fb) {
4220                 planea_wm = intel_calculate_wm(crtc->mode.clock,
4221                                                wm_info, fifo_size,
4222                                                crtc->fb->bits_per_pixel / 8,
4223                                                latency_ns);
4224                 enabled = crtc;
4225         } else
4226                 planea_wm = fifo_size - wm_info->guard_size;
4227
4228         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4229         crtc = intel_get_crtc_for_plane(dev, 1);
4230         if (crtc->enabled && crtc->fb) {
4231                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4232                                                wm_info, fifo_size,
4233                                                crtc->fb->bits_per_pixel / 8,
4234                                                latency_ns);
4235                 if (enabled == NULL)
4236                         enabled = crtc;
4237                 else
4238                         enabled = NULL;
4239         } else
4240                 planeb_wm = fifo_size - wm_info->guard_size;
4241
4242         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4243
4244         /*
4245          * Overlay gets an aggressive default since video jitter is bad.
4246          */
4247         cwm = 2;
4248
4249         /* Play safe and disable self-refresh before adjusting watermarks. */
4250         if (IS_I945G(dev) || IS_I945GM(dev))
4251                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4252         else if (IS_I915GM(dev))
4253                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4254
4255         /* Calc sr entries for one plane configs */
4256         if (HAS_FW_BLC(dev) && enabled) {
4257                 /* self-refresh has much higher latency */
4258                 static const int sr_latency_ns = 6000;
4259                 int clock = enabled->mode.clock;
4260                 int htotal = enabled->mode.htotal;
4261                 int hdisplay = enabled->mode.hdisplay;
4262                 int pixel_size = enabled->fb->bits_per_pixel / 8;
4263                 unsigned long line_time_us;
4264                 int entries;
4265
4266                 line_time_us = (htotal * 1000) / clock;
4267
4268                 /* Use ns/us then divide to preserve precision */
4269                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4270                         pixel_size * hdisplay;
4271                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4272                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4273                 srwm = wm_info->fifo_size - entries;
4274                 if (srwm < 0)
4275                         srwm = 1;
4276
4277                 if (IS_I945G(dev) || IS_I945GM(dev))
4278                         I915_WRITE(FW_BLC_SELF,
4279                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4280                 else if (IS_I915GM(dev))
4281                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4282         }
4283
4284         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4285                       planea_wm, planeb_wm, cwm, srwm);
4286
4287         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4288         fwater_hi = (cwm & 0x1f);
4289
4290         /* Set request length to 8 cachelines per fetch */
4291         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4292         fwater_hi = fwater_hi | (1 << 8);
4293
4294         I915_WRITE(FW_BLC, fwater_lo);
4295         I915_WRITE(FW_BLC2, fwater_hi);
4296
4297         if (HAS_FW_BLC(dev)) {
4298                 if (enabled) {
4299                         if (IS_I945G(dev) || IS_I945GM(dev))
4300                                 I915_WRITE(FW_BLC_SELF,
4301                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4302                         else if (IS_I915GM(dev))
4303                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4304                         DRM_DEBUG_KMS("memory self refresh enabled\n");
4305                 } else
4306                         DRM_DEBUG_KMS("memory self refresh disabled\n");
4307         }
4308 }
4309
4310 static void i830_update_wm(struct drm_device *dev)
4311 {
4312         struct drm_i915_private *dev_priv = dev->dev_private;
4313         struct drm_crtc *crtc;
4314         uint32_t fwater_lo;
4315         int planea_wm;
4316
4317         crtc = single_enabled_crtc(dev);
4318         if (crtc == NULL)
4319                 return;
4320
4321         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4322                                        dev_priv->display.get_fifo_size(dev, 0),
4323                                        crtc->fb->bits_per_pixel / 8,
4324                                        latency_ns);
4325         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4326         fwater_lo |= (3<<8) | planea_wm;
4327
4328         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4329
4330         I915_WRITE(FW_BLC, fwater_lo);
4331 }
4332
4333 #define ILK_LP0_PLANE_LATENCY           700
4334 #define ILK_LP0_CURSOR_LATENCY          1300
4335
4336 /*
4337  * Check the wm result.
4338  *
4339  * If any calculated watermark values is larger than the maximum value that
4340  * can be programmed into the associated watermark register, that watermark
4341  * must be disabled.
4342  */
4343 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4344                                 int fbc_wm, int display_wm, int cursor_wm,
4345                                 const struct intel_watermark_params *display,
4346                                 const struct intel_watermark_params *cursor)
4347 {
4348         struct drm_i915_private *dev_priv = dev->dev_private;
4349
4350         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4351                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4352
4353         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4354                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4355                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4356
4357                 /* fbc has it's own way to disable FBC WM */
4358                 I915_WRITE(DISP_ARB_CTL,
4359                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4360                 return false;
4361         }
4362
4363         if (display_wm > display->max_wm) {
4364                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4365                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4366                 return false;
4367         }
4368
4369         if (cursor_wm > cursor->max_wm) {
4370                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4371                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4372                 return false;
4373         }
4374
4375         if (!(fbc_wm || display_wm || cursor_wm)) {
4376                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4377                 return false;
4378         }
4379
4380         return true;
4381 }
4382
4383 /*
4384  * Compute watermark values of WM[1-3],
4385  */
4386 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4387                                   int latency_ns,
4388                                   const struct intel_watermark_params *display,
4389                                   const struct intel_watermark_params *cursor,
4390                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4391 {
4392         struct drm_crtc *crtc;
4393         unsigned long line_time_us;
4394         int hdisplay, htotal, pixel_size, clock;
4395         int line_count, line_size;
4396         int small, large;
4397         int entries;
4398
4399         if (!latency_ns) {
4400                 *fbc_wm = *display_wm = *cursor_wm = 0;
4401                 return false;
4402         }
4403
4404         crtc = intel_get_crtc_for_plane(dev, plane);
4405         hdisplay = crtc->mode.hdisplay;
4406         htotal = crtc->mode.htotal;
4407         clock = crtc->mode.clock;
4408         pixel_size = crtc->fb->bits_per_pixel / 8;
4409
4410         line_time_us = (htotal * 1000) / clock;
4411         line_count = (latency_ns / line_time_us + 1000) / 1000;
4412         line_size = hdisplay * pixel_size;
4413
4414         /* Use the minimum of the small and large buffer method for primary */
4415         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4416         large = line_count * line_size;
4417
4418         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4419         *display_wm = entries + display->guard_size;
4420
4421         /*
4422          * Spec says:
4423          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4424          */
4425         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4426
4427         /* calculate the self-refresh watermark for display cursor */
4428         entries = line_count * pixel_size * 64;
4429         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4430         *cursor_wm = entries + cursor->guard_size;
4431
4432         return ironlake_check_srwm(dev, level,
4433                                    *fbc_wm, *display_wm, *cursor_wm,
4434                                    display, cursor);
4435 }
4436
4437 static void ironlake_update_wm(struct drm_device *dev)
4438 {
4439         struct drm_i915_private *dev_priv = dev->dev_private;
4440         int fbc_wm, plane_wm, cursor_wm;
4441         unsigned int enabled;
4442
4443         enabled = 0;
4444         if (g4x_compute_wm0(dev, 0,
4445                             &ironlake_display_wm_info,
4446                             ILK_LP0_PLANE_LATENCY,
4447                             &ironlake_cursor_wm_info,
4448                             ILK_LP0_CURSOR_LATENCY,
4449                             &plane_wm, &cursor_wm)) {
4450                 I915_WRITE(WM0_PIPEA_ILK,
4451                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4452                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4453                               " plane %d, " "cursor: %d\n",
4454                               plane_wm, cursor_wm);
4455                 enabled |= 1;
4456         }
4457
4458         if (g4x_compute_wm0(dev, 1,
4459                             &ironlake_display_wm_info,
4460                             ILK_LP0_PLANE_LATENCY,
4461                             &ironlake_cursor_wm_info,
4462                             ILK_LP0_CURSOR_LATENCY,
4463                             &plane_wm, &cursor_wm)) {
4464                 I915_WRITE(WM0_PIPEB_ILK,
4465                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4466                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4467                               " plane %d, cursor: %d\n",
4468                               plane_wm, cursor_wm);
4469                 enabled |= 2;
4470         }
4471
4472         /*
4473          * Calculate and update the self-refresh watermark only when one
4474          * display plane is used.
4475          */
4476         I915_WRITE(WM3_LP_ILK, 0);
4477         I915_WRITE(WM2_LP_ILK, 0);
4478         I915_WRITE(WM1_LP_ILK, 0);
4479
4480         if (!single_plane_enabled(enabled))
4481                 return;
4482         enabled = ffs(enabled) - 1;
4483
4484         /* WM1 */
4485         if (!ironlake_compute_srwm(dev, 1, enabled,
4486                                    ILK_READ_WM1_LATENCY() * 500,
4487                                    &ironlake_display_srwm_info,
4488                                    &ironlake_cursor_srwm_info,
4489                                    &fbc_wm, &plane_wm, &cursor_wm))
4490                 return;
4491
4492         I915_WRITE(WM1_LP_ILK,
4493                    WM1_LP_SR_EN |
4494                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4495                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4496                    (plane_wm << WM1_LP_SR_SHIFT) |
4497                    cursor_wm);
4498
4499         /* WM2 */
4500         if (!ironlake_compute_srwm(dev, 2, enabled,
4501                                    ILK_READ_WM2_LATENCY() * 500,
4502                                    &ironlake_display_srwm_info,
4503                                    &ironlake_cursor_srwm_info,
4504                                    &fbc_wm, &plane_wm, &cursor_wm))
4505                 return;
4506
4507         I915_WRITE(WM2_LP_ILK,
4508                    WM2_LP_EN |
4509                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4510                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4511                    (plane_wm << WM1_LP_SR_SHIFT) |
4512                    cursor_wm);
4513
4514         /*
4515          * WM3 is unsupported on ILK, probably because we don't have latency
4516          * data for that power state
4517          */
4518 }
4519
4520 void sandybridge_update_wm(struct drm_device *dev)
4521 {
4522         struct drm_i915_private *dev_priv = dev->dev_private;
4523         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4524         int fbc_wm, plane_wm, cursor_wm;
4525         unsigned int enabled;
4526
4527         enabled = 0;
4528         if (g4x_compute_wm0(dev, 0,
4529                             &sandybridge_display_wm_info, latency,
4530                             &sandybridge_cursor_wm_info, latency,
4531                             &plane_wm, &cursor_wm)) {
4532                 I915_WRITE(WM0_PIPEA_ILK,
4533                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4534                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4535                               " plane %d, " "cursor: %d\n",
4536                               plane_wm, cursor_wm);
4537                 enabled |= 1;
4538         }
4539
4540         if (g4x_compute_wm0(dev, 1,
4541                             &sandybridge_display_wm_info, latency,
4542                             &sandybridge_cursor_wm_info, latency,
4543                             &plane_wm, &cursor_wm)) {
4544                 I915_WRITE(WM0_PIPEB_ILK,
4545                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4546                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4547                               " plane %d, cursor: %d\n",
4548                               plane_wm, cursor_wm);
4549                 enabled |= 2;
4550         }
4551
4552         /* IVB has 3 pipes */
4553         if (IS_IVYBRIDGE(dev) &&
4554             g4x_compute_wm0(dev, 2,
4555                             &sandybridge_display_wm_info, latency,
4556                             &sandybridge_cursor_wm_info, latency,
4557                             &plane_wm, &cursor_wm)) {
4558                 I915_WRITE(WM0_PIPEC_IVB,
4559                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4560                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4561                               " plane %d, cursor: %d\n",
4562                               plane_wm, cursor_wm);
4563                 enabled |= 3;
4564         }
4565
4566         /*
4567          * Calculate and update the self-refresh watermark only when one
4568          * display plane is used.
4569          *
4570          * SNB support 3 levels of watermark.
4571          *
4572          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4573          * and disabled in the descending order
4574          *
4575          */
4576         I915_WRITE(WM3_LP_ILK, 0);
4577         I915_WRITE(WM2_LP_ILK, 0);
4578         I915_WRITE(WM1_LP_ILK, 0);
4579
4580         if (!single_plane_enabled(enabled) ||
4581             dev_priv->sprite_scaling_enabled)
4582                 return;
4583         enabled = ffs(enabled) - 1;
4584
4585         /* WM1 */
4586         if (!ironlake_compute_srwm(dev, 1, enabled,
4587                                    SNB_READ_WM1_LATENCY() * 500,
4588                                    &sandybridge_display_srwm_info,
4589                                    &sandybridge_cursor_srwm_info,
4590                                    &fbc_wm, &plane_wm, &cursor_wm))
4591                 return;
4592
4593         I915_WRITE(WM1_LP_ILK,
4594                    WM1_LP_SR_EN |
4595                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4596                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4597                    (plane_wm << WM1_LP_SR_SHIFT) |
4598                    cursor_wm);
4599
4600         /* WM2 */
4601         if (!ironlake_compute_srwm(dev, 2, enabled,
4602                                    SNB_READ_WM2_LATENCY() * 500,
4603                                    &sandybridge_display_srwm_info,
4604                                    &sandybridge_cursor_srwm_info,
4605                                    &fbc_wm, &plane_wm, &cursor_wm))
4606                 return;
4607
4608         I915_WRITE(WM2_LP_ILK,
4609                    WM2_LP_EN |
4610                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4611                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4612                    (plane_wm << WM1_LP_SR_SHIFT) |
4613                    cursor_wm);
4614
4615         /* WM3 */
4616         if (!ironlake_compute_srwm(dev, 3, enabled,
4617                                    SNB_READ_WM3_LATENCY() * 500,
4618                                    &sandybridge_display_srwm_info,
4619                                    &sandybridge_cursor_srwm_info,
4620                                    &fbc_wm, &plane_wm, &cursor_wm))
4621                 return;
4622
4623         I915_WRITE(WM3_LP_ILK,
4624                    WM3_LP_EN |
4625                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4626                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4627                    (plane_wm << WM1_LP_SR_SHIFT) |
4628                    cursor_wm);
4629 }
4630
4631 static bool
4632 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4633                               uint32_t sprite_width, int pixel_size,
4634                               const struct intel_watermark_params *display,
4635                               int display_latency_ns, int *sprite_wm)
4636 {
4637         struct drm_crtc *crtc;
4638         int clock;
4639         int entries, tlb_miss;
4640
4641         crtc = intel_get_crtc_for_plane(dev, plane);
4642         if (crtc->fb == NULL || !crtc->enabled) {
4643                 *sprite_wm = display->guard_size;
4644                 return false;
4645         }
4646
4647         clock = crtc->mode.clock;
4648
4649         /* Use the small buffer method to calculate the sprite watermark */
4650         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4651         tlb_miss = display->fifo_size*display->cacheline_size -
4652                 sprite_width * 8;
4653         if (tlb_miss > 0)
4654                 entries += tlb_miss;
4655         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4656         *sprite_wm = entries + display->guard_size;
4657         if (*sprite_wm > (int)display->max_wm)
4658                 *sprite_wm = display->max_wm;
4659
4660         return true;
4661 }
4662
4663 static bool
4664 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4665                                 uint32_t sprite_width, int pixel_size,
4666                                 const struct intel_watermark_params *display,
4667                                 int latency_ns, int *sprite_wm)
4668 {
4669         struct drm_crtc *crtc;
4670         unsigned long line_time_us;
4671         int clock;
4672         int line_count, line_size;
4673         int small, large;
4674         int entries;
4675
4676         if (!latency_ns) {
4677                 *sprite_wm = 0;
4678                 return false;
4679         }
4680
4681         crtc = intel_get_crtc_for_plane(dev, plane);
4682         clock = crtc->mode.clock;
4683
4684         line_time_us = (sprite_width * 1000) / clock;
4685         line_count = (latency_ns / line_time_us + 1000) / 1000;
4686         line_size = sprite_width * pixel_size;
4687
4688         /* Use the minimum of the small and large buffer method for primary */
4689         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4690         large = line_count * line_size;
4691
4692         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4693         *sprite_wm = entries + display->guard_size;
4694
4695         return *sprite_wm > 0x3ff ? false : true;
4696 }
4697
4698 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4699                                          uint32_t sprite_width, int pixel_size)
4700 {
4701         struct drm_i915_private *dev_priv = dev->dev_private;
4702         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4703         int sprite_wm, reg;
4704         int ret;
4705
4706         switch (pipe) {
4707         case 0:
4708                 reg = WM0_PIPEA_ILK;
4709                 break;
4710         case 1:
4711                 reg = WM0_PIPEB_ILK;
4712                 break;
4713         case 2:
4714                 reg = WM0_PIPEC_IVB;
4715                 break;
4716         default:
4717                 return; /* bad pipe */
4718         }
4719
4720         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4721                                             &sandybridge_display_wm_info,
4722                                             latency, &sprite_wm);
4723         if (!ret) {
4724                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4725                               pipe);
4726                 return;
4727         }
4728
4729         I915_WRITE(reg, I915_READ(reg) | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
4730         DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4731
4732
4733         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4734                                               pixel_size,
4735                                               &sandybridge_display_srwm_info,
4736                                               SNB_READ_WM1_LATENCY() * 500,
4737                                               &sprite_wm);
4738         if (!ret) {
4739                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4740                               pipe);
4741                 return;
4742         }
4743         I915_WRITE(WM1S_LP_ILK, sprite_wm);
4744
4745         /* Only IVB has two more LP watermarks for sprite */
4746         if (!IS_IVYBRIDGE(dev))
4747                 return;
4748
4749         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4750                                               pixel_size,
4751                                               &sandybridge_display_srwm_info,
4752                                               SNB_READ_WM2_LATENCY() * 500,
4753                                               &sprite_wm);
4754         if (!ret) {
4755                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4756                               pipe);
4757                 return;
4758         }
4759         I915_WRITE(WM2S_LP_IVB, sprite_wm);
4760
4761         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4762                                               pixel_size,
4763                                               &sandybridge_display_srwm_info,
4764                                               SNB_READ_WM3_LATENCY() * 500,
4765                                               &sprite_wm);
4766         if (!ret) {
4767                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4768                               pipe);
4769                 return;
4770         }
4771         I915_WRITE(WM3S_LP_IVB, sprite_wm);
4772 }
4773
4774 /**
4775  * intel_update_watermarks - update FIFO watermark values based on current modes
4776  *
4777  * Calculate watermark values for the various WM regs based on current mode
4778  * and plane configuration.
4779  *
4780  * There are several cases to deal with here:
4781  *   - normal (i.e. non-self-refresh)
4782  *   - self-refresh (SR) mode
4783  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4784  *   - lines are small relative to FIFO size (buffer can hold more than 2
4785  *     lines), so need to account for TLB latency
4786  *
4787  *   The normal calculation is:
4788  *     watermark = dotclock * bytes per pixel * latency
4789  *   where latency is platform & configuration dependent (we assume pessimal
4790  *   values here).
4791  *
4792  *   The SR calculation is:
4793  *     watermark = (trunc(latency/line time)+1) * surface width *
4794  *       bytes per pixel
4795  *   where
4796  *     line time = htotal / dotclock
4797  *     surface width = hdisplay for normal plane and 64 for cursor
4798  *   and latency is assumed to be high, as above.
4799  *
4800  * The final value programmed to the register should always be rounded up,
4801  * and include an extra 2 entries to account for clock crossings.
4802  *
4803  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4804  * to set the non-SR watermarks to 8.
4805  */
4806 static void intel_update_watermarks(struct drm_device *dev)
4807 {
4808         struct drm_i915_private *dev_priv = dev->dev_private;
4809
4810         if (dev_priv->display.update_wm)
4811                 dev_priv->display.update_wm(dev);
4812 }
4813
4814 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4815                                     uint32_t sprite_width, int pixel_size)
4816 {
4817         struct drm_i915_private *dev_priv = dev->dev_private;
4818
4819         if (dev_priv->display.update_sprite_wm)
4820                 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4821                                                    pixel_size);
4822 }
4823
4824 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4825 {
4826         if (i915_panel_use_ssc >= 0)
4827                 return i915_panel_use_ssc != 0;
4828         return dev_priv->lvds_use_ssc
4829                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4830 }
4831
4832 /**
4833  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4834  * @crtc: CRTC structure
4835  * @mode: requested mode
4836  *
4837  * A pipe may be connected to one or more outputs.  Based on the depth of the
4838  * attached framebuffer, choose a good color depth to use on the pipe.
4839  *
4840  * If possible, match the pipe depth to the fb depth.  In some cases, this
4841  * isn't ideal, because the connected output supports a lesser or restricted
4842  * set of depths.  Resolve that here:
4843  *    LVDS typically supports only 6bpc, so clamp down in that case
4844  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4845  *    Displays may support a restricted set as well, check EDID and clamp as
4846  *      appropriate.
4847  *    DP may want to dither down to 6bpc to fit larger modes
4848  *
4849  * RETURNS:
4850  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4851  * true if they don't match).
4852  */
4853 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4854                                          unsigned int *pipe_bpp,
4855                                          struct drm_display_mode *mode)
4856 {
4857         struct drm_device *dev = crtc->dev;
4858         struct drm_i915_private *dev_priv = dev->dev_private;
4859         struct drm_encoder *encoder;
4860         struct drm_connector *connector;
4861         unsigned int display_bpc = UINT_MAX, bpc;
4862
4863         /* Walk the encoders & connectors on this crtc, get min bpc */
4864         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4865                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4866
4867                 if (encoder->crtc != crtc)
4868                         continue;
4869
4870                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4871                         unsigned int lvds_bpc;
4872
4873                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4874                             LVDS_A3_POWER_UP)
4875                                 lvds_bpc = 8;
4876                         else
4877                                 lvds_bpc = 6;
4878
4879                         if (lvds_bpc < display_bpc) {
4880                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4881                                 display_bpc = lvds_bpc;
4882                         }
4883                         continue;
4884                 }
4885
4886                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4887                         /* Use VBT settings if we have an eDP panel */
4888                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4889
4890                         if (edp_bpc < display_bpc) {
4891                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4892                                 display_bpc = edp_bpc;
4893                         }
4894                         continue;
4895                 }
4896
4897                 /* Not one of the known troublemakers, check the EDID */
4898                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4899                                     head) {
4900                         if (connector->encoder != encoder)
4901                                 continue;
4902
4903                         /* Don't use an invalid EDID bpc value */
4904                         if (connector->display_info.bpc &&
4905                             connector->display_info.bpc < display_bpc) {
4906                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4907                                 display_bpc = connector->display_info.bpc;
4908                         }
4909                 }
4910
4911                 /*
4912                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4913                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4914                  */
4915                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4916                         if (display_bpc > 8 && display_bpc < 12) {
4917                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4918                                 display_bpc = 12;
4919                         } else {
4920                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4921                                 display_bpc = 8;
4922                         }
4923                 }
4924         }
4925
4926         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4927                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4928                 display_bpc = 6;
4929         }
4930
4931         /*
4932          * We could just drive the pipe at the highest bpc all the time and
4933          * enable dithering as needed, but that costs bandwidth.  So choose
4934          * the minimum value that expresses the full color range of the fb but
4935          * also stays within the max display bpc discovered above.
4936          */
4937
4938         switch (crtc->fb->depth) {
4939         case 8:
4940                 bpc = 8; /* since we go through a colormap */
4941                 break;
4942         case 15:
4943         case 16:
4944                 bpc = 6; /* min is 18bpp */
4945                 break;
4946         case 24:
4947                 bpc = 8;
4948                 break;
4949         case 30:
4950                 bpc = 10;
4951                 break;
4952         case 48:
4953                 bpc = 12;
4954                 break;
4955         default:
4956                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4957                 bpc = min((unsigned int)8, display_bpc);
4958                 break;
4959         }
4960
4961         display_bpc = min(display_bpc, bpc);
4962
4963         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4964                       bpc, display_bpc);
4965
4966         *pipe_bpp = display_bpc * 3;
4967
4968         return display_bpc != bpc;
4969 }
4970
4971 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4972                               struct drm_display_mode *mode,
4973                               struct drm_display_mode *adjusted_mode,
4974                               int x, int y,
4975                               struct drm_framebuffer *old_fb)
4976 {
4977         struct drm_device *dev = crtc->dev;
4978         struct drm_i915_private *dev_priv = dev->dev_private;
4979         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4980         int pipe = intel_crtc->pipe;
4981         int plane = intel_crtc->plane;
4982         int refclk, num_connectors = 0;
4983         intel_clock_t clock, reduced_clock;
4984         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4985         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4986         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4987         struct drm_mode_config *mode_config = &dev->mode_config;
4988         struct intel_encoder *encoder;
4989         const intel_limit_t *limit;
4990         int ret;
4991         u32 temp;
4992         u32 lvds_sync = 0;
4993
4994         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4995                 if (encoder->base.crtc != crtc)
4996                         continue;
4997
4998                 switch (encoder->type) {
4999                 case INTEL_OUTPUT_LVDS:
5000                         is_lvds = true;
5001                         break;
5002                 case INTEL_OUTPUT_SDVO:
5003                 case INTEL_OUTPUT_HDMI:
5004                         is_sdvo = true;
5005                         if (encoder->needs_tv_clock)
5006                                 is_tv = true;
5007                         break;
5008                 case INTEL_OUTPUT_DVO:
5009                         is_dvo = true;
5010                         break;
5011                 case INTEL_OUTPUT_TVOUT:
5012                         is_tv = true;
5013                         break;
5014                 case INTEL_OUTPUT_ANALOG:
5015                         is_crt = true;
5016                         break;
5017                 case INTEL_OUTPUT_DISPLAYPORT:
5018                         is_dp = true;
5019                         break;
5020                 }
5021
5022                 num_connectors++;
5023         }
5024
5025         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5026                 refclk = dev_priv->lvds_ssc_freq * 1000;
5027                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5028                               refclk / 1000);
5029         } else if (!IS_GEN2(dev)) {
5030                 refclk = 96000;
5031         } else {
5032                 refclk = 48000;
5033         }
5034
5035         /*
5036          * Returns a set of divisors for the desired target clock with the given
5037          * refclk, or FALSE.  The returned values represent the clock equation:
5038          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5039          */
5040         limit = intel_limit(crtc, refclk);
5041         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5042         if (!ok) {
5043                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5044                 return -EINVAL;
5045         }
5046
5047         /* Ensure that the cursor is valid for the new mode before changing... */
5048         intel_crtc_update_cursor(crtc, true);
5049
5050         if (is_lvds && dev_priv->lvds_downclock_avail) {
5051                 has_reduced_clock = limit->find_pll(limit, crtc,
5052                                                     dev_priv->lvds_downclock,
5053                                                     refclk,
5054                                                     &reduced_clock);
5055                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5056                         /*
5057                          * If the different P is found, it means that we can't
5058                          * switch the display clock by using the FP0/FP1.
5059                          * In such case we will disable the LVDS downclock
5060                          * feature.
5061                          */
5062                         DRM_DEBUG_KMS("Different P is found for "
5063                                       "LVDS clock/downclock\n");
5064                         has_reduced_clock = 0;
5065                 }
5066         }
5067         /* SDVO TV has fixed PLL values depend on its clock range,
5068            this mirrors vbios setting. */
5069         if (is_sdvo && is_tv) {
5070                 if (adjusted_mode->clock >= 100000
5071                     && adjusted_mode->clock < 140500) {
5072                         clock.p1 = 2;
5073                         clock.p2 = 10;
5074                         clock.n = 3;
5075                         clock.m1 = 16;
5076                         clock.m2 = 8;
5077                 } else if (adjusted_mode->clock >= 140500
5078                            && adjusted_mode->clock <= 200000) {
5079                         clock.p1 = 1;
5080                         clock.p2 = 10;
5081                         clock.n = 6;
5082                         clock.m1 = 12;
5083                         clock.m2 = 8;
5084                 }
5085         }
5086
5087         if (IS_PINEVIEW(dev)) {
5088                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
5089                 if (has_reduced_clock)
5090                         fp2 = (1 << reduced_clock.n) << 16 |
5091                                 reduced_clock.m1 << 8 | reduced_clock.m2;
5092         } else {
5093                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5094                 if (has_reduced_clock)
5095                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5096                                 reduced_clock.m2;
5097         }
5098
5099         dpll = DPLL_VGA_MODE_DIS;
5100
5101         if (!IS_GEN2(dev)) {
5102                 if (is_lvds)
5103                         dpll |= DPLLB_MODE_LVDS;
5104                 else
5105                         dpll |= DPLLB_MODE_DAC_SERIAL;
5106                 if (is_sdvo) {
5107                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5108                         if (pixel_multiplier > 1) {
5109                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5110                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
5111                         }
5112                         dpll |= DPLL_DVO_HIGH_SPEED;
5113                 }
5114                 if (is_dp)
5115                         dpll |= DPLL_DVO_HIGH_SPEED;
5116
5117                 /* compute bitmask from p1 value */
5118                 if (IS_PINEVIEW(dev))
5119                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5120                 else {
5121                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5122                         if (IS_G4X(dev) && has_reduced_clock)
5123                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5124                 }
5125                 switch (clock.p2) {
5126                 case 5:
5127                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5128                         break;
5129                 case 7:
5130                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5131                         break;
5132                 case 10:
5133                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5134                         break;
5135                 case 14:
5136                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5137                         break;
5138                 }
5139                 if (INTEL_INFO(dev)->gen >= 4)
5140                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5141         } else {
5142                 if (is_lvds) {
5143                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5144                 } else {
5145                         if (clock.p1 == 2)
5146                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
5147                         else
5148                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5149                         if (clock.p2 == 4)
5150                                 dpll |= PLL_P2_DIVIDE_BY_4;
5151                 }
5152         }
5153
5154         if (is_sdvo && is_tv)
5155                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5156         else if (is_tv)
5157                 /* XXX: just matching BIOS for now */
5158                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5159                 dpll |= 3;
5160         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5161                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5162         else
5163                 dpll |= PLL_REF_INPUT_DREFCLK;
5164
5165         /* setup pipeconf */
5166         pipeconf = I915_READ(PIPECONF(pipe));
5167
5168         /* Set up the display plane register */
5169         dspcntr = DISPPLANE_GAMMA_ENABLE;
5170
5171         /* Ironlake's plane is forced to pipe, bit 24 is to
5172            enable color space conversion */
5173         if (pipe == 0)
5174                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5175         else
5176                 dspcntr |= DISPPLANE_SEL_PIPE_B;
5177
5178         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5179                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5180                  * core speed.
5181                  *
5182                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5183                  * pipe == 0 check?
5184                  */
5185                 if (mode->clock >
5186                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5187                         pipeconf |= PIPECONF_DOUBLE_WIDE;
5188                 else
5189                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5190         }
5191
5192         /* default to 8bpc */
5193         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5194         if (is_dp) {
5195                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5196                         pipeconf |= PIPECONF_BPP_6 |
5197                                     PIPECONF_DITHER_EN |
5198                                     PIPECONF_DITHER_TYPE_SP;
5199                 }
5200         }
5201
5202         dpll |= DPLL_VCO_ENABLE;
5203
5204         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5205         drm_mode_debug_printmodeline(mode);
5206
5207         I915_WRITE(FP0(pipe), fp);
5208         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5209
5210         POSTING_READ(DPLL(pipe));
5211         udelay(150);
5212
5213         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5214          * This is an exception to the general rule that mode_set doesn't turn
5215          * things on.
5216          */
5217         if (is_lvds) {
5218                 temp = I915_READ(LVDS);
5219                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5220                 if (pipe == 1) {
5221                         temp |= LVDS_PIPEB_SELECT;
5222                 } else {
5223                         temp &= ~LVDS_PIPEB_SELECT;
5224                 }
5225                 /* set the corresponsding LVDS_BORDER bit */
5226                 temp |= dev_priv->lvds_border_bits;
5227                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5228                  * set the DPLLs for dual-channel mode or not.
5229                  */
5230                 if (clock.p2 == 7)
5231                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5232                 else
5233                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5234
5235                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5236                  * appropriately here, but we need to look more thoroughly into how
5237                  * panels behave in the two modes.
5238                  */
5239                 /* set the dithering flag on LVDS as needed */
5240                 if (INTEL_INFO(dev)->gen >= 4) {
5241                         if (dev_priv->lvds_dither)
5242                                 temp |= LVDS_ENABLE_DITHER;
5243                         else
5244                                 temp &= ~LVDS_ENABLE_DITHER;
5245                 }
5246                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5247                         lvds_sync |= LVDS_HSYNC_POLARITY;
5248                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5249                         lvds_sync |= LVDS_VSYNC_POLARITY;
5250                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5251                     != lvds_sync) {
5252                         char flags[2] = "-+";
5253                         DRM_INFO("Changing LVDS panel from "
5254                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5255                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5256                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5257                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5258                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5259                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5260                         temp |= lvds_sync;
5261                 }
5262                 I915_WRITE(LVDS, temp);
5263         }
5264
5265         if (is_dp) {
5266                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5267         }
5268
5269         I915_WRITE(DPLL(pipe), dpll);
5270
5271         /* Wait for the clocks to stabilize. */
5272         POSTING_READ(DPLL(pipe));
5273         udelay(150);
5274
5275         if (INTEL_INFO(dev)->gen >= 4) {
5276                 temp = 0;
5277                 if (is_sdvo) {
5278                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5279                         if (temp > 1)
5280                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5281                         else
5282                                 temp = 0;
5283                 }
5284                 I915_WRITE(DPLL_MD(pipe), temp);
5285         } else {
5286                 /* The pixel multiplier can only be updated once the
5287                  * DPLL is enabled and the clocks are stable.
5288                  *
5289                  * So write it again.
5290                  */
5291                 I915_WRITE(DPLL(pipe), dpll);
5292         }
5293
5294         intel_crtc->lowfreq_avail = false;
5295         if (is_lvds && has_reduced_clock && i915_powersave) {
5296                 I915_WRITE(FP1(pipe), fp2);
5297                 intel_crtc->lowfreq_avail = true;
5298                 if (HAS_PIPE_CXSR(dev)) {
5299                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5300                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5301                 }
5302         } else {
5303                 I915_WRITE(FP1(pipe), fp);
5304                 if (HAS_PIPE_CXSR(dev)) {
5305                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5306                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5307                 }
5308         }
5309
5310         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5311                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5312                 /* the chip adds 2 halflines automatically */
5313                 adjusted_mode->crtc_vdisplay -= 1;
5314                 adjusted_mode->crtc_vtotal -= 1;
5315                 adjusted_mode->crtc_vblank_start -= 1;
5316                 adjusted_mode->crtc_vblank_end -= 1;
5317                 adjusted_mode->crtc_vsync_end -= 1;
5318                 adjusted_mode->crtc_vsync_start -= 1;
5319         } else
5320                 pipeconf &= ~PIPECONF_INTERLACE_MASK; /* progressive */
5321
5322         I915_WRITE(HTOTAL(pipe),
5323                    (adjusted_mode->crtc_hdisplay - 1) |
5324                    ((adjusted_mode->crtc_htotal - 1) << 16));
5325         I915_WRITE(HBLANK(pipe),
5326                    (adjusted_mode->crtc_hblank_start - 1) |
5327                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5328         I915_WRITE(HSYNC(pipe),
5329                    (adjusted_mode->crtc_hsync_start - 1) |
5330                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5331
5332         I915_WRITE(VTOTAL(pipe),
5333                    (adjusted_mode->crtc_vdisplay - 1) |
5334                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5335         I915_WRITE(VBLANK(pipe),
5336                    (adjusted_mode->crtc_vblank_start - 1) |
5337                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5338         I915_WRITE(VSYNC(pipe),
5339                    (adjusted_mode->crtc_vsync_start - 1) |
5340                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5341
5342         /* pipesrc and dspsize control the size that is scaled from,
5343          * which should always be the user's requested size.
5344          */
5345         I915_WRITE(DSPSIZE(plane),
5346                    ((mode->vdisplay - 1) << 16) |
5347                    (mode->hdisplay - 1));
5348         I915_WRITE(DSPPOS(plane), 0);
5349         I915_WRITE(PIPESRC(pipe),
5350                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5351
5352         I915_WRITE(PIPECONF(pipe), pipeconf);
5353         POSTING_READ(PIPECONF(pipe));
5354         intel_enable_pipe(dev_priv, pipe, false);
5355
5356         intel_wait_for_vblank(dev, pipe);
5357
5358         I915_WRITE(DSPCNTR(plane), dspcntr);
5359         POSTING_READ(DSPCNTR(plane));
5360         intel_enable_plane(dev_priv, plane, pipe);
5361
5362         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5363
5364         intel_update_watermarks(dev);
5365
5366         return ret;
5367 }
5368
5369 /*
5370  * Initialize reference clocks when the driver loads
5371  */
5372 void ironlake_init_pch_refclk(struct drm_device *dev)
5373 {
5374         struct drm_i915_private *dev_priv = dev->dev_private;
5375         struct drm_mode_config *mode_config = &dev->mode_config;
5376         struct intel_encoder *encoder;
5377         u32 temp;
5378         bool has_lvds = false;
5379         bool has_cpu_edp = false;
5380         bool has_pch_edp = false;
5381         bool has_panel = false;
5382         bool has_ck505 = false;
5383         bool can_ssc = false;
5384
5385         /* We need to take the global config into account */
5386         list_for_each_entry(encoder, &mode_config->encoder_list,
5387                             base.head) {
5388                 switch (encoder->type) {
5389                 case INTEL_OUTPUT_LVDS:
5390                         has_panel = true;
5391                         has_lvds = true;
5392                         break;
5393                 case INTEL_OUTPUT_EDP:
5394                         has_panel = true;
5395                         if (intel_encoder_is_pch_edp(&encoder->base))
5396                                 has_pch_edp = true;
5397                         else
5398                                 has_cpu_edp = true;
5399                         break;
5400                 }
5401         }
5402
5403         if (HAS_PCH_IBX(dev)) {
5404                 has_ck505 = dev_priv->display_clock_mode;
5405                 can_ssc = has_ck505;
5406         } else {
5407                 has_ck505 = false;
5408                 can_ssc = true;
5409         }
5410
5411         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5412                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5413                       has_ck505);
5414
5415         /* Ironlake: try to setup display ref clock before DPLL
5416          * enabling. This is only under driver's control after
5417          * PCH B stepping, previous chipset stepping should be
5418          * ignoring this setting.
5419          */
5420         temp = I915_READ(PCH_DREF_CONTROL);
5421         /* Always enable nonspread source */
5422         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5423
5424         if (has_ck505)
5425                 temp |= DREF_NONSPREAD_CK505_ENABLE;
5426         else
5427                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5428
5429         if (has_panel) {
5430                 temp &= ~DREF_SSC_SOURCE_MASK;
5431                 temp |= DREF_SSC_SOURCE_ENABLE;
5432
5433                 /* SSC must be turned on before enabling the CPU output  */
5434                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5435                         DRM_DEBUG_KMS("Using SSC on panel\n");
5436                         temp |= DREF_SSC1_ENABLE;
5437                 }
5438
5439                 /* Get SSC going before enabling the outputs */
5440                 I915_WRITE(PCH_DREF_CONTROL, temp);
5441                 POSTING_READ(PCH_DREF_CONTROL);
5442                 udelay(200);
5443
5444                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5445
5446                 /* Enable CPU source on CPU attached eDP */
5447                 if (has_cpu_edp) {
5448                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5449                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5450                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5451                         }
5452                         else
5453                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5454                 } else
5455                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5456
5457                 I915_WRITE(PCH_DREF_CONTROL, temp);
5458                 POSTING_READ(PCH_DREF_CONTROL);
5459                 udelay(200);
5460         } else {
5461                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5462
5463                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5464
5465                 /* Turn off CPU output */
5466                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5467
5468                 I915_WRITE(PCH_DREF_CONTROL, temp);
5469                 POSTING_READ(PCH_DREF_CONTROL);
5470                 udelay(200);
5471
5472                 /* Turn off the SSC source */
5473                 temp &= ~DREF_SSC_SOURCE_MASK;
5474                 temp |= DREF_SSC_SOURCE_DISABLE;
5475
5476                 /* Turn off SSC1 */
5477                 temp &= ~ DREF_SSC1_ENABLE;
5478
5479                 I915_WRITE(PCH_DREF_CONTROL, temp);
5480                 POSTING_READ(PCH_DREF_CONTROL);
5481                 udelay(200);
5482         }
5483 }
5484
5485 static int ironlake_get_refclk(struct drm_crtc *crtc)
5486 {
5487         struct drm_device *dev = crtc->dev;
5488         struct drm_i915_private *dev_priv = dev->dev_private;
5489         struct intel_encoder *encoder;
5490         struct drm_mode_config *mode_config = &dev->mode_config;
5491         struct intel_encoder *edp_encoder = NULL;
5492         int num_connectors = 0;
5493         bool is_lvds = false;
5494
5495         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5496                 if (encoder->base.crtc != crtc)
5497                         continue;
5498
5499                 switch (encoder->type) {
5500                 case INTEL_OUTPUT_LVDS:
5501                         is_lvds = true;
5502                         break;
5503                 case INTEL_OUTPUT_EDP:
5504                         edp_encoder = encoder;
5505                         break;
5506                 }
5507                 num_connectors++;
5508         }
5509
5510         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5511                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5512                               dev_priv->lvds_ssc_freq);
5513                 return dev_priv->lvds_ssc_freq * 1000;
5514         }
5515
5516         return 120000;
5517 }
5518
5519 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5520                                   struct drm_display_mode *mode,
5521                                   struct drm_display_mode *adjusted_mode,
5522                                   int x, int y,
5523                                   struct drm_framebuffer *old_fb)
5524 {
5525         struct drm_device *dev = crtc->dev;
5526         struct drm_i915_private *dev_priv = dev->dev_private;
5527         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5528         int pipe = intel_crtc->pipe;
5529         int plane = intel_crtc->plane;
5530         int refclk, num_connectors = 0;
5531         intel_clock_t clock, reduced_clock;
5532         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5533         bool ok, has_reduced_clock = false, is_sdvo = false;
5534         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5535         struct intel_encoder *has_edp_encoder = NULL;
5536         struct drm_mode_config *mode_config = &dev->mode_config;
5537         struct intel_encoder *encoder;
5538         const intel_limit_t *limit;
5539         int ret;
5540         struct fdi_m_n m_n = {0};
5541         u32 temp;
5542         u32 lvds_sync = 0;
5543         int target_clock, pixel_multiplier, lane, link_bw, factor;
5544         unsigned int pipe_bpp;
5545         bool dither;
5546
5547         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5548                 if (encoder->base.crtc != crtc)
5549                         continue;
5550
5551                 switch (encoder->type) {
5552                 case INTEL_OUTPUT_LVDS:
5553                         is_lvds = true;
5554                         break;
5555                 case INTEL_OUTPUT_SDVO:
5556                 case INTEL_OUTPUT_HDMI:
5557                         is_sdvo = true;
5558                         if (encoder->needs_tv_clock)
5559                                 is_tv = true;
5560                         break;
5561                 case INTEL_OUTPUT_TVOUT:
5562                         is_tv = true;
5563                         break;
5564                 case INTEL_OUTPUT_ANALOG:
5565                         is_crt = true;
5566                         break;
5567                 case INTEL_OUTPUT_DISPLAYPORT:
5568                         is_dp = true;
5569                         break;
5570                 case INTEL_OUTPUT_EDP:
5571                         has_edp_encoder = encoder;
5572                         break;
5573                 }
5574
5575                 num_connectors++;
5576         }
5577
5578         refclk = ironlake_get_refclk(crtc);
5579
5580         /*
5581          * Returns a set of divisors for the desired target clock with the given
5582          * refclk, or FALSE.  The returned values represent the clock equation:
5583          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5584          */
5585         limit = intel_limit(crtc, refclk);
5586         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5587         if (!ok) {
5588                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5589                 return -EINVAL;
5590         }
5591
5592         /* Ensure that the cursor is valid for the new mode before changing... */
5593         intel_crtc_update_cursor(crtc, true);
5594
5595         if (is_lvds && dev_priv->lvds_downclock_avail) {
5596                 has_reduced_clock = limit->find_pll(limit, crtc,
5597                                                     dev_priv->lvds_downclock,
5598                                                     refclk,
5599                                                     &reduced_clock);
5600                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5601                         /*
5602                          * If the different P is found, it means that we can't
5603                          * switch the display clock by using the FP0/FP1.
5604                          * In such case we will disable the LVDS downclock
5605                          * feature.
5606                          */
5607                         DRM_DEBUG_KMS("Different P is found for "
5608                                       "LVDS clock/downclock\n");
5609                         has_reduced_clock = 0;
5610                 }
5611         }
5612         /* SDVO TV has fixed PLL values depend on its clock range,
5613            this mirrors vbios setting. */
5614         if (is_sdvo && is_tv) {
5615                 if (adjusted_mode->clock >= 100000
5616                     && adjusted_mode->clock < 140500) {
5617                         clock.p1 = 2;
5618                         clock.p2 = 10;
5619                         clock.n = 3;
5620                         clock.m1 = 16;
5621                         clock.m2 = 8;
5622                 } else if (adjusted_mode->clock >= 140500
5623                            && adjusted_mode->clock <= 200000) {
5624                         clock.p1 = 1;
5625                         clock.p2 = 10;
5626                         clock.n = 6;
5627                         clock.m1 = 12;
5628                         clock.m2 = 8;
5629                 }
5630         }
5631
5632         /* FDI link */
5633         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5634         lane = 0;
5635         /* CPU eDP doesn't require FDI link, so just set DP M/N
5636            according to current link config */
5637         if (has_edp_encoder &&
5638             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5639                 target_clock = mode->clock;
5640                 intel_edp_link_config(has_edp_encoder,
5641                                       &lane, &link_bw);
5642         } else {
5643                 /* [e]DP over FDI requires target mode clock
5644                    instead of link clock */
5645                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5646                         target_clock = mode->clock;
5647                 else
5648                         target_clock = adjusted_mode->clock;
5649
5650                 /* FDI is a binary signal running at ~2.7GHz, encoding
5651                  * each output octet as 10 bits. The actual frequency
5652                  * is stored as a divider into a 100MHz clock, and the
5653                  * mode pixel clock is stored in units of 1KHz.
5654                  * Hence the bw of each lane in terms of the mode signal
5655                  * is:
5656                  */
5657                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5658         }
5659
5660         /* determine panel color depth */
5661         temp = I915_READ(PIPECONF(pipe));
5662         temp &= ~PIPE_BPC_MASK;
5663         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5664         switch (pipe_bpp) {
5665         case 18:
5666                 temp |= PIPE_6BPC;
5667                 break;
5668         case 24:
5669                 temp |= PIPE_8BPC;
5670                 break;
5671         case 30:
5672                 temp |= PIPE_10BPC;
5673                 break;
5674         case 36:
5675                 temp |= PIPE_12BPC;
5676                 break;
5677         default:
5678                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5679                         pipe_bpp);
5680                 temp |= PIPE_8BPC;
5681                 pipe_bpp = 24;
5682                 break;
5683         }
5684
5685         intel_crtc->bpp = pipe_bpp;
5686         I915_WRITE(PIPECONF(pipe), temp);
5687
5688         if (!lane) {
5689                 /*
5690                  * Account for spread spectrum to avoid
5691                  * oversubscribing the link. Max center spread
5692                  * is 2.5%; use 5% for safety's sake.
5693                  */
5694                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5695                 lane = bps / (link_bw * 8) + 1;
5696         }
5697
5698         intel_crtc->fdi_lanes = lane;
5699
5700         if (pixel_multiplier > 1)
5701                 link_bw *= pixel_multiplier;
5702         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5703                              &m_n);
5704
5705         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5706         if (has_reduced_clock)
5707                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5708                         reduced_clock.m2;
5709
5710         /* Enable autotuning of the PLL clock (if permissible) */
5711         factor = 21;
5712         if (is_lvds) {
5713                 if ((intel_panel_use_ssc(dev_priv) &&
5714                      dev_priv->lvds_ssc_freq == 100) ||
5715                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5716                         factor = 25;
5717         } else if (is_sdvo && is_tv)
5718                 factor = 20;
5719
5720         if (clock.m < factor * clock.n)
5721                 fp |= FP_CB_TUNE;
5722
5723         dpll = 0;
5724
5725         if (is_lvds)
5726                 dpll |= DPLLB_MODE_LVDS;
5727         else
5728                 dpll |= DPLLB_MODE_DAC_SERIAL;
5729         if (is_sdvo) {
5730                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5731                 if (pixel_multiplier > 1) {
5732                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5733                 }
5734                 dpll |= DPLL_DVO_HIGH_SPEED;
5735         }
5736         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5737                 dpll |= DPLL_DVO_HIGH_SPEED;
5738
5739         /* compute bitmask from p1 value */
5740         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5741         /* also FPA1 */
5742         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5743
5744         switch (clock.p2) {
5745         case 5:
5746                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5747                 break;
5748         case 7:
5749                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5750                 break;
5751         case 10:
5752                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5753                 break;
5754         case 14:
5755                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5756                 break;
5757         }
5758
5759         if (is_sdvo && is_tv)
5760                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5761         else if (is_tv)
5762                 /* XXX: just matching BIOS for now */
5763                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5764                 dpll |= 3;
5765         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5766                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5767         else
5768                 dpll |= PLL_REF_INPUT_DREFCLK;
5769
5770         /* setup pipeconf */
5771         pipeconf = I915_READ(PIPECONF(pipe));
5772
5773         /* Set up the display plane register */
5774         dspcntr = DISPPLANE_GAMMA_ENABLE;
5775
5776         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5777         drm_mode_debug_printmodeline(mode);
5778
5779         /* PCH eDP needs FDI, but CPU eDP does not */
5780         if (!intel_crtc->no_pll) {
5781                 if (!has_edp_encoder ||
5782                     intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5783                         I915_WRITE(PCH_FP0(pipe), fp);
5784                         I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5785
5786                         POSTING_READ(PCH_DPLL(pipe));
5787                         udelay(150);
5788                 }
5789         } else {
5790                 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5791                     fp == I915_READ(PCH_FP0(0))) {
5792                         intel_crtc->use_pll_a = true;
5793                         DRM_DEBUG_KMS("using pipe a dpll\n");
5794                 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5795                            fp == I915_READ(PCH_FP0(1))) {
5796                         intel_crtc->use_pll_a = false;
5797                         DRM_DEBUG_KMS("using pipe b dpll\n");
5798                 } else {
5799                         DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5800                         return -EINVAL;
5801                 }
5802         }
5803
5804         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5805          * This is an exception to the general rule that mode_set doesn't turn
5806          * things on.
5807          */
5808         if (is_lvds) {
5809                 temp = I915_READ(PCH_LVDS);
5810                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5811                 if (HAS_PCH_CPT(dev))
5812                         temp |= PORT_TRANS_SEL_CPT(pipe);
5813                 else if (pipe == 1)
5814                         temp |= LVDS_PIPEB_SELECT;
5815                 else
5816                         temp &= ~LVDS_PIPEB_SELECT;
5817
5818                 /* set the corresponsding LVDS_BORDER bit */
5819                 temp |= dev_priv->lvds_border_bits;
5820                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5821                  * set the DPLLs for dual-channel mode or not.
5822                  */
5823                 if (clock.p2 == 7)
5824                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5825                 else
5826                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5827
5828                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5829                  * appropriately here, but we need to look more thoroughly into how
5830                  * panels behave in the two modes.
5831                  */
5832                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5833                         lvds_sync |= LVDS_HSYNC_POLARITY;
5834                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5835                         lvds_sync |= LVDS_VSYNC_POLARITY;
5836                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5837                     != lvds_sync) {
5838                         char flags[2] = "-+";
5839                         DRM_INFO("Changing LVDS panel from "
5840                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5841                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5842                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5843                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5844                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5845                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5846                         temp |= lvds_sync;
5847                 }
5848                 I915_WRITE(PCH_LVDS, temp);
5849         }
5850
5851         pipeconf &= ~PIPECONF_DITHER_EN;
5852         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5853         if ((is_lvds && dev_priv->lvds_dither) || dither) {
5854                 pipeconf |= PIPECONF_DITHER_EN;
5855                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
5856         }
5857         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5858                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5859         } else {
5860                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5861                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5862                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5863                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5864                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5865         }
5866
5867         if (!intel_crtc->no_pll &&
5868             (!has_edp_encoder ||
5869              intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
5870                 I915_WRITE(PCH_DPLL(pipe), dpll);
5871
5872                 /* Wait for the clocks to stabilize. */
5873                 POSTING_READ(PCH_DPLL(pipe));
5874                 udelay(150);
5875
5876                 /* The pixel multiplier can only be updated once the
5877                  * DPLL is enabled and the clocks are stable.
5878                  *
5879                  * So write it again.
5880                  */
5881                 I915_WRITE(PCH_DPLL(pipe), dpll);
5882         }
5883
5884         intel_crtc->lowfreq_avail = false;
5885         if (!intel_crtc->no_pll) {
5886                 if (is_lvds && has_reduced_clock && i915_powersave) {
5887                         I915_WRITE(PCH_FP1(pipe), fp2);
5888                         intel_crtc->lowfreq_avail = true;
5889                         if (HAS_PIPE_CXSR(dev)) {
5890                                 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5891                                 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5892                         }
5893                 } else {
5894                         I915_WRITE(PCH_FP1(pipe), fp);
5895                         if (HAS_PIPE_CXSR(dev)) {
5896                                 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5897                                 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5898                         }
5899                 }
5900         }
5901
5902         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5903                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5904                 /* the chip adds 2 halflines automatically */
5905                 adjusted_mode->crtc_vdisplay -= 1;
5906                 adjusted_mode->crtc_vtotal -= 1;
5907                 adjusted_mode->crtc_vblank_start -= 1;
5908                 adjusted_mode->crtc_vblank_end -= 1;
5909                 adjusted_mode->crtc_vsync_end -= 1;
5910                 adjusted_mode->crtc_vsync_start -= 1;
5911         } else
5912                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5913
5914         I915_WRITE(HTOTAL(pipe),
5915                    (adjusted_mode->crtc_hdisplay - 1) |
5916                    ((adjusted_mode->crtc_htotal - 1) << 16));
5917         I915_WRITE(HBLANK(pipe),
5918                    (adjusted_mode->crtc_hblank_start - 1) |
5919                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5920         I915_WRITE(HSYNC(pipe),
5921                    (adjusted_mode->crtc_hsync_start - 1) |
5922                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5923
5924         I915_WRITE(VTOTAL(pipe),
5925                    (adjusted_mode->crtc_vdisplay - 1) |
5926                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5927         I915_WRITE(VBLANK(pipe),
5928                    (adjusted_mode->crtc_vblank_start - 1) |
5929                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5930         I915_WRITE(VSYNC(pipe),
5931                    (adjusted_mode->crtc_vsync_start - 1) |
5932                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5933
5934         /* pipesrc controls the size that is scaled from, which should
5935          * always be the user's requested size.
5936          */
5937         I915_WRITE(PIPESRC(pipe),
5938                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5939
5940         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5941         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5942         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5943         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5944
5945         if (has_edp_encoder &&
5946             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5947                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5948         }
5949
5950         I915_WRITE(PIPECONF(pipe), pipeconf);
5951         POSTING_READ(PIPECONF(pipe));
5952
5953         intel_wait_for_vblank(dev, pipe);
5954
5955         if (IS_GEN5(dev)) {
5956                 /* enable address swizzle for tiling buffer */
5957                 temp = I915_READ(DISP_ARB_CTL);
5958                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5959         }
5960
5961         I915_WRITE(DSPCNTR(plane), dspcntr);
5962         POSTING_READ(DSPCNTR(plane));
5963
5964         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5965
5966         intel_update_watermarks(dev);
5967
5968         return ret;
5969 }
5970
5971 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5972                                struct drm_display_mode *mode,
5973                     &nb