Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/kaber/nf-next-2.6
[linux-2.6.git] / drivers / gpu / drm / i915 / i915_suspend.c
1 /*
2  *
3  * Copyright 2008 (c) Intel Corporation
4  *   Jesse Barnes <jbarnes@virtuousgeek.org>
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the
8  * "Software"), to deal in the Software without restriction, including
9  * without limitation the rights to use, copy, modify, merge, publish,
10  * distribute, sub license, and/or sell copies of the Software, and to
11  * permit persons to whom the Software is furnished to do so, subject to
12  * the following conditions:
13  *
14  * The above copyright notice and this permission notice (including the
15  * next paragraph) shall be included in all copies or substantial portions
16  * of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25  */
26
27 #include "drmP.h"
28 #include "drm.h"
29 #include "i915_drm.h"
30 #include "i915_drv.h"
31
32 static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
33 {
34         struct drm_i915_private *dev_priv = dev->dev_private;
35         u32     dpll_reg;
36
37         if (IS_IGDNG(dev)) {
38                 dpll_reg = (pipe == PIPE_A) ? PCH_DPLL_A: PCH_DPLL_B;
39         } else {
40                 dpll_reg = (pipe == PIPE_A) ? DPLL_A: DPLL_B;
41         }
42
43         return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
44 }
45
46 static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
47 {
48         struct drm_i915_private *dev_priv = dev->dev_private;
49         unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
50         u32 *array;
51         int i;
52
53         if (!i915_pipe_enabled(dev, pipe))
54                 return;
55
56         if (IS_IGDNG(dev))
57                 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B;
58
59         if (pipe == PIPE_A)
60                 array = dev_priv->save_palette_a;
61         else
62                 array = dev_priv->save_palette_b;
63
64         for(i = 0; i < 256; i++)
65                 array[i] = I915_READ(reg + (i << 2));
66 }
67
68 static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
69 {
70         struct drm_i915_private *dev_priv = dev->dev_private;
71         unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
72         u32 *array;
73         int i;
74
75         if (!i915_pipe_enabled(dev, pipe))
76                 return;
77
78         if (IS_IGDNG(dev))
79                 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B;
80
81         if (pipe == PIPE_A)
82                 array = dev_priv->save_palette_a;
83         else
84                 array = dev_priv->save_palette_b;
85
86         for(i = 0; i < 256; i++)
87                 I915_WRITE(reg + (i << 2), array[i]);
88 }
89
90 static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
91 {
92         struct drm_i915_private *dev_priv = dev->dev_private;
93
94         I915_WRITE8(index_port, reg);
95         return I915_READ8(data_port);
96 }
97
98 static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
99 {
100         struct drm_i915_private *dev_priv = dev->dev_private;
101
102         I915_READ8(st01);
103         I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
104         return I915_READ8(VGA_AR_DATA_READ);
105 }
106
107 static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
108 {
109         struct drm_i915_private *dev_priv = dev->dev_private;
110
111         I915_READ8(st01);
112         I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
113         I915_WRITE8(VGA_AR_DATA_WRITE, val);
114 }
115
116 static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
117 {
118         struct drm_i915_private *dev_priv = dev->dev_private;
119
120         I915_WRITE8(index_port, reg);
121         I915_WRITE8(data_port, val);
122 }
123
124 static void i915_save_vga(struct drm_device *dev)
125 {
126         struct drm_i915_private *dev_priv = dev->dev_private;
127         int i;
128         u16 cr_index, cr_data, st01;
129
130         /* VGA color palette registers */
131         dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK);
132
133         /* MSR bits */
134         dev_priv->saveMSR = I915_READ8(VGA_MSR_READ);
135         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
136                 cr_index = VGA_CR_INDEX_CGA;
137                 cr_data = VGA_CR_DATA_CGA;
138                 st01 = VGA_ST01_CGA;
139         } else {
140                 cr_index = VGA_CR_INDEX_MDA;
141                 cr_data = VGA_CR_DATA_MDA;
142                 st01 = VGA_ST01_MDA;
143         }
144
145         /* CRT controller regs */
146         i915_write_indexed(dev, cr_index, cr_data, 0x11,
147                            i915_read_indexed(dev, cr_index, cr_data, 0x11) &
148                            (~0x80));
149         for (i = 0; i <= 0x24; i++)
150                 dev_priv->saveCR[i] =
151                         i915_read_indexed(dev, cr_index, cr_data, i);
152         /* Make sure we don't turn off CR group 0 writes */
153         dev_priv->saveCR[0x11] &= ~0x80;
154
155         /* Attribute controller registers */
156         I915_READ8(st01);
157         dev_priv->saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
158         for (i = 0; i <= 0x14; i++)
159                 dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0);
160         I915_READ8(st01);
161         I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX);
162         I915_READ8(st01);
163
164         /* Graphics controller registers */
165         for (i = 0; i < 9; i++)
166                 dev_priv->saveGR[i] =
167                         i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
168
169         dev_priv->saveGR[0x10] =
170                 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
171         dev_priv->saveGR[0x11] =
172                 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
173         dev_priv->saveGR[0x18] =
174                 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
175
176         /* Sequencer registers */
177         for (i = 0; i < 8; i++)
178                 dev_priv->saveSR[i] =
179                         i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
180 }
181
182 static void i915_restore_vga(struct drm_device *dev)
183 {
184         struct drm_i915_private *dev_priv = dev->dev_private;
185         int i;
186         u16 cr_index, cr_data, st01;
187
188         /* MSR bits */
189         I915_WRITE8(VGA_MSR_WRITE, dev_priv->saveMSR);
190         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
191                 cr_index = VGA_CR_INDEX_CGA;
192                 cr_data = VGA_CR_DATA_CGA;
193                 st01 = VGA_ST01_CGA;
194         } else {
195                 cr_index = VGA_CR_INDEX_MDA;
196                 cr_data = VGA_CR_DATA_MDA;
197                 st01 = VGA_ST01_MDA;
198         }
199
200         /* Sequencer registers, don't write SR07 */
201         for (i = 0; i < 7; i++)
202                 i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
203                                    dev_priv->saveSR[i]);
204
205         /* CRT controller regs */
206         /* Enable CR group 0 writes */
207         i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
208         for (i = 0; i <= 0x24; i++)
209                 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->saveCR[i]);
210
211         /* Graphics controller regs */
212         for (i = 0; i < 9; i++)
213                 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
214                                    dev_priv->saveGR[i]);
215
216         i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
217                            dev_priv->saveGR[0x10]);
218         i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
219                            dev_priv->saveGR[0x11]);
220         i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
221                            dev_priv->saveGR[0x18]);
222
223         /* Attribute controller registers */
224         I915_READ8(st01); /* switch back to index mode */
225         for (i = 0; i <= 0x14; i++)
226                 i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0);
227         I915_READ8(st01); /* switch back to index mode */
228         I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX | 0x20);
229         I915_READ8(st01);
230
231         /* VGA color palette registers */
232         I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK);
233 }
234
235 static void i915_save_modeset_reg(struct drm_device *dev)
236 {
237         struct drm_i915_private *dev_priv = dev->dev_private;
238
239         if (drm_core_check_feature(dev, DRIVER_MODESET))
240                 return;
241
242         if (IS_IGDNG(dev)) {
243                 dev_priv->savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
244                 dev_priv->saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
245         }
246
247         /* Pipe & plane A info */
248         dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
249         dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
250         if (IS_IGDNG(dev)) {
251                 dev_priv->saveFPA0 = I915_READ(PCH_FPA0);
252                 dev_priv->saveFPA1 = I915_READ(PCH_FPA1);
253                 dev_priv->saveDPLL_A = I915_READ(PCH_DPLL_A);
254         } else {
255                 dev_priv->saveFPA0 = I915_READ(FPA0);
256                 dev_priv->saveFPA1 = I915_READ(FPA1);
257                 dev_priv->saveDPLL_A = I915_READ(DPLL_A);
258         }
259         if (IS_I965G(dev) && !IS_IGDNG(dev))
260                 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
261         dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
262         dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
263         dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
264         dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
265         dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
266         dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
267         if (!IS_IGDNG(dev))
268                 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
269
270         if (IS_IGDNG(dev)) {
271                 dev_priv->savePIPEA_DATA_M1 = I915_READ(PIPEA_DATA_M1);
272                 dev_priv->savePIPEA_DATA_N1 = I915_READ(PIPEA_DATA_N1);
273                 dev_priv->savePIPEA_LINK_M1 = I915_READ(PIPEA_LINK_M1);
274                 dev_priv->savePIPEA_LINK_N1 = I915_READ(PIPEA_LINK_N1);
275
276                 dev_priv->saveFDI_TXA_CTL = I915_READ(FDI_TXA_CTL);
277                 dev_priv->saveFDI_RXA_CTL = I915_READ(FDI_RXA_CTL);
278
279                 dev_priv->savePFA_CTL_1 = I915_READ(PFA_CTL_1);
280                 dev_priv->savePFA_WIN_SZ = I915_READ(PFA_WIN_SZ);
281                 dev_priv->savePFA_WIN_POS = I915_READ(PFA_WIN_POS);
282
283                 dev_priv->saveTRANSACONF = I915_READ(TRANSACONF);
284                 dev_priv->saveTRANS_HTOTAL_A = I915_READ(TRANS_HTOTAL_A);
285                 dev_priv->saveTRANS_HBLANK_A = I915_READ(TRANS_HBLANK_A);
286                 dev_priv->saveTRANS_HSYNC_A = I915_READ(TRANS_HSYNC_A);
287                 dev_priv->saveTRANS_VTOTAL_A = I915_READ(TRANS_VTOTAL_A);
288                 dev_priv->saveTRANS_VBLANK_A = I915_READ(TRANS_VBLANK_A);
289                 dev_priv->saveTRANS_VSYNC_A = I915_READ(TRANS_VSYNC_A);
290         }
291
292         dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
293         dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
294         dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
295         dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
296         dev_priv->saveDSPAADDR = I915_READ(DSPAADDR);
297         if (IS_I965G(dev)) {
298                 dev_priv->saveDSPASURF = I915_READ(DSPASURF);
299                 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
300         }
301         i915_save_palette(dev, PIPE_A);
302         dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT);
303
304         /* Pipe & plane B info */
305         dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
306         dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
307         if (IS_IGDNG(dev)) {
308                 dev_priv->saveFPB0 = I915_READ(PCH_FPB0);
309                 dev_priv->saveFPB1 = I915_READ(PCH_FPB1);
310                 dev_priv->saveDPLL_B = I915_READ(PCH_DPLL_B);
311         } else {
312                 dev_priv->saveFPB0 = I915_READ(FPB0);
313                 dev_priv->saveFPB1 = I915_READ(FPB1);
314                 dev_priv->saveDPLL_B = I915_READ(DPLL_B);
315         }
316         if (IS_I965G(dev) && !IS_IGDNG(dev))
317                 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
318         dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
319         dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
320         dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
321         dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
322         dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
323         dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
324         if (!IS_IGDNG(dev))
325                 dev_priv->saveBCLRPAT_B = I915_READ(BCLRPAT_B);
326
327         if (IS_IGDNG(dev)) {
328                 dev_priv->savePIPEB_DATA_M1 = I915_READ(PIPEB_DATA_M1);
329                 dev_priv->savePIPEB_DATA_N1 = I915_READ(PIPEB_DATA_N1);
330                 dev_priv->savePIPEB_LINK_M1 = I915_READ(PIPEB_LINK_M1);
331                 dev_priv->savePIPEB_LINK_N1 = I915_READ(PIPEB_LINK_N1);
332
333                 dev_priv->saveFDI_TXB_CTL = I915_READ(FDI_TXB_CTL);
334                 dev_priv->saveFDI_RXB_CTL = I915_READ(FDI_RXB_CTL);
335
336                 dev_priv->savePFB_CTL_1 = I915_READ(PFB_CTL_1);
337                 dev_priv->savePFB_WIN_SZ = I915_READ(PFB_WIN_SZ);
338                 dev_priv->savePFB_WIN_POS = I915_READ(PFB_WIN_POS);
339
340                 dev_priv->saveTRANSBCONF = I915_READ(TRANSBCONF);
341                 dev_priv->saveTRANS_HTOTAL_B = I915_READ(TRANS_HTOTAL_B);
342                 dev_priv->saveTRANS_HBLANK_B = I915_READ(TRANS_HBLANK_B);
343                 dev_priv->saveTRANS_HSYNC_B = I915_READ(TRANS_HSYNC_B);
344                 dev_priv->saveTRANS_VTOTAL_B = I915_READ(TRANS_VTOTAL_B);
345                 dev_priv->saveTRANS_VBLANK_B = I915_READ(TRANS_VBLANK_B);
346                 dev_priv->saveTRANS_VSYNC_B = I915_READ(TRANS_VSYNC_B);
347         }
348
349         dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
350         dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
351         dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
352         dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
353         dev_priv->saveDSPBADDR = I915_READ(DSPBADDR);
354         if (IS_I965GM(dev) || IS_GM45(dev)) {
355                 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
356                 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
357         }
358         i915_save_palette(dev, PIPE_B);
359         dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);
360         return;
361 }
362
363 static void i915_restore_modeset_reg(struct drm_device *dev)
364 {
365         struct drm_i915_private *dev_priv = dev->dev_private;
366         int dpll_a_reg, fpa0_reg, fpa1_reg;
367         int dpll_b_reg, fpb0_reg, fpb1_reg;
368
369         if (drm_core_check_feature(dev, DRIVER_MODESET))
370                 return;
371
372         if (IS_IGDNG(dev)) {
373                 dpll_a_reg = PCH_DPLL_A;
374                 dpll_b_reg = PCH_DPLL_B;
375                 fpa0_reg = PCH_FPA0;
376                 fpb0_reg = PCH_FPB0;
377                 fpa1_reg = PCH_FPA1;
378                 fpb1_reg = PCH_FPB1;
379         } else {
380                 dpll_a_reg = DPLL_A;
381                 dpll_b_reg = DPLL_B;
382                 fpa0_reg = FPA0;
383                 fpb0_reg = FPB0;
384                 fpa1_reg = FPA1;
385                 fpb1_reg = FPB1;
386         }
387
388         if (IS_IGDNG(dev)) {
389                 I915_WRITE(PCH_DREF_CONTROL, dev_priv->savePCH_DREF_CONTROL);
390                 I915_WRITE(DISP_ARB_CTL, dev_priv->saveDISP_ARB_CTL);
391         }
392
393         /* Pipe & plane A info */
394         /* Prime the clock */
395         if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
396                 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A &
397                            ~DPLL_VCO_ENABLE);
398                 DRM_UDELAY(150);
399         }
400         I915_WRITE(fpa0_reg, dev_priv->saveFPA0);
401         I915_WRITE(fpa1_reg, dev_priv->saveFPA1);
402         /* Actually enable it */
403         I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A);
404         DRM_UDELAY(150);
405         if (IS_I965G(dev) && !IS_IGDNG(dev))
406                 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
407         DRM_UDELAY(150);
408
409         /* Restore mode */
410         I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
411         I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
412         I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
413         I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
414         I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
415         I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
416         if (!IS_IGDNG(dev))
417                 I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
418
419         if (IS_IGDNG(dev)) {
420                 I915_WRITE(PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1);
421                 I915_WRITE(PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1);
422                 I915_WRITE(PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1);
423                 I915_WRITE(PIPEA_LINK_N1, dev_priv->savePIPEA_LINK_N1);
424
425                 I915_WRITE(FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL);
426                 I915_WRITE(FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL);
427
428                 I915_WRITE(PFA_CTL_1, dev_priv->savePFA_CTL_1);
429                 I915_WRITE(PFA_WIN_SZ, dev_priv->savePFA_WIN_SZ);
430                 I915_WRITE(PFA_WIN_POS, dev_priv->savePFA_WIN_POS);
431
432                 I915_WRITE(TRANSACONF, dev_priv->saveTRANSACONF);
433                 I915_WRITE(TRANS_HTOTAL_A, dev_priv->saveTRANS_HTOTAL_A);
434                 I915_WRITE(TRANS_HBLANK_A, dev_priv->saveTRANS_HBLANK_A);
435                 I915_WRITE(TRANS_HSYNC_A, dev_priv->saveTRANS_HSYNC_A);
436                 I915_WRITE(TRANS_VTOTAL_A, dev_priv->saveTRANS_VTOTAL_A);
437                 I915_WRITE(TRANS_VBLANK_A, dev_priv->saveTRANS_VBLANK_A);
438                 I915_WRITE(TRANS_VSYNC_A, dev_priv->saveTRANS_VSYNC_A);
439         }
440
441         /* Restore plane info */
442         I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
443         I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
444         I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
445         I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);
446         I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
447         if (IS_I965G(dev)) {
448                 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
449                 I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
450         }
451
452         I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
453
454         i915_restore_palette(dev, PIPE_A);
455         /* Enable the plane */
456         I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
457         I915_WRITE(DSPAADDR, I915_READ(DSPAADDR));
458
459         /* Pipe & plane B info */
460         if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
461                 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B &
462                            ~DPLL_VCO_ENABLE);
463                 DRM_UDELAY(150);
464         }
465         I915_WRITE(fpb0_reg, dev_priv->saveFPB0);
466         I915_WRITE(fpb1_reg, dev_priv->saveFPB1);
467         /* Actually enable it */
468         I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B);
469         DRM_UDELAY(150);
470         if (IS_I965G(dev) && !IS_IGDNG(dev))
471                 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
472         DRM_UDELAY(150);
473
474         /* Restore mode */
475         I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
476         I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
477         I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
478         I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
479         I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
480         I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
481         if (!IS_IGDNG(dev))
482                 I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
483
484         if (IS_IGDNG(dev)) {
485                 I915_WRITE(PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1);
486                 I915_WRITE(PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1);
487                 I915_WRITE(PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1);
488                 I915_WRITE(PIPEB_LINK_N1, dev_priv->savePIPEB_LINK_N1);
489
490                 I915_WRITE(FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL);
491                 I915_WRITE(FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL);
492
493                 I915_WRITE(PFB_CTL_1, dev_priv->savePFB_CTL_1);
494                 I915_WRITE(PFB_WIN_SZ, dev_priv->savePFB_WIN_SZ);
495                 I915_WRITE(PFB_WIN_POS, dev_priv->savePFB_WIN_POS);
496
497                 I915_WRITE(TRANSBCONF, dev_priv->saveTRANSBCONF);
498                 I915_WRITE(TRANS_HTOTAL_B, dev_priv->saveTRANS_HTOTAL_B);
499                 I915_WRITE(TRANS_HBLANK_B, dev_priv->saveTRANS_HBLANK_B);
500                 I915_WRITE(TRANS_HSYNC_B, dev_priv->saveTRANS_HSYNC_B);
501                 I915_WRITE(TRANS_VTOTAL_B, dev_priv->saveTRANS_VTOTAL_B);
502                 I915_WRITE(TRANS_VBLANK_B, dev_priv->saveTRANS_VBLANK_B);
503                 I915_WRITE(TRANS_VSYNC_B, dev_priv->saveTRANS_VSYNC_B);
504         }
505
506         /* Restore plane info */
507         I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
508         I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
509         I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
510         I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);
511         I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
512         if (IS_I965G(dev)) {
513                 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
514                 I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
515         }
516
517         I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
518
519         i915_restore_palette(dev, PIPE_B);
520         /* Enable the plane */
521         I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
522         I915_WRITE(DSPBADDR, I915_READ(DSPBADDR));
523
524         return;
525 }
526
527 void i915_save_display(struct drm_device *dev)
528 {
529         struct drm_i915_private *dev_priv = dev->dev_private;
530
531         /* Display arbitration control */
532         dev_priv->saveDSPARB = I915_READ(DSPARB);
533
534         /* This is only meaningful in non-KMS mode */
535         /* Don't save them in KMS mode */
536         i915_save_modeset_reg(dev);
537
538         /* Cursor state */
539         dev_priv->saveCURACNTR = I915_READ(CURACNTR);
540         dev_priv->saveCURAPOS = I915_READ(CURAPOS);
541         dev_priv->saveCURABASE = I915_READ(CURABASE);
542         dev_priv->saveCURBCNTR = I915_READ(CURBCNTR);
543         dev_priv->saveCURBPOS = I915_READ(CURBPOS);
544         dev_priv->saveCURBBASE = I915_READ(CURBBASE);
545         if (!IS_I9XX(dev))
546                 dev_priv->saveCURSIZE = I915_READ(CURSIZE);
547
548         /* CRT state */
549         if (IS_IGDNG(dev)) {
550                 dev_priv->saveADPA = I915_READ(PCH_ADPA);
551         } else {
552                 dev_priv->saveADPA = I915_READ(ADPA);
553         }
554
555         /* LVDS state */
556         if (IS_IGDNG(dev)) {
557                 dev_priv->savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
558                 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
559                 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
560                 dev_priv->saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
561                 dev_priv->saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
562                 dev_priv->saveLVDS = I915_READ(PCH_LVDS);
563         } else {
564                 dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
565                 dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
566                 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
567                 dev_priv->saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
568                 if (IS_I965G(dev))
569                         dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
570                 if (IS_MOBILE(dev) && !IS_I830(dev))
571                         dev_priv->saveLVDS = I915_READ(LVDS);
572         }
573
574         if (!IS_I830(dev) && !IS_845G(dev) && !IS_IGDNG(dev))
575                 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
576
577         if (IS_IGDNG(dev)) {
578                 dev_priv->savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
579                 dev_priv->savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
580                 dev_priv->savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
581         } else {
582                 dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
583                 dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
584                 dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
585         }
586
587         /* Display Port state */
588         if (SUPPORTS_INTEGRATED_DP(dev)) {
589                 dev_priv->saveDP_B = I915_READ(DP_B);
590                 dev_priv->saveDP_C = I915_READ(DP_C);
591                 dev_priv->saveDP_D = I915_READ(DP_D);
592                 dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(PIPEA_GMCH_DATA_M);
593                 dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(PIPEB_GMCH_DATA_M);
594                 dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(PIPEA_GMCH_DATA_N);
595                 dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(PIPEB_GMCH_DATA_N);
596                 dev_priv->savePIPEA_DP_LINK_M = I915_READ(PIPEA_DP_LINK_M);
597                 dev_priv->savePIPEB_DP_LINK_M = I915_READ(PIPEB_DP_LINK_M);
598                 dev_priv->savePIPEA_DP_LINK_N = I915_READ(PIPEA_DP_LINK_N);
599                 dev_priv->savePIPEB_DP_LINK_N = I915_READ(PIPEB_DP_LINK_N);
600         }
601         /* FIXME: save TV & SDVO state */
602
603         /* FBC state */
604         if (IS_GM45(dev)) {
605                 dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
606         } else {
607                 dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
608                 dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
609                 dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
610                 dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
611         }
612
613         /* VGA state */
614         dev_priv->saveVGA0 = I915_READ(VGA0);
615         dev_priv->saveVGA1 = I915_READ(VGA1);
616         dev_priv->saveVGA_PD = I915_READ(VGA_PD);
617         if (IS_IGDNG(dev))
618                 dev_priv->saveVGACNTRL = I915_READ(CPU_VGACNTRL);
619         else
620                 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
621
622         i915_save_vga(dev);
623 }
624
625 void i915_restore_display(struct drm_device *dev)
626 {
627         struct drm_i915_private *dev_priv = dev->dev_private;
628
629         /* Display arbitration */
630         I915_WRITE(DSPARB, dev_priv->saveDSPARB);
631
632         /* Display port ratios (must be done before clock is set) */
633         if (SUPPORTS_INTEGRATED_DP(dev)) {
634                 I915_WRITE(PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M);
635                 I915_WRITE(PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M);
636                 I915_WRITE(PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N);
637                 I915_WRITE(PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N);
638                 I915_WRITE(PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M);
639                 I915_WRITE(PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M);
640                 I915_WRITE(PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N);
641                 I915_WRITE(PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N);
642         }
643
644         /* This is only meaningful in non-KMS mode */
645         /* Don't restore them in KMS mode */
646         i915_restore_modeset_reg(dev);
647
648         /* Cursor state */
649         I915_WRITE(CURAPOS, dev_priv->saveCURAPOS);
650         I915_WRITE(CURACNTR, dev_priv->saveCURACNTR);
651         I915_WRITE(CURABASE, dev_priv->saveCURABASE);
652         I915_WRITE(CURBPOS, dev_priv->saveCURBPOS);
653         I915_WRITE(CURBCNTR, dev_priv->saveCURBCNTR);
654         I915_WRITE(CURBBASE, dev_priv->saveCURBBASE);
655         if (!IS_I9XX(dev))
656                 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
657
658         /* CRT state */
659         if (IS_IGDNG(dev))
660                 I915_WRITE(PCH_ADPA, dev_priv->saveADPA);
661         else
662                 I915_WRITE(ADPA, dev_priv->saveADPA);
663
664         /* LVDS state */
665         if (IS_I965G(dev) && !IS_IGDNG(dev))
666                 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
667
668         if (IS_IGDNG(dev)) {
669                 I915_WRITE(PCH_LVDS, dev_priv->saveLVDS);
670         } else if (IS_MOBILE(dev) && !IS_I830(dev))
671                 I915_WRITE(LVDS, dev_priv->saveLVDS);
672
673         if (!IS_I830(dev) && !IS_845G(dev) && !IS_IGDNG(dev))
674                 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
675
676         if (IS_IGDNG(dev)) {
677                 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL);
678                 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2);
679                 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL);
680                 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->saveBLC_CPU_PWM_CTL2);
681                 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
682                 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
683                 I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR);
684                 I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL);
685         } else {
686                 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
687                 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
688                 I915_WRITE(BLC_HIST_CTL, dev_priv->saveBLC_HIST_CTL);
689                 I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
690                 I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
691                 I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
692                 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
693         }
694
695         /* Display Port state */
696         if (SUPPORTS_INTEGRATED_DP(dev)) {
697                 I915_WRITE(DP_B, dev_priv->saveDP_B);
698                 I915_WRITE(DP_C, dev_priv->saveDP_C);
699                 I915_WRITE(DP_D, dev_priv->saveDP_D);
700         }
701         /* FIXME: restore TV & SDVO state */
702
703         /* FBC info */
704         if (IS_GM45(dev)) {
705                 g4x_disable_fbc(dev);
706                 I915_WRITE(DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
707         } else {
708                 i8xx_disable_fbc(dev);
709                 I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
710                 I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
711                 I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
712                 I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
713         }
714
715         /* VGA state */
716         if (IS_IGDNG(dev))
717                 I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL);
718         else
719                 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
720         I915_WRITE(VGA0, dev_priv->saveVGA0);
721         I915_WRITE(VGA1, dev_priv->saveVGA1);
722         I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
723         DRM_UDELAY(150);
724
725         i915_restore_vga(dev);
726 }
727
728 int i915_save_state(struct drm_device *dev)
729 {
730         struct drm_i915_private *dev_priv = dev->dev_private;
731         int i;
732
733         pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
734
735         /* Render Standby */
736         if (IS_I965G(dev) && IS_MOBILE(dev))
737                 dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY);
738
739         /* Hardware status page */
740         dev_priv->saveHWS = I915_READ(HWS_PGA);
741
742         i915_save_display(dev);
743
744         /* Interrupt state */
745         if (IS_IGDNG(dev)) {
746                 dev_priv->saveDEIER = I915_READ(DEIER);
747                 dev_priv->saveDEIMR = I915_READ(DEIMR);
748                 dev_priv->saveGTIER = I915_READ(GTIER);
749                 dev_priv->saveGTIMR = I915_READ(GTIMR);
750                 dev_priv->saveFDI_RXA_IMR = I915_READ(FDI_RXA_IMR);
751                 dev_priv->saveFDI_RXB_IMR = I915_READ(FDI_RXB_IMR);
752         } else {
753                 dev_priv->saveIER = I915_READ(IER);
754                 dev_priv->saveIMR = I915_READ(IMR);
755         }
756
757         /* Clock gating state */
758         dev_priv->saveD_STATE = I915_READ(D_STATE);
759         dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D); /* Not sure about this */
760
761         /* Cache mode state */
762         dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
763
764         /* Memory Arbitration state */
765         dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
766
767         /* Scratch space */
768         for (i = 0; i < 16; i++) {
769                 dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));
770                 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
771         }
772         for (i = 0; i < 3; i++)
773                 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
774
775         /* Fences */
776         if (IS_I965G(dev)) {
777                 for (i = 0; i < 16; i++)
778                         dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
779         } else {
780                 for (i = 0; i < 8; i++)
781                         dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
782
783                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
784                         for (i = 0; i < 8; i++)
785                                 dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
786         }
787
788         return 0;
789 }
790
791 int i915_restore_state(struct drm_device *dev)
792 {
793         struct drm_i915_private *dev_priv = dev->dev_private;
794         int i;
795
796         pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
797
798         /* Render Standby */
799         if (IS_I965G(dev) && IS_MOBILE(dev))
800                 I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY);
801
802         /* Hardware status page */
803         I915_WRITE(HWS_PGA, dev_priv->saveHWS);
804
805         /* Fences */
806         if (IS_I965G(dev)) {
807                 for (i = 0; i < 16; i++)
808                         I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]);
809         } else {
810                 for (i = 0; i < 8; i++)
811                         I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]);
812                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
813                         for (i = 0; i < 8; i++)
814                                 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);
815         }
816
817         i915_restore_display(dev);
818
819         /* Interrupt state */
820         if (IS_IGDNG(dev)) {
821                 I915_WRITE(DEIER, dev_priv->saveDEIER);
822                 I915_WRITE(DEIMR, dev_priv->saveDEIMR);
823                 I915_WRITE(GTIER, dev_priv->saveGTIER);
824                 I915_WRITE(GTIMR, dev_priv->saveGTIMR);
825                 I915_WRITE(FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR);
826                 I915_WRITE(FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR);
827         } else {
828                 I915_WRITE (IER, dev_priv->saveIER);
829                 I915_WRITE (IMR,  dev_priv->saveIMR);
830         }
831
832         /* Clock gating state */
833         I915_WRITE (D_STATE, dev_priv->saveD_STATE);
834         I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
835
836         /* Cache mode state */
837         I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
838
839         /* Memory arbitration state */
840         I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
841
842         for (i = 0; i < 16; i++) {
843                 I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
844                 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i]);
845         }
846         for (i = 0; i < 3; i++)
847                 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
848
849         return 0;
850 }
851