Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[linux-2.6.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2  */
3 /*
4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5  * All Rights Reserved.
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a
8  * copy of this software and associated documentation files (the
9  * "Software"), to deal in the Software without restriction, including
10  * without limitation the rights to use, copy, modify, merge, publish,
11  * distribute, sub license, and/or sell copies of the Software, and to
12  * permit persons to whom the Software is furnished to do so, subject to
13  * the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the
16  * next paragraph) shall be included in all copies or substantial portions
17  * of the Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26  *
27  */
28
29 #include <linux/sysrq.h>
30 #include <linux/slab.h>
31 #include "drmP.h"
32 #include "drm.h"
33 #include "i915_drm.h"
34 #include "i915_drv.h"
35 #include "i915_trace.h"
36 #include "intel_drv.h"
37
38 #define MAX_NOPID ((u32)~0)
39
40 /**
41  * Interrupts that are always left unmasked.
42  *
43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
44  * we leave them always unmasked in IMR and then control enabling them through
45  * PIPESTAT alone.
46  */
47 #define I915_INTERRUPT_ENABLE_FIX                       \
48         (I915_ASLE_INTERRUPT |                          \
49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
54
55 /** Interrupts that we mask and unmask at runtime. */
56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
57
58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
59                                  PIPE_VBLANK_INTERRUPT_STATUS)
60
61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
63
64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
65                                          DRM_I915_VBLANK_PIPE_B)
66
67 /* For display hotplug interrupt */
68 static void
69 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
70 {
71         if ((dev_priv->irq_mask & mask) != 0) {
72                 dev_priv->irq_mask &= ~mask;
73                 I915_WRITE(DEIMR, dev_priv->irq_mask);
74                 POSTING_READ(DEIMR);
75         }
76 }
77
78 static inline void
79 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
80 {
81         if ((dev_priv->irq_mask & mask) != mask) {
82                 dev_priv->irq_mask |= mask;
83                 I915_WRITE(DEIMR, dev_priv->irq_mask);
84                 POSTING_READ(DEIMR);
85         }
86 }
87
88 static inline u32
89 i915_pipestat(int pipe)
90 {
91         if (pipe == 0)
92                 return PIPEASTAT;
93         if (pipe == 1)
94                 return PIPEBSTAT;
95         BUG();
96 }
97
98 void
99 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
100 {
101         if ((dev_priv->pipestat[pipe] & mask) != mask) {
102                 u32 reg = i915_pipestat(pipe);
103
104                 dev_priv->pipestat[pipe] |= mask;
105                 /* Enable the interrupt, clear any pending status */
106                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
107                 POSTING_READ(reg);
108         }
109 }
110
111 void
112 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
113 {
114         if ((dev_priv->pipestat[pipe] & mask) != 0) {
115                 u32 reg = i915_pipestat(pipe);
116
117                 dev_priv->pipestat[pipe] &= ~mask;
118                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
119                 POSTING_READ(reg);
120         }
121 }
122
123 /**
124  * intel_enable_asle - enable ASLE interrupt for OpRegion
125  */
126 void intel_enable_asle(struct drm_device *dev)
127 {
128         drm_i915_private_t *dev_priv = dev->dev_private;
129         unsigned long irqflags;
130
131         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
132
133         if (HAS_PCH_SPLIT(dev))
134                 ironlake_enable_display_irq(dev_priv, DE_GSE);
135         else {
136                 i915_enable_pipestat(dev_priv, 1,
137                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
138                 if (INTEL_INFO(dev)->gen >= 4)
139                         i915_enable_pipestat(dev_priv, 0,
140                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
141         }
142
143         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
144 }
145
146 /**
147  * i915_pipe_enabled - check if a pipe is enabled
148  * @dev: DRM device
149  * @pipe: pipe to check
150  *
151  * Reading certain registers when the pipe is disabled can hang the chip.
152  * Use this routine to make sure the PLL is running and the pipe is active
153  * before reading such registers if unsure.
154  */
155 static int
156 i915_pipe_enabled(struct drm_device *dev, int pipe)
157 {
158         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
159         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
160 }
161
162 /* Called from drm generic code, passed a 'crtc', which
163  * we use as a pipe index
164  */
165 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
166 {
167         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
168         unsigned long high_frame;
169         unsigned long low_frame;
170         u32 high1, high2, low;
171
172         if (!i915_pipe_enabled(dev, pipe)) {
173                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
174                                 "pipe %d\n", pipe);
175                 return 0;
176         }
177
178         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
179         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
180
181         /*
182          * High & low register fields aren't synchronized, so make sure
183          * we get a low value that's stable across two reads of the high
184          * register.
185          */
186         do {
187                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
188                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
189                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
190         } while (high1 != high2);
191
192         high1 >>= PIPE_FRAME_HIGH_SHIFT;
193         low >>= PIPE_FRAME_LOW_SHIFT;
194         return (high1 << 8) | low;
195 }
196
197 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
198 {
199         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
200         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
201
202         if (!i915_pipe_enabled(dev, pipe)) {
203                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
204                                         "pipe %d\n", pipe);
205                 return 0;
206         }
207
208         return I915_READ(reg);
209 }
210
211 int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
212                              int *vpos, int *hpos)
213 {
214         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
215         u32 vbl = 0, position = 0;
216         int vbl_start, vbl_end, htotal, vtotal;
217         bool in_vbl = true;
218         int ret = 0;
219
220         if (!i915_pipe_enabled(dev, pipe)) {
221                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
222                                         "pipe %d\n", pipe);
223                 return 0;
224         }
225
226         /* Get vtotal. */
227         vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
228
229         if (INTEL_INFO(dev)->gen >= 4) {
230                 /* No obvious pixelcount register. Only query vertical
231                  * scanout position from Display scan line register.
232                  */
233                 position = I915_READ(PIPEDSL(pipe));
234
235                 /* Decode into vertical scanout position. Don't have
236                  * horizontal scanout position.
237                  */
238                 *vpos = position & 0x1fff;
239                 *hpos = 0;
240         } else {
241                 /* Have access to pixelcount since start of frame.
242                  * We can split this into vertical and horizontal
243                  * scanout position.
244                  */
245                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
246
247                 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
248                 *vpos = position / htotal;
249                 *hpos = position - (*vpos * htotal);
250         }
251
252         /* Query vblank area. */
253         vbl = I915_READ(VBLANK(pipe));
254
255         /* Test position against vblank region. */
256         vbl_start = vbl & 0x1fff;
257         vbl_end = (vbl >> 16) & 0x1fff;
258
259         if ((*vpos < vbl_start) || (*vpos > vbl_end))
260                 in_vbl = false;
261
262         /* Inside "upper part" of vblank area? Apply corrective offset: */
263         if (in_vbl && (*vpos >= vbl_start))
264                 *vpos = *vpos - vtotal;
265
266         /* Readouts valid? */
267         if (vbl > 0)
268                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
269
270         /* In vblank? */
271         if (in_vbl)
272                 ret |= DRM_SCANOUTPOS_INVBL;
273
274         return ret;
275 }
276
277 int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
278                               int *max_error,
279                               struct timeval *vblank_time,
280                               unsigned flags)
281 {
282         struct drm_i915_private *dev_priv = dev->dev_private;
283         struct drm_crtc *crtc;
284
285         if (pipe < 0 || pipe >= dev_priv->num_pipe) {
286                 DRM_ERROR("Invalid crtc %d\n", pipe);
287                 return -EINVAL;
288         }
289
290         /* Get drm_crtc to timestamp: */
291         crtc = intel_get_crtc_for_pipe(dev, pipe);
292         if (crtc == NULL) {
293                 DRM_ERROR("Invalid crtc %d\n", pipe);
294                 return -EINVAL;
295         }
296
297         if (!crtc->enabled) {
298                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
299                 return -EBUSY;
300         }
301
302         /* Helper routine in DRM core does all the work: */
303         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
304                                                      vblank_time, flags,
305                                                      crtc);
306 }
307
308 /*
309  * Handle hotplug events outside the interrupt handler proper.
310  */
311 static void i915_hotplug_work_func(struct work_struct *work)
312 {
313         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
314                                                     hotplug_work);
315         struct drm_device *dev = dev_priv->dev;
316         struct drm_mode_config *mode_config = &dev->mode_config;
317         struct intel_encoder *encoder;
318
319         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
320                 if (encoder->hot_plug)
321                         encoder->hot_plug(encoder);
322
323         /* Just fire off a uevent and let userspace tell us what to do */
324         drm_helper_hpd_irq_event(dev);
325 }
326
327 static void i915_handle_rps_change(struct drm_device *dev)
328 {
329         drm_i915_private_t *dev_priv = dev->dev_private;
330         u32 busy_up, busy_down, max_avg, min_avg;
331         u8 new_delay = dev_priv->cur_delay;
332
333         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
334         busy_up = I915_READ(RCPREVBSYTUPAVG);
335         busy_down = I915_READ(RCPREVBSYTDNAVG);
336         max_avg = I915_READ(RCBMAXAVG);
337         min_avg = I915_READ(RCBMINAVG);
338
339         /* Handle RCS change request from hw */
340         if (busy_up > max_avg) {
341                 if (dev_priv->cur_delay != dev_priv->max_delay)
342                         new_delay = dev_priv->cur_delay - 1;
343                 if (new_delay < dev_priv->max_delay)
344                         new_delay = dev_priv->max_delay;
345         } else if (busy_down < min_avg) {
346                 if (dev_priv->cur_delay != dev_priv->min_delay)
347                         new_delay = dev_priv->cur_delay + 1;
348                 if (new_delay > dev_priv->min_delay)
349                         new_delay = dev_priv->min_delay;
350         }
351
352         if (ironlake_set_drps(dev, new_delay))
353                 dev_priv->cur_delay = new_delay;
354
355         return;
356 }
357
358 static void notify_ring(struct drm_device *dev,
359                         struct intel_ring_buffer *ring)
360 {
361         struct drm_i915_private *dev_priv = dev->dev_private;
362         u32 seqno;
363
364         if (ring->obj == NULL)
365                 return;
366
367         seqno = ring->get_seqno(ring);
368         trace_i915_gem_request_complete(dev, seqno);
369
370         ring->irq_seqno = seqno;
371         wake_up_all(&ring->irq_queue);
372
373         dev_priv->hangcheck_count = 0;
374         mod_timer(&dev_priv->hangcheck_timer,
375                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
376 }
377
378 static void gen6_pm_irq_handler(struct drm_device *dev)
379 {
380         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
381         u8 new_delay = dev_priv->cur_delay;
382         u32 pm_iir;
383
384         pm_iir = I915_READ(GEN6_PMIIR);
385         if (!pm_iir)
386                 return;
387
388         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
389                 if (dev_priv->cur_delay != dev_priv->max_delay)
390                         new_delay = dev_priv->cur_delay + 1;
391                 if (new_delay > dev_priv->max_delay)
392                         new_delay = dev_priv->max_delay;
393         } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
394                 if (dev_priv->cur_delay != dev_priv->min_delay)
395                         new_delay = dev_priv->cur_delay - 1;
396                 if (new_delay < dev_priv->min_delay) {
397                         new_delay = dev_priv->min_delay;
398                         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
399                                    I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
400                                    ((new_delay << 16) & 0x3f0000));
401                 } else {
402                         /* Make sure we continue to get down interrupts
403                          * until we hit the minimum frequency */
404                         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
405                                    I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
406                 }
407
408         }
409
410         gen6_set_rps(dev, new_delay);
411         dev_priv->cur_delay = new_delay;
412
413         I915_WRITE(GEN6_PMIIR, pm_iir);
414 }
415
416 static void pch_irq_handler(struct drm_device *dev)
417 {
418         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
419         u32 pch_iir;
420
421         pch_iir = I915_READ(SDEIIR);
422
423         if (pch_iir & SDE_AUDIO_POWER_MASK)
424                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
425                                  (pch_iir & SDE_AUDIO_POWER_MASK) >>
426                                  SDE_AUDIO_POWER_SHIFT);
427
428         if (pch_iir & SDE_GMBUS)
429                 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
430
431         if (pch_iir & SDE_AUDIO_HDCP_MASK)
432                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
433
434         if (pch_iir & SDE_AUDIO_TRANS_MASK)
435                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
436
437         if (pch_iir & SDE_POISON)
438                 DRM_ERROR("PCH poison interrupt\n");
439
440         if (pch_iir & SDE_FDI_MASK) {
441                 u32 fdia, fdib;
442
443                 fdia = I915_READ(FDI_RXA_IIR);
444                 fdib = I915_READ(FDI_RXB_IIR);
445                 DRM_DEBUG_DRIVER("PCH FDI RX interrupt; FDI RXA IIR: 0x%08x, FDI RXB IIR: 0x%08x\n", fdia, fdib);
446         }
447
448         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
449                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
450
451         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
452                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
453
454         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
455                 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
456         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
457                 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
458 }
459
460 static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
461 {
462         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
463         int ret = IRQ_NONE;
464         u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
465         u32 hotplug_mask;
466         struct drm_i915_master_private *master_priv;
467         u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
468
469         if (IS_GEN6(dev))
470                 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
471
472         /* disable master interrupt before clearing iir  */
473         de_ier = I915_READ(DEIER);
474         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
475         POSTING_READ(DEIER);
476
477         de_iir = I915_READ(DEIIR);
478         gt_iir = I915_READ(GTIIR);
479         pch_iir = I915_READ(SDEIIR);
480         pm_iir = I915_READ(GEN6_PMIIR);
481
482         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
483             (!IS_GEN6(dev) || pm_iir == 0))
484                 goto done;
485
486         if (HAS_PCH_CPT(dev))
487                 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
488         else
489                 hotplug_mask = SDE_HOTPLUG_MASK;
490
491         ret = IRQ_HANDLED;
492
493         if (dev->primary->master) {
494                 master_priv = dev->primary->master->driver_priv;
495                 if (master_priv->sarea_priv)
496                         master_priv->sarea_priv->last_dispatch =
497                                 READ_BREADCRUMB(dev_priv);
498         }
499
500         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
501                 notify_ring(dev, &dev_priv->ring[RCS]);
502         if (gt_iir & bsd_usr_interrupt)
503                 notify_ring(dev, &dev_priv->ring[VCS]);
504         if (gt_iir & GT_BLT_USER_INTERRUPT)
505                 notify_ring(dev, &dev_priv->ring[BCS]);
506
507         if (de_iir & DE_GSE)
508                 intel_opregion_gse_intr(dev);
509
510         if (de_iir & DE_PLANEA_FLIP_DONE) {
511                 intel_prepare_page_flip(dev, 0);
512                 intel_finish_page_flip_plane(dev, 0);
513         }
514
515         if (de_iir & DE_PLANEB_FLIP_DONE) {
516                 intel_prepare_page_flip(dev, 1);
517                 intel_finish_page_flip_plane(dev, 1);
518         }
519
520         if (de_iir & DE_PIPEA_VBLANK)
521                 drm_handle_vblank(dev, 0);
522
523         if (de_iir & DE_PIPEB_VBLANK)
524                 drm_handle_vblank(dev, 1);
525
526         /* check event from PCH */
527         if (de_iir & DE_PCH_EVENT) {
528                 if (pch_iir & hotplug_mask)
529                         queue_work(dev_priv->wq, &dev_priv->hotplug_work);
530                 pch_irq_handler(dev);
531         }
532
533         if (de_iir & DE_PCU_EVENT) {
534                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
535                 i915_handle_rps_change(dev);
536         }
537
538         if (IS_GEN6(dev))
539                 gen6_pm_irq_handler(dev);
540
541         /* should clear PCH hotplug event before clear CPU irq */
542         I915_WRITE(SDEIIR, pch_iir);
543         I915_WRITE(GTIIR, gt_iir);
544         I915_WRITE(DEIIR, de_iir);
545
546 done:
547         I915_WRITE(DEIER, de_ier);
548         POSTING_READ(DEIER);
549
550         return ret;
551 }
552
553 /**
554  * i915_error_work_func - do process context error handling work
555  * @work: work struct
556  *
557  * Fire an error uevent so userspace can see that a hang or error
558  * was detected.
559  */
560 static void i915_error_work_func(struct work_struct *work)
561 {
562         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
563                                                     error_work);
564         struct drm_device *dev = dev_priv->dev;
565         char *error_event[] = { "ERROR=1", NULL };
566         char *reset_event[] = { "RESET=1", NULL };
567         char *reset_done_event[] = { "ERROR=0", NULL };
568
569         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
570
571         if (atomic_read(&dev_priv->mm.wedged)) {
572                 DRM_DEBUG_DRIVER("resetting chip\n");
573                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
574                 if (!i915_reset(dev, GRDOM_RENDER)) {
575                         atomic_set(&dev_priv->mm.wedged, 0);
576                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
577                 }
578                 complete_all(&dev_priv->error_completion);
579         }
580 }
581
582 #ifdef CONFIG_DEBUG_FS
583 static struct drm_i915_error_object *
584 i915_error_object_create(struct drm_i915_private *dev_priv,
585                          struct drm_i915_gem_object *src)
586 {
587         struct drm_i915_error_object *dst;
588         int page, page_count;
589         u32 reloc_offset;
590
591         if (src == NULL || src->pages == NULL)
592                 return NULL;
593
594         page_count = src->base.size / PAGE_SIZE;
595
596         dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
597         if (dst == NULL)
598                 return NULL;
599
600         reloc_offset = src->gtt_offset;
601         for (page = 0; page < page_count; page++) {
602                 unsigned long flags;
603                 void __iomem *s;
604                 void *d;
605
606                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
607                 if (d == NULL)
608                         goto unwind;
609
610                 local_irq_save(flags);
611                 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
612                                              reloc_offset);
613                 memcpy_fromio(d, s, PAGE_SIZE);
614                 io_mapping_unmap_atomic(s);
615                 local_irq_restore(flags);
616
617                 dst->pages[page] = d;
618
619                 reloc_offset += PAGE_SIZE;
620         }
621         dst->page_count = page_count;
622         dst->gtt_offset = src->gtt_offset;
623
624         return dst;
625
626 unwind:
627         while (page--)
628                 kfree(dst->pages[page]);
629         kfree(dst);
630         return NULL;
631 }
632
633 static void
634 i915_error_object_free(struct drm_i915_error_object *obj)
635 {
636         int page;
637
638         if (obj == NULL)
639                 return;
640
641         for (page = 0; page < obj->page_count; page++)
642                 kfree(obj->pages[page]);
643
644         kfree(obj);
645 }
646
647 static void
648 i915_error_state_free(struct drm_device *dev,
649                       struct drm_i915_error_state *error)
650 {
651         i915_error_object_free(error->batchbuffer[0]);
652         i915_error_object_free(error->batchbuffer[1]);
653         i915_error_object_free(error->ringbuffer);
654         kfree(error->active_bo);
655         kfree(error->overlay);
656         kfree(error);
657 }
658
659 static u32 capture_bo_list(struct drm_i915_error_buffer *err,
660                            int count,
661                            struct list_head *head)
662 {
663         struct drm_i915_gem_object *obj;
664         int i = 0;
665
666         list_for_each_entry(obj, head, mm_list) {
667                 err->size = obj->base.size;
668                 err->name = obj->base.name;
669                 err->seqno = obj->last_rendering_seqno;
670                 err->gtt_offset = obj->gtt_offset;
671                 err->read_domains = obj->base.read_domains;
672                 err->write_domain = obj->base.write_domain;
673                 err->fence_reg = obj->fence_reg;
674                 err->pinned = 0;
675                 if (obj->pin_count > 0)
676                         err->pinned = 1;
677                 if (obj->user_pin_count > 0)
678                         err->pinned = -1;
679                 err->tiling = obj->tiling_mode;
680                 err->dirty = obj->dirty;
681                 err->purgeable = obj->madv != I915_MADV_WILLNEED;
682                 err->ring = obj->ring ? obj->ring->id : 0;
683                 err->agp_type = obj->agp_type == AGP_USER_CACHED_MEMORY;
684
685                 if (++i == count)
686                         break;
687
688                 err++;
689         }
690
691         return i;
692 }
693
694 static void i915_gem_record_fences(struct drm_device *dev,
695                                    struct drm_i915_error_state *error)
696 {
697         struct drm_i915_private *dev_priv = dev->dev_private;
698         int i;
699
700         /* Fences */
701         switch (INTEL_INFO(dev)->gen) {
702         case 6:
703                 for (i = 0; i < 16; i++)
704                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
705                 break;
706         case 5:
707         case 4:
708                 for (i = 0; i < 16; i++)
709                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
710                 break;
711         case 3:
712                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
713                         for (i = 0; i < 8; i++)
714                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
715         case 2:
716                 for (i = 0; i < 8; i++)
717                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
718                 break;
719
720         }
721 }
722
723 static struct drm_i915_error_object *
724 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
725                              struct intel_ring_buffer *ring)
726 {
727         struct drm_i915_gem_object *obj;
728         u32 seqno;
729
730         if (!ring->get_seqno)
731                 return NULL;
732
733         seqno = ring->get_seqno(ring);
734         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
735                 if (obj->ring != ring)
736                         continue;
737
738                 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
739                         continue;
740
741                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
742                         continue;
743
744                 /* We need to copy these to an anonymous buffer as the simplest
745                  * method to avoid being overwritten by userspace.
746                  */
747                 return i915_error_object_create(dev_priv, obj);
748         }
749
750         return NULL;
751 }
752
753 /**
754  * i915_capture_error_state - capture an error record for later analysis
755  * @dev: drm device
756  *
757  * Should be called when an error is detected (either a hang or an error
758  * interrupt) to capture error state from the time of the error.  Fills
759  * out a structure which becomes available in debugfs for user level tools
760  * to pick up.
761  */
762 static void i915_capture_error_state(struct drm_device *dev)
763 {
764         struct drm_i915_private *dev_priv = dev->dev_private;
765         struct drm_i915_gem_object *obj;
766         struct drm_i915_error_state *error;
767         unsigned long flags;
768         int i;
769
770         spin_lock_irqsave(&dev_priv->error_lock, flags);
771         error = dev_priv->first_error;
772         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
773         if (error)
774                 return;
775
776         error = kmalloc(sizeof(*error), GFP_ATOMIC);
777         if (!error) {
778                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
779                 return;
780         }
781
782         DRM_DEBUG_DRIVER("generating error event\n");
783
784         error->seqno = dev_priv->ring[RCS].get_seqno(&dev_priv->ring[RCS]);
785         error->eir = I915_READ(EIR);
786         error->pgtbl_er = I915_READ(PGTBL_ER);
787         error->pipeastat = I915_READ(PIPEASTAT);
788         error->pipebstat = I915_READ(PIPEBSTAT);
789         error->instpm = I915_READ(INSTPM);
790         error->error = 0;
791         if (INTEL_INFO(dev)->gen >= 6) {
792                 error->error = I915_READ(ERROR_GEN6);
793
794                 error->bcs_acthd = I915_READ(BCS_ACTHD);
795                 error->bcs_ipehr = I915_READ(BCS_IPEHR);
796                 error->bcs_ipeir = I915_READ(BCS_IPEIR);
797                 error->bcs_instdone = I915_READ(BCS_INSTDONE);
798                 error->bcs_seqno = 0;
799                 if (dev_priv->ring[BCS].get_seqno)
800                         error->bcs_seqno = dev_priv->ring[BCS].get_seqno(&dev_priv->ring[BCS]);
801
802                 error->vcs_acthd = I915_READ(VCS_ACTHD);
803                 error->vcs_ipehr = I915_READ(VCS_IPEHR);
804                 error->vcs_ipeir = I915_READ(VCS_IPEIR);
805                 error->vcs_instdone = I915_READ(VCS_INSTDONE);
806                 error->vcs_seqno = 0;
807                 if (dev_priv->ring[VCS].get_seqno)
808                         error->vcs_seqno = dev_priv->ring[VCS].get_seqno(&dev_priv->ring[VCS]);
809         }
810         if (INTEL_INFO(dev)->gen >= 4) {
811                 error->ipeir = I915_READ(IPEIR_I965);
812                 error->ipehr = I915_READ(IPEHR_I965);
813                 error->instdone = I915_READ(INSTDONE_I965);
814                 error->instps = I915_READ(INSTPS);
815                 error->instdone1 = I915_READ(INSTDONE1);
816                 error->acthd = I915_READ(ACTHD_I965);
817                 error->bbaddr = I915_READ64(BB_ADDR);
818         } else {
819                 error->ipeir = I915_READ(IPEIR);
820                 error->ipehr = I915_READ(IPEHR);
821                 error->instdone = I915_READ(INSTDONE);
822                 error->acthd = I915_READ(ACTHD);
823                 error->bbaddr = 0;
824         }
825         i915_gem_record_fences(dev, error);
826
827         /* Record the active batchbuffers */
828         for (i = 0; i < I915_NUM_RINGS; i++)
829                 error->batchbuffer[i] =
830                         i915_error_first_batchbuffer(dev_priv,
831                                                      &dev_priv->ring[i]);
832
833         /* Record the ringbuffer */
834         error->ringbuffer = i915_error_object_create(dev_priv,
835                                                      dev_priv->ring[RCS].obj);
836
837         /* Record buffers on the active and pinned lists. */
838         error->active_bo = NULL;
839         error->pinned_bo = NULL;
840
841         i = 0;
842         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
843                 i++;
844         error->active_bo_count = i;
845         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
846                 i++;
847         error->pinned_bo_count = i - error->active_bo_count;
848
849         error->active_bo = NULL;
850         error->pinned_bo = NULL;
851         if (i) {
852                 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
853                                            GFP_ATOMIC);
854                 if (error->active_bo)
855                         error->pinned_bo =
856                                 error->active_bo + error->active_bo_count;
857         }
858
859         if (error->active_bo)
860                 error->active_bo_count =
861                         capture_bo_list(error->active_bo,
862                                         error->active_bo_count,
863                                         &dev_priv->mm.active_list);
864
865         if (error->pinned_bo)
866                 error->pinned_bo_count =
867                         capture_bo_list(error->pinned_bo,
868                                         error->pinned_bo_count,
869                                         &dev_priv->mm.pinned_list);
870
871         do_gettimeofday(&error->time);
872
873         error->overlay = intel_overlay_capture_error_state(dev);
874         error->display = intel_display_capture_error_state(dev);
875
876         spin_lock_irqsave(&dev_priv->error_lock, flags);
877         if (dev_priv->first_error == NULL) {
878                 dev_priv->first_error = error;
879                 error = NULL;
880         }
881         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
882
883         if (error)
884                 i915_error_state_free(dev, error);
885 }
886
887 void i915_destroy_error_state(struct drm_device *dev)
888 {
889         struct drm_i915_private *dev_priv = dev->dev_private;
890         struct drm_i915_error_state *error;
891
892         spin_lock(&dev_priv->error_lock);
893         error = dev_priv->first_error;
894         dev_priv->first_error = NULL;
895         spin_unlock(&dev_priv->error_lock);
896
897         if (error)
898                 i915_error_state_free(dev, error);
899 }
900 #else
901 #define i915_capture_error_state(x)
902 #endif
903
904 static void i915_report_and_clear_eir(struct drm_device *dev)
905 {
906         struct drm_i915_private *dev_priv = dev->dev_private;
907         u32 eir = I915_READ(EIR);
908
909         if (!eir)
910                 return;
911
912         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
913                eir);
914
915         if (IS_G4X(dev)) {
916                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
917                         u32 ipeir = I915_READ(IPEIR_I965);
918
919                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
920                                I915_READ(IPEIR_I965));
921                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
922                                I915_READ(IPEHR_I965));
923                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
924                                I915_READ(INSTDONE_I965));
925                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
926                                I915_READ(INSTPS));
927                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
928                                I915_READ(INSTDONE1));
929                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
930                                I915_READ(ACTHD_I965));
931                         I915_WRITE(IPEIR_I965, ipeir);
932                         POSTING_READ(IPEIR_I965);
933                 }
934                 if (eir & GM45_ERROR_PAGE_TABLE) {
935                         u32 pgtbl_err = I915_READ(PGTBL_ER);
936                         printk(KERN_ERR "page table error\n");
937                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
938                                pgtbl_err);
939                         I915_WRITE(PGTBL_ER, pgtbl_err);
940                         POSTING_READ(PGTBL_ER);
941                 }
942         }
943
944         if (!IS_GEN2(dev)) {
945                 if (eir & I915_ERROR_PAGE_TABLE) {
946                         u32 pgtbl_err = I915_READ(PGTBL_ER);
947                         printk(KERN_ERR "page table error\n");
948                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
949                                pgtbl_err);
950                         I915_WRITE(PGTBL_ER, pgtbl_err);
951                         POSTING_READ(PGTBL_ER);
952                 }
953         }
954
955         if (eir & I915_ERROR_MEMORY_REFRESH) {
956                 u32 pipea_stats = I915_READ(PIPEASTAT);
957                 u32 pipeb_stats = I915_READ(PIPEBSTAT);
958
959                 printk(KERN_ERR "memory refresh error\n");
960                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
961                        pipea_stats);
962                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
963                        pipeb_stats);
964                 /* pipestat has already been acked */
965         }
966         if (eir & I915_ERROR_INSTRUCTION) {
967                 printk(KERN_ERR "instruction error\n");
968                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
969                        I915_READ(INSTPM));
970                 if (INTEL_INFO(dev)->gen < 4) {
971                         u32 ipeir = I915_READ(IPEIR);
972
973                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
974                                I915_READ(IPEIR));
975                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
976                                I915_READ(IPEHR));
977                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
978                                I915_READ(INSTDONE));
979                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
980                                I915_READ(ACTHD));
981                         I915_WRITE(IPEIR, ipeir);
982                         POSTING_READ(IPEIR);
983                 } else {
984                         u32 ipeir = I915_READ(IPEIR_I965);
985
986                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
987                                I915_READ(IPEIR_I965));
988                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
989                                I915_READ(IPEHR_I965));
990                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
991                                I915_READ(INSTDONE_I965));
992                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
993                                I915_READ(INSTPS));
994                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
995                                I915_READ(INSTDONE1));
996                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
997                                I915_READ(ACTHD_I965));
998                         I915_WRITE(IPEIR_I965, ipeir);
999                         POSTING_READ(IPEIR_I965);
1000                 }
1001         }
1002
1003         I915_WRITE(EIR, eir);
1004         POSTING_READ(EIR);
1005         eir = I915_READ(EIR);
1006         if (eir) {
1007                 /*
1008                  * some errors might have become stuck,
1009                  * mask them.
1010                  */
1011                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1012                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1013                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1014         }
1015 }
1016
1017 /**
1018  * i915_handle_error - handle an error interrupt
1019  * @dev: drm device
1020  *
1021  * Do some basic checking of regsiter state at error interrupt time and
1022  * dump it to the syslog.  Also call i915_capture_error_state() to make
1023  * sure we get a record and make it available in debugfs.  Fire a uevent
1024  * so userspace knows something bad happened (should trigger collection
1025  * of a ring dump etc.).
1026  */
1027 void i915_handle_error(struct drm_device *dev, bool wedged)
1028 {
1029         struct drm_i915_private *dev_priv = dev->dev_private;
1030
1031         i915_capture_error_state(dev);
1032         i915_report_and_clear_eir(dev);
1033
1034         if (wedged) {
1035                 INIT_COMPLETION(dev_priv->error_completion);
1036                 atomic_set(&dev_priv->mm.wedged, 1);
1037
1038                 /*
1039                  * Wakeup waiting processes so they don't hang
1040                  */
1041                 wake_up_all(&dev_priv->ring[RCS].irq_queue);
1042                 if (HAS_BSD(dev))
1043                         wake_up_all(&dev_priv->ring[VCS].irq_queue);
1044                 if (HAS_BLT(dev))
1045                         wake_up_all(&dev_priv->ring[BCS].irq_queue);
1046         }
1047
1048         queue_work(dev_priv->wq, &dev_priv->error_work);
1049 }
1050
1051 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1052 {
1053         drm_i915_private_t *dev_priv = dev->dev_private;
1054         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1055         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1056         struct drm_i915_gem_object *obj;
1057         struct intel_unpin_work *work;
1058         unsigned long flags;
1059         bool stall_detected;
1060
1061         /* Ignore early vblank irqs */
1062         if (intel_crtc == NULL)
1063                 return;
1064
1065         spin_lock_irqsave(&dev->event_lock, flags);
1066         work = intel_crtc->unpin_work;
1067
1068         if (work == NULL || work->pending || !work->enable_stall_check) {
1069                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1070                 spin_unlock_irqrestore(&dev->event_lock, flags);
1071                 return;
1072         }
1073
1074         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1075         obj = work->pending_flip_obj;
1076         if (INTEL_INFO(dev)->gen >= 4) {
1077                 int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF;
1078                 stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
1079         } else {
1080                 int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR;
1081                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1082                                                         crtc->y * crtc->fb->pitch +
1083                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1084         }
1085
1086         spin_unlock_irqrestore(&dev->event_lock, flags);
1087
1088         if (stall_detected) {
1089                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1090                 intel_prepare_page_flip(dev, intel_crtc->plane);
1091         }
1092 }
1093
1094 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1095 {
1096         struct drm_device *dev = (struct drm_device *) arg;
1097         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1098         struct drm_i915_master_private *master_priv;
1099         u32 iir, new_iir;
1100         u32 pipea_stats, pipeb_stats;
1101         u32 vblank_status;
1102         int vblank = 0;
1103         unsigned long irqflags;
1104         int irq_received;
1105         int ret = IRQ_NONE;
1106
1107         atomic_inc(&dev_priv->irq_received);
1108
1109         if (HAS_PCH_SPLIT(dev))
1110                 return ironlake_irq_handler(dev);
1111
1112         iir = I915_READ(IIR);
1113
1114         if (INTEL_INFO(dev)->gen >= 4)
1115                 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
1116         else
1117                 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
1118
1119         for (;;) {
1120                 irq_received = iir != 0;
1121
1122                 /* Can't rely on pipestat interrupt bit in iir as it might
1123                  * have been cleared after the pipestat interrupt was received.
1124                  * It doesn't set the bit in iir again, but it still produces
1125                  * interrupts (for non-MSI).
1126                  */
1127                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1128                 pipea_stats = I915_READ(PIPEASTAT);
1129                 pipeb_stats = I915_READ(PIPEBSTAT);
1130
1131                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
1132                         i915_handle_error(dev, false);
1133
1134                 /*
1135                  * Clear the PIPE(A|B)STAT regs before the IIR
1136                  */
1137                 if (pipea_stats & 0x8000ffff) {
1138                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
1139                                 DRM_DEBUG_DRIVER("pipe a underrun\n");
1140                         I915_WRITE(PIPEASTAT, pipea_stats);
1141                         irq_received = 1;
1142                 }
1143
1144                 if (pipeb_stats & 0x8000ffff) {
1145                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
1146                                 DRM_DEBUG_DRIVER("pipe b underrun\n");
1147                         I915_WRITE(PIPEBSTAT, pipeb_stats);
1148                         irq_received = 1;
1149                 }
1150                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1151
1152                 if (!irq_received)
1153                         break;
1154
1155                 ret = IRQ_HANDLED;
1156
1157                 /* Consume port.  Then clear IIR or we'll miss events */
1158                 if ((I915_HAS_HOTPLUG(dev)) &&
1159                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1160                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1161
1162                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1163                                   hotplug_status);
1164                         if (hotplug_status & dev_priv->hotplug_supported_mask)
1165                                 queue_work(dev_priv->wq,
1166                                            &dev_priv->hotplug_work);
1167
1168                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1169                         I915_READ(PORT_HOTPLUG_STAT);
1170                 }
1171
1172                 I915_WRITE(IIR, iir);
1173                 new_iir = I915_READ(IIR); /* Flush posted writes */
1174
1175                 if (dev->primary->master) {
1176                         master_priv = dev->primary->master->driver_priv;
1177                         if (master_priv->sarea_priv)
1178                                 master_priv->sarea_priv->last_dispatch =
1179                                         READ_BREADCRUMB(dev_priv);
1180                 }
1181
1182                 if (iir & I915_USER_INTERRUPT)
1183                         notify_ring(dev, &dev_priv->ring[RCS]);
1184                 if (iir & I915_BSD_USER_INTERRUPT)
1185                         notify_ring(dev, &dev_priv->ring[VCS]);
1186
1187                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1188                         intel_prepare_page_flip(dev, 0);
1189                         if (dev_priv->flip_pending_is_done)
1190                                 intel_finish_page_flip_plane(dev, 0);
1191                 }
1192
1193                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1194                         intel_prepare_page_flip(dev, 1);
1195                         if (dev_priv->flip_pending_is_done)
1196                                 intel_finish_page_flip_plane(dev, 1);
1197                 }
1198
1199                 if (pipea_stats & vblank_status &&
1200                     drm_handle_vblank(dev, 0)) {
1201                         vblank++;
1202                         if (!dev_priv->flip_pending_is_done) {
1203                                 i915_pageflip_stall_check(dev, 0);
1204                                 intel_finish_page_flip(dev, 0);
1205                         }
1206                 }
1207
1208                 if (pipeb_stats & vblank_status &&
1209                     drm_handle_vblank(dev, 1)) {
1210                         vblank++;
1211                         if (!dev_priv->flip_pending_is_done) {
1212                                 i915_pageflip_stall_check(dev, 1);
1213                                 intel_finish_page_flip(dev, 1);
1214                         }
1215                 }
1216
1217                 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1218                     (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1219                     (iir & I915_ASLE_INTERRUPT))
1220                         intel_opregion_asle_intr(dev);
1221
1222                 /* With MSI, interrupts are only generated when iir
1223                  * transitions from zero to nonzero.  If another bit got
1224                  * set while we were handling the existing iir bits, then
1225                  * we would never get another interrupt.
1226                  *
1227                  * This is fine on non-MSI as well, as if we hit this path
1228                  * we avoid exiting the interrupt handler only to generate
1229                  * another one.
1230                  *
1231                  * Note that for MSI this could cause a stray interrupt report
1232                  * if an interrupt landed in the time between writing IIR and
1233                  * the posting read.  This should be rare enough to never
1234                  * trigger the 99% of 100,000 interrupts test for disabling
1235                  * stray interrupts.
1236                  */
1237                 iir = new_iir;
1238         }
1239
1240         return ret;
1241 }
1242
1243 static int i915_emit_irq(struct drm_device * dev)
1244 {
1245         drm_i915_private_t *dev_priv = dev->dev_private;
1246         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1247
1248         i915_kernel_lost_context(dev);
1249
1250         DRM_DEBUG_DRIVER("\n");
1251
1252         dev_priv->counter++;
1253         if (dev_priv->counter > 0x7FFFFFFFUL)
1254                 dev_priv->counter = 1;
1255         if (master_priv->sarea_priv)
1256                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1257
1258         if (BEGIN_LP_RING(4) == 0) {
1259                 OUT_RING(MI_STORE_DWORD_INDEX);
1260                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1261                 OUT_RING(dev_priv->counter);
1262                 OUT_RING(MI_USER_INTERRUPT);
1263                 ADVANCE_LP_RING();
1264         }
1265
1266         return dev_priv->counter;
1267 }
1268
1269 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1270 {
1271         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1272         struct intel_ring_buffer *ring = LP_RING(dev_priv);
1273
1274         if (dev_priv->trace_irq_seqno == 0 &&
1275             ring->irq_get(ring))
1276                 dev_priv->trace_irq_seqno = seqno;
1277 }
1278
1279 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1280 {
1281         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1282         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1283         int ret = 0;
1284         struct intel_ring_buffer *ring = LP_RING(dev_priv);
1285
1286         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1287                   READ_BREADCRUMB(dev_priv));
1288
1289         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1290                 if (master_priv->sarea_priv)
1291                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1292                 return 0;
1293         }
1294
1295         if (master_priv->sarea_priv)
1296                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1297
1298         if (ring->irq_get(ring)) {
1299                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
1300                             READ_BREADCRUMB(dev_priv) >= irq_nr);
1301                 ring->irq_put(ring);
1302         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
1303                 ret = -EBUSY;
1304
1305         if (ret == -EBUSY) {
1306                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1307                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1308         }
1309
1310         return ret;
1311 }
1312
1313 /* Needs the lock as it touches the ring.
1314  */
1315 int i915_irq_emit(struct drm_device *dev, void *data,
1316                          struct drm_file *file_priv)
1317 {
1318         drm_i915_private_t *dev_priv = dev->dev_private;
1319         drm_i915_irq_emit_t *emit = data;
1320         int result;
1321
1322         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
1323                 DRM_ERROR("called with no initialization\n");
1324                 return -EINVAL;
1325         }
1326
1327         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1328
1329         mutex_lock(&dev->struct_mutex);
1330         result = i915_emit_irq(dev);
1331         mutex_unlock(&dev->struct_mutex);
1332
1333         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1334                 DRM_ERROR("copy_to_user\n");
1335                 return -EFAULT;
1336         }
1337
1338         return 0;
1339 }
1340
1341 /* Doesn't need the hardware lock.
1342  */
1343 int i915_irq_wait(struct drm_device *dev, void *data,
1344                          struct drm_file *file_priv)
1345 {
1346         drm_i915_private_t *dev_priv = dev->dev_private;
1347         drm_i915_irq_wait_t *irqwait = data;
1348
1349         if (!dev_priv) {
1350                 DRM_ERROR("called with no initialization\n");
1351                 return -EINVAL;
1352         }
1353
1354         return i915_wait_irq(dev, irqwait->irq_seq);
1355 }
1356
1357 /* Called from drm generic code, passed 'crtc' which
1358  * we use as a pipe index
1359  */
1360 int i915_enable_vblank(struct drm_device *dev, int pipe)
1361 {
1362         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1363         unsigned long irqflags;
1364
1365         if (!i915_pipe_enabled(dev, pipe))
1366                 return -EINVAL;
1367
1368         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1369         if (HAS_PCH_SPLIT(dev))
1370                 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1371                                             DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1372         else if (INTEL_INFO(dev)->gen >= 4)
1373                 i915_enable_pipestat(dev_priv, pipe,
1374                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1375         else
1376                 i915_enable_pipestat(dev_priv, pipe,
1377                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1378         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1379         return 0;
1380 }
1381
1382 /* Called from drm generic code, passed 'crtc' which
1383  * we use as a pipe index
1384  */
1385 void i915_disable_vblank(struct drm_device *dev, int pipe)
1386 {
1387         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1388         unsigned long irqflags;
1389
1390         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1391         if (HAS_PCH_SPLIT(dev))
1392                 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1393                                              DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1394         else
1395                 i915_disable_pipestat(dev_priv, pipe,
1396                                       PIPE_VBLANK_INTERRUPT_ENABLE |
1397                                       PIPE_START_VBLANK_INTERRUPT_ENABLE);
1398         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1399 }
1400
1401 void i915_enable_interrupt (struct drm_device *dev)
1402 {
1403         struct drm_i915_private *dev_priv = dev->dev_private;
1404
1405         if (!HAS_PCH_SPLIT(dev))
1406                 intel_opregion_enable_asle(dev);
1407         dev_priv->irq_enabled = 1;
1408 }
1409
1410
1411 /* Set the vblank monitor pipe
1412  */
1413 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1414                          struct drm_file *file_priv)
1415 {
1416         drm_i915_private_t *dev_priv = dev->dev_private;
1417
1418         if (!dev_priv) {
1419                 DRM_ERROR("called with no initialization\n");
1420                 return -EINVAL;
1421         }
1422
1423         return 0;
1424 }
1425
1426 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1427                          struct drm_file *file_priv)
1428 {
1429         drm_i915_private_t *dev_priv = dev->dev_private;
1430         drm_i915_vblank_pipe_t *pipe = data;
1431
1432         if (!dev_priv) {
1433                 DRM_ERROR("called with no initialization\n");
1434                 return -EINVAL;
1435         }
1436
1437         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1438
1439         return 0;
1440 }
1441
1442 /**
1443  * Schedule buffer swap at given vertical blank.
1444  */
1445 int i915_vblank_swap(struct drm_device *dev, void *data,
1446                      struct drm_file *file_priv)
1447 {
1448         /* The delayed swap mechanism was fundamentally racy, and has been
1449          * removed.  The model was that the client requested a delayed flip/swap
1450          * from the kernel, then waited for vblank before continuing to perform
1451          * rendering.  The problem was that the kernel might wake the client
1452          * up before it dispatched the vblank swap (since the lock has to be
1453          * held while touching the ringbuffer), in which case the client would
1454          * clear and start the next frame before the swap occurred, and
1455          * flicker would occur in addition to likely missing the vblank.
1456          *
1457          * In the absence of this ioctl, userland falls back to a correct path
1458          * of waiting for a vblank, then dispatching the swap on its own.
1459          * Context switching to userland and back is plenty fast enough for
1460          * meeting the requirements of vblank swapping.
1461          */
1462         return -EINVAL;
1463 }
1464
1465 static u32
1466 ring_last_seqno(struct intel_ring_buffer *ring)
1467 {
1468         return list_entry(ring->request_list.prev,
1469                           struct drm_i915_gem_request, list)->seqno;
1470 }
1471
1472 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1473 {
1474         if (list_empty(&ring->request_list) ||
1475             i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1476                 /* Issue a wake-up to catch stuck h/w. */
1477                 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
1478                         DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1479                                   ring->name,
1480                                   ring->waiting_seqno,
1481                                   ring->get_seqno(ring));
1482                         wake_up_all(&ring->irq_queue);
1483                         *err = true;
1484                 }
1485                 return true;
1486         }
1487         return false;
1488 }
1489
1490 static bool kick_ring(struct intel_ring_buffer *ring)
1491 {
1492         struct drm_device *dev = ring->dev;
1493         struct drm_i915_private *dev_priv = dev->dev_private;
1494         u32 tmp = I915_READ_CTL(ring);
1495         if (tmp & RING_WAIT) {
1496                 DRM_ERROR("Kicking stuck wait on %s\n",
1497                           ring->name);
1498                 I915_WRITE_CTL(ring, tmp);
1499                 return true;
1500         }
1501         if (IS_GEN6(dev) &&
1502             (tmp & RING_WAIT_SEMAPHORE)) {
1503                 DRM_ERROR("Kicking stuck semaphore on %s\n",
1504                           ring->name);
1505                 I915_WRITE_CTL(ring, tmp);
1506                 return true;
1507         }
1508         return false;
1509 }
1510
1511 /**
1512  * This is called when the chip hasn't reported back with completed
1513  * batchbuffers in a long time. The first time this is called we simply record
1514  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1515  * again, we assume the chip is wedged and try to fix it.
1516  */
1517 void i915_hangcheck_elapsed(unsigned long data)
1518 {
1519         struct drm_device *dev = (struct drm_device *)data;
1520         drm_i915_private_t *dev_priv = dev->dev_private;
1521         uint32_t acthd, instdone, instdone1;
1522         bool err = false;
1523
1524         /* If all work is done then ACTHD clearly hasn't advanced. */
1525         if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
1526             i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
1527             i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
1528                 dev_priv->hangcheck_count = 0;
1529                 if (err)
1530                         goto repeat;
1531                 return;
1532         }
1533
1534         if (INTEL_INFO(dev)->gen < 4) {
1535                 acthd = I915_READ(ACTHD);
1536                 instdone = I915_READ(INSTDONE);
1537                 instdone1 = 0;
1538         } else {
1539                 acthd = I915_READ(ACTHD_I965);
1540                 instdone = I915_READ(INSTDONE_I965);
1541                 instdone1 = I915_READ(INSTDONE1);
1542         }
1543
1544         if (dev_priv->last_acthd == acthd &&
1545             dev_priv->last_instdone == instdone &&
1546             dev_priv->last_instdone1 == instdone1) {
1547                 if (dev_priv->hangcheck_count++ > 1) {
1548                         DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1549
1550                         if (!IS_GEN2(dev)) {
1551                                 /* Is the chip hanging on a WAIT_FOR_EVENT?
1552                                  * If so we can simply poke the RB_WAIT bit
1553                                  * and break the hang. This should work on
1554                                  * all but the second generation chipsets.
1555                                  */
1556
1557                                 if (kick_ring(&dev_priv->ring[RCS]))
1558                                         goto repeat;
1559
1560                                 if (HAS_BSD(dev) &&
1561                                     kick_ring(&dev_priv->ring[VCS]))
1562                                         goto repeat;
1563
1564                                 if (HAS_BLT(dev) &&
1565                                     kick_ring(&dev_priv->ring[BCS]))
1566                                         goto repeat;
1567                         }
1568
1569                         i915_handle_error(dev, true);
1570                         return;
1571                 }
1572         } else {
1573                 dev_priv->hangcheck_count = 0;
1574
1575                 dev_priv->last_acthd = acthd;
1576                 dev_priv->last_instdone = instdone;
1577                 dev_priv->last_instdone1 = instdone1;
1578         }
1579
1580 repeat:
1581         /* Reset timer case chip hangs without another request being added */
1582         mod_timer(&dev_priv->hangcheck_timer,
1583                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1584 }
1585
1586 /* drm_dma.h hooks
1587 */
1588 static void ironlake_irq_preinstall(struct drm_device *dev)
1589 {
1590         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1591
1592         I915_WRITE(HWSTAM, 0xeffe);
1593
1594         /* XXX hotplug from PCH */
1595
1596         I915_WRITE(DEIMR, 0xffffffff);
1597         I915_WRITE(DEIER, 0x0);
1598         POSTING_READ(DEIER);
1599
1600         /* and GT */
1601         I915_WRITE(GTIMR, 0xffffffff);
1602         I915_WRITE(GTIER, 0x0);
1603         POSTING_READ(GTIER);
1604
1605         /* south display irq */
1606         I915_WRITE(SDEIMR, 0xffffffff);
1607         I915_WRITE(SDEIER, 0x0);
1608         POSTING_READ(SDEIER);
1609 }
1610
1611 static int ironlake_irq_postinstall(struct drm_device *dev)
1612 {
1613         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1614         /* enable kind of interrupts always enabled */
1615         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1616                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1617         u32 render_irqs;
1618         u32 hotplug_mask;
1619
1620         dev_priv->irq_mask = ~display_mask;
1621
1622         /* should always can generate irq */
1623         I915_WRITE(DEIIR, I915_READ(DEIIR));
1624         I915_WRITE(DEIMR, dev_priv->irq_mask);
1625         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1626         POSTING_READ(DEIER);
1627
1628         dev_priv->gt_irq_mask = ~0;
1629
1630         I915_WRITE(GTIIR, I915_READ(GTIIR));
1631         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1632
1633         if (IS_GEN6(dev))
1634                 render_irqs =
1635                         GT_USER_INTERRUPT |
1636                         GT_GEN6_BSD_USER_INTERRUPT |
1637                         GT_BLT_USER_INTERRUPT;
1638         else
1639                 render_irqs =
1640                         GT_USER_INTERRUPT |
1641                         GT_PIPE_NOTIFY |
1642                         GT_BSD_USER_INTERRUPT;
1643         I915_WRITE(GTIER, render_irqs);
1644         POSTING_READ(GTIER);
1645
1646         if (HAS_PCH_CPT(dev)) {
1647                 hotplug_mask = SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT  |
1648                                SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT ;
1649         } else {
1650                 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1651                                SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1652                 hotplug_mask |= SDE_AUX_MASK | SDE_FDI_MASK | SDE_TRANS_MASK;
1653                 I915_WRITE(FDI_RXA_IMR, 0);
1654                 I915_WRITE(FDI_RXB_IMR, 0);
1655         }
1656
1657         dev_priv->pch_irq_mask = ~hotplug_mask;
1658
1659         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1660         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1661         I915_WRITE(SDEIER, hotplug_mask);
1662         POSTING_READ(SDEIER);
1663
1664         if (IS_IRONLAKE_M(dev)) {
1665                 /* Clear & enable PCU event interrupts */
1666                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1667                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1668                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1669         }
1670
1671         return 0;
1672 }
1673
1674 void i915_driver_irq_preinstall(struct drm_device * dev)
1675 {
1676         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1677
1678         atomic_set(&dev_priv->irq_received, 0);
1679
1680         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1681         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1682
1683         if (HAS_PCH_SPLIT(dev)) {
1684                 ironlake_irq_preinstall(dev);
1685                 return;
1686         }
1687
1688         if (I915_HAS_HOTPLUG(dev)) {
1689                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1690                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1691         }
1692
1693         I915_WRITE(HWSTAM, 0xeffe);
1694         I915_WRITE(PIPEASTAT, 0);
1695         I915_WRITE(PIPEBSTAT, 0);
1696         I915_WRITE(IMR, 0xffffffff);
1697         I915_WRITE(IER, 0x0);
1698         POSTING_READ(IER);
1699 }
1700
1701 /*
1702  * Must be called after intel_modeset_init or hotplug interrupts won't be
1703  * enabled correctly.
1704  */
1705 int i915_driver_irq_postinstall(struct drm_device *dev)
1706 {
1707         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1708         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1709         u32 error_mask;
1710
1711         DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1712         if (HAS_BSD(dev))
1713                 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1714         if (HAS_BLT(dev))
1715                 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1716
1717         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1718
1719         if (HAS_PCH_SPLIT(dev))
1720                 return ironlake_irq_postinstall(dev);
1721
1722         /* Unmask the interrupts that we always want on. */
1723         dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
1724
1725         dev_priv->pipestat[0] = 0;
1726         dev_priv->pipestat[1] = 0;
1727
1728         if (I915_HAS_HOTPLUG(dev)) {
1729                 /* Enable in IER... */
1730                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1731                 /* and unmask in IMR */
1732                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
1733         }
1734
1735         /*
1736          * Enable some error detection, note the instruction error mask
1737          * bit is reserved, so we leave it masked.
1738          */
1739         if (IS_G4X(dev)) {
1740                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1741                                GM45_ERROR_MEM_PRIV |
1742                                GM45_ERROR_CP_PRIV |
1743                                I915_ERROR_MEMORY_REFRESH);
1744         } else {
1745                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1746                                I915_ERROR_MEMORY_REFRESH);
1747         }
1748         I915_WRITE(EMR, error_mask);
1749
1750         I915_WRITE(IMR, dev_priv->irq_mask);
1751         I915_WRITE(IER, enable_mask);
1752         POSTING_READ(IER);
1753
1754         if (I915_HAS_HOTPLUG(dev)) {
1755                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1756
1757                 /* Note HDMI and DP share bits */
1758                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1759                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1760                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1761                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1762                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1763                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1764                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1765                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1766                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1767                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1768                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1769                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1770
1771                         /* Programming the CRT detection parameters tends
1772                            to generate a spurious hotplug event about three
1773                            seconds later.  So just do it once.
1774                         */
1775                         if (IS_G4X(dev))
1776                                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1777                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1778                 }
1779
1780                 /* Ignore TV since it's buggy */
1781
1782                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1783         }
1784
1785         intel_opregion_enable_asle(dev);
1786
1787         return 0;
1788 }
1789
1790 static void ironlake_irq_uninstall(struct drm_device *dev)
1791 {
1792         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1793         I915_WRITE(HWSTAM, 0xffffffff);
1794
1795         I915_WRITE(DEIMR, 0xffffffff);
1796         I915_WRITE(DEIER, 0x0);
1797         I915_WRITE(DEIIR, I915_READ(DEIIR));
1798
1799         I915_WRITE(GTIMR, 0xffffffff);
1800         I915_WRITE(GTIER, 0x0);
1801         I915_WRITE(GTIIR, I915_READ(GTIIR));
1802 }
1803
1804 void i915_driver_irq_uninstall(struct drm_device * dev)
1805 {
1806         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1807
1808         if (!dev_priv)
1809                 return;
1810
1811         dev_priv->vblank_pipe = 0;
1812
1813         if (HAS_PCH_SPLIT(dev)) {
1814                 ironlake_irq_uninstall(dev);
1815                 return;
1816         }
1817
1818         if (I915_HAS_HOTPLUG(dev)) {
1819                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1820                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1821         }
1822
1823         I915_WRITE(HWSTAM, 0xffffffff);
1824         I915_WRITE(PIPEASTAT, 0);
1825         I915_WRITE(PIPEBSTAT, 0);
1826         I915_WRITE(IMR, 0xffffffff);
1827         I915_WRITE(IER, 0x0);
1828
1829         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1830         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1831         I915_WRITE(IIR, I915_READ(IIR));
1832 }