Merge branch 'for-davem' of ssh://master.kernel.org/pub/scm/linux/kernel/git/linville...
[linux-2.6.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2  */
3 /*
4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5  * All Rights Reserved.
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a
8  * copy of this software and associated documentation files (the
9  * "Software"), to deal in the Software without restriction, including
10  * without limitation the rights to use, copy, modify, merge, publish,
11  * distribute, sub license, and/or sell copies of the Software, and to
12  * permit persons to whom the Software is furnished to do so, subject to
13  * the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the
16  * next paragraph) shall be included in all copies or substantial portions
17  * of the Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26  *
27  */
28
29 #include <linux/sysrq.h>
30 #include <linux/slab.h>
31 #include "drmP.h"
32 #include "drm.h"
33 #include "i915_drm.h"
34 #include "i915_drv.h"
35 #include "i915_trace.h"
36 #include "intel_drv.h"
37
38 #define MAX_NOPID ((u32)~0)
39
40 /**
41  * Interrupts that are always left unmasked.
42  *
43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
44  * we leave them always unmasked in IMR and then control enabling them through
45  * PIPESTAT alone.
46  */
47 #define I915_INTERRUPT_ENABLE_FIX                       \
48         (I915_ASLE_INTERRUPT |                          \
49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
54
55 /** Interrupts that we mask and unmask at runtime. */
56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
57
58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
59                                  PIPE_VBLANK_INTERRUPT_STATUS)
60
61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
63
64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
65                                          DRM_I915_VBLANK_PIPE_B)
66
67 /* For display hotplug interrupt */
68 static void
69 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
70 {
71         if ((dev_priv->irq_mask & mask) != 0) {
72                 dev_priv->irq_mask &= ~mask;
73                 I915_WRITE(DEIMR, dev_priv->irq_mask);
74                 POSTING_READ(DEIMR);
75         }
76 }
77
78 static inline void
79 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
80 {
81         if ((dev_priv->irq_mask & mask) != mask) {
82                 dev_priv->irq_mask |= mask;
83                 I915_WRITE(DEIMR, dev_priv->irq_mask);
84                 POSTING_READ(DEIMR);
85         }
86 }
87
88 static inline u32
89 i915_pipestat(int pipe)
90 {
91         if (pipe == 0)
92                 return PIPEASTAT;
93         if (pipe == 1)
94                 return PIPEBSTAT;
95         BUG();
96 }
97
98 void
99 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
100 {
101         if ((dev_priv->pipestat[pipe] & mask) != mask) {
102                 u32 reg = i915_pipestat(pipe);
103
104                 dev_priv->pipestat[pipe] |= mask;
105                 /* Enable the interrupt, clear any pending status */
106                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
107                 POSTING_READ(reg);
108         }
109 }
110
111 void
112 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
113 {
114         if ((dev_priv->pipestat[pipe] & mask) != 0) {
115                 u32 reg = i915_pipestat(pipe);
116
117                 dev_priv->pipestat[pipe] &= ~mask;
118                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
119                 POSTING_READ(reg);
120         }
121 }
122
123 /**
124  * intel_enable_asle - enable ASLE interrupt for OpRegion
125  */
126 void intel_enable_asle(struct drm_device *dev)
127 {
128         drm_i915_private_t *dev_priv = dev->dev_private;
129         unsigned long irqflags;
130
131         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
132
133         if (HAS_PCH_SPLIT(dev))
134                 ironlake_enable_display_irq(dev_priv, DE_GSE);
135         else {
136                 i915_enable_pipestat(dev_priv, 1,
137                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
138                 if (INTEL_INFO(dev)->gen >= 4)
139                         i915_enable_pipestat(dev_priv, 0,
140                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
141         }
142
143         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
144 }
145
146 /**
147  * i915_pipe_enabled - check if a pipe is enabled
148  * @dev: DRM device
149  * @pipe: pipe to check
150  *
151  * Reading certain registers when the pipe is disabled can hang the chip.
152  * Use this routine to make sure the PLL is running and the pipe is active
153  * before reading such registers if unsure.
154  */
155 static int
156 i915_pipe_enabled(struct drm_device *dev, int pipe)
157 {
158         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
159         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
160 }
161
162 /* Called from drm generic code, passed a 'crtc', which
163  * we use as a pipe index
164  */
165 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
166 {
167         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
168         unsigned long high_frame;
169         unsigned long low_frame;
170         u32 high1, high2, low;
171
172         if (!i915_pipe_enabled(dev, pipe)) {
173                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
174                                 "pipe %d\n", pipe);
175                 return 0;
176         }
177
178         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
179         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
180
181         /*
182          * High & low register fields aren't synchronized, so make sure
183          * we get a low value that's stable across two reads of the high
184          * register.
185          */
186         do {
187                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
188                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
189                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
190         } while (high1 != high2);
191
192         high1 >>= PIPE_FRAME_HIGH_SHIFT;
193         low >>= PIPE_FRAME_LOW_SHIFT;
194         return (high1 << 8) | low;
195 }
196
197 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
198 {
199         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
200         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
201
202         if (!i915_pipe_enabled(dev, pipe)) {
203                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
204                                         "pipe %d\n", pipe);
205                 return 0;
206         }
207
208         return I915_READ(reg);
209 }
210
211 int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
212                              int *vpos, int *hpos)
213 {
214         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
215         u32 vbl = 0, position = 0;
216         int vbl_start, vbl_end, htotal, vtotal;
217         bool in_vbl = true;
218         int ret = 0;
219
220         if (!i915_pipe_enabled(dev, pipe)) {
221                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
222                                         "pipe %d\n", pipe);
223                 return 0;
224         }
225
226         /* Get vtotal. */
227         vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
228
229         if (INTEL_INFO(dev)->gen >= 4) {
230                 /* No obvious pixelcount register. Only query vertical
231                  * scanout position from Display scan line register.
232                  */
233                 position = I915_READ(PIPEDSL(pipe));
234
235                 /* Decode into vertical scanout position. Don't have
236                  * horizontal scanout position.
237                  */
238                 *vpos = position & 0x1fff;
239                 *hpos = 0;
240         } else {
241                 /* Have access to pixelcount since start of frame.
242                  * We can split this into vertical and horizontal
243                  * scanout position.
244                  */
245                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
246
247                 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
248                 *vpos = position / htotal;
249                 *hpos = position - (*vpos * htotal);
250         }
251
252         /* Query vblank area. */
253         vbl = I915_READ(VBLANK(pipe));
254
255         /* Test position against vblank region. */
256         vbl_start = vbl & 0x1fff;
257         vbl_end = (vbl >> 16) & 0x1fff;
258
259         if ((*vpos < vbl_start) || (*vpos > vbl_end))
260                 in_vbl = false;
261
262         /* Inside "upper part" of vblank area? Apply corrective offset: */
263         if (in_vbl && (*vpos >= vbl_start))
264                 *vpos = *vpos - vtotal;
265
266         /* Readouts valid? */
267         if (vbl > 0)
268                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
269
270         /* In vblank? */
271         if (in_vbl)
272                 ret |= DRM_SCANOUTPOS_INVBL;
273
274         return ret;
275 }
276
277 int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
278                               int *max_error,
279                               struct timeval *vblank_time,
280                               unsigned flags)
281 {
282         struct drm_i915_private *dev_priv = dev->dev_private;
283         struct drm_crtc *crtc;
284
285         if (pipe < 0 || pipe >= dev_priv->num_pipe) {
286                 DRM_ERROR("Invalid crtc %d\n", pipe);
287                 return -EINVAL;
288         }
289
290         /* Get drm_crtc to timestamp: */
291         crtc = intel_get_crtc_for_pipe(dev, pipe);
292         if (crtc == NULL) {
293                 DRM_ERROR("Invalid crtc %d\n", pipe);
294                 return -EINVAL;
295         }
296
297         if (!crtc->enabled) {
298                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
299                 return -EBUSY;
300         }
301
302         /* Helper routine in DRM core does all the work: */
303         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
304                                                      vblank_time, flags,
305                                                      crtc);
306 }
307
308 /*
309  * Handle hotplug events outside the interrupt handler proper.
310  */
311 static void i915_hotplug_work_func(struct work_struct *work)
312 {
313         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
314                                                     hotplug_work);
315         struct drm_device *dev = dev_priv->dev;
316         struct drm_mode_config *mode_config = &dev->mode_config;
317         struct intel_encoder *encoder;
318
319         DRM_DEBUG_KMS("running encoder hotplug functions\n");
320
321         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
322                 if (encoder->hot_plug)
323                         encoder->hot_plug(encoder);
324
325         /* Just fire off a uevent and let userspace tell us what to do */
326         drm_helper_hpd_irq_event(dev);
327 }
328
329 static void i915_handle_rps_change(struct drm_device *dev)
330 {
331         drm_i915_private_t *dev_priv = dev->dev_private;
332         u32 busy_up, busy_down, max_avg, min_avg;
333         u8 new_delay = dev_priv->cur_delay;
334
335         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
336         busy_up = I915_READ(RCPREVBSYTUPAVG);
337         busy_down = I915_READ(RCPREVBSYTDNAVG);
338         max_avg = I915_READ(RCBMAXAVG);
339         min_avg = I915_READ(RCBMINAVG);
340
341         /* Handle RCS change request from hw */
342         if (busy_up > max_avg) {
343                 if (dev_priv->cur_delay != dev_priv->max_delay)
344                         new_delay = dev_priv->cur_delay - 1;
345                 if (new_delay < dev_priv->max_delay)
346                         new_delay = dev_priv->max_delay;
347         } else if (busy_down < min_avg) {
348                 if (dev_priv->cur_delay != dev_priv->min_delay)
349                         new_delay = dev_priv->cur_delay + 1;
350                 if (new_delay > dev_priv->min_delay)
351                         new_delay = dev_priv->min_delay;
352         }
353
354         if (ironlake_set_drps(dev, new_delay))
355                 dev_priv->cur_delay = new_delay;
356
357         return;
358 }
359
360 static void notify_ring(struct drm_device *dev,
361                         struct intel_ring_buffer *ring)
362 {
363         struct drm_i915_private *dev_priv = dev->dev_private;
364         u32 seqno;
365
366         if (ring->obj == NULL)
367                 return;
368
369         seqno = ring->get_seqno(ring);
370         trace_i915_gem_request_complete(dev, seqno);
371
372         ring->irq_seqno = seqno;
373         wake_up_all(&ring->irq_queue);
374
375         dev_priv->hangcheck_count = 0;
376         mod_timer(&dev_priv->hangcheck_timer,
377                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
378 }
379
380 static void gen6_pm_irq_handler(struct drm_device *dev)
381 {
382         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
383         u8 new_delay = dev_priv->cur_delay;
384         u32 pm_iir;
385
386         pm_iir = I915_READ(GEN6_PMIIR);
387         if (!pm_iir)
388                 return;
389
390         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
391                 if (dev_priv->cur_delay != dev_priv->max_delay)
392                         new_delay = dev_priv->cur_delay + 1;
393                 if (new_delay > dev_priv->max_delay)
394                         new_delay = dev_priv->max_delay;
395         } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
396                 if (dev_priv->cur_delay != dev_priv->min_delay)
397                         new_delay = dev_priv->cur_delay - 1;
398                 if (new_delay < dev_priv->min_delay) {
399                         new_delay = dev_priv->min_delay;
400                         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
401                                    I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
402                                    ((new_delay << 16) & 0x3f0000));
403                 } else {
404                         /* Make sure we continue to get down interrupts
405                          * until we hit the minimum frequency */
406                         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
407                                    I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
408                 }
409
410         }
411
412         gen6_set_rps(dev, new_delay);
413         dev_priv->cur_delay = new_delay;
414
415         I915_WRITE(GEN6_PMIIR, pm_iir);
416 }
417
418 static void pch_irq_handler(struct drm_device *dev)
419 {
420         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
421         u32 pch_iir;
422
423         pch_iir = I915_READ(SDEIIR);
424
425         if (pch_iir & SDE_AUDIO_POWER_MASK)
426                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
427                                  (pch_iir & SDE_AUDIO_POWER_MASK) >>
428                                  SDE_AUDIO_POWER_SHIFT);
429
430         if (pch_iir & SDE_GMBUS)
431                 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
432
433         if (pch_iir & SDE_AUDIO_HDCP_MASK)
434                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
435
436         if (pch_iir & SDE_AUDIO_TRANS_MASK)
437                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
438
439         if (pch_iir & SDE_POISON)
440                 DRM_ERROR("PCH poison interrupt\n");
441
442         if (pch_iir & SDE_FDI_MASK) {
443                 u32 fdia, fdib;
444
445                 fdia = I915_READ(FDI_RXA_IIR);
446                 fdib = I915_READ(FDI_RXB_IIR);
447                 DRM_DEBUG_DRIVER("PCH FDI RX interrupt; FDI RXA IIR: 0x%08x, FDI RXB IIR: 0x%08x\n", fdia, fdib);
448         }
449
450         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
451                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
452
453         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
454                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
455
456         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
457                 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
458         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
459                 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
460 }
461
462 static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
463 {
464         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
465         int ret = IRQ_NONE;
466         u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
467         u32 hotplug_mask;
468         struct drm_i915_master_private *master_priv;
469         u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
470
471         if (IS_GEN6(dev))
472                 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
473
474         /* disable master interrupt before clearing iir  */
475         de_ier = I915_READ(DEIER);
476         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
477         POSTING_READ(DEIER);
478
479         de_iir = I915_READ(DEIIR);
480         gt_iir = I915_READ(GTIIR);
481         pch_iir = I915_READ(SDEIIR);
482         pm_iir = I915_READ(GEN6_PMIIR);
483
484         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
485             (!IS_GEN6(dev) || pm_iir == 0))
486                 goto done;
487
488         if (HAS_PCH_CPT(dev))
489                 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
490         else
491                 hotplug_mask = SDE_HOTPLUG_MASK;
492
493         ret = IRQ_HANDLED;
494
495         if (dev->primary->master) {
496                 master_priv = dev->primary->master->driver_priv;
497                 if (master_priv->sarea_priv)
498                         master_priv->sarea_priv->last_dispatch =
499                                 READ_BREADCRUMB(dev_priv);
500         }
501
502         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
503                 notify_ring(dev, &dev_priv->ring[RCS]);
504         if (gt_iir & bsd_usr_interrupt)
505                 notify_ring(dev, &dev_priv->ring[VCS]);
506         if (gt_iir & GT_BLT_USER_INTERRUPT)
507                 notify_ring(dev, &dev_priv->ring[BCS]);
508
509         if (de_iir & DE_GSE)
510                 intel_opregion_gse_intr(dev);
511
512         if (de_iir & DE_PLANEA_FLIP_DONE) {
513                 intel_prepare_page_flip(dev, 0);
514                 intel_finish_page_flip_plane(dev, 0);
515         }
516
517         if (de_iir & DE_PLANEB_FLIP_DONE) {
518                 intel_prepare_page_flip(dev, 1);
519                 intel_finish_page_flip_plane(dev, 1);
520         }
521
522         if (de_iir & DE_PIPEA_VBLANK)
523                 drm_handle_vblank(dev, 0);
524
525         if (de_iir & DE_PIPEB_VBLANK)
526                 drm_handle_vblank(dev, 1);
527
528         /* check event from PCH */
529         if (de_iir & DE_PCH_EVENT) {
530                 if (pch_iir & hotplug_mask)
531                         queue_work(dev_priv->wq, &dev_priv->hotplug_work);
532                 pch_irq_handler(dev);
533         }
534
535         if (de_iir & DE_PCU_EVENT) {
536                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
537                 i915_handle_rps_change(dev);
538         }
539
540         if (IS_GEN6(dev))
541                 gen6_pm_irq_handler(dev);
542
543         /* should clear PCH hotplug event before clear CPU irq */
544         I915_WRITE(SDEIIR, pch_iir);
545         I915_WRITE(GTIIR, gt_iir);
546         I915_WRITE(DEIIR, de_iir);
547
548 done:
549         I915_WRITE(DEIER, de_ier);
550         POSTING_READ(DEIER);
551
552         return ret;
553 }
554
555 /**
556  * i915_error_work_func - do process context error handling work
557  * @work: work struct
558  *
559  * Fire an error uevent so userspace can see that a hang or error
560  * was detected.
561  */
562 static void i915_error_work_func(struct work_struct *work)
563 {
564         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
565                                                     error_work);
566         struct drm_device *dev = dev_priv->dev;
567         char *error_event[] = { "ERROR=1", NULL };
568         char *reset_event[] = { "RESET=1", NULL };
569         char *reset_done_event[] = { "ERROR=0", NULL };
570
571         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
572
573         if (atomic_read(&dev_priv->mm.wedged)) {
574                 DRM_DEBUG_DRIVER("resetting chip\n");
575                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
576                 if (!i915_reset(dev, GRDOM_RENDER)) {
577                         atomic_set(&dev_priv->mm.wedged, 0);
578                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
579                 }
580                 complete_all(&dev_priv->error_completion);
581         }
582 }
583
584 #ifdef CONFIG_DEBUG_FS
585 static struct drm_i915_error_object *
586 i915_error_object_create(struct drm_i915_private *dev_priv,
587                          struct drm_i915_gem_object *src)
588 {
589         struct drm_i915_error_object *dst;
590         int page, page_count;
591         u32 reloc_offset;
592
593         if (src == NULL || src->pages == NULL)
594                 return NULL;
595
596         page_count = src->base.size / PAGE_SIZE;
597
598         dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
599         if (dst == NULL)
600                 return NULL;
601
602         reloc_offset = src->gtt_offset;
603         for (page = 0; page < page_count; page++) {
604                 unsigned long flags;
605                 void __iomem *s;
606                 void *d;
607
608                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
609                 if (d == NULL)
610                         goto unwind;
611
612                 local_irq_save(flags);
613                 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
614                                              reloc_offset);
615                 memcpy_fromio(d, s, PAGE_SIZE);
616                 io_mapping_unmap_atomic(s);
617                 local_irq_restore(flags);
618
619                 dst->pages[page] = d;
620
621                 reloc_offset += PAGE_SIZE;
622         }
623         dst->page_count = page_count;
624         dst->gtt_offset = src->gtt_offset;
625
626         return dst;
627
628 unwind:
629         while (page--)
630                 kfree(dst->pages[page]);
631         kfree(dst);
632         return NULL;
633 }
634
635 static void
636 i915_error_object_free(struct drm_i915_error_object *obj)
637 {
638         int page;
639
640         if (obj == NULL)
641                 return;
642
643         for (page = 0; page < obj->page_count; page++)
644                 kfree(obj->pages[page]);
645
646         kfree(obj);
647 }
648
649 static void
650 i915_error_state_free(struct drm_device *dev,
651                       struct drm_i915_error_state *error)
652 {
653         i915_error_object_free(error->batchbuffer[0]);
654         i915_error_object_free(error->batchbuffer[1]);
655         i915_error_object_free(error->ringbuffer);
656         kfree(error->active_bo);
657         kfree(error->overlay);
658         kfree(error);
659 }
660
661 static u32 capture_bo_list(struct drm_i915_error_buffer *err,
662                            int count,
663                            struct list_head *head)
664 {
665         struct drm_i915_gem_object *obj;
666         int i = 0;
667
668         list_for_each_entry(obj, head, mm_list) {
669                 err->size = obj->base.size;
670                 err->name = obj->base.name;
671                 err->seqno = obj->last_rendering_seqno;
672                 err->gtt_offset = obj->gtt_offset;
673                 err->read_domains = obj->base.read_domains;
674                 err->write_domain = obj->base.write_domain;
675                 err->fence_reg = obj->fence_reg;
676                 err->pinned = 0;
677                 if (obj->pin_count > 0)
678                         err->pinned = 1;
679                 if (obj->user_pin_count > 0)
680                         err->pinned = -1;
681                 err->tiling = obj->tiling_mode;
682                 err->dirty = obj->dirty;
683                 err->purgeable = obj->madv != I915_MADV_WILLNEED;
684                 err->ring = obj->ring ? obj->ring->id : 0;
685                 err->agp_type = obj->agp_type == AGP_USER_CACHED_MEMORY;
686
687                 if (++i == count)
688                         break;
689
690                 err++;
691         }
692
693         return i;
694 }
695
696 static void i915_gem_record_fences(struct drm_device *dev,
697                                    struct drm_i915_error_state *error)
698 {
699         struct drm_i915_private *dev_priv = dev->dev_private;
700         int i;
701
702         /* Fences */
703         switch (INTEL_INFO(dev)->gen) {
704         case 6:
705                 for (i = 0; i < 16; i++)
706                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
707                 break;
708         case 5:
709         case 4:
710                 for (i = 0; i < 16; i++)
711                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
712                 break;
713         case 3:
714                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
715                         for (i = 0; i < 8; i++)
716                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
717         case 2:
718                 for (i = 0; i < 8; i++)
719                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
720                 break;
721
722         }
723 }
724
725 static struct drm_i915_error_object *
726 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
727                              struct intel_ring_buffer *ring)
728 {
729         struct drm_i915_gem_object *obj;
730         u32 seqno;
731
732         if (!ring->get_seqno)
733                 return NULL;
734
735         seqno = ring->get_seqno(ring);
736         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
737                 if (obj->ring != ring)
738                         continue;
739
740                 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
741                         continue;
742
743                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
744                         continue;
745
746                 /* We need to copy these to an anonymous buffer as the simplest
747                  * method to avoid being overwritten by userspace.
748                  */
749                 return i915_error_object_create(dev_priv, obj);
750         }
751
752         return NULL;
753 }
754
755 /**
756  * i915_capture_error_state - capture an error record for later analysis
757  * @dev: drm device
758  *
759  * Should be called when an error is detected (either a hang or an error
760  * interrupt) to capture error state from the time of the error.  Fills
761  * out a structure which becomes available in debugfs for user level tools
762  * to pick up.
763  */
764 static void i915_capture_error_state(struct drm_device *dev)
765 {
766         struct drm_i915_private *dev_priv = dev->dev_private;
767         struct drm_i915_gem_object *obj;
768         struct drm_i915_error_state *error;
769         unsigned long flags;
770         int i;
771
772         spin_lock_irqsave(&dev_priv->error_lock, flags);
773         error = dev_priv->first_error;
774         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
775         if (error)
776                 return;
777
778         error = kmalloc(sizeof(*error), GFP_ATOMIC);
779         if (!error) {
780                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
781                 return;
782         }
783
784         DRM_DEBUG_DRIVER("generating error event\n");
785
786         error->seqno = dev_priv->ring[RCS].get_seqno(&dev_priv->ring[RCS]);
787         error->eir = I915_READ(EIR);
788         error->pgtbl_er = I915_READ(PGTBL_ER);
789         error->pipeastat = I915_READ(PIPEASTAT);
790         error->pipebstat = I915_READ(PIPEBSTAT);
791         error->instpm = I915_READ(INSTPM);
792         error->error = 0;
793         if (INTEL_INFO(dev)->gen >= 6) {
794                 error->error = I915_READ(ERROR_GEN6);
795
796                 error->bcs_acthd = I915_READ(BCS_ACTHD);
797                 error->bcs_ipehr = I915_READ(BCS_IPEHR);
798                 error->bcs_ipeir = I915_READ(BCS_IPEIR);
799                 error->bcs_instdone = I915_READ(BCS_INSTDONE);
800                 error->bcs_seqno = 0;
801                 if (dev_priv->ring[BCS].get_seqno)
802                         error->bcs_seqno = dev_priv->ring[BCS].get_seqno(&dev_priv->ring[BCS]);
803
804                 error->vcs_acthd = I915_READ(VCS_ACTHD);
805                 error->vcs_ipehr = I915_READ(VCS_IPEHR);
806                 error->vcs_ipeir = I915_READ(VCS_IPEIR);
807                 error->vcs_instdone = I915_READ(VCS_INSTDONE);
808                 error->vcs_seqno = 0;
809                 if (dev_priv->ring[VCS].get_seqno)
810                         error->vcs_seqno = dev_priv->ring[VCS].get_seqno(&dev_priv->ring[VCS]);
811         }
812         if (INTEL_INFO(dev)->gen >= 4) {
813                 error->ipeir = I915_READ(IPEIR_I965);
814                 error->ipehr = I915_READ(IPEHR_I965);
815                 error->instdone = I915_READ(INSTDONE_I965);
816                 error->instps = I915_READ(INSTPS);
817                 error->instdone1 = I915_READ(INSTDONE1);
818                 error->acthd = I915_READ(ACTHD_I965);
819                 error->bbaddr = I915_READ64(BB_ADDR);
820         } else {
821                 error->ipeir = I915_READ(IPEIR);
822                 error->ipehr = I915_READ(IPEHR);
823                 error->instdone = I915_READ(INSTDONE);
824                 error->acthd = I915_READ(ACTHD);
825                 error->bbaddr = 0;
826         }
827         i915_gem_record_fences(dev, error);
828
829         /* Record the active batchbuffers */
830         for (i = 0; i < I915_NUM_RINGS; i++)
831                 error->batchbuffer[i] =
832                         i915_error_first_batchbuffer(dev_priv,
833                                                      &dev_priv->ring[i]);
834
835         /* Record the ringbuffer */
836         error->ringbuffer = i915_error_object_create(dev_priv,
837                                                      dev_priv->ring[RCS].obj);
838
839         /* Record buffers on the active and pinned lists. */
840         error->active_bo = NULL;
841         error->pinned_bo = NULL;
842
843         i = 0;
844         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
845                 i++;
846         error->active_bo_count = i;
847         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
848                 i++;
849         error->pinned_bo_count = i - error->active_bo_count;
850
851         error->active_bo = NULL;
852         error->pinned_bo = NULL;
853         if (i) {
854                 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
855                                            GFP_ATOMIC);
856                 if (error->active_bo)
857                         error->pinned_bo =
858                                 error->active_bo + error->active_bo_count;
859         }
860
861         if (error->active_bo)
862                 error->active_bo_count =
863                         capture_bo_list(error->active_bo,
864                                         error->active_bo_count,
865                                         &dev_priv->mm.active_list);
866
867         if (error->pinned_bo)
868                 error->pinned_bo_count =
869                         capture_bo_list(error->pinned_bo,
870                                         error->pinned_bo_count,
871                                         &dev_priv->mm.pinned_list);
872
873         do_gettimeofday(&error->time);
874
875         error->overlay = intel_overlay_capture_error_state(dev);
876         error->display = intel_display_capture_error_state(dev);
877
878         spin_lock_irqsave(&dev_priv->error_lock, flags);
879         if (dev_priv->first_error == NULL) {
880                 dev_priv->first_error = error;
881                 error = NULL;
882         }
883         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
884
885         if (error)
886                 i915_error_state_free(dev, error);
887 }
888
889 void i915_destroy_error_state(struct drm_device *dev)
890 {
891         struct drm_i915_private *dev_priv = dev->dev_private;
892         struct drm_i915_error_state *error;
893
894         spin_lock(&dev_priv->error_lock);
895         error = dev_priv->first_error;
896         dev_priv->first_error = NULL;
897         spin_unlock(&dev_priv->error_lock);
898
899         if (error)
900                 i915_error_state_free(dev, error);
901 }
902 #else
903 #define i915_capture_error_state(x)
904 #endif
905
906 static void i915_report_and_clear_eir(struct drm_device *dev)
907 {
908         struct drm_i915_private *dev_priv = dev->dev_private;
909         u32 eir = I915_READ(EIR);
910
911         if (!eir)
912                 return;
913
914         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
915                eir);
916
917         if (IS_G4X(dev)) {
918                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
919                         u32 ipeir = I915_READ(IPEIR_I965);
920
921                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
922                                I915_READ(IPEIR_I965));
923                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
924                                I915_READ(IPEHR_I965));
925                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
926                                I915_READ(INSTDONE_I965));
927                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
928                                I915_READ(INSTPS));
929                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
930                                I915_READ(INSTDONE1));
931                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
932                                I915_READ(ACTHD_I965));
933                         I915_WRITE(IPEIR_I965, ipeir);
934                         POSTING_READ(IPEIR_I965);
935                 }
936                 if (eir & GM45_ERROR_PAGE_TABLE) {
937                         u32 pgtbl_err = I915_READ(PGTBL_ER);
938                         printk(KERN_ERR "page table error\n");
939                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
940                                pgtbl_err);
941                         I915_WRITE(PGTBL_ER, pgtbl_err);
942                         POSTING_READ(PGTBL_ER);
943                 }
944         }
945
946         if (!IS_GEN2(dev)) {
947                 if (eir & I915_ERROR_PAGE_TABLE) {
948                         u32 pgtbl_err = I915_READ(PGTBL_ER);
949                         printk(KERN_ERR "page table error\n");
950                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
951                                pgtbl_err);
952                         I915_WRITE(PGTBL_ER, pgtbl_err);
953                         POSTING_READ(PGTBL_ER);
954                 }
955         }
956
957         if (eir & I915_ERROR_MEMORY_REFRESH) {
958                 u32 pipea_stats = I915_READ(PIPEASTAT);
959                 u32 pipeb_stats = I915_READ(PIPEBSTAT);
960
961                 printk(KERN_ERR "memory refresh error\n");
962                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
963                        pipea_stats);
964                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
965                        pipeb_stats);
966                 /* pipestat has already been acked */
967         }
968         if (eir & I915_ERROR_INSTRUCTION) {
969                 printk(KERN_ERR "instruction error\n");
970                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
971                        I915_READ(INSTPM));
972                 if (INTEL_INFO(dev)->gen < 4) {
973                         u32 ipeir = I915_READ(IPEIR);
974
975                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
976                                I915_READ(IPEIR));
977                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
978                                I915_READ(IPEHR));
979                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
980                                I915_READ(INSTDONE));
981                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
982                                I915_READ(ACTHD));
983                         I915_WRITE(IPEIR, ipeir);
984                         POSTING_READ(IPEIR);
985                 } else {
986                         u32 ipeir = I915_READ(IPEIR_I965);
987
988                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
989                                I915_READ(IPEIR_I965));
990                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
991                                I915_READ(IPEHR_I965));
992                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
993                                I915_READ(INSTDONE_I965));
994                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
995                                I915_READ(INSTPS));
996                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
997                                I915_READ(INSTDONE1));
998                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
999                                I915_READ(ACTHD_I965));
1000                         I915_WRITE(IPEIR_I965, ipeir);
1001                         POSTING_READ(IPEIR_I965);
1002                 }
1003         }
1004
1005         I915_WRITE(EIR, eir);
1006         POSTING_READ(EIR);
1007         eir = I915_READ(EIR);
1008         if (eir) {
1009                 /*
1010                  * some errors might have become stuck,
1011                  * mask them.
1012                  */
1013                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1014                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1015                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1016         }
1017 }
1018
1019 /**
1020  * i915_handle_error - handle an error interrupt
1021  * @dev: drm device
1022  *
1023  * Do some basic checking of regsiter state at error interrupt time and
1024  * dump it to the syslog.  Also call i915_capture_error_state() to make
1025  * sure we get a record and make it available in debugfs.  Fire a uevent
1026  * so userspace knows something bad happened (should trigger collection
1027  * of a ring dump etc.).
1028  */
1029 void i915_handle_error(struct drm_device *dev, bool wedged)
1030 {
1031         struct drm_i915_private *dev_priv = dev->dev_private;
1032
1033         i915_capture_error_state(dev);
1034         i915_report_and_clear_eir(dev);
1035
1036         if (wedged) {
1037                 INIT_COMPLETION(dev_priv->error_completion);
1038                 atomic_set(&dev_priv->mm.wedged, 1);
1039
1040                 /*
1041                  * Wakeup waiting processes so they don't hang
1042                  */
1043                 wake_up_all(&dev_priv->ring[RCS].irq_queue);
1044                 if (HAS_BSD(dev))
1045                         wake_up_all(&dev_priv->ring[VCS].irq_queue);
1046                 if (HAS_BLT(dev))
1047                         wake_up_all(&dev_priv->ring[BCS].irq_queue);
1048         }
1049
1050         queue_work(dev_priv->wq, &dev_priv->error_work);
1051 }
1052
1053 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1054 {
1055         drm_i915_private_t *dev_priv = dev->dev_private;
1056         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1057         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1058         struct drm_i915_gem_object *obj;
1059         struct intel_unpin_work *work;
1060         unsigned long flags;
1061         bool stall_detected;
1062
1063         /* Ignore early vblank irqs */
1064         if (intel_crtc == NULL)
1065                 return;
1066
1067         spin_lock_irqsave(&dev->event_lock, flags);
1068         work = intel_crtc->unpin_work;
1069
1070         if (work == NULL || work->pending || !work->enable_stall_check) {
1071                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1072                 spin_unlock_irqrestore(&dev->event_lock, flags);
1073                 return;
1074         }
1075
1076         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1077         obj = work->pending_flip_obj;
1078         if (INTEL_INFO(dev)->gen >= 4) {
1079                 int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF;
1080                 stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
1081         } else {
1082                 int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR;
1083                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1084                                                         crtc->y * crtc->fb->pitch +
1085                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1086         }
1087
1088         spin_unlock_irqrestore(&dev->event_lock, flags);
1089
1090         if (stall_detected) {
1091                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1092                 intel_prepare_page_flip(dev, intel_crtc->plane);
1093         }
1094 }
1095
1096 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1097 {
1098         struct drm_device *dev = (struct drm_device *) arg;
1099         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1100         struct drm_i915_master_private *master_priv;
1101         u32 iir, new_iir;
1102         u32 pipea_stats, pipeb_stats;
1103         u32 vblank_status;
1104         int vblank = 0;
1105         unsigned long irqflags;
1106         int irq_received;
1107         int ret = IRQ_NONE;
1108
1109         atomic_inc(&dev_priv->irq_received);
1110
1111         if (HAS_PCH_SPLIT(dev))
1112                 return ironlake_irq_handler(dev);
1113
1114         iir = I915_READ(IIR);
1115
1116         if (INTEL_INFO(dev)->gen >= 4)
1117                 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
1118         else
1119                 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
1120
1121         for (;;) {
1122                 irq_received = iir != 0;
1123
1124                 /* Can't rely on pipestat interrupt bit in iir as it might
1125                  * have been cleared after the pipestat interrupt was received.
1126                  * It doesn't set the bit in iir again, but it still produces
1127                  * interrupts (for non-MSI).
1128                  */
1129                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1130                 pipea_stats = I915_READ(PIPEASTAT);
1131                 pipeb_stats = I915_READ(PIPEBSTAT);
1132
1133                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
1134                         i915_handle_error(dev, false);
1135
1136                 /*
1137                  * Clear the PIPE(A|B)STAT regs before the IIR
1138                  */
1139                 if (pipea_stats & 0x8000ffff) {
1140                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
1141                                 DRM_DEBUG_DRIVER("pipe a underrun\n");
1142                         I915_WRITE(PIPEASTAT, pipea_stats);
1143                         irq_received = 1;
1144                 }
1145
1146                 if (pipeb_stats & 0x8000ffff) {
1147                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
1148                                 DRM_DEBUG_DRIVER("pipe b underrun\n");
1149                         I915_WRITE(PIPEBSTAT, pipeb_stats);
1150                         irq_received = 1;
1151                 }
1152                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1153
1154                 if (!irq_received)
1155                         break;
1156
1157                 ret = IRQ_HANDLED;
1158
1159                 /* Consume port.  Then clear IIR or we'll miss events */
1160                 if ((I915_HAS_HOTPLUG(dev)) &&
1161                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1162                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1163
1164                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1165                                   hotplug_status);
1166                         if (hotplug_status & dev_priv->hotplug_supported_mask)
1167                                 queue_work(dev_priv->wq,
1168                                            &dev_priv->hotplug_work);
1169
1170                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1171                         I915_READ(PORT_HOTPLUG_STAT);
1172                 }
1173
1174                 I915_WRITE(IIR, iir);
1175                 new_iir = I915_READ(IIR); /* Flush posted writes */
1176
1177                 if (dev->primary->master) {
1178                         master_priv = dev->primary->master->driver_priv;
1179                         if (master_priv->sarea_priv)
1180                                 master_priv->sarea_priv->last_dispatch =
1181                                         READ_BREADCRUMB(dev_priv);
1182                 }
1183
1184                 if (iir & I915_USER_INTERRUPT)
1185                         notify_ring(dev, &dev_priv->ring[RCS]);
1186                 if (iir & I915_BSD_USER_INTERRUPT)
1187                         notify_ring(dev, &dev_priv->ring[VCS]);
1188
1189                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1190                         intel_prepare_page_flip(dev, 0);
1191                         if (dev_priv->flip_pending_is_done)
1192                                 intel_finish_page_flip_plane(dev, 0);
1193                 }
1194
1195                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1196                         intel_prepare_page_flip(dev, 1);
1197                         if (dev_priv->flip_pending_is_done)
1198                                 intel_finish_page_flip_plane(dev, 1);
1199                 }
1200
1201                 if (pipea_stats & vblank_status &&
1202                     drm_handle_vblank(dev, 0)) {
1203                         vblank++;
1204                         if (!dev_priv->flip_pending_is_done) {
1205                                 i915_pageflip_stall_check(dev, 0);
1206                                 intel_finish_page_flip(dev, 0);
1207                         }
1208                 }
1209
1210                 if (pipeb_stats & vblank_status &&
1211                     drm_handle_vblank(dev, 1)) {
1212                         vblank++;
1213                         if (!dev_priv->flip_pending_is_done) {
1214                                 i915_pageflip_stall_check(dev, 1);
1215                                 intel_finish_page_flip(dev, 1);
1216                         }
1217                 }
1218
1219                 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1220                     (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1221                     (iir & I915_ASLE_INTERRUPT))
1222                         intel_opregion_asle_intr(dev);
1223
1224                 /* With MSI, interrupts are only generated when iir
1225                  * transitions from zero to nonzero.  If another bit got
1226                  * set while we were handling the existing iir bits, then
1227                  * we would never get another interrupt.
1228                  *
1229                  * This is fine on non-MSI as well, as if we hit this path
1230                  * we avoid exiting the interrupt handler only to generate
1231                  * another one.
1232                  *
1233                  * Note that for MSI this could cause a stray interrupt report
1234                  * if an interrupt landed in the time between writing IIR and
1235                  * the posting read.  This should be rare enough to never
1236                  * trigger the 99% of 100,000 interrupts test for disabling
1237                  * stray interrupts.
1238                  */
1239                 iir = new_iir;
1240         }
1241
1242         return ret;
1243 }
1244
1245 static int i915_emit_irq(struct drm_device * dev)
1246 {
1247         drm_i915_private_t *dev_priv = dev->dev_private;
1248         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1249
1250         i915_kernel_lost_context(dev);
1251
1252         DRM_DEBUG_DRIVER("\n");
1253
1254         dev_priv->counter++;
1255         if (dev_priv->counter > 0x7FFFFFFFUL)
1256                 dev_priv->counter = 1;
1257         if (master_priv->sarea_priv)
1258                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1259
1260         if (BEGIN_LP_RING(4) == 0) {
1261                 OUT_RING(MI_STORE_DWORD_INDEX);
1262                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1263                 OUT_RING(dev_priv->counter);
1264                 OUT_RING(MI_USER_INTERRUPT);
1265                 ADVANCE_LP_RING();
1266         }
1267
1268         return dev_priv->counter;
1269 }
1270
1271 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1272 {
1273         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1274         struct intel_ring_buffer *ring = LP_RING(dev_priv);
1275
1276         if (dev_priv->trace_irq_seqno == 0 &&
1277             ring->irq_get(ring))
1278                 dev_priv->trace_irq_seqno = seqno;
1279 }
1280
1281 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1282 {
1283         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1284         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1285         int ret = 0;
1286         struct intel_ring_buffer *ring = LP_RING(dev_priv);
1287
1288         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1289                   READ_BREADCRUMB(dev_priv));
1290
1291         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1292                 if (master_priv->sarea_priv)
1293                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1294                 return 0;
1295         }
1296
1297         if (master_priv->sarea_priv)
1298                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1299
1300         if (ring->irq_get(ring)) {
1301                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
1302                             READ_BREADCRUMB(dev_priv) >= irq_nr);
1303                 ring->irq_put(ring);
1304         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
1305                 ret = -EBUSY;
1306
1307         if (ret == -EBUSY) {
1308                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1309                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1310         }
1311
1312         return ret;
1313 }
1314
1315 /* Needs the lock as it touches the ring.
1316  */
1317 int i915_irq_emit(struct drm_device *dev, void *data,
1318                          struct drm_file *file_priv)
1319 {
1320         drm_i915_private_t *dev_priv = dev->dev_private;
1321         drm_i915_irq_emit_t *emit = data;
1322         int result;
1323
1324         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
1325                 DRM_ERROR("called with no initialization\n");
1326                 return -EINVAL;
1327         }
1328
1329         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1330
1331         mutex_lock(&dev->struct_mutex);
1332         result = i915_emit_irq(dev);
1333         mutex_unlock(&dev->struct_mutex);
1334
1335         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1336                 DRM_ERROR("copy_to_user\n");
1337                 return -EFAULT;
1338         }
1339
1340         return 0;
1341 }
1342
1343 /* Doesn't need the hardware lock.
1344  */
1345 int i915_irq_wait(struct drm_device *dev, void *data,
1346                          struct drm_file *file_priv)
1347 {
1348         drm_i915_private_t *dev_priv = dev->dev_private;
1349         drm_i915_irq_wait_t *irqwait = data;
1350
1351         if (!dev_priv) {
1352                 DRM_ERROR("called with no initialization\n");
1353                 return -EINVAL;
1354         }
1355
1356         return i915_wait_irq(dev, irqwait->irq_seq);
1357 }
1358
1359 /* Called from drm generic code, passed 'crtc' which
1360  * we use as a pipe index
1361  */
1362 int i915_enable_vblank(struct drm_device *dev, int pipe)
1363 {
1364         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1365         unsigned long irqflags;
1366
1367         if (!i915_pipe_enabled(dev, pipe))
1368                 return -EINVAL;
1369
1370         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1371         if (HAS_PCH_SPLIT(dev))
1372                 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1373                                             DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1374         else if (INTEL_INFO(dev)->gen >= 4)
1375                 i915_enable_pipestat(dev_priv, pipe,
1376                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1377         else
1378                 i915_enable_pipestat(dev_priv, pipe,
1379                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1380         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1381         return 0;
1382 }
1383
1384 /* Called from drm generic code, passed 'crtc' which
1385  * we use as a pipe index
1386  */
1387 void i915_disable_vblank(struct drm_device *dev, int pipe)
1388 {
1389         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1390         unsigned long irqflags;
1391
1392         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1393         if (HAS_PCH_SPLIT(dev))
1394                 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1395                                              DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1396         else
1397                 i915_disable_pipestat(dev_priv, pipe,
1398                                       PIPE_VBLANK_INTERRUPT_ENABLE |
1399                                       PIPE_START_VBLANK_INTERRUPT_ENABLE);
1400         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1401 }
1402
1403 void i915_enable_interrupt (struct drm_device *dev)
1404 {
1405         struct drm_i915_private *dev_priv = dev->dev_private;
1406
1407         if (!HAS_PCH_SPLIT(dev))
1408                 intel_opregion_enable_asle(dev);
1409         dev_priv->irq_enabled = 1;
1410 }
1411
1412
1413 /* Set the vblank monitor pipe
1414  */
1415 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1416                          struct drm_file *file_priv)
1417 {
1418         drm_i915_private_t *dev_priv = dev->dev_private;
1419
1420         if (!dev_priv) {
1421                 DRM_ERROR("called with no initialization\n");
1422                 return -EINVAL;
1423         }
1424
1425         return 0;
1426 }
1427
1428 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1429                          struct drm_file *file_priv)
1430 {
1431         drm_i915_private_t *dev_priv = dev->dev_private;
1432         drm_i915_vblank_pipe_t *pipe = data;
1433
1434         if (!dev_priv) {
1435                 DRM_ERROR("called with no initialization\n");
1436                 return -EINVAL;
1437         }
1438
1439         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1440
1441         return 0;
1442 }
1443
1444 /**
1445  * Schedule buffer swap at given vertical blank.
1446  */
1447 int i915_vblank_swap(struct drm_device *dev, void *data,
1448                      struct drm_file *file_priv)
1449 {
1450         /* The delayed swap mechanism was fundamentally racy, and has been
1451          * removed.  The model was that the client requested a delayed flip/swap
1452          * from the kernel, then waited for vblank before continuing to perform
1453          * rendering.  The problem was that the kernel might wake the client
1454          * up before it dispatched the vblank swap (since the lock has to be
1455          * held while touching the ringbuffer), in which case the client would
1456          * clear and start the next frame before the swap occurred, and
1457          * flicker would occur in addition to likely missing the vblank.
1458          *
1459          * In the absence of this ioctl, userland falls back to a correct path
1460          * of waiting for a vblank, then dispatching the swap on its own.
1461          * Context switching to userland and back is plenty fast enough for
1462          * meeting the requirements of vblank swapping.
1463          */
1464         return -EINVAL;
1465 }
1466
1467 static u32
1468 ring_last_seqno(struct intel_ring_buffer *ring)
1469 {
1470         return list_entry(ring->request_list.prev,
1471                           struct drm_i915_gem_request, list)->seqno;
1472 }
1473
1474 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1475 {
1476         if (list_empty(&ring->request_list) ||
1477             i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1478                 /* Issue a wake-up to catch stuck h/w. */
1479                 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
1480                         DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1481                                   ring->name,
1482                                   ring->waiting_seqno,
1483                                   ring->get_seqno(ring));
1484                         wake_up_all(&ring->irq_queue);
1485                         *err = true;
1486                 }
1487                 return true;
1488         }
1489         return false;
1490 }
1491
1492 static bool kick_ring(struct intel_ring_buffer *ring)
1493 {
1494         struct drm_device *dev = ring->dev;
1495         struct drm_i915_private *dev_priv = dev->dev_private;
1496         u32 tmp = I915_READ_CTL(ring);
1497         if (tmp & RING_WAIT) {
1498                 DRM_ERROR("Kicking stuck wait on %s\n",
1499                           ring->name);
1500                 I915_WRITE_CTL(ring, tmp);
1501                 return true;
1502         }
1503         if (IS_GEN6(dev) &&
1504             (tmp & RING_WAIT_SEMAPHORE)) {
1505                 DRM_ERROR("Kicking stuck semaphore on %s\n",
1506                           ring->name);
1507                 I915_WRITE_CTL(ring, tmp);
1508                 return true;
1509         }
1510         return false;
1511 }
1512
1513 /**
1514  * This is called when the chip hasn't reported back with completed
1515  * batchbuffers in a long time. The first time this is called we simply record
1516  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1517  * again, we assume the chip is wedged and try to fix it.
1518  */
1519 void i915_hangcheck_elapsed(unsigned long data)
1520 {
1521         struct drm_device *dev = (struct drm_device *)data;
1522         drm_i915_private_t *dev_priv = dev->dev_private;
1523         uint32_t acthd, instdone, instdone1;
1524         bool err = false;
1525
1526         /* If all work is done then ACTHD clearly hasn't advanced. */
1527         if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
1528             i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
1529             i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
1530                 dev_priv->hangcheck_count = 0;
1531                 if (err)
1532                         goto repeat;
1533                 return;
1534         }
1535
1536         if (INTEL_INFO(dev)->gen < 4) {
1537                 acthd = I915_READ(ACTHD);
1538                 instdone = I915_READ(INSTDONE);
1539                 instdone1 = 0;
1540         } else {
1541                 acthd = I915_READ(ACTHD_I965);
1542                 instdone = I915_READ(INSTDONE_I965);
1543                 instdone1 = I915_READ(INSTDONE1);
1544         }
1545
1546         if (dev_priv->last_acthd == acthd &&
1547             dev_priv->last_instdone == instdone &&
1548             dev_priv->last_instdone1 == instdone1) {
1549                 if (dev_priv->hangcheck_count++ > 1) {
1550                         DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1551
1552                         if (!IS_GEN2(dev)) {
1553                                 /* Is the chip hanging on a WAIT_FOR_EVENT?
1554                                  * If so we can simply poke the RB_WAIT bit
1555                                  * and break the hang. This should work on
1556                                  * all but the second generation chipsets.
1557                                  */
1558
1559                                 if (kick_ring(&dev_priv->ring[RCS]))
1560                                         goto repeat;
1561
1562                                 if (HAS_BSD(dev) &&
1563                                     kick_ring(&dev_priv->ring[VCS]))
1564                                         goto repeat;
1565
1566                                 if (HAS_BLT(dev) &&
1567                                     kick_ring(&dev_priv->ring[BCS]))
1568                                         goto repeat;
1569                         }
1570
1571                         i915_handle_error(dev, true);
1572                         return;
1573                 }
1574         } else {
1575                 dev_priv->hangcheck_count = 0;
1576
1577                 dev_priv->last_acthd = acthd;
1578                 dev_priv->last_instdone = instdone;
1579                 dev_priv->last_instdone1 = instdone1;
1580         }
1581
1582 repeat:
1583         /* Reset timer case chip hangs without another request being added */
1584         mod_timer(&dev_priv->hangcheck_timer,
1585                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1586 }
1587
1588 /* drm_dma.h hooks
1589 */
1590 static void ironlake_irq_preinstall(struct drm_device *dev)
1591 {
1592         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1593
1594         I915_WRITE(HWSTAM, 0xeffe);
1595
1596         /* XXX hotplug from PCH */
1597
1598         I915_WRITE(DEIMR, 0xffffffff);
1599         I915_WRITE(DEIER, 0x0);
1600         POSTING_READ(DEIER);
1601
1602         /* and GT */
1603         I915_WRITE(GTIMR, 0xffffffff);
1604         I915_WRITE(GTIER, 0x0);
1605         POSTING_READ(GTIER);
1606
1607         /* south display irq */
1608         I915_WRITE(SDEIMR, 0xffffffff);
1609         I915_WRITE(SDEIER, 0x0);
1610         POSTING_READ(SDEIER);
1611 }
1612
1613 static int ironlake_irq_postinstall(struct drm_device *dev)
1614 {
1615         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1616         /* enable kind of interrupts always enabled */
1617         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1618                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1619         u32 render_irqs;
1620         u32 hotplug_mask;
1621
1622         dev_priv->irq_mask = ~display_mask;
1623
1624         /* should always can generate irq */
1625         I915_WRITE(DEIIR, I915_READ(DEIIR));
1626         I915_WRITE(DEIMR, dev_priv->irq_mask);
1627         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1628         POSTING_READ(DEIER);
1629
1630         dev_priv->gt_irq_mask = ~0;
1631
1632         I915_WRITE(GTIIR, I915_READ(GTIIR));
1633         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1634
1635         if (IS_GEN6(dev))
1636                 render_irqs =
1637                         GT_USER_INTERRUPT |
1638                         GT_GEN6_BSD_USER_INTERRUPT |
1639                         GT_BLT_USER_INTERRUPT;
1640         else
1641                 render_irqs =
1642                         GT_USER_INTERRUPT |
1643                         GT_PIPE_NOTIFY |
1644                         GT_BSD_USER_INTERRUPT;
1645         I915_WRITE(GTIER, render_irqs);
1646         POSTING_READ(GTIER);
1647
1648         if (HAS_PCH_CPT(dev)) {
1649                 hotplug_mask = SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT  |
1650                                SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT ;
1651         } else {
1652                 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1653                                SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1654                 hotplug_mask |= SDE_AUX_MASK;
1655         }
1656
1657         dev_priv->pch_irq_mask = ~hotplug_mask;
1658
1659         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1660         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1661         I915_WRITE(SDEIER, hotplug_mask);
1662         POSTING_READ(SDEIER);
1663
1664         if (IS_IRONLAKE_M(dev)) {
1665                 /* Clear & enable PCU event interrupts */
1666                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1667                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1668                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1669         }
1670
1671         return 0;
1672 }
1673
1674 void i915_driver_irq_preinstall(struct drm_device * dev)
1675 {
1676         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1677
1678         atomic_set(&dev_priv->irq_received, 0);
1679
1680         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1681         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1682
1683         if (HAS_PCH_SPLIT(dev)) {
1684                 ironlake_irq_preinstall(dev);
1685                 return;
1686         }
1687
1688         if (I915_HAS_HOTPLUG(dev)) {
1689                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1690                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1691         }
1692
1693         I915_WRITE(HWSTAM, 0xeffe);
1694         I915_WRITE(PIPEASTAT, 0);
1695         I915_WRITE(PIPEBSTAT, 0);
1696         I915_WRITE(IMR, 0xffffffff);
1697         I915_WRITE(IER, 0x0);
1698         POSTING_READ(IER);
1699 }
1700
1701 /*
1702  * Must be called after intel_modeset_init or hotplug interrupts won't be
1703  * enabled correctly.
1704  */
1705 int i915_driver_irq_postinstall(struct drm_device *dev)
1706 {
1707         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1708         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1709         u32 error_mask;
1710
1711         DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1712         if (HAS_BSD(dev))
1713                 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1714         if (HAS_BLT(dev))
1715                 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1716
1717         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1718
1719         if (HAS_PCH_SPLIT(dev))
1720                 return ironlake_irq_postinstall(dev);
1721
1722         /* Unmask the interrupts that we always want on. */
1723         dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
1724
1725         dev_priv->pipestat[0] = 0;
1726         dev_priv->pipestat[1] = 0;
1727
1728         if (I915_HAS_HOTPLUG(dev)) {
1729                 /* Enable in IER... */
1730                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1731                 /* and unmask in IMR */
1732                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
1733         }
1734
1735         /*
1736          * Enable some error detection, note the instruction error mask
1737          * bit is reserved, so we leave it masked.
1738          */
1739         if (IS_G4X(dev)) {
1740                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1741                                GM45_ERROR_MEM_PRIV |
1742                                GM45_ERROR_CP_PRIV |
1743                                I915_ERROR_MEMORY_REFRESH);
1744         } else {
1745                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1746                                I915_ERROR_MEMORY_REFRESH);
1747         }
1748         I915_WRITE(EMR, error_mask);
1749
1750         I915_WRITE(IMR, dev_priv->irq_mask);
1751         I915_WRITE(IER, enable_mask);
1752         POSTING_READ(IER);
1753
1754         if (I915_HAS_HOTPLUG(dev)) {
1755                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1756
1757                 /* Note HDMI and DP share bits */
1758                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1759                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1760                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1761                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1762                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1763                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1764                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1765                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1766                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1767                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1768                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1769                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1770
1771                         /* Programming the CRT detection parameters tends
1772                            to generate a spurious hotplug event about three
1773                            seconds later.  So just do it once.
1774                         */
1775                         if (IS_G4X(dev))
1776                                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1777                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1778                 }
1779
1780                 /* Ignore TV since it's buggy */
1781
1782                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1783         }
1784
1785         intel_opregion_enable_asle(dev);
1786
1787         return 0;
1788 }
1789
1790 static void ironlake_irq_uninstall(struct drm_device *dev)
1791 {
1792         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1793         I915_WRITE(HWSTAM, 0xffffffff);
1794
1795         I915_WRITE(DEIMR, 0xffffffff);
1796         I915_WRITE(DEIER, 0x0);
1797         I915_WRITE(DEIIR, I915_READ(DEIIR));
1798
1799         I915_WRITE(GTIMR, 0xffffffff);
1800         I915_WRITE(GTIER, 0x0);
1801         I915_WRITE(GTIIR, I915_READ(GTIIR));
1802 }
1803
1804 void i915_driver_irq_uninstall(struct drm_device * dev)
1805 {
1806         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1807
1808         if (!dev_priv)
1809                 return;
1810
1811         dev_priv->vblank_pipe = 0;
1812
1813         if (HAS_PCH_SPLIT(dev)) {
1814                 ironlake_irq_uninstall(dev);
1815                 return;
1816         }
1817
1818         if (I915_HAS_HOTPLUG(dev)) {
1819                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1820                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1821         }
1822
1823         I915_WRITE(HWSTAM, 0xffffffff);
1824         I915_WRITE(PIPEASTAT, 0);
1825         I915_WRITE(PIPEBSTAT, 0);
1826         I915_WRITE(IMR, 0xffffffff);
1827         I915_WRITE(IER, 0x0);
1828
1829         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1830         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1831         I915_WRITE(IIR, I915_READ(IIR));
1832 }