Merge branch 'x86/core' into cpus4096
[linux-2.6.git] / drivers / gpu / drm / i915 / i915_gem.c
1 /*
2  * Copyright © 2008 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Eric Anholt <eric@anholt.net>
25  *
26  */
27
28 #include "drmP.h"
29 #include "drm.h"
30 #include "i915_drm.h"
31 #include "i915_drv.h"
32 #include <linux/swap.h>
33 #include <linux/pci.h>
34
35 #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
36
37 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
38 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
39 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
40 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
41                                              int write);
42 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
43                                                      uint64_t offset,
44                                                      uint64_t size);
45 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
46 static int i915_gem_object_get_page_list(struct drm_gem_object *obj);
47 static void i915_gem_object_free_page_list(struct drm_gem_object *obj);
48 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
50                                            unsigned alignment);
51 static int i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write);
52 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
53 static int i915_gem_evict_something(struct drm_device *dev);
54 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
55                                 struct drm_i915_gem_pwrite *args,
56                                 struct drm_file *file_priv);
57
58 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
59                      unsigned long end)
60 {
61         drm_i915_private_t *dev_priv = dev->dev_private;
62
63         if (start >= end ||
64             (start & (PAGE_SIZE - 1)) != 0 ||
65             (end & (PAGE_SIZE - 1)) != 0) {
66                 return -EINVAL;
67         }
68
69         drm_mm_init(&dev_priv->mm.gtt_space, start,
70                     end - start);
71
72         dev->gtt_total = (uint32_t) (end - start);
73
74         return 0;
75 }
76
77 int
78 i915_gem_init_ioctl(struct drm_device *dev, void *data,
79                     struct drm_file *file_priv)
80 {
81         struct drm_i915_gem_init *args = data;
82         int ret;
83
84         mutex_lock(&dev->struct_mutex);
85         ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
86         mutex_unlock(&dev->struct_mutex);
87
88         return ret;
89 }
90
91 int
92 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
93                             struct drm_file *file_priv)
94 {
95         struct drm_i915_gem_get_aperture *args = data;
96
97         if (!(dev->driver->driver_features & DRIVER_GEM))
98                 return -ENODEV;
99
100         args->aper_size = dev->gtt_total;
101         args->aper_available_size = (args->aper_size -
102                                      atomic_read(&dev->pin_memory));
103
104         return 0;
105 }
106
107
108 /**
109  * Creates a new mm object and returns a handle to it.
110  */
111 int
112 i915_gem_create_ioctl(struct drm_device *dev, void *data,
113                       struct drm_file *file_priv)
114 {
115         struct drm_i915_gem_create *args = data;
116         struct drm_gem_object *obj;
117         int handle, ret;
118
119         args->size = roundup(args->size, PAGE_SIZE);
120
121         /* Allocate the new object */
122         obj = drm_gem_object_alloc(dev, args->size);
123         if (obj == NULL)
124                 return -ENOMEM;
125
126         ret = drm_gem_handle_create(file_priv, obj, &handle);
127         mutex_lock(&dev->struct_mutex);
128         drm_gem_object_handle_unreference(obj);
129         mutex_unlock(&dev->struct_mutex);
130
131         if (ret)
132                 return ret;
133
134         args->handle = handle;
135
136         return 0;
137 }
138
139 /**
140  * Reads data from the object referenced by handle.
141  *
142  * On error, the contents of *data are undefined.
143  */
144 int
145 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
146                      struct drm_file *file_priv)
147 {
148         struct drm_i915_gem_pread *args = data;
149         struct drm_gem_object *obj;
150         struct drm_i915_gem_object *obj_priv;
151         ssize_t read;
152         loff_t offset;
153         int ret;
154
155         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
156         if (obj == NULL)
157                 return -EBADF;
158         obj_priv = obj->driver_private;
159
160         /* Bounds check source.
161          *
162          * XXX: This could use review for overflow issues...
163          */
164         if (args->offset > obj->size || args->size > obj->size ||
165             args->offset + args->size > obj->size) {
166                 drm_gem_object_unreference(obj);
167                 return -EINVAL;
168         }
169
170         mutex_lock(&dev->struct_mutex);
171
172         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
173                                                         args->size);
174         if (ret != 0) {
175                 drm_gem_object_unreference(obj);
176                 mutex_unlock(&dev->struct_mutex);
177                 return ret;
178         }
179
180         offset = args->offset;
181
182         read = vfs_read(obj->filp, (char __user *)(uintptr_t)args->data_ptr,
183                         args->size, &offset);
184         if (read != args->size) {
185                 drm_gem_object_unreference(obj);
186                 mutex_unlock(&dev->struct_mutex);
187                 if (read < 0)
188                         return read;
189                 else
190                         return -EINVAL;
191         }
192
193         drm_gem_object_unreference(obj);
194         mutex_unlock(&dev->struct_mutex);
195
196         return 0;
197 }
198
199 /* This is the fast write path which cannot handle
200  * page faults in the source data
201  */
202
203 static inline int
204 fast_user_write(struct io_mapping *mapping,
205                 loff_t page_base, int page_offset,
206                 char __user *user_data,
207                 int length)
208 {
209         char *vaddr_atomic;
210         unsigned long unwritten;
211
212         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
213         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
214                                                       user_data, length);
215         io_mapping_unmap_atomic(vaddr_atomic);
216         if (unwritten)
217                 return -EFAULT;
218         return 0;
219 }
220
221 /* Here's the write path which can sleep for
222  * page faults
223  */
224
225 static inline int
226 slow_user_write(struct io_mapping *mapping,
227                 loff_t page_base, int page_offset,
228                 char __user *user_data,
229                 int length)
230 {
231         char __iomem *vaddr;
232         unsigned long unwritten;
233
234         vaddr = io_mapping_map_wc(mapping, page_base);
235         if (vaddr == NULL)
236                 return -EFAULT;
237         unwritten = __copy_from_user(vaddr + page_offset,
238                                      user_data, length);
239         io_mapping_unmap(vaddr);
240         if (unwritten)
241                 return -EFAULT;
242         return 0;
243 }
244
245 static int
246 i915_gem_gtt_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
247                     struct drm_i915_gem_pwrite *args,
248                     struct drm_file *file_priv)
249 {
250         struct drm_i915_gem_object *obj_priv = obj->driver_private;
251         drm_i915_private_t *dev_priv = dev->dev_private;
252         ssize_t remain;
253         loff_t offset, page_base;
254         char __user *user_data;
255         int page_offset, page_length;
256         int ret;
257
258         user_data = (char __user *) (uintptr_t) args->data_ptr;
259         remain = args->size;
260         if (!access_ok(VERIFY_READ, user_data, remain))
261                 return -EFAULT;
262
263
264         mutex_lock(&dev->struct_mutex);
265         ret = i915_gem_object_pin(obj, 0);
266         if (ret) {
267                 mutex_unlock(&dev->struct_mutex);
268                 return ret;
269         }
270         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
271         if (ret)
272                 goto fail;
273
274         obj_priv = obj->driver_private;
275         offset = obj_priv->gtt_offset + args->offset;
276         obj_priv->dirty = 1;
277
278         while (remain > 0) {
279                 /* Operation in this page
280                  *
281                  * page_base = page offset within aperture
282                  * page_offset = offset within page
283                  * page_length = bytes to copy for this page
284                  */
285                 page_base = (offset & ~(PAGE_SIZE-1));
286                 page_offset = offset & (PAGE_SIZE-1);
287                 page_length = remain;
288                 if ((page_offset + remain) > PAGE_SIZE)
289                         page_length = PAGE_SIZE - page_offset;
290
291                 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
292                                        page_offset, user_data, page_length);
293
294                 /* If we get a fault while copying data, then (presumably) our
295                  * source page isn't available. In this case, use the
296                  * non-atomic function
297                  */
298                 if (ret) {
299                         ret = slow_user_write (dev_priv->mm.gtt_mapping,
300                                                page_base, page_offset,
301                                                user_data, page_length);
302                         if (ret)
303                                 goto fail;
304                 }
305
306                 remain -= page_length;
307                 user_data += page_length;
308                 offset += page_length;
309         }
310
311 fail:
312         i915_gem_object_unpin(obj);
313         mutex_unlock(&dev->struct_mutex);
314
315         return ret;
316 }
317
318 static int
319 i915_gem_shmem_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
320                       struct drm_i915_gem_pwrite *args,
321                       struct drm_file *file_priv)
322 {
323         int ret;
324         loff_t offset;
325         ssize_t written;
326
327         mutex_lock(&dev->struct_mutex);
328
329         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
330         if (ret) {
331                 mutex_unlock(&dev->struct_mutex);
332                 return ret;
333         }
334
335         offset = args->offset;
336
337         written = vfs_write(obj->filp,
338                             (char __user *)(uintptr_t) args->data_ptr,
339                             args->size, &offset);
340         if (written != args->size) {
341                 mutex_unlock(&dev->struct_mutex);
342                 if (written < 0)
343                         return written;
344                 else
345                         return -EINVAL;
346         }
347
348         mutex_unlock(&dev->struct_mutex);
349
350         return 0;
351 }
352
353 /**
354  * Writes data to the object referenced by handle.
355  *
356  * On error, the contents of the buffer that were to be modified are undefined.
357  */
358 int
359 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
360                       struct drm_file *file_priv)
361 {
362         struct drm_i915_gem_pwrite *args = data;
363         struct drm_gem_object *obj;
364         struct drm_i915_gem_object *obj_priv;
365         int ret = 0;
366
367         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
368         if (obj == NULL)
369                 return -EBADF;
370         obj_priv = obj->driver_private;
371
372         /* Bounds check destination.
373          *
374          * XXX: This could use review for overflow issues...
375          */
376         if (args->offset > obj->size || args->size > obj->size ||
377             args->offset + args->size > obj->size) {
378                 drm_gem_object_unreference(obj);
379                 return -EINVAL;
380         }
381
382         /* We can only do the GTT pwrite on untiled buffers, as otherwise
383          * it would end up going through the fenced access, and we'll get
384          * different detiling behavior between reading and writing.
385          * pread/pwrite currently are reading and writing from the CPU
386          * perspective, requiring manual detiling by the client.
387          */
388         if (obj_priv->phys_obj)
389                 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
390         else if (obj_priv->tiling_mode == I915_TILING_NONE &&
391                  dev->gtt_total != 0)
392                 ret = i915_gem_gtt_pwrite(dev, obj, args, file_priv);
393         else
394                 ret = i915_gem_shmem_pwrite(dev, obj, args, file_priv);
395
396 #if WATCH_PWRITE
397         if (ret)
398                 DRM_INFO("pwrite failed %d\n", ret);
399 #endif
400
401         drm_gem_object_unreference(obj);
402
403         return ret;
404 }
405
406 /**
407  * Called when user space prepares to use an object with the CPU, either
408  * through the mmap ioctl's mapping or a GTT mapping.
409  */
410 int
411 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
412                           struct drm_file *file_priv)
413 {
414         struct drm_i915_gem_set_domain *args = data;
415         struct drm_gem_object *obj;
416         uint32_t read_domains = args->read_domains;
417         uint32_t write_domain = args->write_domain;
418         int ret;
419
420         if (!(dev->driver->driver_features & DRIVER_GEM))
421                 return -ENODEV;
422
423         /* Only handle setting domains to types used by the CPU. */
424         if (write_domain & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
425                 return -EINVAL;
426
427         if (read_domains & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
428                 return -EINVAL;
429
430         /* Having something in the write domain implies it's in the read
431          * domain, and only that read domain.  Enforce that in the request.
432          */
433         if (write_domain != 0 && read_domains != write_domain)
434                 return -EINVAL;
435
436         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
437         if (obj == NULL)
438                 return -EBADF;
439
440         mutex_lock(&dev->struct_mutex);
441 #if WATCH_BUF
442         DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n",
443                  obj, obj->size, read_domains, write_domain);
444 #endif
445         if (read_domains & I915_GEM_DOMAIN_GTT) {
446                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
447
448                 /* Silently promote "you're not bound, there was nothing to do"
449                  * to success, since the client was just asking us to
450                  * make sure everything was done.
451                  */
452                 if (ret == -EINVAL)
453                         ret = 0;
454         } else {
455                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
456         }
457
458         drm_gem_object_unreference(obj);
459         mutex_unlock(&dev->struct_mutex);
460         return ret;
461 }
462
463 /**
464  * Called when user space has done writes to this buffer
465  */
466 int
467 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
468                       struct drm_file *file_priv)
469 {
470         struct drm_i915_gem_sw_finish *args = data;
471         struct drm_gem_object *obj;
472         struct drm_i915_gem_object *obj_priv;
473         int ret = 0;
474
475         if (!(dev->driver->driver_features & DRIVER_GEM))
476                 return -ENODEV;
477
478         mutex_lock(&dev->struct_mutex);
479         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
480         if (obj == NULL) {
481                 mutex_unlock(&dev->struct_mutex);
482                 return -EBADF;
483         }
484
485 #if WATCH_BUF
486         DRM_INFO("%s: sw_finish %d (%p %d)\n",
487                  __func__, args->handle, obj, obj->size);
488 #endif
489         obj_priv = obj->driver_private;
490
491         /* Pinned buffers may be scanout, so flush the cache */
492         if (obj_priv->pin_count)
493                 i915_gem_object_flush_cpu_write_domain(obj);
494
495         drm_gem_object_unreference(obj);
496         mutex_unlock(&dev->struct_mutex);
497         return ret;
498 }
499
500 /**
501  * Maps the contents of an object, returning the address it is mapped
502  * into.
503  *
504  * While the mapping holds a reference on the contents of the object, it doesn't
505  * imply a ref on the object itself.
506  */
507 int
508 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
509                    struct drm_file *file_priv)
510 {
511         struct drm_i915_gem_mmap *args = data;
512         struct drm_gem_object *obj;
513         loff_t offset;
514         unsigned long addr;
515
516         if (!(dev->driver->driver_features & DRIVER_GEM))
517                 return -ENODEV;
518
519         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
520         if (obj == NULL)
521                 return -EBADF;
522
523         offset = args->offset;
524
525         down_write(&current->mm->mmap_sem);
526         addr = do_mmap(obj->filp, 0, args->size,
527                        PROT_READ | PROT_WRITE, MAP_SHARED,
528                        args->offset);
529         up_write(&current->mm->mmap_sem);
530         mutex_lock(&dev->struct_mutex);
531         drm_gem_object_unreference(obj);
532         mutex_unlock(&dev->struct_mutex);
533         if (IS_ERR((void *)addr))
534                 return addr;
535
536         args->addr_ptr = (uint64_t) addr;
537
538         return 0;
539 }
540
541 /**
542  * i915_gem_fault - fault a page into the GTT
543  * vma: VMA in question
544  * vmf: fault info
545  *
546  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
547  * from userspace.  The fault handler takes care of binding the object to
548  * the GTT (if needed), allocating and programming a fence register (again,
549  * only if needed based on whether the old reg is still valid or the object
550  * is tiled) and inserting a new PTE into the faulting process.
551  *
552  * Note that the faulting process may involve evicting existing objects
553  * from the GTT and/or fence registers to make room.  So performance may
554  * suffer if the GTT working set is large or there are few fence registers
555  * left.
556  */
557 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
558 {
559         struct drm_gem_object *obj = vma->vm_private_data;
560         struct drm_device *dev = obj->dev;
561         struct drm_i915_private *dev_priv = dev->dev_private;
562         struct drm_i915_gem_object *obj_priv = obj->driver_private;
563         pgoff_t page_offset;
564         unsigned long pfn;
565         int ret = 0;
566         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
567
568         /* We don't use vmf->pgoff since that has the fake offset */
569         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
570                 PAGE_SHIFT;
571
572         /* Now bind it into the GTT if needed */
573         mutex_lock(&dev->struct_mutex);
574         if (!obj_priv->gtt_space) {
575                 ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
576                 if (ret) {
577                         mutex_unlock(&dev->struct_mutex);
578                         return VM_FAULT_SIGBUS;
579                 }
580                 list_add(&obj_priv->list, &dev_priv->mm.inactive_list);
581         }
582
583         /* Need a new fence register? */
584         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
585             obj_priv->tiling_mode != I915_TILING_NONE) {
586                 ret = i915_gem_object_get_fence_reg(obj, write);
587                 if (ret) {
588                         mutex_unlock(&dev->struct_mutex);
589                         return VM_FAULT_SIGBUS;
590                 }
591         }
592
593         pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
594                 page_offset;
595
596         /* Finally, remap it using the new GTT offset */
597         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
598
599         mutex_unlock(&dev->struct_mutex);
600
601         switch (ret) {
602         case -ENOMEM:
603         case -EAGAIN:
604                 return VM_FAULT_OOM;
605         case -EFAULT:
606                 return VM_FAULT_SIGBUS;
607         default:
608                 return VM_FAULT_NOPAGE;
609         }
610 }
611
612 /**
613  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
614  * @obj: obj in question
615  *
616  * GEM memory mapping works by handing back to userspace a fake mmap offset
617  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
618  * up the object based on the offset and sets up the various memory mapping
619  * structures.
620  *
621  * This routine allocates and attaches a fake offset for @obj.
622  */
623 static int
624 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
625 {
626         struct drm_device *dev = obj->dev;
627         struct drm_gem_mm *mm = dev->mm_private;
628         struct drm_i915_gem_object *obj_priv = obj->driver_private;
629         struct drm_map_list *list;
630         struct drm_map *map;
631         int ret = 0;
632
633         /* Set the object up for mmap'ing */
634         list = &obj->map_list;
635         list->map = drm_calloc(1, sizeof(struct drm_map_list),
636                                DRM_MEM_DRIVER);
637         if (!list->map)
638                 return -ENOMEM;
639
640         map = list->map;
641         map->type = _DRM_GEM;
642         map->size = obj->size;
643         map->handle = obj;
644
645         /* Get a DRM GEM mmap offset allocated... */
646         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
647                                                     obj->size / PAGE_SIZE, 0, 0);
648         if (!list->file_offset_node) {
649                 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
650                 ret = -ENOMEM;
651                 goto out_free_list;
652         }
653
654         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
655                                                   obj->size / PAGE_SIZE, 0);
656         if (!list->file_offset_node) {
657                 ret = -ENOMEM;
658                 goto out_free_list;
659         }
660
661         list->hash.key = list->file_offset_node->start;
662         if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
663                 DRM_ERROR("failed to add to map hash\n");
664                 goto out_free_mm;
665         }
666
667         /* By now we should be all set, any drm_mmap request on the offset
668          * below will get to our mmap & fault handler */
669         obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
670
671         return 0;
672
673 out_free_mm:
674         drm_mm_put_block(list->file_offset_node);
675 out_free_list:
676         drm_free(list->map, sizeof(struct drm_map_list), DRM_MEM_DRIVER);
677
678         return ret;
679 }
680
681 static void
682 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
683 {
684         struct drm_device *dev = obj->dev;
685         struct drm_i915_gem_object *obj_priv = obj->driver_private;
686         struct drm_gem_mm *mm = dev->mm_private;
687         struct drm_map_list *list;
688
689         list = &obj->map_list;
690         drm_ht_remove_item(&mm->offset_hash, &list->hash);
691
692         if (list->file_offset_node) {
693                 drm_mm_put_block(list->file_offset_node);
694                 list->file_offset_node = NULL;
695         }
696
697         if (list->map) {
698                 drm_free(list->map, sizeof(struct drm_map), DRM_MEM_DRIVER);
699                 list->map = NULL;
700         }
701
702         obj_priv->mmap_offset = 0;
703 }
704
705 /**
706  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
707  * @obj: object to check
708  *
709  * Return the required GTT alignment for an object, taking into account
710  * potential fence register mapping if needed.
711  */
712 static uint32_t
713 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
714 {
715         struct drm_device *dev = obj->dev;
716         struct drm_i915_gem_object *obj_priv = obj->driver_private;
717         int start, i;
718
719         /*
720          * Minimum alignment is 4k (GTT page size), but might be greater
721          * if a fence register is needed for the object.
722          */
723         if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
724                 return 4096;
725
726         /*
727          * Previous chips need to be aligned to the size of the smallest
728          * fence register that can contain the object.
729          */
730         if (IS_I9XX(dev))
731                 start = 1024*1024;
732         else
733                 start = 512*1024;
734
735         for (i = start; i < obj->size; i <<= 1)
736                 ;
737
738         return i;
739 }
740
741 /**
742  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
743  * @dev: DRM device
744  * @data: GTT mapping ioctl data
745  * @file_priv: GEM object info
746  *
747  * Simply returns the fake offset to userspace so it can mmap it.
748  * The mmap call will end up in drm_gem_mmap(), which will set things
749  * up so we can get faults in the handler above.
750  *
751  * The fault handler will take care of binding the object into the GTT
752  * (since it may have been evicted to make room for something), allocating
753  * a fence register, and mapping the appropriate aperture address into
754  * userspace.
755  */
756 int
757 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
758                         struct drm_file *file_priv)
759 {
760         struct drm_i915_gem_mmap_gtt *args = data;
761         struct drm_i915_private *dev_priv = dev->dev_private;
762         struct drm_gem_object *obj;
763         struct drm_i915_gem_object *obj_priv;
764         int ret;
765
766         if (!(dev->driver->driver_features & DRIVER_GEM))
767                 return -ENODEV;
768
769         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
770         if (obj == NULL)
771                 return -EBADF;
772
773         mutex_lock(&dev->struct_mutex);
774
775         obj_priv = obj->driver_private;
776
777         if (!obj_priv->mmap_offset) {
778                 ret = i915_gem_create_mmap_offset(obj);
779                 if (ret) {
780                         drm_gem_object_unreference(obj);
781                         mutex_unlock(&dev->struct_mutex);
782                         return ret;
783                 }
784         }
785
786         args->offset = obj_priv->mmap_offset;
787
788         obj_priv->gtt_alignment = i915_gem_get_gtt_alignment(obj);
789
790         /* Make sure the alignment is correct for fence regs etc */
791         if (obj_priv->agp_mem &&
792             (obj_priv->gtt_offset & (obj_priv->gtt_alignment - 1))) {
793                 drm_gem_object_unreference(obj);
794                 mutex_unlock(&dev->struct_mutex);
795                 return -EINVAL;
796         }
797
798         /*
799          * Pull it into the GTT so that we have a page list (makes the
800          * initial fault faster and any subsequent flushing possible).
801          */
802         if (!obj_priv->agp_mem) {
803                 ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
804                 if (ret) {
805                         drm_gem_object_unreference(obj);
806                         mutex_unlock(&dev->struct_mutex);
807                         return ret;
808                 }
809                 list_add(&obj_priv->list, &dev_priv->mm.inactive_list);
810         }
811
812         drm_gem_object_unreference(obj);
813         mutex_unlock(&dev->struct_mutex);
814
815         return 0;
816 }
817
818 static void
819 i915_gem_object_free_page_list(struct drm_gem_object *obj)
820 {
821         struct drm_i915_gem_object *obj_priv = obj->driver_private;
822         int page_count = obj->size / PAGE_SIZE;
823         int i;
824
825         if (obj_priv->page_list == NULL)
826                 return;
827
828
829         for (i = 0; i < page_count; i++)
830                 if (obj_priv->page_list[i] != NULL) {
831                         if (obj_priv->dirty)
832                                 set_page_dirty(obj_priv->page_list[i]);
833                         mark_page_accessed(obj_priv->page_list[i]);
834                         page_cache_release(obj_priv->page_list[i]);
835                 }
836         obj_priv->dirty = 0;
837
838         drm_free(obj_priv->page_list,
839                  page_count * sizeof(struct page *),
840                  DRM_MEM_DRIVER);
841         obj_priv->page_list = NULL;
842 }
843
844 static void
845 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
846 {
847         struct drm_device *dev = obj->dev;
848         drm_i915_private_t *dev_priv = dev->dev_private;
849         struct drm_i915_gem_object *obj_priv = obj->driver_private;
850
851         /* Add a reference if we're newly entering the active list. */
852         if (!obj_priv->active) {
853                 drm_gem_object_reference(obj);
854                 obj_priv->active = 1;
855         }
856         /* Move from whatever list we were on to the tail of execution. */
857         list_move_tail(&obj_priv->list,
858                        &dev_priv->mm.active_list);
859         obj_priv->last_rendering_seqno = seqno;
860 }
861
862 static void
863 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
864 {
865         struct drm_device *dev = obj->dev;
866         drm_i915_private_t *dev_priv = dev->dev_private;
867         struct drm_i915_gem_object *obj_priv = obj->driver_private;
868
869         BUG_ON(!obj_priv->active);
870         list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
871         obj_priv->last_rendering_seqno = 0;
872 }
873
874 static void
875 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
876 {
877         struct drm_device *dev = obj->dev;
878         drm_i915_private_t *dev_priv = dev->dev_private;
879         struct drm_i915_gem_object *obj_priv = obj->driver_private;
880
881         i915_verify_inactive(dev, __FILE__, __LINE__);
882         if (obj_priv->pin_count != 0)
883                 list_del_init(&obj_priv->list);
884         else
885                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
886
887         obj_priv->last_rendering_seqno = 0;
888         if (obj_priv->active) {
889                 obj_priv->active = 0;
890                 drm_gem_object_unreference(obj);
891         }
892         i915_verify_inactive(dev, __FILE__, __LINE__);
893 }
894
895 /**
896  * Creates a new sequence number, emitting a write of it to the status page
897  * plus an interrupt, which will trigger i915_user_interrupt_handler.
898  *
899  * Must be called with struct_lock held.
900  *
901  * Returned sequence numbers are nonzero on success.
902  */
903 static uint32_t
904 i915_add_request(struct drm_device *dev, uint32_t flush_domains)
905 {
906         drm_i915_private_t *dev_priv = dev->dev_private;
907         struct drm_i915_gem_request *request;
908         uint32_t seqno;
909         int was_empty;
910         RING_LOCALS;
911
912         request = drm_calloc(1, sizeof(*request), DRM_MEM_DRIVER);
913         if (request == NULL)
914                 return 0;
915
916         /* Grab the seqno we're going to make this request be, and bump the
917          * next (skipping 0 so it can be the reserved no-seqno value).
918          */
919         seqno = dev_priv->mm.next_gem_seqno;
920         dev_priv->mm.next_gem_seqno++;
921         if (dev_priv->mm.next_gem_seqno == 0)
922                 dev_priv->mm.next_gem_seqno++;
923
924         BEGIN_LP_RING(4);
925         OUT_RING(MI_STORE_DWORD_INDEX);
926         OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
927         OUT_RING(seqno);
928
929         OUT_RING(MI_USER_INTERRUPT);
930         ADVANCE_LP_RING();
931
932         DRM_DEBUG("%d\n", seqno);
933
934         request->seqno = seqno;
935         request->emitted_jiffies = jiffies;
936         was_empty = list_empty(&dev_priv->mm.request_list);
937         list_add_tail(&request->list, &dev_priv->mm.request_list);
938
939         /* Associate any objects on the flushing list matching the write
940          * domain we're flushing with our flush.
941          */
942         if (flush_domains != 0) {
943                 struct drm_i915_gem_object *obj_priv, *next;
944
945                 list_for_each_entry_safe(obj_priv, next,
946                                          &dev_priv->mm.flushing_list, list) {
947                         struct drm_gem_object *obj = obj_priv->obj;
948
949                         if ((obj->write_domain & flush_domains) ==
950                             obj->write_domain) {
951                                 obj->write_domain = 0;
952                                 i915_gem_object_move_to_active(obj, seqno);
953                         }
954                 }
955
956         }
957
958         if (was_empty && !dev_priv->mm.suspended)
959                 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
960         return seqno;
961 }
962
963 /**
964  * Command execution barrier
965  *
966  * Ensures that all commands in the ring are finished
967  * before signalling the CPU
968  */
969 static uint32_t
970 i915_retire_commands(struct drm_device *dev)
971 {
972         drm_i915_private_t *dev_priv = dev->dev_private;
973         uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
974         uint32_t flush_domains = 0;
975         RING_LOCALS;
976
977         /* The sampler always gets flushed on i965 (sigh) */
978         if (IS_I965G(dev))
979                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
980         BEGIN_LP_RING(2);
981         OUT_RING(cmd);
982         OUT_RING(0); /* noop */
983         ADVANCE_LP_RING();
984         return flush_domains;
985 }
986
987 /**
988  * Moves buffers associated only with the given active seqno from the active
989  * to inactive list, potentially freeing them.
990  */
991 static void
992 i915_gem_retire_request(struct drm_device *dev,
993                         struct drm_i915_gem_request *request)
994 {
995         drm_i915_private_t *dev_priv = dev->dev_private;
996
997         /* Move any buffers on the active list that are no longer referenced
998          * by the ringbuffer to the flushing/inactive lists as appropriate.
999          */
1000         while (!list_empty(&dev_priv->mm.active_list)) {
1001                 struct drm_gem_object *obj;
1002                 struct drm_i915_gem_object *obj_priv;
1003
1004                 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1005                                             struct drm_i915_gem_object,
1006                                             list);
1007                 obj = obj_priv->obj;
1008
1009                 /* If the seqno being retired doesn't match the oldest in the
1010                  * list, then the oldest in the list must still be newer than
1011                  * this seqno.
1012                  */
1013                 if (obj_priv->last_rendering_seqno != request->seqno)
1014                         return;
1015
1016 #if WATCH_LRU
1017                 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1018                          __func__, request->seqno, obj);
1019 #endif
1020
1021                 if (obj->write_domain != 0)
1022                         i915_gem_object_move_to_flushing(obj);
1023                 else
1024                         i915_gem_object_move_to_inactive(obj);
1025         }
1026 }
1027
1028 /**
1029  * Returns true if seq1 is later than seq2.
1030  */
1031 static int
1032 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1033 {
1034         return (int32_t)(seq1 - seq2) >= 0;
1035 }
1036
1037 uint32_t
1038 i915_get_gem_seqno(struct drm_device *dev)
1039 {
1040         drm_i915_private_t *dev_priv = dev->dev_private;
1041
1042         return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1043 }
1044
1045 /**
1046  * This function clears the request list as sequence numbers are passed.
1047  */
1048 void
1049 i915_gem_retire_requests(struct drm_device *dev)
1050 {
1051         drm_i915_private_t *dev_priv = dev->dev_private;
1052         uint32_t seqno;
1053
1054         if (!dev_priv->hw_status_page)
1055                 return;
1056
1057         seqno = i915_get_gem_seqno(dev);
1058
1059         while (!list_empty(&dev_priv->mm.request_list)) {
1060                 struct drm_i915_gem_request *request;
1061                 uint32_t retiring_seqno;
1062
1063                 request = list_first_entry(&dev_priv->mm.request_list,
1064                                            struct drm_i915_gem_request,
1065                                            list);
1066                 retiring_seqno = request->seqno;
1067
1068                 if (i915_seqno_passed(seqno, retiring_seqno) ||
1069                     dev_priv->mm.wedged) {
1070                         i915_gem_retire_request(dev, request);
1071
1072                         list_del(&request->list);
1073                         drm_free(request, sizeof(*request), DRM_MEM_DRIVER);
1074                 } else
1075                         break;
1076         }
1077 }
1078
1079 void
1080 i915_gem_retire_work_handler(struct work_struct *work)
1081 {
1082         drm_i915_private_t *dev_priv;
1083         struct drm_device *dev;
1084
1085         dev_priv = container_of(work, drm_i915_private_t,
1086                                 mm.retire_work.work);
1087         dev = dev_priv->dev;
1088
1089         mutex_lock(&dev->struct_mutex);
1090         i915_gem_retire_requests(dev);
1091         if (!dev_priv->mm.suspended &&
1092             !list_empty(&dev_priv->mm.request_list))
1093                 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
1094         mutex_unlock(&dev->struct_mutex);
1095 }
1096
1097 /**
1098  * Waits for a sequence number to be signaled, and cleans up the
1099  * request and object lists appropriately for that event.
1100  */
1101 static int
1102 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1103 {
1104         drm_i915_private_t *dev_priv = dev->dev_private;
1105         int ret = 0;
1106
1107         BUG_ON(seqno == 0);
1108
1109         if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1110                 dev_priv->mm.waiting_gem_seqno = seqno;
1111                 i915_user_irq_get(dev);
1112                 ret = wait_event_interruptible(dev_priv->irq_queue,
1113                                                i915_seqno_passed(i915_get_gem_seqno(dev),
1114                                                                  seqno) ||
1115                                                dev_priv->mm.wedged);
1116                 i915_user_irq_put(dev);
1117                 dev_priv->mm.waiting_gem_seqno = 0;
1118         }
1119         if (dev_priv->mm.wedged)
1120                 ret = -EIO;
1121
1122         if (ret && ret != -ERESTARTSYS)
1123                 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1124                           __func__, ret, seqno, i915_get_gem_seqno(dev));
1125
1126         /* Directly dispatch request retiring.  While we have the work queue
1127          * to handle this, the waiter on a request often wants an associated
1128          * buffer to have made it to the inactive list, and we would need
1129          * a separate wait queue to handle that.
1130          */
1131         if (ret == 0)
1132                 i915_gem_retire_requests(dev);
1133
1134         return ret;
1135 }
1136
1137 static void
1138 i915_gem_flush(struct drm_device *dev,
1139                uint32_t invalidate_domains,
1140                uint32_t flush_domains)
1141 {
1142         drm_i915_private_t *dev_priv = dev->dev_private;
1143         uint32_t cmd;
1144         RING_LOCALS;
1145
1146 #if WATCH_EXEC
1147         DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1148                   invalidate_domains, flush_domains);
1149 #endif
1150
1151         if (flush_domains & I915_GEM_DOMAIN_CPU)
1152                 drm_agp_chipset_flush(dev);
1153
1154         if ((invalidate_domains | flush_domains) & ~(I915_GEM_DOMAIN_CPU |
1155                                                      I915_GEM_DOMAIN_GTT)) {
1156                 /*
1157                  * read/write caches:
1158                  *
1159                  * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1160                  * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
1161                  * also flushed at 2d versus 3d pipeline switches.
1162                  *
1163                  * read-only caches:
1164                  *
1165                  * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1166                  * MI_READ_FLUSH is set, and is always flushed on 965.
1167                  *
1168                  * I915_GEM_DOMAIN_COMMAND may not exist?
1169                  *
1170                  * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1171                  * invalidated when MI_EXE_FLUSH is set.
1172                  *
1173                  * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1174                  * invalidated with every MI_FLUSH.
1175                  *
1176                  * TLBs:
1177                  *
1178                  * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1179                  * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1180                  * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1181                  * are flushed at any MI_FLUSH.
1182                  */
1183
1184                 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1185                 if ((invalidate_domains|flush_domains) &
1186                     I915_GEM_DOMAIN_RENDER)
1187                         cmd &= ~MI_NO_WRITE_FLUSH;
1188                 if (!IS_I965G(dev)) {
1189                         /*
1190                          * On the 965, the sampler cache always gets flushed
1191                          * and this bit is reserved.
1192                          */
1193                         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1194                                 cmd |= MI_READ_FLUSH;
1195                 }
1196                 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1197                         cmd |= MI_EXE_FLUSH;
1198
1199 #if WATCH_EXEC
1200                 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1201 #endif
1202                 BEGIN_LP_RING(2);
1203                 OUT_RING(cmd);
1204                 OUT_RING(0); /* noop */
1205                 ADVANCE_LP_RING();
1206         }
1207 }
1208
1209 /**
1210  * Ensures that all rendering to the object has completed and the object is
1211  * safe to unbind from the GTT or access from the CPU.
1212  */
1213 static int
1214 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1215 {
1216         struct drm_device *dev = obj->dev;
1217         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1218         int ret;
1219
1220         /* This function only exists to support waiting for existing rendering,
1221          * not for emitting required flushes.
1222          */
1223         BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1224
1225         /* If there is rendering queued on the buffer being evicted, wait for
1226          * it.
1227          */
1228         if (obj_priv->active) {
1229 #if WATCH_BUF
1230                 DRM_INFO("%s: object %p wait for seqno %08x\n",
1231                           __func__, obj, obj_priv->last_rendering_seqno);
1232 #endif
1233                 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1234                 if (ret != 0)
1235                         return ret;
1236         }
1237
1238         return 0;
1239 }
1240
1241 /**
1242  * Unbinds an object from the GTT aperture.
1243  */
1244 int
1245 i915_gem_object_unbind(struct drm_gem_object *obj)
1246 {
1247         struct drm_device *dev = obj->dev;
1248         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1249         loff_t offset;
1250         int ret = 0;
1251
1252 #if WATCH_BUF
1253         DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1254         DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1255 #endif
1256         if (obj_priv->gtt_space == NULL)
1257                 return 0;
1258
1259         if (obj_priv->pin_count != 0) {
1260                 DRM_ERROR("Attempting to unbind pinned buffer\n");
1261                 return -EINVAL;
1262         }
1263
1264         /* Move the object to the CPU domain to ensure that
1265          * any possible CPU writes while it's not in the GTT
1266          * are flushed when we go to remap it. This will
1267          * also ensure that all pending GPU writes are finished
1268          * before we unbind.
1269          */
1270         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1271         if (ret) {
1272                 if (ret != -ERESTARTSYS)
1273                         DRM_ERROR("set_domain failed: %d\n", ret);
1274                 return ret;
1275         }
1276
1277         if (obj_priv->agp_mem != NULL) {
1278                 drm_unbind_agp(obj_priv->agp_mem);
1279                 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1280                 obj_priv->agp_mem = NULL;
1281         }
1282
1283         BUG_ON(obj_priv->active);
1284
1285         /* blow away mappings if mapped through GTT */
1286         offset = ((loff_t) obj->map_list.hash.key) << PAGE_SHIFT;
1287         if (dev->dev_mapping)
1288                 unmap_mapping_range(dev->dev_mapping, offset, obj->size, 1);
1289
1290         if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1291                 i915_gem_clear_fence_reg(obj);
1292
1293         i915_gem_object_free_page_list(obj);
1294
1295         if (obj_priv->gtt_space) {
1296                 atomic_dec(&dev->gtt_count);
1297                 atomic_sub(obj->size, &dev->gtt_memory);
1298
1299                 drm_mm_put_block(obj_priv->gtt_space);
1300                 obj_priv->gtt_space = NULL;
1301         }
1302
1303         /* Remove ourselves from the LRU list if present. */
1304         if (!list_empty(&obj_priv->list))
1305                 list_del_init(&obj_priv->list);
1306
1307         return 0;
1308 }
1309
1310 static int
1311 i915_gem_evict_something(struct drm_device *dev)
1312 {
1313         drm_i915_private_t *dev_priv = dev->dev_private;
1314         struct drm_gem_object *obj;
1315         struct drm_i915_gem_object *obj_priv;
1316         int ret = 0;
1317
1318         for (;;) {
1319                 /* If there's an inactive buffer available now, grab it
1320                  * and be done.
1321                  */
1322                 if (!list_empty(&dev_priv->mm.inactive_list)) {
1323                         obj_priv = list_first_entry(&dev_priv->mm.inactive_list,
1324                                                     struct drm_i915_gem_object,
1325                                                     list);
1326                         obj = obj_priv->obj;
1327                         BUG_ON(obj_priv->pin_count != 0);
1328 #if WATCH_LRU
1329                         DRM_INFO("%s: evicting %p\n", __func__, obj);
1330 #endif
1331                         BUG_ON(obj_priv->active);
1332
1333                         /* Wait on the rendering and unbind the buffer. */
1334                         ret = i915_gem_object_unbind(obj);
1335                         break;
1336                 }
1337
1338                 /* If we didn't get anything, but the ring is still processing
1339                  * things, wait for one of those things to finish and hopefully
1340                  * leave us a buffer to evict.
1341                  */
1342                 if (!list_empty(&dev_priv->mm.request_list)) {
1343                         struct drm_i915_gem_request *request;
1344
1345                         request = list_first_entry(&dev_priv->mm.request_list,
1346                                                    struct drm_i915_gem_request,
1347                                                    list);
1348
1349                         ret = i915_wait_request(dev, request->seqno);
1350                         if (ret)
1351                                 break;
1352
1353                         /* if waiting caused an object to become inactive,
1354                          * then loop around and wait for it. Otherwise, we
1355                          * assume that waiting freed and unbound something,
1356                          * so there should now be some space in the GTT
1357                          */
1358                         if (!list_empty(&dev_priv->mm.inactive_list))
1359                                 continue;
1360                         break;
1361                 }
1362
1363                 /* If we didn't have anything on the request list but there
1364                  * are buffers awaiting a flush, emit one and try again.
1365                  * When we wait on it, those buffers waiting for that flush
1366                  * will get moved to inactive.
1367                  */
1368                 if (!list_empty(&dev_priv->mm.flushing_list)) {
1369                         obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1370                                                     struct drm_i915_gem_object,
1371                                                     list);
1372                         obj = obj_priv->obj;
1373
1374                         i915_gem_flush(dev,
1375                                        obj->write_domain,
1376                                        obj->write_domain);
1377                         i915_add_request(dev, obj->write_domain);
1378
1379                         obj = NULL;
1380                         continue;
1381                 }
1382
1383                 DRM_ERROR("inactive empty %d request empty %d "
1384                           "flushing empty %d\n",
1385                           list_empty(&dev_priv->mm.inactive_list),
1386                           list_empty(&dev_priv->mm.request_list),
1387                           list_empty(&dev_priv->mm.flushing_list));
1388                 /* If we didn't do any of the above, there's nothing to be done
1389                  * and we just can't fit it in.
1390                  */
1391                 return -ENOMEM;
1392         }
1393         return ret;
1394 }
1395
1396 static int
1397 i915_gem_evict_everything(struct drm_device *dev)
1398 {
1399         int ret;
1400
1401         for (;;) {
1402                 ret = i915_gem_evict_something(dev);
1403                 if (ret != 0)
1404                         break;
1405         }
1406         if (ret == -ENOMEM)
1407                 return 0;
1408         return ret;
1409 }
1410
1411 static int
1412 i915_gem_object_get_page_list(struct drm_gem_object *obj)
1413 {
1414         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1415         int page_count, i;
1416         struct address_space *mapping;
1417         struct inode *inode;
1418         struct page *page;
1419         int ret;
1420
1421         if (obj_priv->page_list)
1422                 return 0;
1423
1424         /* Get the list of pages out of our struct file.  They'll be pinned
1425          * at this point until we release them.
1426          */
1427         page_count = obj->size / PAGE_SIZE;
1428         BUG_ON(obj_priv->page_list != NULL);
1429         obj_priv->page_list = drm_calloc(page_count, sizeof(struct page *),
1430                                          DRM_MEM_DRIVER);
1431         if (obj_priv->page_list == NULL) {
1432                 DRM_ERROR("Faled to allocate page list\n");
1433                 return -ENOMEM;
1434         }
1435
1436         inode = obj->filp->f_path.dentry->d_inode;
1437         mapping = inode->i_mapping;
1438         for (i = 0; i < page_count; i++) {
1439                 page = read_mapping_page(mapping, i, NULL);
1440                 if (IS_ERR(page)) {
1441                         ret = PTR_ERR(page);
1442                         DRM_ERROR("read_mapping_page failed: %d\n", ret);
1443                         i915_gem_object_free_page_list(obj);
1444                         return ret;
1445                 }
1446                 obj_priv->page_list[i] = page;
1447         }
1448         return 0;
1449 }
1450
1451 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
1452 {
1453         struct drm_gem_object *obj = reg->obj;
1454         struct drm_device *dev = obj->dev;
1455         drm_i915_private_t *dev_priv = dev->dev_private;
1456         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1457         int regnum = obj_priv->fence_reg;
1458         uint64_t val;
1459
1460         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
1461                     0xfffff000) << 32;
1462         val |= obj_priv->gtt_offset & 0xfffff000;
1463         val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
1464         if (obj_priv->tiling_mode == I915_TILING_Y)
1465                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
1466         val |= I965_FENCE_REG_VALID;
1467
1468         I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
1469 }
1470
1471 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
1472 {
1473         struct drm_gem_object *obj = reg->obj;
1474         struct drm_device *dev = obj->dev;
1475         drm_i915_private_t *dev_priv = dev->dev_private;
1476         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1477         int regnum = obj_priv->fence_reg;
1478         int tile_width;
1479         uint32_t val;
1480         uint32_t pitch_val;
1481
1482         if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
1483             (obj_priv->gtt_offset & (obj->size - 1))) {
1484                 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
1485                      __func__, obj_priv->gtt_offset, obj->size);
1486                 return;
1487         }
1488
1489         if (obj_priv->tiling_mode == I915_TILING_Y &&
1490             HAS_128_BYTE_Y_TILING(dev))
1491                 tile_width = 128;
1492         else
1493                 tile_width = 512;
1494
1495         /* Note: pitch better be a power of two tile widths */
1496         pitch_val = obj_priv->stride / tile_width;
1497         pitch_val = ffs(pitch_val) - 1;
1498
1499         val = obj_priv->gtt_offset;
1500         if (obj_priv->tiling_mode == I915_TILING_Y)
1501                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1502         val |= I915_FENCE_SIZE_BITS(obj->size);
1503         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1504         val |= I830_FENCE_REG_VALID;
1505
1506         I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
1507 }
1508
1509 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
1510 {
1511         struct drm_gem_object *obj = reg->obj;
1512         struct drm_device *dev = obj->dev;
1513         drm_i915_private_t *dev_priv = dev->dev_private;
1514         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1515         int regnum = obj_priv->fence_reg;
1516         uint32_t val;
1517         uint32_t pitch_val;
1518
1519         if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
1520             (obj_priv->gtt_offset & (obj->size - 1))) {
1521                 WARN(1, "%s: object 0x%08x not 1M or size aligned\n",
1522                      __func__, obj_priv->gtt_offset);
1523                 return;
1524         }
1525
1526         pitch_val = (obj_priv->stride / 128) - 1;
1527
1528         val = obj_priv->gtt_offset;
1529         if (obj_priv->tiling_mode == I915_TILING_Y)
1530                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1531         val |= I830_FENCE_SIZE_BITS(obj->size);
1532         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1533         val |= I830_FENCE_REG_VALID;
1534
1535         I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
1536
1537 }
1538
1539 /**
1540  * i915_gem_object_get_fence_reg - set up a fence reg for an object
1541  * @obj: object to map through a fence reg
1542  * @write: object is about to be written
1543  *
1544  * When mapping objects through the GTT, userspace wants to be able to write
1545  * to them without having to worry about swizzling if the object is tiled.
1546  *
1547  * This function walks the fence regs looking for a free one for @obj,
1548  * stealing one if it can't find any.
1549  *
1550  * It then sets up the reg based on the object's properties: address, pitch
1551  * and tiling format.
1552  */
1553 static int
1554 i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write)
1555 {
1556         struct drm_device *dev = obj->dev;
1557         struct drm_i915_private *dev_priv = dev->dev_private;
1558         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1559         struct drm_i915_fence_reg *reg = NULL;
1560         int i, ret;
1561
1562         switch (obj_priv->tiling_mode) {
1563         case I915_TILING_NONE:
1564                 WARN(1, "allocating a fence for non-tiled object?\n");
1565                 break;
1566         case I915_TILING_X:
1567                 if (!obj_priv->stride)
1568                         return -EINVAL;
1569                 WARN((obj_priv->stride & (512 - 1)),
1570                      "object 0x%08x is X tiled but has non-512B pitch\n",
1571                      obj_priv->gtt_offset);
1572                 break;
1573         case I915_TILING_Y:
1574                 if (!obj_priv->stride)
1575                         return -EINVAL;
1576                 WARN((obj_priv->stride & (128 - 1)),
1577                      "object 0x%08x is Y tiled but has non-128B pitch\n",
1578                      obj_priv->gtt_offset);
1579                 break;
1580         }
1581
1582         /* First try to find a free reg */
1583         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
1584                 reg = &dev_priv->fence_regs[i];
1585                 if (!reg->obj)
1586                         break;
1587         }
1588
1589         /* None available, try to steal one or wait for a user to finish */
1590         if (i == dev_priv->num_fence_regs) {
1591                 struct drm_i915_gem_object *old_obj_priv = NULL;
1592                 loff_t offset;
1593
1594 try_again:
1595                 /* Could try to use LRU here instead... */
1596                 for (i = dev_priv->fence_reg_start;
1597                      i < dev_priv->num_fence_regs; i++) {
1598                         reg = &dev_priv->fence_regs[i];
1599                         old_obj_priv = reg->obj->driver_private;
1600                         if (!old_obj_priv->pin_count)
1601                                 break;
1602                 }
1603
1604                 /*
1605                  * Now things get ugly... we have to wait for one of the
1606                  * objects to finish before trying again.
1607                  */
1608                 if (i == dev_priv->num_fence_regs) {
1609                         ret = i915_gem_object_set_to_gtt_domain(reg->obj, 0);
1610                         if (ret) {
1611                                 WARN(ret != -ERESTARTSYS,
1612                                      "switch to GTT domain failed: %d\n", ret);
1613                                 return ret;
1614                         }
1615                         goto try_again;
1616                 }
1617
1618                 /*
1619                  * Zap this virtual mapping so we can set up a fence again
1620                  * for this object next time we need it.
1621                  */
1622                 offset = ((loff_t) reg->obj->map_list.hash.key) << PAGE_SHIFT;
1623                 if (dev->dev_mapping)
1624                         unmap_mapping_range(dev->dev_mapping, offset,
1625                                             reg->obj->size, 1);
1626                 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
1627         }
1628
1629         obj_priv->fence_reg = i;
1630         reg->obj = obj;
1631
1632         if (IS_I965G(dev))
1633                 i965_write_fence_reg(reg);
1634         else if (IS_I9XX(dev))
1635                 i915_write_fence_reg(reg);
1636         else
1637                 i830_write_fence_reg(reg);
1638
1639         return 0;
1640 }
1641
1642 /**
1643  * i915_gem_clear_fence_reg - clear out fence register info
1644  * @obj: object to clear
1645  *
1646  * Zeroes out the fence register itself and clears out the associated
1647  * data structures in dev_priv and obj_priv.
1648  */
1649 static void
1650 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
1651 {
1652         struct drm_device *dev = obj->dev;
1653         drm_i915_private_t *dev_priv = dev->dev_private;
1654         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1655
1656         if (IS_I965G(dev))
1657                 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
1658         else
1659                 I915_WRITE(FENCE_REG_830_0 + (obj_priv->fence_reg * 4), 0);
1660
1661         dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
1662         obj_priv->fence_reg = I915_FENCE_REG_NONE;
1663 }
1664
1665 /**
1666  * Finds free space in the GTT aperture and binds the object there.
1667  */
1668 static int
1669 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
1670 {
1671         struct drm_device *dev = obj->dev;
1672         drm_i915_private_t *dev_priv = dev->dev_private;
1673         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1674         struct drm_mm_node *free_space;
1675         int page_count, ret;
1676
1677         if (dev_priv->mm.suspended)
1678                 return -EBUSY;
1679         if (alignment == 0)
1680                 alignment = i915_gem_get_gtt_alignment(obj);
1681         if (alignment & (PAGE_SIZE - 1)) {
1682                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
1683                 return -EINVAL;
1684         }
1685
1686  search_free:
1687         free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
1688                                         obj->size, alignment, 0);
1689         if (free_space != NULL) {
1690                 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
1691                                                        alignment);
1692                 if (obj_priv->gtt_space != NULL) {
1693                         obj_priv->gtt_space->private = obj;
1694                         obj_priv->gtt_offset = obj_priv->gtt_space->start;
1695                 }
1696         }
1697         if (obj_priv->gtt_space == NULL) {
1698                 /* If the gtt is empty and we're still having trouble
1699                  * fitting our object in, we're out of memory.
1700                  */
1701 #if WATCH_LRU
1702                 DRM_INFO("%s: GTT full, evicting something\n", __func__);
1703 #endif
1704                 if (list_empty(&dev_priv->mm.inactive_list) &&
1705                     list_empty(&dev_priv->mm.flushing_list) &&
1706                     list_empty(&dev_priv->mm.active_list)) {
1707                         DRM_ERROR("GTT full, but LRU list empty\n");
1708                         return -ENOMEM;
1709                 }
1710
1711                 ret = i915_gem_evict_something(dev);
1712                 if (ret != 0) {
1713                         if (ret != -ERESTARTSYS)
1714                                 DRM_ERROR("Failed to evict a buffer %d\n", ret);
1715                         return ret;
1716                 }
1717                 goto search_free;
1718         }
1719
1720 #if WATCH_BUF
1721         DRM_INFO("Binding object of size %d at 0x%08x\n",
1722                  obj->size, obj_priv->gtt_offset);
1723 #endif
1724         ret = i915_gem_object_get_page_list(obj);
1725         if (ret) {
1726                 drm_mm_put_block(obj_priv->gtt_space);
1727                 obj_priv->gtt_space = NULL;
1728                 return ret;
1729         }
1730
1731         page_count = obj->size / PAGE_SIZE;
1732         /* Create an AGP memory structure pointing at our pages, and bind it
1733          * into the GTT.
1734          */
1735         obj_priv->agp_mem = drm_agp_bind_pages(dev,
1736                                                obj_priv->page_list,
1737                                                page_count,
1738                                                obj_priv->gtt_offset,
1739                                                obj_priv->agp_type);
1740         if (obj_priv->agp_mem == NULL) {
1741                 i915_gem_object_free_page_list(obj);
1742                 drm_mm_put_block(obj_priv->gtt_space);
1743                 obj_priv->gtt_space = NULL;
1744                 return -ENOMEM;
1745         }
1746         atomic_inc(&dev->gtt_count);
1747         atomic_add(obj->size, &dev->gtt_memory);
1748
1749         /* Assert that the object is not currently in any GPU domain. As it
1750          * wasn't in the GTT, there shouldn't be any way it could have been in
1751          * a GPU cache
1752          */
1753         BUG_ON(obj->read_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1754         BUG_ON(obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1755
1756         return 0;
1757 }
1758
1759 void
1760 i915_gem_clflush_object(struct drm_gem_object *obj)
1761 {
1762         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
1763
1764         /* If we don't have a page list set up, then we're not pinned
1765          * to GPU, and we can ignore the cache flush because it'll happen
1766          * again at bind time.
1767          */
1768         if (obj_priv->page_list == NULL)
1769                 return;
1770
1771         drm_clflush_pages(obj_priv->page_list, obj->size / PAGE_SIZE);
1772 }
1773
1774 /** Flushes any GPU write domain for the object if it's dirty. */
1775 static void
1776 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
1777 {
1778         struct drm_device *dev = obj->dev;
1779         uint32_t seqno;
1780
1781         if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
1782                 return;
1783
1784         /* Queue the GPU write cache flushing we need. */
1785         i915_gem_flush(dev, 0, obj->write_domain);
1786         seqno = i915_add_request(dev, obj->write_domain);
1787         obj->write_domain = 0;
1788         i915_gem_object_move_to_active(obj, seqno);
1789 }
1790
1791 /** Flushes the GTT write domain for the object if it's dirty. */
1792 static void
1793 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
1794 {
1795         if (obj->write_domain != I915_GEM_DOMAIN_GTT)
1796                 return;
1797
1798         /* No actual flushing is required for the GTT write domain.   Writes
1799          * to it immediately go to main memory as far as we know, so there's
1800          * no chipset flush.  It also doesn't land in render cache.
1801          */
1802         obj->write_domain = 0;
1803 }
1804
1805 /** Flushes the CPU write domain for the object if it's dirty. */
1806 static void
1807 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
1808 {
1809         struct drm_device *dev = obj->dev;
1810
1811         if (obj->write_domain != I915_GEM_DOMAIN_CPU)
1812                 return;
1813
1814         i915_gem_clflush_object(obj);
1815         drm_agp_chipset_flush(dev);
1816         obj->write_domain = 0;
1817 }
1818
1819 /**
1820  * Moves a single object to the GTT read, and possibly write domain.
1821  *
1822  * This function returns when the move is complete, including waiting on
1823  * flushes to occur.
1824  */
1825 int
1826 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
1827 {
1828         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1829         int ret;
1830
1831         /* Not valid to be called on unbound objects. */
1832         if (obj_priv->gtt_space == NULL)
1833                 return -EINVAL;
1834
1835         i915_gem_object_flush_gpu_write_domain(obj);
1836         /* Wait on any GPU rendering and flushing to occur. */
1837         ret = i915_gem_object_wait_rendering(obj);
1838         if (ret != 0)
1839                 return ret;
1840
1841         /* If we're writing through the GTT domain, then CPU and GPU caches
1842          * will need to be invalidated at next use.
1843          */
1844         if (write)
1845                 obj->read_domains &= I915_GEM_DOMAIN_GTT;
1846
1847         i915_gem_object_flush_cpu_write_domain(obj);
1848
1849         /* It should now be out of any other write domains, and we can update
1850          * the domain values for our changes.
1851          */
1852         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
1853         obj->read_domains |= I915_GEM_DOMAIN_GTT;
1854         if (write) {
1855                 obj->write_domain = I915_GEM_DOMAIN_GTT;
1856                 obj_priv->dirty = 1;
1857         }
1858
1859         return 0;
1860 }
1861
1862 /**
1863  * Moves a single object to the CPU read, and possibly write domain.
1864  *
1865  * This function returns when the move is complete, including waiting on
1866  * flushes to occur.
1867  */
1868 static int
1869 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
1870 {
1871         struct drm_device *dev = obj->dev;
1872         int ret;
1873
1874         i915_gem_object_flush_gpu_write_domain(obj);
1875         /* Wait on any GPU rendering and flushing to occur. */
1876         ret = i915_gem_object_wait_rendering(obj);
1877         if (ret != 0)
1878                 return ret;
1879
1880         i915_gem_object_flush_gtt_write_domain(obj);
1881
1882         /* If we have a partially-valid cache of the object in the CPU,
1883          * finish invalidating it and free the per-page flags.
1884          */
1885         i915_gem_object_set_to_full_cpu_read_domain(obj);
1886
1887         /* Flush the CPU cache if it's still invalid. */
1888         if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
1889                 i915_gem_clflush_object(obj);
1890                 drm_agp_chipset_flush(dev);
1891
1892                 obj->read_domains |= I915_GEM_DOMAIN_CPU;
1893         }
1894
1895         /* It should now be out of any other write domains, and we can update
1896          * the domain values for our changes.
1897          */
1898         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
1899
1900         /* If we're writing through the CPU, then the GPU read domains will
1901          * need to be invalidated at next use.
1902          */
1903         if (write) {
1904                 obj->read_domains &= I915_GEM_DOMAIN_CPU;
1905                 obj->write_domain = I915_GEM_DOMAIN_CPU;
1906         }
1907
1908         return 0;
1909 }
1910
1911 /*
1912  * Set the next domain for the specified object. This
1913  * may not actually perform the necessary flushing/invaliding though,
1914  * as that may want to be batched with other set_domain operations
1915  *
1916  * This is (we hope) the only really tricky part of gem. The goal
1917  * is fairly simple -- track which caches hold bits of the object
1918  * and make sure they remain coherent. A few concrete examples may
1919  * help to explain how it works. For shorthand, we use the notation
1920  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
1921  * a pair of read and write domain masks.
1922  *
1923  * Case 1: the batch buffer
1924  *
1925  *      1. Allocated
1926  *      2. Written by CPU
1927  *      3. Mapped to GTT
1928  *      4. Read by GPU
1929  *      5. Unmapped from GTT
1930  *      6. Freed
1931  *
1932  *      Let's take these a step at a time
1933  *
1934  *      1. Allocated
1935  *              Pages allocated from the kernel may still have
1936  *              cache contents, so we set them to (CPU, CPU) always.
1937  *      2. Written by CPU (using pwrite)
1938  *              The pwrite function calls set_domain (CPU, CPU) and
1939  *              this function does nothing (as nothing changes)
1940  *      3. Mapped by GTT
1941  *              This function asserts that the object is not
1942  *              currently in any GPU-based read or write domains
1943  *      4. Read by GPU
1944  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
1945  *              As write_domain is zero, this function adds in the
1946  *              current read domains (CPU+COMMAND, 0).
1947  *              flush_domains is set to CPU.
1948  *              invalidate_domains is set to COMMAND
1949  *              clflush is run to get data out of the CPU caches
1950  *              then i915_dev_set_domain calls i915_gem_flush to
1951  *              emit an MI_FLUSH and drm_agp_chipset_flush
1952  *      5. Unmapped from GTT
1953  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
1954  *              flush_domains and invalidate_domains end up both zero
1955  *              so no flushing/invalidating happens
1956  *      6. Freed
1957  *              yay, done
1958  *
1959  * Case 2: The shared render buffer
1960  *
1961  *      1. Allocated
1962  *      2. Mapped to GTT
1963  *      3. Read/written by GPU
1964  *      4. set_domain to (CPU,CPU)
1965  *      5. Read/written by CPU
1966  *      6. Read/written by GPU
1967  *
1968  *      1. Allocated
1969  *              Same as last example, (CPU, CPU)
1970  *      2. Mapped to GTT
1971  *              Nothing changes (assertions find that it is not in the GPU)
1972  *      3. Read/written by GPU
1973  *              execbuffer calls set_domain (RENDER, RENDER)
1974  *              flush_domains gets CPU
1975  *              invalidate_domains gets GPU
1976  *              clflush (obj)
1977  *              MI_FLUSH and drm_agp_chipset_flush
1978  *      4. set_domain (CPU, CPU)
1979  *              flush_domains gets GPU
1980  *              invalidate_domains gets CPU
1981  *              wait_rendering (obj) to make sure all drawing is complete.
1982  *              This will include an MI_FLUSH to get the data from GPU
1983  *              to memory
1984  *              clflush (obj) to invalidate the CPU cache
1985  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
1986  *      5. Read/written by CPU
1987  *              cache lines are loaded and dirtied
1988  *      6. Read written by GPU
1989  *              Same as last GPU access
1990  *
1991  * Case 3: The constant buffer
1992  *
1993  *      1. Allocated
1994  *      2. Written by CPU
1995  *      3. Read by GPU
1996  *      4. Updated (written) by CPU again
1997  *      5. Read by GPU
1998  *
1999  *      1. Allocated
2000  *              (CPU, CPU)
2001  *      2. Written by CPU
2002  *              (CPU, CPU)
2003  *      3. Read by GPU
2004  *              (CPU+RENDER, 0)
2005  *              flush_domains = CPU
2006  *              invalidate_domains = RENDER
2007  *              clflush (obj)
2008  *              MI_FLUSH
2009  *              drm_agp_chipset_flush
2010  *      4. Updated (written) by CPU again
2011  *              (CPU, CPU)
2012  *              flush_domains = 0 (no previous write domain)
2013  *              invalidate_domains = 0 (no new read domains)
2014  *      5. Read by GPU
2015  *              (CPU+RENDER, 0)
2016  *              flush_domains = CPU
2017  *              invalidate_domains = RENDER
2018  *              clflush (obj)
2019  *              MI_FLUSH
2020  *              drm_agp_chipset_flush
2021  */
2022 static void
2023 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2024 {
2025         struct drm_device               *dev = obj->dev;
2026         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
2027         uint32_t                        invalidate_domains = 0;
2028         uint32_t                        flush_domains = 0;
2029
2030         BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2031         BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
2032
2033 #if WATCH_BUF
2034         DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2035                  __func__, obj,
2036                  obj->read_domains, obj->pending_read_domains,
2037                  obj->write_domain, obj->pending_write_domain);
2038 #endif
2039         /*
2040          * If the object isn't moving to a new write domain,
2041          * let the object stay in multiple read domains
2042          */
2043         if (obj->pending_write_domain == 0)
2044                 obj->pending_read_domains |= obj->read_domains;
2045         else
2046                 obj_priv->dirty = 1;
2047
2048         /*
2049          * Flush the current write domain if
2050          * the new read domains don't match. Invalidate
2051          * any read domains which differ from the old
2052          * write domain
2053          */
2054         if (obj->write_domain &&
2055             obj->write_domain != obj->pending_read_domains) {
2056                 flush_domains |= obj->write_domain;
2057                 invalidate_domains |=
2058                         obj->pending_read_domains & ~obj->write_domain;
2059         }
2060         /*
2061          * Invalidate any read caches which may have
2062          * stale data. That is, any new read domains.
2063          */
2064         invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
2065         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
2066 #if WATCH_BUF
2067                 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
2068                          __func__, flush_domains, invalidate_domains);
2069 #endif
2070                 i915_gem_clflush_object(obj);
2071         }
2072
2073         /* The actual obj->write_domain will be updated with
2074          * pending_write_domain after we emit the accumulated flush for all
2075          * of our domain changes in execbuffers (which clears objects'
2076          * write_domains).  So if we have a current write domain that we
2077          * aren't changing, set pending_write_domain to that.
2078          */
2079         if (flush_domains == 0 && obj->pending_write_domain == 0)
2080                 obj->pending_write_domain = obj->write_domain;
2081         obj->read_domains = obj->pending_read_domains;
2082
2083         dev->invalidate_domains |= invalidate_domains;
2084         dev->flush_domains |= flush_domains;
2085 #if WATCH_BUF
2086         DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
2087                  __func__,
2088                  obj->read_domains, obj->write_domain,
2089                  dev->invalidate_domains, dev->flush_domains);
2090 #endif
2091 }
2092
2093 /**
2094  * Moves the object from a partially CPU read to a full one.
2095  *
2096  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
2097  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
2098  */
2099 static void
2100 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
2101 {
2102         struct drm_device *dev = obj->dev;
2103         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2104
2105         if (!obj_priv->page_cpu_valid)
2106                 return;
2107
2108         /* If we're partially in the CPU read domain, finish moving it in.
2109          */
2110         if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
2111                 int i;
2112
2113                 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
2114                         if (obj_priv->page_cpu_valid[i])
2115                                 continue;
2116                         drm_clflush_pages(obj_priv->page_list + i, 1);
2117                 }
2118                 drm_agp_chipset_flush(dev);
2119         }
2120
2121         /* Free the page_cpu_valid mappings which are now stale, whether
2122          * or not we've got I915_GEM_DOMAIN_CPU.
2123          */
2124         drm_free(obj_priv->page_cpu_valid, obj->size / PAGE_SIZE,
2125                  DRM_MEM_DRIVER);
2126         obj_priv->page_cpu_valid = NULL;
2127 }
2128
2129 /**
2130  * Set the CPU read domain on a range of the object.
2131  *
2132  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
2133  * not entirely valid.  The page_cpu_valid member of the object flags which
2134  * pages have been flushed, and will be respected by
2135  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
2136  * of the whole object.
2137  *
2138  * This function returns when the move is complete, including waiting on
2139  * flushes to occur.
2140  */
2141 static int
2142 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
2143                                           uint64_t offset, uint64_t size)
2144 {
2145         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2146         int i, ret;
2147
2148         if (offset == 0 && size == obj->size)
2149                 return i915_gem_object_set_to_cpu_domain(obj, 0);
2150
2151         i915_gem_object_flush_gpu_write_domain(obj);
2152         /* Wait on any GPU rendering and flushing to occur. */
2153         ret = i915_gem_object_wait_rendering(obj);
2154         if (ret != 0)
2155                 return ret;
2156         i915_gem_object_flush_gtt_write_domain(obj);
2157
2158         /* If we're already fully in the CPU read domain, we're done. */
2159         if (obj_priv->page_cpu_valid == NULL &&
2160             (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
2161                 return 0;
2162
2163         /* Otherwise, create/clear the per-page CPU read domain flag if we're
2164          * newly adding I915_GEM_DOMAIN_CPU
2165          */
2166         if (obj_priv->page_cpu_valid == NULL) {
2167                 obj_priv->page_cpu_valid = drm_calloc(1, obj->size / PAGE_SIZE,
2168                                                       DRM_MEM_DRIVER);
2169                 if (obj_priv->page_cpu_valid == NULL)
2170                         return -ENOMEM;
2171         } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
2172                 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
2173
2174         /* Flush the cache on any pages that are still invalid from the CPU's
2175          * perspective.
2176          */
2177         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
2178              i++) {
2179                 if (obj_priv->page_cpu_valid[i])
2180                         continue;
2181
2182                 drm_clflush_pages(obj_priv->page_list + i, 1);
2183
2184                 obj_priv->page_cpu_valid[i] = 1;
2185         }
2186
2187         /* It should now be out of any other write domains, and we can update
2188          * the domain values for our changes.
2189          */
2190         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2191
2192         obj->read_domains |= I915_GEM_DOMAIN_CPU;
2193
2194         return 0;
2195 }
2196
2197 /**
2198  * Pin an object to the GTT and evaluate the relocations landing in it.
2199  */
2200 static int
2201 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
2202                                  struct drm_file *file_priv,
2203                                  struct drm_i915_gem_exec_object *entry)
2204 {
2205         struct drm_device *dev = obj->dev;
2206         drm_i915_private_t *dev_priv = dev->dev_private;
2207         struct drm_i915_gem_relocation_entry reloc;
2208         struct drm_i915_gem_relocation_entry __user *relocs;
2209         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2210         int i, ret;
2211         void __iomem *reloc_page;
2212
2213         /* Choose the GTT offset for our buffer and put it there. */
2214         ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
2215         if (ret)
2216                 return ret;
2217
2218         entry->offset = obj_priv->gtt_offset;
2219
2220         relocs = (struct drm_i915_gem_relocation_entry __user *)
2221                  (uintptr_t) entry->relocs_ptr;
2222         /* Apply the relocations, using the GTT aperture to avoid cache
2223          * flushing requirements.
2224          */
2225         for (i = 0; i < entry->relocation_count; i++) {
2226                 struct drm_gem_object *target_obj;
2227                 struct drm_i915_gem_object *target_obj_priv;
2228                 uint32_t reloc_val, reloc_offset;
2229                 uint32_t __iomem *reloc_entry;
2230
2231                 ret = copy_from_user(&reloc, relocs + i, sizeof(reloc));
2232                 if (ret != 0) {
2233                         i915_gem_object_unpin(obj);
2234                         return ret;
2235                 }
2236
2237                 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
2238                                                    reloc.target_handle);
2239                 if (target_obj == NULL) {
2240                         i915_gem_object_unpin(obj);
2241                         return -EBADF;
2242                 }
2243                 target_obj_priv = target_obj->driver_private;
2244
2245                 /* The target buffer should have appeared before us in the
2246                  * exec_object list, so it should have a GTT space bound by now.
2247                  */
2248                 if (target_obj_priv->gtt_space == NULL) {
2249                         DRM_ERROR("No GTT space found for object %d\n",
2250                                   reloc.target_handle);
2251                         drm_gem_object_unreference(target_obj);
2252                         i915_gem_object_unpin(obj);
2253                         return -EINVAL;
2254                 }
2255
2256                 if (reloc.offset > obj->size - 4) {
2257                         DRM_ERROR("Relocation beyond object bounds: "
2258                                   "obj %p target %d offset %d size %d.\n",
2259                                   obj, reloc.target_handle,
2260                                   (int) reloc.offset, (int) obj->size);
2261                         drm_gem_object_unreference(target_obj);
2262                         i915_gem_object_unpin(obj);
2263                         return -EINVAL;
2264                 }
2265                 if (reloc.offset & 3) {
2266                         DRM_ERROR("Relocation not 4-byte aligned: "
2267                                   "obj %p target %d offset %d.\n",
2268                                   obj, reloc.target_handle,
2269                                   (int) reloc.offset);
2270                         drm_gem_object_unreference(target_obj);
2271                         i915_gem_object_unpin(obj);
2272                         return -EINVAL;
2273                 }
2274
2275                 if (reloc.write_domain & I915_GEM_DOMAIN_CPU ||
2276                     reloc.read_domains & I915_GEM_DOMAIN_CPU) {
2277                         DRM_ERROR("reloc with read/write CPU domains: "
2278                                   "obj %p target %d offset %d "
2279                                   "read %08x write %08x",
2280                                   obj, reloc.target_handle,
2281                                   (int) reloc.offset,
2282                                   reloc.read_domains,
2283                                   reloc.write_domain);
2284                         drm_gem_object_unreference(target_obj);
2285                         i915_gem_object_unpin(obj);
2286                         return -EINVAL;
2287                 }
2288
2289                 if (reloc.write_domain && target_obj->pending_write_domain &&
2290                     reloc.write_domain != target_obj->pending_write_domain) {
2291                         DRM_ERROR("Write domain conflict: "
2292                                   "obj %p target %d offset %d "
2293                                   "new %08x old %08x\n",
2294                                   obj, reloc.target_handle,
2295                                   (int) reloc.offset,
2296                                   reloc.write_domain,
2297                                   target_obj->pending_write_domain);
2298                         drm_gem_object_unreference(target_obj);
2299                         i915_gem_object_unpin(obj);
2300                         return -EINVAL;
2301                 }
2302
2303 #if WATCH_RELOC
2304                 DRM_INFO("%s: obj %p offset %08x target %d "
2305                          "read %08x write %08x gtt %08x "
2306                          "presumed %08x delta %08x\n",
2307                          __func__,
2308                          obj,
2309                          (int) reloc.offset,
2310                          (int) reloc.target_handle,
2311                          (int) reloc.read_domains,
2312                          (int) reloc.write_domain,
2313                          (int) target_obj_priv->gtt_offset,
2314                          (int) reloc.presumed_offset,
2315                          reloc.delta);
2316 #endif
2317
2318                 target_obj->pending_read_domains |= reloc.read_domains;
2319                 target_obj->pending_write_domain |= reloc.write_domain;
2320
2321                 /* If the relocation already has the right value in it, no
2322                  * more work needs to be done.
2323                  */
2324                 if (target_obj_priv->gtt_offset == reloc.presumed_offset) {
2325                         drm_gem_object_unreference(target_obj);
2326                         continue;
2327                 }
2328
2329                 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
2330                 if (ret != 0) {
2331                         drm_gem_object_unreference(target_obj);
2332                         i915_gem_object_unpin(obj);
2333                         return -EINVAL;
2334                 }
2335
2336                 /* Map the page containing the relocation we're going to
2337                  * perform.
2338                  */
2339                 reloc_offset = obj_priv->gtt_offset + reloc.offset;
2340                 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
2341                                                       (reloc_offset &
2342                                                        ~(PAGE_SIZE - 1)));
2343                 reloc_entry = (uint32_t __iomem *)(reloc_page +
2344                                                    (reloc_offset & (PAGE_SIZE - 1)));
2345                 reloc_val = target_obj_priv->gtt_offset + reloc.delta;
2346
2347 #if WATCH_BUF
2348                 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
2349                           obj, (unsigned int) reloc.offset,
2350                           readl(reloc_entry), reloc_val);
2351 #endif
2352                 writel(reloc_val, reloc_entry);
2353                 io_mapping_unmap_atomic(reloc_page);
2354
2355                 /* Write the updated presumed offset for this entry back out
2356                  * to the user.
2357                  */
2358                 reloc.presumed_offset = target_obj_priv->gtt_offset;
2359                 ret = copy_to_user(relocs + i, &reloc, sizeof(reloc));
2360                 if (ret != 0) {
2361                         drm_gem_object_unreference(target_obj);
2362                         i915_gem_object_unpin(obj);
2363                         return ret;
2364                 }
2365
2366                 drm_gem_object_unreference(target_obj);
2367         }
2368
2369 #if WATCH_BUF
2370         if (0)
2371                 i915_gem_dump_object(obj, 128, __func__, ~0);
2372 #endif
2373         return 0;
2374 }
2375
2376 /** Dispatch a batchbuffer to the ring
2377  */
2378 static int
2379 i915_dispatch_gem_execbuffer(struct drm_device *dev,
2380                               struct drm_i915_gem_execbuffer *exec,
2381                               uint64_t exec_offset)
2382 {
2383         drm_i915_private_t *dev_priv = dev->dev_private;
2384         struct drm_clip_rect __user *boxes = (struct drm_clip_rect __user *)
2385                                              (uintptr_t) exec->cliprects_ptr;
2386         int nbox = exec->num_cliprects;
2387         int i = 0, count;
2388         uint32_t        exec_start, exec_len;
2389         RING_LOCALS;
2390
2391         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
2392         exec_len = (uint32_t) exec->batch_len;
2393
2394         if ((exec_start | exec_len) & 0x7) {
2395                 DRM_ERROR("alignment\n");
2396                 return -EINVAL;
2397         }
2398
2399         if (!exec_start)
2400                 return -EINVAL;
2401
2402         count = nbox ? nbox : 1;
2403
2404         for (i = 0; i < count; i++) {
2405                 if (i < nbox) {
2406                         int ret = i915_emit_box(dev, boxes, i,
2407                                                 exec->DR1, exec->DR4);
2408                         if (ret)
2409                                 return ret;
2410                 }
2411
2412                 if (IS_I830(dev) || IS_845G(dev)) {
2413                         BEGIN_LP_RING(4);
2414                         OUT_RING(MI_BATCH_BUFFER);
2415                         OUT_RING(exec_start | MI_BATCH_NON_SECURE);
2416                         OUT_RING(exec_start + exec_len - 4);
2417                         OUT_RING(0);
2418                         ADVANCE_LP_RING();
2419                 } else {
2420                         BEGIN_LP_RING(2);
2421                         if (IS_I965G(dev)) {
2422                                 OUT_RING(MI_BATCH_BUFFER_START |
2423                                          (2 << 6) |
2424                                          MI_BATCH_NON_SECURE_I965);
2425                                 OUT_RING(exec_start);
2426                         } else {
2427                                 OUT_RING(MI_BATCH_BUFFER_START |
2428                                          (2 << 6));
2429                                 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
2430                         }
2431                         ADVANCE_LP_RING();
2432                 }
2433         }
2434
2435         /* XXX breadcrumb */
2436         return 0;
2437 }
2438
2439 /* Throttle our rendering by waiting until the ring has completed our requests
2440  * emitted over 20 msec ago.
2441  *
2442  * This should get us reasonable parallelism between CPU and GPU but also
2443  * relatively low latency when blocking on a particular request to finish.
2444  */
2445 static int
2446 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
2447 {
2448         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
2449         int ret = 0;
2450         uint32_t seqno;
2451
2452         mutex_lock(&dev->struct_mutex);
2453         seqno = i915_file_priv->mm.last_gem_throttle_seqno;
2454         i915_file_priv->mm.last_gem_throttle_seqno =
2455                 i915_file_priv->mm.last_gem_seqno;
2456         if (seqno)
2457                 ret = i915_wait_request(dev, seqno);
2458         mutex_unlock(&dev->struct_mutex);
2459         return ret;
2460 }
2461
2462 int
2463 i915_gem_execbuffer(struct drm_device *dev, void *data,
2464                     struct drm_file *file_priv)
2465 {
2466         drm_i915_private_t *dev_priv = dev->dev_private;
2467         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
2468         struct drm_i915_gem_execbuffer *args = data;
2469         struct drm_i915_gem_exec_object *exec_list = NULL;
2470         struct drm_gem_object **object_list = NULL;
2471         struct drm_gem_object *batch_obj;
2472         int ret, i, pinned = 0;
2473         uint64_t exec_offset;
2474         uint32_t seqno, flush_domains;
2475         int pin_tries;
2476
2477 #if WATCH_EXEC
2478         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
2479                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
2480 #endif
2481
2482         if (args->buffer_count < 1) {
2483                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
2484                 return -EINVAL;
2485         }
2486         /* Copy in the exec list from userland */
2487         exec_list = drm_calloc(sizeof(*exec_list), args->buffer_count,
2488                                DRM_MEM_DRIVER);
2489         object_list = drm_calloc(sizeof(*object_list), args->buffer_count,
2490                                  DRM_MEM_DRIVER);
2491         if (exec_list == NULL || object_list == NULL) {
2492                 DRM_ERROR("Failed to allocate exec or object list "
2493                           "for %d buffers\n",
2494                           args->buffer_count);
2495                 ret = -ENOMEM;
2496                 goto pre_mutex_err;
2497         }
2498         ret = copy_from_user(exec_list,
2499                              (struct drm_i915_relocation_entry __user *)
2500                              (uintptr_t) args->buffers_ptr,
2501                              sizeof(*exec_list) * args->buffer_count);
2502         if (ret != 0) {
2503                 DRM_ERROR("copy %d exec entries failed %d\n",
2504                           args->buffer_count, ret);
2505                 goto pre_mutex_err;
2506         }
2507
2508         mutex_lock(&dev->struct_mutex);
2509
2510         i915_verify_inactive(dev, __FILE__, __LINE__);
2511
2512         if (dev_priv->mm.wedged) {
2513                 DRM_ERROR("Execbuf while wedged\n");
2514                 mutex_unlock(&dev->struct_mutex);
2515                 ret = -EIO;
2516                 goto pre_mutex_err;
2517         }
2518
2519         if (dev_priv->mm.suspended) {
2520                 DRM_ERROR("Execbuf while VT-switched.\n");
2521                 mutex_unlock(&dev->struct_mutex);
2522                 ret = -EBUSY;
2523                 goto pre_mutex_err;
2524         }
2525
2526         /* Look up object handles */
2527         for (i = 0; i < args->buffer_count; i++) {
2528                 object_list[i] = drm_gem_object_lookup(dev, file_priv,
2529                                                        exec_list[i].handle);
2530                 if (object_list[i] == NULL) {
2531                         DRM_ERROR("Invalid object handle %d at index %d\n",
2532                                    exec_list[i].handle, i);
2533                         ret = -EBADF;
2534                         goto err;
2535                 }
2536         }
2537
2538         /* Pin and relocate */
2539         for (pin_tries = 0; ; pin_tries++) {
2540                 ret = 0;
2541                 for (i = 0; i < args->buffer_count; i++) {
2542                         object_list[i]->pending_read_domains = 0;
2543                         object_list[i]->pending_write_domain = 0;
2544                         ret = i915_gem_object_pin_and_relocate(object_list[i],
2545                                                                file_priv,
2546                                                                &exec_list[i]);
2547                         if (ret)
2548                                 break;
2549                         pinned = i + 1;
2550                 }
2551                 /* success */
2552                 if (ret == 0)
2553                         break;
2554
2555                 /* error other than GTT full, or we've already tried again */
2556                 if (ret != -ENOMEM || pin_tries >= 1) {
2557                         if (ret != -ERESTARTSYS)
2558                                 DRM_ERROR("Failed to pin buffers %d\n", ret);
2559                         goto err;
2560                 }
2561
2562                 /* unpin all of our buffers */
2563                 for (i = 0; i < pinned; i++)
2564                         i915_gem_object_unpin(object_list[i]);
2565                 pinned = 0;
2566
2567                 /* evict everyone we can from the aperture */
2568                 ret = i915_gem_evict_everything(dev);
2569                 if (ret)
2570                         goto err;
2571         }
2572
2573         /* Set the pending read domains for the batch buffer to COMMAND */
2574         batch_obj = object_list[args->buffer_count-1];
2575         batch_obj->pending_read_domains = I915_GEM_DOMAIN_COMMAND;
2576         batch_obj->pending_write_domain = 0;
2577
2578         i915_verify_inactive(dev, __FILE__, __LINE__);
2579
2580         /* Zero the global flush/invalidate flags. These
2581          * will be modified as new domains are computed
2582          * for each object
2583          */
2584         dev->invalidate_domains = 0;
2585         dev->flush_domains = 0;
2586
2587         for (i = 0; i < args->buffer_count; i++) {
2588                 struct drm_gem_object *obj = object_list[i];
2589
2590                 /* Compute new gpu domains and update invalidate/flush */
2591                 i915_gem_object_set_to_gpu_domain(obj);
2592         }
2593
2594         i915_verify_inactive(dev, __FILE__, __LINE__);
2595
2596         if (dev->invalidate_domains | dev->flush_domains) {
2597 #if WATCH_EXEC
2598                 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
2599                           __func__,
2600                          dev->invalidate_domains,
2601                          dev->flush_domains);
2602 #endif
2603                 i915_gem_flush(dev,
2604                                dev->invalidate_domains,
2605                                dev->flush_domains);
2606                 if (dev->flush_domains)
2607                         (void)i915_add_request(dev, dev->flush_domains);
2608         }
2609
2610         for (i = 0; i < args->buffer_count; i++) {
2611                 struct drm_gem_object *obj = object_list[i];
2612
2613                 obj->write_domain = obj->pending_write_domain;
2614         }
2615
2616         i915_verify_inactive(dev, __FILE__, __LINE__);
2617
2618 #if WATCH_COHERENCY
2619         for (i = 0; i < args->buffer_count; i++) {
2620                 i915_gem_object_check_coherency(object_list[i],
2621                                                 exec_list[i].handle);
2622         }
2623 #endif
2624
2625         exec_offset = exec_list[args->buffer_count - 1].offset;
2626
2627 #if WATCH_EXEC
2628         i915_gem_dump_object(object_list[args->buffer_count - 1],
2629                               args->batch_len,
2630                               __func__,
2631                               ~0);
2632 #endif
2633
2634         /* Exec the batchbuffer */
2635         ret = i915_dispatch_gem_execbuffer(dev, args, exec_offset);
2636         if (ret) {
2637                 DRM_ERROR("dispatch failed %d\n", ret);
2638                 goto err;
2639         }
2640
2641         /*
2642          * Ensure that the commands in the batch buffer are
2643          * finished before the interrupt fires
2644          */
2645         flush_domains = i915_retire_commands(dev);
2646
2647         i915_verify_inactive(dev, __FILE__, __LINE__);
2648
2649         /*
2650          * Get a seqno representing the execution of the current buffer,
2651          * which we can wait on.  We would like to mitigate these interrupts,
2652          * likely by only creating seqnos occasionally (so that we have
2653          * *some* interrupts representing completion of buffers that we can
2654          * wait on when trying to clear up gtt space).
2655          */
2656         seqno = i915_add_request(dev, flush_domains);
2657         BUG_ON(seqno == 0);
2658         i915_file_priv->mm.last_gem_seqno = seqno;
2659         for (i = 0; i < args->buffer_count; i++) {
2660                 struct drm_gem_object *obj = object_list[i];
2661
2662                 i915_gem_object_move_to_active(obj, seqno);
2663 #if WATCH_LRU
2664                 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
2665 #endif
2666         }
2667 #if WATCH_LRU
2668         i915_dump_lru(dev, __func__);
2669 #endif
2670
2671         i915_verify_inactive(dev, __FILE__, __LINE__);
2672
2673 err:
2674         for (i = 0; i < pinned; i++)
2675                 i915_gem_object_unpin(object_list[i]);
2676
2677         for (i = 0; i < args->buffer_count; i++)
2678                 drm_gem_object_unreference(object_list[i]);
2679
2680         mutex_unlock(&dev->struct_mutex);
2681
2682         if (!ret) {
2683                 /* Copy the new buffer offsets back to the user's exec list. */
2684                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
2685                                    (uintptr_t) args->buffers_ptr,
2686                                    exec_list,
2687                                    sizeof(*exec_list) * args->buffer_count);
2688                 if (ret)
2689                         DRM_ERROR("failed to copy %d exec entries "
2690                                   "back to user (%d)\n",
2691                                   args->buffer_count, ret);
2692         }
2693
2694 pre_mutex_err:
2695         drm_free(object_list, sizeof(*object_list) * args->buffer_count,
2696                  DRM_MEM_DRIVER);
2697         drm_free(exec_list, sizeof(*exec_list) * args->buffer_count,
2698                  DRM_MEM_DRIVER);
2699
2700         return ret;
2701 }
2702
2703 int
2704 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
2705 {
2706         struct drm_device *dev = obj->dev;
2707         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2708         int ret;
2709
2710         i915_verify_inactive(dev, __FILE__, __LINE__);
2711         if (obj_priv->gtt_space == NULL) {
2712                 ret = i915_gem_object_bind_to_gtt(obj, alignment);
2713                 if (ret != 0) {
2714                         if (ret != -EBUSY && ret != -ERESTARTSYS)
2715                                 DRM_ERROR("Failure to bind: %d", ret);
2716                         return ret;
2717                 }
2718                 /*
2719                  * Pre-965 chips need a fence register set up in order to
2720                  * properly handle tiled surfaces.
2721                  */
2722                 if (!IS_I965G(dev) &&
2723                     obj_priv->fence_reg == I915_FENCE_REG_NONE &&
2724                     obj_priv->tiling_mode != I915_TILING_NONE)
2725                         i915_gem_object_get_fence_reg(obj, true);
2726         }
2727         obj_priv->pin_count++;
2728
2729         /* If the object is not active and not pending a flush,
2730          * remove it from the inactive list
2731          */
2732         if (obj_priv->pin_count == 1) {
2733                 atomic_inc(&dev->pin_count);
2734                 atomic_add(obj->size, &dev->pin_memory);
2735                 if (!obj_priv->active &&
2736                     (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
2737                                            I915_GEM_DOMAIN_GTT)) == 0 &&
2738                     !list_empty(&obj_priv->list))
2739                         list_del_init(&obj_priv->list);
2740         }
2741         i915_verify_inactive(dev, __FILE__, __LINE__);
2742
2743         return 0;
2744 }
2745
2746 void
2747 i915_gem_object_unpin(struct drm_gem_object *obj)
2748 {
2749         struct drm_device *dev = obj->dev;
2750         drm_i915_private_t *dev_priv = dev->dev_private;
2751         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2752
2753         i915_verify_inactive(dev, __FILE__, __LINE__);
2754         obj_priv->pin_count--;
2755         BUG_ON(obj_priv->pin_count < 0);
2756         BUG_ON(obj_priv->gtt_space == NULL);
2757
2758         /* If the object is no longer pinned, and is
2759          * neither active nor being flushed, then stick it on
2760          * the inactive list
2761          */
2762         if (obj_priv->pin_count == 0) {
2763                 if (!obj_priv->active &&
2764                     (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
2765                                            I915_GEM_DOMAIN_GTT)) == 0)
2766                         list_move_tail(&obj_priv->list,
2767                                        &dev_priv->mm.inactive_list);
2768                 atomic_dec(&dev->pin_count);
2769                 atomic_sub(obj->size, &dev->pin_memory);
2770         }
2771         i915_verify_inactive(dev, __FILE__, __LINE__);
2772 }
2773
2774 int
2775 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2776                    struct drm_file *file_priv)
2777 {
2778         struct drm_i915_gem_pin *args = data;
2779         struct drm_gem_object *obj;
2780         struct drm_i915_gem_object *obj_priv;
2781         int ret;
2782
2783         mutex_lock(&dev->struct_mutex);
2784
2785         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2786         if (obj == NULL) {
2787                 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
2788                           args->handle);
2789                 mutex_unlock(&dev->struct_mutex);
2790                 return -EBADF;
2791         }
2792         obj_priv = obj->driver_private;
2793
2794         if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
2795                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
2796                           args->handle);
2797                 drm_gem_object_unreference(obj);
2798                 mutex_unlock(&dev->struct_mutex);
2799                 return -EINVAL;
2800         }
2801
2802         obj_priv->user_pin_count++;
2803         obj_priv->pin_filp = file_priv;
2804         if (obj_priv->user_pin_count == 1) {
2805                 ret = i915_gem_object_pin(obj, args->alignment);
2806                 if (ret != 0) {
2807                         drm_gem_object_unreference(obj);
2808                         mutex_unlock(&dev->struct_mutex);
2809                         return ret;
2810                 }
2811         }
2812
2813         /* XXX - flush the CPU caches for pinned objects
2814          * as the X server doesn't manage domains yet
2815          */
2816         i915_gem_object_flush_cpu_write_domain(obj);
2817         args->offset = obj_priv->gtt_offset;
2818         drm_gem_object_unreference(obj);
2819         mutex_unlock(&dev->struct_mutex);
2820
2821         return 0;
2822 }
2823
2824 int
2825 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2826                      struct drm_file *file_priv)
2827 {
2828         struct drm_i915_gem_pin *args = data;
2829         struct drm_gem_object *obj;
2830         struct drm_i915_gem_object *obj_priv;
2831
2832         mutex_lock(&dev->struct_mutex);
2833
2834         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2835         if (obj == NULL) {
2836                 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
2837                           args->handle);
2838                 mutex_unlock(&dev->struct_mutex);
2839                 return -EBADF;
2840         }
2841
2842         obj_priv = obj->driver_private;
2843         if (obj_priv->pin_filp != file_priv) {
2844                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
2845                           args->handle);
2846                 drm_gem_object_unreference(obj);
2847                 mutex_unlock(&dev->struct_mutex);
2848                 return -EINVAL;
2849         }
2850         obj_priv->user_pin_count--;
2851         if (obj_priv->user_pin_count == 0) {
2852                 obj_priv->pin_filp = NULL;
2853                 i915_gem_object_unpin(obj);
2854         }
2855
2856         drm_gem_object_unreference(obj);
2857         mutex_unlock(&dev->struct_mutex);
2858         return 0;
2859 }
2860
2861 int
2862 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2863                     struct drm_file *file_priv)
2864 {
2865         struct drm_i915_gem_busy *args = data;
2866         struct drm_gem_object *obj;
2867         struct drm_i915_gem_object *obj_priv;
2868
2869         mutex_lock(&dev->struct_mutex);
2870         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2871         if (obj == NULL) {
2872                 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
2873                           args->handle);
2874                 mutex_unlock(&dev->struct_mutex);
2875                 return -EBADF;
2876         }
2877
2878         /* Update the active list for the hardware's current position.
2879          * Otherwise this only updates on a delayed timer or when irqs are
2880          * actually unmasked, and our working set ends up being larger than
2881          * required.
2882          */
2883         i915_gem_retire_requests(dev);
2884
2885         obj_priv = obj->driver_private;
2886         /* Don't count being on the flushing list against the object being
2887          * done.  Otherwise, a buffer left on the flushing list but not getting
2888          * flushed (because nobody's flushing that domain) won't ever return
2889          * unbusy and get reused by libdrm's bo cache.  The other expected
2890          * consumer of this interface, OpenGL's occlusion queries, also specs
2891          * that the objects get unbusy "eventually" without any interference.
2892          */
2893         args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
2894
2895         drm_gem_object_unreference(obj);
2896         mutex_unlock(&dev->struct_mutex);
2897         return 0;
2898 }
2899
2900 int
2901 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2902                         struct drm_file *file_priv)
2903 {
2904     return i915_gem_ring_throttle(dev, file_priv);
2905 }
2906
2907 int i915_gem_init_object(struct drm_gem_object *obj)
2908 {
2909         struct drm_i915_gem_object *obj_priv;
2910
2911         obj_priv = drm_calloc(1, sizeof(*obj_priv), DRM_MEM_DRIVER);
2912         if (obj_priv == NULL)
2913                 return -ENOMEM;
2914
2915         /*
2916          * We've just allocated pages from the kernel,
2917          * so they've just been written by the CPU with
2918          * zeros. They'll need to be clflushed before we
2919          * use them with the GPU.
2920          */
2921         obj->write_domain = I915_GEM_DOMAIN_CPU;
2922         obj->read_domains = I915_GEM_DOMAIN_CPU;
2923
2924         obj_priv->agp_type = AGP_USER_MEMORY;
2925
2926         obj->driver_private = obj_priv;
2927         obj_priv->obj = obj;
2928         obj_priv->fence_reg = I915_FENCE_REG_NONE;
2929         INIT_LIST_HEAD(&obj_priv->list);
2930
2931         return 0;
2932 }
2933
2934 void i915_gem_free_object(struct drm_gem_object *obj)
2935 {
2936         struct drm_device *dev = obj->dev;
2937         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2938
2939         while (obj_priv->pin_count > 0)
2940                 i915_gem_object_unpin(obj);
2941
2942         if (obj_priv->phys_obj)
2943                 i915_gem_detach_phys_object(dev, obj);
2944
2945         i915_gem_object_unbind(obj);
2946
2947         i915_gem_free_mmap_offset(obj);
2948
2949         drm_free(obj_priv->page_cpu_valid, 1, DRM_MEM_DRIVER);
2950         drm_free(obj->driver_private, 1, DRM_MEM_DRIVER);
2951 }
2952
2953 /** Unbinds all objects that are on the given buffer list. */
2954 static int
2955 i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
2956 {
2957         struct drm_gem_object *obj;
2958         struct drm_i915_gem_object *obj_priv;
2959         int ret;
2960
2961         while (!list_empty(head)) {
2962                 obj_priv = list_first_entry(head,
2963                                             struct drm_i915_gem_object,
2964                                             list);
2965                 obj = obj_priv->obj;
2966
2967                 if (obj_priv->pin_count != 0) {
2968                         DRM_ERROR("Pinned object in unbind list\n");
2969                         mutex_unlock(&dev->struct_mutex);
2970                         return -EINVAL;
2971                 }
2972
2973                 ret = i915_gem_object_unbind(obj);
2974                 if (ret != 0) {
2975                         DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
2976                                   ret);
2977                         mutex_unlock(&dev->struct_mutex);
2978                         return ret;
2979                 }
2980         }
2981
2982
2983         return 0;
2984 }
2985
2986 int
2987 i915_gem_idle(struct drm_device *dev)
2988 {
2989         drm_i915_private_t *dev_priv = dev->dev_private;
2990         uint32_t seqno, cur_seqno, last_seqno;
2991         int stuck, ret;
2992
2993         mutex_lock(&dev->struct_mutex);
2994
2995         if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
2996                 mutex_unlock(&dev->struct_mutex);
2997                 return 0;
2998         }
2999
3000         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
3001          * We need to replace this with a semaphore, or something.
3002          */
3003         dev_priv->mm.suspended = 1;
3004
3005         /* Cancel the retire work handler, wait for it to finish if running
3006          */
3007         mutex_unlock(&dev->struct_mutex);
3008         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3009         mutex_lock(&dev->struct_mutex);
3010
3011         i915_kernel_lost_context(dev);
3012
3013         /* Flush the GPU along with all non-CPU write domains
3014          */
3015         i915_gem_flush(dev, ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT),
3016                        ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
3017         seqno = i915_add_request(dev, ~I915_GEM_DOMAIN_CPU);
3018
3019         if (seqno == 0) {
3020                 mutex_unlock(&dev->struct_mutex);
3021                 return -ENOMEM;
3022         }
3023
3024         dev_priv->mm.waiting_gem_seqno = seqno;
3025         last_seqno = 0;
3026         stuck = 0;
3027         for (;;) {
3028                 cur_seqno = i915_get_gem_seqno(dev);
3029                 if (i915_seqno_passed(cur_seqno, seqno))
3030                         break;
3031                 if (last_seqno == cur_seqno) {
3032                         if (stuck++ > 100) {
3033                                 DRM_ERROR("hardware wedged\n");
3034                                 dev_priv->mm.wedged = 1;
3035                                 DRM_WAKEUP(&dev_priv->irq_queue);
3036                                 break;
3037                         }
3038                 }
3039                 msleep(10);
3040                 last_seqno = cur_seqno;
3041         }
3042         dev_priv->mm.waiting_gem_seqno = 0;
3043
3044         i915_gem_retire_requests(dev);
3045
3046         if (!dev_priv->mm.wedged) {
3047                 /* Active and flushing should now be empty as we've
3048                  * waited for a sequence higher than any pending execbuffer
3049                  */
3050                 WARN_ON(!list_empty(&dev_priv->mm.active_list));
3051                 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
3052                 /* Request should now be empty as we've also waited
3053                  * for the last request in the list
3054                  */
3055                 WARN_ON(!list_empty(&dev_priv->mm.request_list));
3056         }
3057
3058         /* Empty the active and flushing lists to inactive.  If there's
3059          * anything left at this point, it means that we're wedged and
3060          * nothing good's going to happen by leaving them there.  So strip
3061          * the GPU domains and just stuff them onto inactive.
3062          */
3063         while (!list_empty(&dev_priv->mm.active_list)) {
3064                 struct drm_i915_gem_object *obj_priv;
3065
3066                 obj_priv = list_first_entry(&dev_priv->mm.active_list,
3067                                             struct drm_i915_gem_object,
3068                                             list);
3069                 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3070                 i915_gem_object_move_to_inactive(obj_priv->obj);
3071         }
3072
3073         while (!list_empty(&dev_priv->mm.flushing_list)) {
3074                 struct drm_i915_gem_object *obj_priv;
3075
3076                 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
3077                                             struct drm_i915_gem_object,
3078                                             list);
3079                 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3080                 i915_gem_object_move_to_inactive(obj_priv->obj);
3081         }
3082
3083
3084         /* Move all inactive buffers out of the GTT. */
3085         ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
3086         WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
3087         if (ret) {
3088                 mutex_unlock(&dev->struct_mutex);
3089                 return ret;
3090         }
3091
3092         i915_gem_cleanup_ringbuffer(dev);
3093         mutex_unlock(&dev->struct_mutex);
3094
3095         return 0;
3096 }
3097
3098 static int
3099 i915_gem_init_hws(struct drm_device *dev)
3100 {
3101         drm_i915_private_t *dev_priv = dev->dev_private;
3102         struct drm_gem_object *obj;
3103         struct drm_i915_gem_object *obj_priv;
3104         int ret;
3105
3106         /* If we need a physical address for the status page, it's already
3107          * initialized at driver load time.
3108          */
3109         if (!I915_NEED_GFX_HWS(dev))
3110                 return 0;
3111
3112         obj = drm_gem_object_alloc(dev, 4096);
3113         if (obj == NULL) {
3114                 DRM_ERROR("Failed to allocate status page\n");
3115                 return -ENOMEM;
3116         }
3117         obj_priv = obj->driver_private;
3118         obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
3119
3120         ret = i915_gem_object_pin(obj, 4096);
3121         if (ret != 0) {
3122                 drm_gem_object_unreference(obj);
3123                 return ret;
3124         }
3125
3126         dev_priv->status_gfx_addr = obj_priv->gtt_offset;
3127
3128         dev_priv->hw_status_page = kmap(obj_priv->page_list[0]);
3129         if (dev_priv->hw_status_page == NULL) {
3130                 DRM_ERROR("Failed to map status page.\n");
3131                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
3132                 i915_gem_object_unpin(obj);
3133                 drm_gem_object_unreference(obj);
3134                 return -EINVAL;
3135         }
3136         dev_priv->hws_obj = obj;
3137         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
3138         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
3139         I915_READ(HWS_PGA); /* posting read */
3140         DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
3141
3142         return 0;
3143 }
3144
3145 static void
3146 i915_gem_cleanup_hws(struct drm_device *dev)
3147 {
3148         drm_i915_private_t *dev_priv = dev->dev_private;
3149         struct drm_gem_object *obj;
3150         struct drm_i915_gem_object *obj_priv;
3151
3152         if (dev_priv->hws_obj == NULL)
3153                 return;
3154
3155         obj = dev_priv->hws_obj;
3156         obj_priv = obj->driver_private;
3157
3158         kunmap(obj_priv->page_list[0]);
3159         i915_gem_object_unpin(obj);
3160         drm_gem_object_unreference(obj);
3161         dev_priv->hws_obj = NULL;
3162
3163         memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
3164         dev_priv->hw_status_page = NULL;
3165
3166         /* Write high address into HWS_PGA when disabling. */
3167         I915_WRITE(HWS_PGA, 0x1ffff000);
3168 }
3169
3170 int
3171 i915_gem_init_ringbuffer(struct drm_device *dev)
3172 {
3173         drm_i915_private_t *dev_priv = dev->dev_private;
3174         struct drm_gem_object *obj;
3175         struct drm_i915_gem_object *obj_priv;
3176         drm_i915_ring_buffer_t *ring = &dev_priv->ring;
3177         int ret;
3178         u32 head;
3179
3180         ret = i915_gem_init_hws(dev);
3181         if (ret != 0)
3182                 return ret;
3183
3184         obj = drm_gem_object_alloc(dev, 128 * 1024);
3185         if (obj == NULL) {
3186                 DRM_ERROR("Failed to allocate ringbuffer\n");
3187                 i915_gem_cleanup_hws(dev);
3188                 return -ENOMEM;
3189         }
3190         obj_priv = obj->driver_private;
3191
3192         ret = i915_gem_object_pin(obj, 4096);
3193         if (ret != 0) {
3194                 drm_gem_object_unreference(obj);
3195                 i915_gem_cleanup_hws(dev);
3196                 return ret;
3197         }
3198
3199         /* Set up the kernel mapping for the ring. */
3200         ring->Size = obj->size;
3201         ring->tail_mask = obj->size - 1;
3202
3203         ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
3204         ring->map.size = obj->size;
3205         ring->map.type = 0;
3206         ring->map.flags = 0;
3207         ring->map.mtrr = 0;
3208
3209         drm_core_ioremap_wc(&ring->map, dev);
3210         if (ring->map.handle == NULL) {
3211                 DRM_ERROR("Failed to map ringbuffer.\n");
3212                 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
3213                 i915_gem_object_unpin(obj);
3214                 drm_gem_object_unreference(obj);
3215                 i915_gem_cleanup_hws(dev);
3216                 return -EINVAL;
3217         }
3218         ring->ring_obj = obj;
3219         ring->virtual_start = ring->map.handle;
3220
3221         /* Stop the ring if it's running. */
3222         I915_WRITE(PRB0_CTL, 0);
3223         I915_WRITE(PRB0_TAIL, 0);
3224         I915_WRITE(PRB0_HEAD, 0);
3225
3226         /* Initialize the ring. */
3227         I915_WRITE(PRB0_START, obj_priv->gtt_offset);
3228         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
3229
3230         /* G45 ring initialization fails to reset head to zero */
3231         if (head != 0) {
3232                 DRM_ERROR("Ring head not reset to zero "
3233                           "ctl %08x head %08x tail %08x start %08x\n",
3234                           I915_READ(PRB0_CTL),
3235                           I915_READ(PRB0_HEAD),
3236                           I915_READ(PRB0_TAIL),
3237                           I915_READ(PRB0_START));
3238                 I915_WRITE(PRB0_HEAD, 0);
3239
3240                 DRM_ERROR("Ring head forced to zero "
3241                           "ctl %08x head %08x tail %08x start %08x\n",
3242                           I915_READ(PRB0_CTL),
3243                           I915_READ(PRB0_HEAD),
3244                           I915_READ(PRB0_TAIL),
3245                           I915_READ(PRB0_START));
3246         }
3247
3248         I915_WRITE(PRB0_CTL,
3249                    ((obj->size - 4096) & RING_NR_PAGES) |
3250                    RING_NO_REPORT |
3251                    RING_VALID);
3252
3253         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
3254
3255         /* If the head is still not zero, the ring is dead */
3256         if (head != 0) {
3257                 DRM_ERROR("Ring initialization failed "
3258                           "ctl %08x head %08x tail %08x start %08x\n",
3259                           I915_READ(PRB0_CTL),
3260                           I915_READ(PRB0_HEAD),
3261                           I915_READ(PRB0_TAIL),
3262                           I915_READ(PRB0_START));
3263                 return -EIO;
3264         }
3265
3266         /* Update our cache of the ring state */
3267         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3268                 i915_kernel_lost_context(dev);
3269         else {
3270                 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
3271                 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
3272                 ring->space = ring->head - (ring->tail + 8);
3273                 if (ring->space < 0)
3274                         ring->space += ring->Size;
3275         }
3276
3277         return 0;
3278 }
3279
3280 void
3281 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3282 {
3283         drm_i915_private_t *dev_priv = dev->dev_private;
3284
3285         if (dev_priv->ring.ring_obj == NULL)
3286                 return;
3287
3288         drm_core_ioremapfree(&dev_priv->ring.map, dev);
3289
3290         i915_gem_object_unpin(dev_priv->ring.ring_obj);
3291         drm_gem_object_unreference(dev_priv->ring.ring_obj);
3292         dev_priv->ring.ring_obj = NULL;
3293         memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
3294
3295         i915_gem_cleanup_hws(dev);
3296 }
3297
3298 int
3299 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3300                        struct drm_file *file_priv)
3301 {
3302         drm_i915_private_t *dev_priv = dev->dev_private;
3303         int ret;
3304
3305         if (drm_core_check_feature(dev, DRIVER_MODESET))
3306                 return 0;
3307
3308         if (dev_priv->mm.wedged) {
3309                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3310                 dev_priv->mm.wedged = 0;
3311         }
3312
3313         mutex_lock(&dev->struct_mutex);
3314         dev_priv->mm.suspended = 0;
3315
3316         ret = i915_gem_init_ringbuffer(dev);
3317         if (ret != 0)
3318                 return ret;
3319
3320         BUG_ON(!list_empty(&dev_priv->mm.active_list));
3321         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3322         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3323         BUG_ON(!list_empty(&dev_priv->mm.request_list));
3324         mutex_unlock(&dev->struct_mutex);
3325
3326         drm_irq_install(dev);
3327
3328         return 0;
3329 }
3330
3331 int
3332 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3333                        struct drm_file *file_priv)
3334 {
3335         int ret;
3336
3337         if (drm_core_check_feature(dev, DRIVER_MODESET))
3338                 return 0;
3339
3340         ret = i915_gem_idle(dev);
3341         drm_irq_uninstall(dev);
3342
3343         return ret;
3344 }
3345
3346 void
3347 i915_gem_lastclose(struct drm_device *dev)
3348 {
3349         int ret;
3350
3351         if (drm_core_check_feature(dev, DRIVER_MODESET))
3352                 return;
3353
3354         ret = i915_gem_idle(dev);
3355         if (ret)
3356                 DRM_ERROR("failed to idle hardware: %d\n", ret);
3357 }
3358
3359 void
3360 i915_gem_load(struct drm_device *dev)
3361 {
3362         drm_i915_private_t *dev_priv = dev->dev_private;
3363
3364         INIT_LIST_HEAD(&dev_priv->mm.active_list);
3365         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3366         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3367         INIT_LIST_HEAD(&dev_priv->mm.request_list);
3368         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3369                           i915_gem_retire_work_handler);
3370         dev_priv->mm.next_gem_seqno = 1;
3371
3372         /* Old X drivers will take 0-2 for front, back, depth buffers */
3373         dev_priv->fence_reg_start = 3;
3374
3375         if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3376                 dev_priv->num_fence_regs = 16;
3377         else
3378                 dev_priv->num_fence_regs = 8;
3379
3380         i915_gem_detect_bit_6_swizzle(dev);
3381 }
3382
3383 /*
3384  * Create a physically contiguous memory object for this object
3385  * e.g. for cursor + overlay regs
3386  */
3387 int i915_gem_init_phys_object(struct drm_device *dev,
3388                               int id, int size)
3389 {
3390         drm_i915_private_t *dev_priv = dev->dev_private;
3391         struct drm_i915_gem_phys_object *phys_obj;
3392         int ret;
3393
3394         if (dev_priv->mm.phys_objs[id - 1] || !size)
3395                 return 0;
3396
3397         phys_obj = drm_calloc(1, sizeof(struct drm_i915_gem_phys_object), DRM_MEM_DRIVER);
3398         if (!phys_obj)
3399                 return -ENOMEM;
3400
3401         phys_obj->id = id;
3402
3403         phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
3404         if (!phys_obj->handle) {
3405                 ret = -ENOMEM;
3406                 goto kfree_obj;
3407         }
3408 #ifdef CONFIG_X86
3409         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3410 #endif
3411
3412         dev_priv->mm.phys_objs[id - 1] = phys_obj;
3413
3414         return 0;
3415 kfree_obj:
3416         drm_free(phys_obj, sizeof(struct drm_i915_gem_phys_object), DRM_MEM_DRIVER);
3417         return ret;
3418 }
3419
3420 void i915_gem_free_phys_object(struct drm_device *dev, int id)
3421 {
3422         drm_i915_private_t *dev_priv = dev->dev_private;
3423         struct drm_i915_gem_phys_object *phys_obj;
3424
3425         if (!dev_priv->mm.phys_objs[id - 1])
3426                 return;
3427
3428         phys_obj = dev_priv->mm.phys_objs[id - 1];
3429         if (phys_obj->cur_obj) {
3430                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3431         }
3432
3433 #ifdef CONFIG_X86
3434         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3435 #endif
3436         drm_pci_free(dev, phys_obj->handle);
3437         kfree(phys_obj);
3438         dev_priv->mm.phys_objs[id - 1] = NULL;
3439 }
3440
3441 void i915_gem_free_all_phys_object(struct drm_device *dev)
3442 {
3443         int i;
3444
3445         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3446                 i915_gem_free_phys_object(dev, i);
3447 }
3448
3449 void i915_gem_detach_phys_object(struct drm_device *dev,
3450                                  struct drm_gem_object *obj)
3451 {
3452         struct drm_i915_gem_object *obj_priv;
3453         int i;
3454         int ret;
3455         int page_count;
3456
3457         obj_priv = obj->driver_private;
3458         if (!obj_priv->phys_obj)
3459                 return;
3460
3461         ret = i915_gem_object_get_page_list(obj);
3462         if (ret)
3463                 goto out;
3464
3465         page_count = obj->size / PAGE_SIZE;
3466
3467         for (i = 0; i < page_count; i++) {
3468                 char *dst = kmap_atomic(obj_priv->page_list[i], KM_USER0);
3469                 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
3470
3471                 memcpy(dst, src, PAGE_SIZE);
3472                 kunmap_atomic(dst, KM_USER0);
3473         }
3474         drm_clflush_pages(obj_priv->page_list, page_count);
3475         drm_agp_chipset_flush(dev);
3476 out:
3477         obj_priv->phys_obj->cur_obj = NULL;
3478         obj_priv->phys_obj = NULL;
3479 }
3480
3481 int
3482 i915_gem_attach_phys_object(struct drm_device *dev,
3483                             struct drm_gem_object *obj, int id)
3484 {
3485         drm_i915_private_t *dev_priv = dev->dev_private;
3486         struct drm_i915_gem_object *obj_priv;
3487         int ret = 0;
3488         int page_count;
3489         int i;
3490
3491         if (id > I915_MAX_PHYS_OBJECT)
3492                 return -EINVAL;
3493
3494         obj_priv = obj->driver_private;
3495
3496         if (obj_priv->phys_obj) {
3497                 if (obj_priv->phys_obj->id == id)
3498                         return 0;
3499                 i915_gem_detach_phys_object(dev, obj);
3500         }
3501
3502
3503         /* create a new object */
3504         if (!dev_priv->mm.phys_objs[id - 1]) {
3505                 ret = i915_gem_init_phys_object(dev, id,
3506                                                 obj->size);
3507                 if (ret) {
3508                         DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
3509                         goto out;
3510                 }
3511         }
3512
3513         /* bind to the object */
3514         obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
3515         obj_priv->phys_obj->cur_obj = obj;
3516
3517         ret = i915_gem_object_get_page_list(obj);
3518         if (ret) {
3519                 DRM_ERROR("failed to get page list\n");
3520                 goto out;
3521         }
3522
3523         page_count = obj->size / PAGE_SIZE;
3524
3525         for (i = 0; i < page_count; i++) {
3526                 char *src = kmap_atomic(obj_priv->page_list[i], KM_USER0);
3527                 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
3528
3529                 memcpy(dst, src, PAGE_SIZE);
3530                 kunmap_atomic(src, KM_USER0);
3531         }
3532
3533         return 0;
3534 out:
3535         return ret;
3536 }
3537
3538 static int
3539 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
3540                      struct drm_i915_gem_pwrite *args,
3541                      struct drm_file *file_priv)
3542 {
3543         struct drm_i915_gem_object *obj_priv = obj->driver_private;
3544         void *obj_addr;
3545         int ret;
3546         char __user *user_data;
3547
3548         user_data = (char __user *) (uintptr_t) args->data_ptr;
3549         obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
3550
3551         DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size);
3552         ret = copy_from_user(obj_addr, user_data, args->size);
3553         if (ret)
3554                 return -EFAULT;
3555
3556         drm_agp_chipset_flush(dev);
3557         return 0;
3558 }