Merge commit 'v2.6.29-rc8' into cpus4096
[linux-2.6.git] / drivers / gpu / drm / i915 / i915_gem.c
1 /*
2  * Copyright © 2008 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Eric Anholt <eric@anholt.net>
25  *
26  */
27
28 #include "drmP.h"
29 #include "drm.h"
30 #include "i915_drm.h"
31 #include "i915_drv.h"
32 #include <linux/swap.h>
33 #include <linux/pci.h>
34
35 #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
36
37 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
38 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
39 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
40 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
41                                              int write);
42 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
43                                                      uint64_t offset,
44                                                      uint64_t size);
45 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
46 static int i915_gem_object_get_page_list(struct drm_gem_object *obj);
47 static void i915_gem_object_free_page_list(struct drm_gem_object *obj);
48 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
50                                            unsigned alignment);
51 static int i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write);
52 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
53 static int i915_gem_evict_something(struct drm_device *dev);
54 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
55                                 struct drm_i915_gem_pwrite *args,
56                                 struct drm_file *file_priv);
57
58 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
59                      unsigned long end)
60 {
61         drm_i915_private_t *dev_priv = dev->dev_private;
62
63         if (start >= end ||
64             (start & (PAGE_SIZE - 1)) != 0 ||
65             (end & (PAGE_SIZE - 1)) != 0) {
66                 return -EINVAL;
67         }
68
69         drm_mm_init(&dev_priv->mm.gtt_space, start,
70                     end - start);
71
72         dev->gtt_total = (uint32_t) (end - start);
73
74         return 0;
75 }
76
77 int
78 i915_gem_init_ioctl(struct drm_device *dev, void *data,
79                     struct drm_file *file_priv)
80 {
81         struct drm_i915_gem_init *args = data;
82         int ret;
83
84         mutex_lock(&dev->struct_mutex);
85         ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
86         mutex_unlock(&dev->struct_mutex);
87
88         return ret;
89 }
90
91 int
92 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
93                             struct drm_file *file_priv)
94 {
95         struct drm_i915_gem_get_aperture *args = data;
96
97         if (!(dev->driver->driver_features & DRIVER_GEM))
98                 return -ENODEV;
99
100         args->aper_size = dev->gtt_total;
101         args->aper_available_size = (args->aper_size -
102                                      atomic_read(&dev->pin_memory));
103
104         return 0;
105 }
106
107
108 /**
109  * Creates a new mm object and returns a handle to it.
110  */
111 int
112 i915_gem_create_ioctl(struct drm_device *dev, void *data,
113                       struct drm_file *file_priv)
114 {
115         struct drm_i915_gem_create *args = data;
116         struct drm_gem_object *obj;
117         int handle, ret;
118
119         args->size = roundup(args->size, PAGE_SIZE);
120
121         /* Allocate the new object */
122         obj = drm_gem_object_alloc(dev, args->size);
123         if (obj == NULL)
124                 return -ENOMEM;
125
126         ret = drm_gem_handle_create(file_priv, obj, &handle);
127         mutex_lock(&dev->struct_mutex);
128         drm_gem_object_handle_unreference(obj);
129         mutex_unlock(&dev->struct_mutex);
130
131         if (ret)
132                 return ret;
133
134         args->handle = handle;
135
136         return 0;
137 }
138
139 /**
140  * Reads data from the object referenced by handle.
141  *
142  * On error, the contents of *data are undefined.
143  */
144 int
145 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
146                      struct drm_file *file_priv)
147 {
148         struct drm_i915_gem_pread *args = data;
149         struct drm_gem_object *obj;
150         struct drm_i915_gem_object *obj_priv;
151         ssize_t read;
152         loff_t offset;
153         int ret;
154
155         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
156         if (obj == NULL)
157                 return -EBADF;
158         obj_priv = obj->driver_private;
159
160         /* Bounds check source.
161          *
162          * XXX: This could use review for overflow issues...
163          */
164         if (args->offset > obj->size || args->size > obj->size ||
165             args->offset + args->size > obj->size) {
166                 drm_gem_object_unreference(obj);
167                 return -EINVAL;
168         }
169
170         mutex_lock(&dev->struct_mutex);
171
172         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
173                                                         args->size);
174         if (ret != 0) {
175                 drm_gem_object_unreference(obj);
176                 mutex_unlock(&dev->struct_mutex);
177                 return ret;
178         }
179
180         offset = args->offset;
181
182         read = vfs_read(obj->filp, (char __user *)(uintptr_t)args->data_ptr,
183                         args->size, &offset);
184         if (read != args->size) {
185                 drm_gem_object_unreference(obj);
186                 mutex_unlock(&dev->struct_mutex);
187                 if (read < 0)
188                         return read;
189                 else
190                         return -EINVAL;
191         }
192
193         drm_gem_object_unreference(obj);
194         mutex_unlock(&dev->struct_mutex);
195
196         return 0;
197 }
198
199 /* This is the fast write path which cannot handle
200  * page faults in the source data
201  */
202
203 static inline int
204 fast_user_write(struct io_mapping *mapping,
205                 loff_t page_base, int page_offset,
206                 char __user *user_data,
207                 int length)
208 {
209         char *vaddr_atomic;
210         unsigned long unwritten;
211
212         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
213         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
214                                                       user_data, length);
215         io_mapping_unmap_atomic(vaddr_atomic);
216         if (unwritten)
217                 return -EFAULT;
218         return 0;
219 }
220
221 /* Here's the write path which can sleep for
222  * page faults
223  */
224
225 static inline int
226 slow_user_write(struct io_mapping *mapping,
227                 loff_t page_base, int page_offset,
228                 char __user *user_data,
229                 int length)
230 {
231         char __iomem *vaddr;
232         unsigned long unwritten;
233
234         vaddr = io_mapping_map_wc(mapping, page_base);
235         if (vaddr == NULL)
236                 return -EFAULT;
237         unwritten = __copy_from_user(vaddr + page_offset,
238                                      user_data, length);
239         io_mapping_unmap(vaddr);
240         if (unwritten)
241                 return -EFAULT;
242         return 0;
243 }
244
245 static int
246 i915_gem_gtt_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
247                     struct drm_i915_gem_pwrite *args,
248                     struct drm_file *file_priv)
249 {
250         struct drm_i915_gem_object *obj_priv = obj->driver_private;
251         drm_i915_private_t *dev_priv = dev->dev_private;
252         ssize_t remain;
253         loff_t offset, page_base;
254         char __user *user_data;
255         int page_offset, page_length;
256         int ret;
257
258         user_data = (char __user *) (uintptr_t) args->data_ptr;
259         remain = args->size;
260         if (!access_ok(VERIFY_READ, user_data, remain))
261                 return -EFAULT;
262
263
264         mutex_lock(&dev->struct_mutex);
265         ret = i915_gem_object_pin(obj, 0);
266         if (ret) {
267                 mutex_unlock(&dev->struct_mutex);
268                 return ret;
269         }
270         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
271         if (ret)
272                 goto fail;
273
274         obj_priv = obj->driver_private;
275         offset = obj_priv->gtt_offset + args->offset;
276         obj_priv->dirty = 1;
277
278         while (remain > 0) {
279                 /* Operation in this page
280                  *
281                  * page_base = page offset within aperture
282                  * page_offset = offset within page
283                  * page_length = bytes to copy for this page
284                  */
285                 page_base = (offset & ~(PAGE_SIZE-1));
286                 page_offset = offset & (PAGE_SIZE-1);
287                 page_length = remain;
288                 if ((page_offset + remain) > PAGE_SIZE)
289                         page_length = PAGE_SIZE - page_offset;
290
291                 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
292                                        page_offset, user_data, page_length);
293
294                 /* If we get a fault while copying data, then (presumably) our
295                  * source page isn't available. In this case, use the
296                  * non-atomic function
297                  */
298                 if (ret) {
299                         ret = slow_user_write (dev_priv->mm.gtt_mapping,
300                                                page_base, page_offset,
301                                                user_data, page_length);
302                         if (ret)
303                                 goto fail;
304                 }
305
306                 remain -= page_length;
307                 user_data += page_length;
308                 offset += page_length;
309         }
310
311 fail:
312         i915_gem_object_unpin(obj);
313         mutex_unlock(&dev->struct_mutex);
314
315         return ret;
316 }
317
318 static int
319 i915_gem_shmem_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
320                       struct drm_i915_gem_pwrite *args,
321                       struct drm_file *file_priv)
322 {
323         int ret;
324         loff_t offset;
325         ssize_t written;
326
327         mutex_lock(&dev->struct_mutex);
328
329         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
330         if (ret) {
331                 mutex_unlock(&dev->struct_mutex);
332                 return ret;
333         }
334
335         offset = args->offset;
336
337         written = vfs_write(obj->filp,
338                             (char __user *)(uintptr_t) args->data_ptr,
339                             args->size, &offset);
340         if (written != args->size) {
341                 mutex_unlock(&dev->struct_mutex);
342                 if (written < 0)
343                         return written;
344                 else
345                         return -EINVAL;
346         }
347
348         mutex_unlock(&dev->struct_mutex);
349
350         return 0;
351 }
352
353 /**
354  * Writes data to the object referenced by handle.
355  *
356  * On error, the contents of the buffer that were to be modified are undefined.
357  */
358 int
359 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
360                       struct drm_file *file_priv)
361 {
362         struct drm_i915_gem_pwrite *args = data;
363         struct drm_gem_object *obj;
364         struct drm_i915_gem_object *obj_priv;
365         int ret = 0;
366
367         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
368         if (obj == NULL)
369                 return -EBADF;
370         obj_priv = obj->driver_private;
371
372         /* Bounds check destination.
373          *
374          * XXX: This could use review for overflow issues...
375          */
376         if (args->offset > obj->size || args->size > obj->size ||
377             args->offset + args->size > obj->size) {
378                 drm_gem_object_unreference(obj);
379                 return -EINVAL;
380         }
381
382         /* We can only do the GTT pwrite on untiled buffers, as otherwise
383          * it would end up going through the fenced access, and we'll get
384          * different detiling behavior between reading and writing.
385          * pread/pwrite currently are reading and writing from the CPU
386          * perspective, requiring manual detiling by the client.
387          */
388         if (obj_priv->phys_obj)
389                 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
390         else if (obj_priv->tiling_mode == I915_TILING_NONE &&
391                  dev->gtt_total != 0)
392                 ret = i915_gem_gtt_pwrite(dev, obj, args, file_priv);
393         else
394                 ret = i915_gem_shmem_pwrite(dev, obj, args, file_priv);
395
396 #if WATCH_PWRITE
397         if (ret)
398                 DRM_INFO("pwrite failed %d\n", ret);
399 #endif
400
401         drm_gem_object_unreference(obj);
402
403         return ret;
404 }
405
406 /**
407  * Called when user space prepares to use an object with the CPU, either
408  * through the mmap ioctl's mapping or a GTT mapping.
409  */
410 int
411 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
412                           struct drm_file *file_priv)
413 {
414         struct drm_i915_gem_set_domain *args = data;
415         struct drm_gem_object *obj;
416         uint32_t read_domains = args->read_domains;
417         uint32_t write_domain = args->write_domain;
418         int ret;
419
420         if (!(dev->driver->driver_features & DRIVER_GEM))
421                 return -ENODEV;
422
423         /* Only handle setting domains to types used by the CPU. */
424         if (write_domain & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
425                 return -EINVAL;
426
427         if (read_domains & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
428                 return -EINVAL;
429
430         /* Having something in the write domain implies it's in the read
431          * domain, and only that read domain.  Enforce that in the request.
432          */
433         if (write_domain != 0 && read_domains != write_domain)
434                 return -EINVAL;
435
436         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
437         if (obj == NULL)
438                 return -EBADF;
439
440         mutex_lock(&dev->struct_mutex);
441 #if WATCH_BUF
442         DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n",
443                  obj, obj->size, read_domains, write_domain);
444 #endif
445         if (read_domains & I915_GEM_DOMAIN_GTT) {
446                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
447
448                 /* Silently promote "you're not bound, there was nothing to do"
449                  * to success, since the client was just asking us to
450                  * make sure everything was done.
451                  */
452                 if (ret == -EINVAL)
453                         ret = 0;
454         } else {
455                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
456         }
457
458         drm_gem_object_unreference(obj);
459         mutex_unlock(&dev->struct_mutex);
460         return ret;
461 }
462
463 /**
464  * Called when user space has done writes to this buffer
465  */
466 int
467 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
468                       struct drm_file *file_priv)
469 {
470         struct drm_i915_gem_sw_finish *args = data;
471         struct drm_gem_object *obj;
472         struct drm_i915_gem_object *obj_priv;
473         int ret = 0;
474
475         if (!(dev->driver->driver_features & DRIVER_GEM))
476                 return -ENODEV;
477
478         mutex_lock(&dev->struct_mutex);
479         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
480         if (obj == NULL) {
481                 mutex_unlock(&dev->struct_mutex);
482                 return -EBADF;
483         }
484
485 #if WATCH_BUF
486         DRM_INFO("%s: sw_finish %d (%p %d)\n",
487                  __func__, args->handle, obj, obj->size);
488 #endif
489         obj_priv = obj->driver_private;
490
491         /* Pinned buffers may be scanout, so flush the cache */
492         if (obj_priv->pin_count)
493                 i915_gem_object_flush_cpu_write_domain(obj);
494
495         drm_gem_object_unreference(obj);
496         mutex_unlock(&dev->struct_mutex);
497         return ret;
498 }
499
500 /**
501  * Maps the contents of an object, returning the address it is mapped
502  * into.
503  *
504  * While the mapping holds a reference on the contents of the object, it doesn't
505  * imply a ref on the object itself.
506  */
507 int
508 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
509                    struct drm_file *file_priv)
510 {
511         struct drm_i915_gem_mmap *args = data;
512         struct drm_gem_object *obj;
513         loff_t offset;
514         unsigned long addr;
515
516         if (!(dev->driver->driver_features & DRIVER_GEM))
517                 return -ENODEV;
518
519         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
520         if (obj == NULL)
521                 return -EBADF;
522
523         offset = args->offset;
524
525         down_write(&current->mm->mmap_sem);
526         addr = do_mmap(obj->filp, 0, args->size,
527                        PROT_READ | PROT_WRITE, MAP_SHARED,
528                        args->offset);
529         up_write(&current->mm->mmap_sem);
530         mutex_lock(&dev->struct_mutex);
531         drm_gem_object_unreference(obj);
532         mutex_unlock(&dev->struct_mutex);
533         if (IS_ERR((void *)addr))
534                 return addr;
535
536         args->addr_ptr = (uint64_t) addr;
537
538         return 0;
539 }
540
541 /**
542  * i915_gem_fault - fault a page into the GTT
543  * vma: VMA in question
544  * vmf: fault info
545  *
546  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
547  * from userspace.  The fault handler takes care of binding the object to
548  * the GTT (if needed), allocating and programming a fence register (again,
549  * only if needed based on whether the old reg is still valid or the object
550  * is tiled) and inserting a new PTE into the faulting process.
551  *
552  * Note that the faulting process may involve evicting existing objects
553  * from the GTT and/or fence registers to make room.  So performance may
554  * suffer if the GTT working set is large or there are few fence registers
555  * left.
556  */
557 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
558 {
559         struct drm_gem_object *obj = vma->vm_private_data;
560         struct drm_device *dev = obj->dev;
561         struct drm_i915_private *dev_priv = dev->dev_private;
562         struct drm_i915_gem_object *obj_priv = obj->driver_private;
563         pgoff_t page_offset;
564         unsigned long pfn;
565         int ret = 0;
566         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
567
568         /* We don't use vmf->pgoff since that has the fake offset */
569         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
570                 PAGE_SHIFT;
571
572         /* Now bind it into the GTT if needed */
573         mutex_lock(&dev->struct_mutex);
574         if (!obj_priv->gtt_space) {
575                 ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
576                 if (ret) {
577                         mutex_unlock(&dev->struct_mutex);
578                         return VM_FAULT_SIGBUS;
579                 }
580                 list_add(&obj_priv->list, &dev_priv->mm.inactive_list);
581         }
582
583         /* Need a new fence register? */
584         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
585             obj_priv->tiling_mode != I915_TILING_NONE) {
586                 ret = i915_gem_object_get_fence_reg(obj, write);
587                 if (ret) {
588                         mutex_unlock(&dev->struct_mutex);
589                         return VM_FAULT_SIGBUS;
590                 }
591         }
592
593         pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
594                 page_offset;
595
596         /* Finally, remap it using the new GTT offset */
597         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
598
599         mutex_unlock(&dev->struct_mutex);
600
601         switch (ret) {
602         case -ENOMEM:
603         case -EAGAIN:
604                 return VM_FAULT_OOM;
605         case -EFAULT:
606                 return VM_FAULT_SIGBUS;
607         default:
608                 return VM_FAULT_NOPAGE;
609         }
610 }
611
612 /**
613  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
614  * @obj: obj in question
615  *
616  * GEM memory mapping works by handing back to userspace a fake mmap offset
617  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
618  * up the object based on the offset and sets up the various memory mapping
619  * structures.
620  *
621  * This routine allocates and attaches a fake offset for @obj.
622  */
623 static int
624 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
625 {
626         struct drm_device *dev = obj->dev;
627         struct drm_gem_mm *mm = dev->mm_private;
628         struct drm_i915_gem_object *obj_priv = obj->driver_private;
629         struct drm_map_list *list;
630         struct drm_map *map;
631         int ret = 0;
632
633         /* Set the object up for mmap'ing */
634         list = &obj->map_list;
635         list->map = drm_calloc(1, sizeof(struct drm_map_list),
636                                DRM_MEM_DRIVER);
637         if (!list->map)
638                 return -ENOMEM;
639
640         map = list->map;
641         map->type = _DRM_GEM;
642         map->size = obj->size;
643         map->handle = obj;
644
645         /* Get a DRM GEM mmap offset allocated... */
646         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
647                                                     obj->size / PAGE_SIZE, 0, 0);
648         if (!list->file_offset_node) {
649                 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
650                 ret = -ENOMEM;
651                 goto out_free_list;
652         }
653
654         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
655                                                   obj->size / PAGE_SIZE, 0);
656         if (!list->file_offset_node) {
657                 ret = -ENOMEM;
658                 goto out_free_list;
659         }
660
661         list->hash.key = list->file_offset_node->start;
662         if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
663                 DRM_ERROR("failed to add to map hash\n");
664                 goto out_free_mm;
665         }
666
667         /* By now we should be all set, any drm_mmap request on the offset
668          * below will get to our mmap & fault handler */
669         obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
670
671         return 0;
672
673 out_free_mm:
674         drm_mm_put_block(list->file_offset_node);
675 out_free_list:
676         drm_free(list->map, sizeof(struct drm_map_list), DRM_MEM_DRIVER);
677
678         return ret;
679 }
680
681 static void
682 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
683 {
684         struct drm_device *dev = obj->dev;
685         struct drm_i915_gem_object *obj_priv = obj->driver_private;
686         struct drm_gem_mm *mm = dev->mm_private;
687         struct drm_map_list *list;
688
689         list = &obj->map_list;
690         drm_ht_remove_item(&mm->offset_hash, &list->hash);
691
692         if (list->file_offset_node) {
693                 drm_mm_put_block(list->file_offset_node);
694                 list->file_offset_node = NULL;
695         }
696
697         if (list->map) {
698                 drm_free(list->map, sizeof(struct drm_map), DRM_MEM_DRIVER);
699                 list->map = NULL;
700         }
701
702         obj_priv->mmap_offset = 0;
703 }
704
705 /**
706  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
707  * @obj: object to check
708  *
709  * Return the required GTT alignment for an object, taking into account
710  * potential fence register mapping if needed.
711  */
712 static uint32_t
713 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
714 {
715         struct drm_device *dev = obj->dev;
716         struct drm_i915_gem_object *obj_priv = obj->driver_private;
717         int start, i;
718
719         /*
720          * Minimum alignment is 4k (GTT page size), but might be greater
721          * if a fence register is needed for the object.
722          */
723         if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
724                 return 4096;
725
726         /*
727          * Previous chips need to be aligned to the size of the smallest
728          * fence register that can contain the object.
729          */
730         if (IS_I9XX(dev))
731                 start = 1024*1024;
732         else
733                 start = 512*1024;
734
735         for (i = start; i < obj->size; i <<= 1)
736                 ;
737
738         return i;
739 }
740
741 /**
742  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
743  * @dev: DRM device
744  * @data: GTT mapping ioctl data
745  * @file_priv: GEM object info
746  *
747  * Simply returns the fake offset to userspace so it can mmap it.
748  * The mmap call will end up in drm_gem_mmap(), which will set things
749  * up so we can get faults in the handler above.
750  *
751  * The fault handler will take care of binding the object into the GTT
752  * (since it may have been evicted to make room for something), allocating
753  * a fence register, and mapping the appropriate aperture address into
754  * userspace.
755  */
756 int
757 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
758                         struct drm_file *file_priv)
759 {
760         struct drm_i915_gem_mmap_gtt *args = data;
761         struct drm_i915_private *dev_priv = dev->dev_private;
762         struct drm_gem_object *obj;
763         struct drm_i915_gem_object *obj_priv;
764         int ret;
765
766         if (!(dev->driver->driver_features & DRIVER_GEM))
767                 return -ENODEV;
768
769         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
770         if (obj == NULL)
771                 return -EBADF;
772
773         mutex_lock(&dev->struct_mutex);
774
775         obj_priv = obj->driver_private;
776
777         if (!obj_priv->mmap_offset) {
778                 ret = i915_gem_create_mmap_offset(obj);
779                 if (ret) {
780                         drm_gem_object_unreference(obj);
781                         mutex_unlock(&dev->struct_mutex);
782                         return ret;
783                 }
784         }
785
786         args->offset = obj_priv->mmap_offset;
787
788         obj_priv->gtt_alignment = i915_gem_get_gtt_alignment(obj);
789
790         /* Make sure the alignment is correct for fence regs etc */
791         if (obj_priv->agp_mem &&
792             (obj_priv->gtt_offset & (obj_priv->gtt_alignment - 1))) {
793                 drm_gem_object_unreference(obj);
794                 mutex_unlock(&dev->struct_mutex);
795                 return -EINVAL;
796         }
797
798         /*
799          * Pull it into the GTT so that we have a page list (makes the
800          * initial fault faster and any subsequent flushing possible).
801          */
802         if (!obj_priv->agp_mem) {
803                 ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
804                 if (ret) {
805                         drm_gem_object_unreference(obj);
806                         mutex_unlock(&dev->struct_mutex);
807                         return ret;
808                 }
809                 list_add(&obj_priv->list, &dev_priv->mm.inactive_list);
810         }
811
812         drm_gem_object_unreference(obj);
813         mutex_unlock(&dev->struct_mutex);
814
815         return 0;
816 }
817
818 static void
819 i915_gem_object_free_page_list(struct drm_gem_object *obj)
820 {
821         struct drm_i915_gem_object *obj_priv = obj->driver_private;
822         int page_count = obj->size / PAGE_SIZE;
823         int i;
824
825         if (obj_priv->page_list == NULL)
826                 return;
827
828
829         for (i = 0; i < page_count; i++)
830                 if (obj_priv->page_list[i] != NULL) {
831                         if (obj_priv->dirty)
832                                 set_page_dirty(obj_priv->page_list[i]);
833                         mark_page_accessed(obj_priv->page_list[i]);
834                         page_cache_release(obj_priv->page_list[i]);
835                 }
836         obj_priv->dirty = 0;
837
838         drm_free(obj_priv->page_list,
839                  page_count * sizeof(struct page *),
840                  DRM_MEM_DRIVER);
841         obj_priv->page_list = NULL;
842 }
843
844 static void
845 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
846 {
847         struct drm_device *dev = obj->dev;
848         drm_i915_private_t *dev_priv = dev->dev_private;
849         struct drm_i915_gem_object *obj_priv = obj->driver_private;
850
851         /* Add a reference if we're newly entering the active list. */
852         if (!obj_priv->active) {
853                 drm_gem_object_reference(obj);
854                 obj_priv->active = 1;
855         }
856         /* Move from whatever list we were on to the tail of execution. */
857         list_move_tail(&obj_priv->list,
858                        &dev_priv->mm.active_list);
859         obj_priv->last_rendering_seqno = seqno;
860 }
861
862 static void
863 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
864 {
865         struct drm_device *dev = obj->dev;
866         drm_i915_private_t *dev_priv = dev->dev_private;
867         struct drm_i915_gem_object *obj_priv = obj->driver_private;
868
869         BUG_ON(!obj_priv->active);
870         list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
871         obj_priv->last_rendering_seqno = 0;
872 }
873
874 static void
875 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
876 {
877         struct drm_device *dev = obj->dev;
878         drm_i915_private_t *dev_priv = dev->dev_private;
879         struct drm_i915_gem_object *obj_priv = obj->driver_private;
880
881         i915_verify_inactive(dev, __FILE__, __LINE__);
882         if (obj_priv->pin_count != 0)
883                 list_del_init(&obj_priv->list);
884         else
885                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
886
887         obj_priv->last_rendering_seqno = 0;
888         if (obj_priv->active) {
889                 obj_priv->active = 0;
890                 drm_gem_object_unreference(obj);
891         }
892         i915_verify_inactive(dev, __FILE__, __LINE__);
893 }
894
895 /**
896  * Creates a new sequence number, emitting a write of it to the status page
897  * plus an interrupt, which will trigger i915_user_interrupt_handler.
898  *
899  * Must be called with struct_lock held.
900  *
901  * Returned sequence numbers are nonzero on success.
902  */
903 static uint32_t
904 i915_add_request(struct drm_device *dev, uint32_t flush_domains)
905 {
906         drm_i915_private_t *dev_priv = dev->dev_private;
907         struct drm_i915_gem_request *request;
908         uint32_t seqno;
909         int was_empty;
910         RING_LOCALS;
911
912         request = drm_calloc(1, sizeof(*request), DRM_MEM_DRIVER);
913         if (request == NULL)
914                 return 0;
915
916         /* Grab the seqno we're going to make this request be, and bump the
917          * next (skipping 0 so it can be the reserved no-seqno value).
918          */
919         seqno = dev_priv->mm.next_gem_seqno;
920         dev_priv->mm.next_gem_seqno++;
921         if (dev_priv->mm.next_gem_seqno == 0)
922                 dev_priv->mm.next_gem_seqno++;
923
924         BEGIN_LP_RING(4);
925         OUT_RING(MI_STORE_DWORD_INDEX);
926         OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
927         OUT_RING(seqno);
928
929         OUT_RING(MI_USER_INTERRUPT);
930         ADVANCE_LP_RING();
931
932         DRM_DEBUG("%d\n", seqno);
933
934         request->seqno = seqno;
935         request->emitted_jiffies = jiffies;
936         was_empty = list_empty(&dev_priv->mm.request_list);
937         list_add_tail(&request->list, &dev_priv->mm.request_list);
938
939         /* Associate any objects on the flushing list matching the write
940          * domain we're flushing with our flush.
941          */
942         if (flush_domains != 0) {
943                 struct drm_i915_gem_object *obj_priv, *next;
944
945                 list_for_each_entry_safe(obj_priv, next,
946                                          &dev_priv->mm.flushing_list, list) {
947                         struct drm_gem_object *obj = obj_priv->obj;
948
949                         if ((obj->write_domain & flush_domains) ==
950                             obj->write_domain) {
951                                 obj->write_domain = 0;
952                                 i915_gem_object_move_to_active(obj, seqno);
953                         }
954                 }
955
956         }
957
958         if (was_empty && !dev_priv->mm.suspended)
959                 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
960         return seqno;
961 }
962
963 /**
964  * Command execution barrier
965  *
966  * Ensures that all commands in the ring are finished
967  * before signalling the CPU
968  */
969 static uint32_t
970 i915_retire_commands(struct drm_device *dev)
971 {
972         drm_i915_private_t *dev_priv = dev->dev_private;
973         uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
974         uint32_t flush_domains = 0;
975         RING_LOCALS;
976
977         /* The sampler always gets flushed on i965 (sigh) */
978         if (IS_I965G(dev))
979                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
980         BEGIN_LP_RING(2);
981         OUT_RING(cmd);
982         OUT_RING(0); /* noop */
983         ADVANCE_LP_RING();
984         return flush_domains;
985 }
986
987 /**
988  * Moves buffers associated only with the given active seqno from the active
989  * to inactive list, potentially freeing them.
990  */
991 static void
992 i915_gem_retire_request(struct drm_device *dev,
993                         struct drm_i915_gem_request *request)
994 {
995         drm_i915_private_t *dev_priv = dev->dev_private;
996
997         /* Move any buffers on the active list that are no longer referenced
998          * by the ringbuffer to the flushing/inactive lists as appropriate.
999          */
1000         while (!list_empty(&dev_priv->mm.active_list)) {
1001                 struct drm_gem_object *obj;
1002                 struct drm_i915_gem_object *obj_priv;
1003
1004                 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1005                                             struct drm_i915_gem_object,
1006                                             list);
1007                 obj = obj_priv->obj;
1008
1009                 /* If the seqno being retired doesn't match the oldest in the
1010                  * list, then the oldest in the list must still be newer than
1011                  * this seqno.
1012                  */
1013                 if (obj_priv->last_rendering_seqno != request->seqno)
1014                         return;
1015
1016 #if WATCH_LRU
1017                 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1018                          __func__, request->seqno, obj);
1019 #endif
1020
1021                 if (obj->write_domain != 0)
1022                         i915_gem_object_move_to_flushing(obj);
1023                 else
1024                         i915_gem_object_move_to_inactive(obj);
1025         }
1026 }
1027
1028 /**
1029  * Returns true if seq1 is later than seq2.
1030  */
1031 static int
1032 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1033 {
1034         return (int32_t)(seq1 - seq2) >= 0;
1035 }
1036
1037 uint32_t
1038 i915_get_gem_seqno(struct drm_device *dev)
1039 {
1040         drm_i915_private_t *dev_priv = dev->dev_private;
1041
1042         return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1043 }
1044
1045 /**
1046  * This function clears the request list as sequence numbers are passed.
1047  */
1048 void
1049 i915_gem_retire_requests(struct drm_device *dev)
1050 {
1051         drm_i915_private_t *dev_priv = dev->dev_private;
1052         uint32_t seqno;
1053
1054         if (!dev_priv->hw_status_page)
1055                 return;
1056
1057         seqno = i915_get_gem_seqno(dev);
1058
1059         while (!list_empty(&dev_priv->mm.request_list)) {
1060                 struct drm_i915_gem_request *request;
1061                 uint32_t retiring_seqno;
1062
1063                 request = list_first_entry(&dev_priv->mm.request_list,
1064                                            struct drm_i915_gem_request,
1065                                            list);
1066                 retiring_seqno = request->seqno;
1067
1068                 if (i915_seqno_passed(seqno, retiring_seqno) ||
1069                     dev_priv->mm.wedged) {
1070                         i915_gem_retire_request(dev, request);
1071
1072                         list_del(&request->list);
1073                         drm_free(request, sizeof(*request), DRM_MEM_DRIVER);
1074                 } else
1075                         break;
1076         }
1077 }
1078
1079 void
1080 i915_gem_retire_work_handler(struct work_struct *work)
1081 {
1082         drm_i915_private_t *dev_priv;
1083         struct drm_device *dev;
1084
1085         dev_priv = container_of(work, drm_i915_private_t,
1086                                 mm.retire_work.work);
1087         dev = dev_priv->dev;
1088
1089         mutex_lock(&dev->struct_mutex);
1090         i915_gem_retire_requests(dev);
1091         if (!dev_priv->mm.suspended &&
1092             !list_empty(&dev_priv->mm.request_list))
1093                 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
1094         mutex_unlock(&dev->struct_mutex);
1095 }
1096
1097 /**
1098  * Waits for a sequence number to be signaled, and cleans up the
1099  * request and object lists appropriately for that event.
1100  */
1101 static int
1102 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1103 {
1104         drm_i915_private_t *dev_priv = dev->dev_private;
1105         int ret = 0;
1106
1107         BUG_ON(seqno == 0);
1108
1109         if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1110                 dev_priv->mm.waiting_gem_seqno = seqno;
1111                 i915_user_irq_get(dev);
1112                 ret = wait_event_interruptible(dev_priv->irq_queue,
1113                                                i915_seqno_passed(i915_get_gem_seqno(dev),
1114                                                                  seqno) ||
1115                                                dev_priv->mm.wedged);
1116                 i915_user_irq_put(dev);
1117                 dev_priv->mm.waiting_gem_seqno = 0;
1118         }
1119         if (dev_priv->mm.wedged)
1120                 ret = -EIO;
1121
1122         if (ret && ret != -ERESTARTSYS)
1123                 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1124                           __func__, ret, seqno, i915_get_gem_seqno(dev));
1125
1126         /* Directly dispatch request retiring.  While we have the work queue
1127          * to handle this, the waiter on a request often wants an associated
1128          * buffer to have made it to the inactive list, and we would need
1129          * a separate wait queue to handle that.
1130          */
1131         if (ret == 0)
1132                 i915_gem_retire_requests(dev);
1133
1134         return ret;
1135 }
1136
1137 static void
1138 i915_gem_flush(struct drm_device *dev,
1139                uint32_t invalidate_domains,
1140                uint32_t flush_domains)
1141 {
1142         drm_i915_private_t *dev_priv = dev->dev_private;
1143         uint32_t cmd;
1144         RING_LOCALS;
1145
1146 #if WATCH_EXEC
1147         DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1148                   invalidate_domains, flush_domains);
1149 #endif
1150
1151         if (flush_domains & I915_GEM_DOMAIN_CPU)
1152                 drm_agp_chipset_flush(dev);
1153
1154         if ((invalidate_domains | flush_domains) & ~(I915_GEM_DOMAIN_CPU |
1155                                                      I915_GEM_DOMAIN_GTT)) {
1156                 /*
1157                  * read/write caches:
1158                  *
1159                  * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1160                  * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
1161                  * also flushed at 2d versus 3d pipeline switches.
1162                  *
1163                  * read-only caches:
1164                  *
1165                  * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1166                  * MI_READ_FLUSH is set, and is always flushed on 965.
1167                  *
1168                  * I915_GEM_DOMAIN_COMMAND may not exist?
1169                  *
1170                  * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1171                  * invalidated when MI_EXE_FLUSH is set.
1172                  *
1173                  * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1174                  * invalidated with every MI_FLUSH.
1175                  *
1176                  * TLBs:
1177                  *
1178                  * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1179                  * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1180                  * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1181                  * are flushed at any MI_FLUSH.
1182                  */
1183
1184                 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1185                 if ((invalidate_domains|flush_domains) &
1186                     I915_GEM_DOMAIN_RENDER)
1187                         cmd &= ~MI_NO_WRITE_FLUSH;
1188                 if (!IS_I965G(dev)) {
1189                         /*
1190                          * On the 965, the sampler cache always gets flushed
1191                          * and this bit is reserved.
1192                          */
1193                         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1194                                 cmd |= MI_READ_FLUSH;
1195                 }
1196                 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1197                         cmd |= MI_EXE_FLUSH;
1198
1199 #if WATCH_EXEC
1200                 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1201 #endif
1202                 BEGIN_LP_RING(2);
1203                 OUT_RING(cmd);
1204                 OUT_RING(0); /* noop */
1205                 ADVANCE_LP_RING();
1206         }
1207 }
1208
1209 /**
1210  * Ensures that all rendering to the object has completed and the object is
1211  * safe to unbind from the GTT or access from the CPU.
1212  */
1213 static int
1214 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1215 {
1216         struct drm_device *dev = obj->dev;
1217         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1218         int ret;
1219
1220         /* This function only exists to support waiting for existing rendering,
1221          * not for emitting required flushes.
1222          */
1223         BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1224
1225         /* If there is rendering queued on the buffer being evicted, wait for
1226          * it.
1227          */
1228         if (obj_priv->active) {
1229 #if WATCH_BUF
1230                 DRM_INFO("%s: object %p wait for seqno %08x\n",
1231                           __func__, obj, obj_priv->last_rendering_seqno);
1232 #endif
1233                 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1234                 if (ret != 0)
1235                         return ret;
1236         }
1237
1238         return 0;
1239 }
1240
1241 /**
1242  * Unbinds an object from the GTT aperture.
1243  */
1244 int
1245 i915_gem_object_unbind(struct drm_gem_object *obj)
1246 {
1247         struct drm_device *dev = obj->dev;
1248         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1249         loff_t offset;
1250         int ret = 0;
1251
1252 #if WATCH_BUF
1253         DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1254         DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1255 #endif
1256         if (obj_priv->gtt_space == NULL)
1257                 return 0;
1258
1259         if (obj_priv->pin_count != 0) {
1260                 DRM_ERROR("Attempting to unbind pinned buffer\n");
1261                 return -EINVAL;
1262         }
1263
1264         /* Move the object to the CPU domain to ensure that
1265          * any possible CPU writes while it's not in the GTT
1266          * are flushed when we go to remap it. This will
1267          * also ensure that all pending GPU writes are finished
1268          * before we unbind.
1269          */
1270         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1271         if (ret) {
1272                 if (ret != -ERESTARTSYS)
1273                         DRM_ERROR("set_domain failed: %d\n", ret);
1274                 return ret;
1275         }
1276
1277         if (obj_priv->agp_mem != NULL) {
1278                 drm_unbind_agp(obj_priv->agp_mem);
1279                 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1280                 obj_priv->agp_mem = NULL;
1281         }
1282
1283         BUG_ON(obj_priv->active);
1284
1285         /* blow away mappings if mapped through GTT */
1286         offset = ((loff_t) obj->map_list.hash.key) << PAGE_SHIFT;
1287         if (dev->dev_mapping)
1288                 unmap_mapping_range(dev->dev_mapping, offset, obj->size, 1);
1289
1290         if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1291                 i915_gem_clear_fence_reg(obj);
1292
1293         i915_gem_object_free_page_list(obj);
1294
1295         if (obj_priv->gtt_space) {
1296                 atomic_dec(&dev->gtt_count);
1297                 atomic_sub(obj->size, &dev->gtt_memory);
1298
1299                 drm_mm_put_block(obj_priv->gtt_space);
1300                 obj_priv->gtt_space = NULL;
1301         }
1302
1303         /* Remove ourselves from the LRU list if present. */
1304         if (!list_empty(&obj_priv->list))
1305                 list_del_init(&obj_priv->list);
1306
1307         return 0;
1308 }
1309
1310 static int
1311 i915_gem_evict_something(struct drm_device *dev)
1312 {
1313         drm_i915_private_t *dev_priv = dev->dev_private;
1314         struct drm_gem_object *obj;
1315         struct drm_i915_gem_object *obj_priv;
1316         int ret = 0;
1317
1318         for (;;) {
1319                 /* If there's an inactive buffer available now, grab it
1320                  * and be done.
1321                  */
1322                 if (!list_empty(&dev_priv->mm.inactive_list)) {
1323                         obj_priv = list_first_entry(&dev_priv->mm.inactive_list,
1324                                                     struct drm_i915_gem_object,
1325                                                     list);
1326                         obj = obj_priv->obj;
1327                         BUG_ON(obj_priv->pin_count != 0);
1328 #if WATCH_LRU
1329                         DRM_INFO("%s: evicting %p\n", __func__, obj);
1330 #endif
1331                         BUG_ON(obj_priv->active);
1332
1333                         /* Wait on the rendering and unbind the buffer. */
1334                         ret = i915_gem_object_unbind(obj);
1335                         break;
1336                 }
1337
1338                 /* If we didn't get anything, but the ring is still processing
1339                  * things, wait for one of those things to finish and hopefully
1340                  * leave us a buffer to evict.
1341                  */
1342                 if (!list_empty(&dev_priv->mm.request_list)) {
1343                         struct drm_i915_gem_request *request;
1344
1345                         request = list_first_entry(&dev_priv->mm.request_list,
1346                                                    struct drm_i915_gem_request,
1347                                                    list);
1348
1349                         ret = i915_wait_request(dev, request->seqno);
1350                         if (ret)
1351                                 break;
1352
1353                         /* if waiting caused an object to become inactive,
1354                          * then loop around and wait for it. Otherwise, we
1355                          * assume that waiting freed and unbound something,
1356                          * so there should now be some space in the GTT
1357                          */
1358                         if (!list_empty(&dev_priv->mm.inactive_list))
1359                                 continue;
1360                         break;
1361                 }
1362
1363                 /* If we didn't have anything on the request list but there
1364                  * are buffers awaiting a flush, emit one and try again.
1365                  * When we wait on it, those buffers waiting for that flush
1366                  * will get moved to inactive.
1367                  */
1368                 if (!list_empty(&dev_priv->mm.flushing_list)) {
1369                         obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1370                                                     struct drm_i915_gem_object,
1371                                                     list);
1372                         obj = obj_priv->obj;
1373
1374                         i915_gem_flush(dev,
1375                                        obj->write_domain,
1376                                        obj->write_domain);
1377                         i915_add_request(dev, obj->write_domain);
1378
1379                         obj = NULL;
1380                         continue;
1381                 }
1382
1383                 DRM_ERROR("inactive empty %d request empty %d "
1384                           "flushing empty %d\n",
1385                           list_empty(&dev_priv->mm.inactive_list),
1386                           list_empty(&dev_priv->mm.request_list),
1387                           list_empty(&dev_priv->mm.flushing_list));
1388                 /* If we didn't do any of the above, there's nothing to be done
1389                  * and we just can't fit it in.
1390                  */
1391                 return -ENOMEM;
1392         }
1393         return ret;
1394 }
1395
1396 static int
1397 i915_gem_evict_everything(struct drm_device *dev)
1398 {
1399         int ret;
1400
1401         for (;;) {
1402                 ret = i915_gem_evict_something(dev);
1403                 if (ret != 0)
1404                         break;
1405         }
1406         if (ret == -ENOMEM)
1407                 return 0;
1408         return ret;
1409 }
1410
1411 static int
1412 i915_gem_object_get_page_list(struct drm_gem_object *obj)
1413 {
1414         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1415         int page_count, i;
1416         struct address_space *mapping;
1417         struct inode *inode;
1418         struct page *page;
1419         int ret;
1420
1421         if (obj_priv->page_list)
1422                 return 0;
1423
1424         /* Get the list of pages out of our struct file.  They'll be pinned
1425          * at this point until we release them.
1426          */
1427         page_count = obj->size / PAGE_SIZE;
1428         BUG_ON(obj_priv->page_list != NULL);
1429         obj_priv->page_list = drm_calloc(page_count, sizeof(struct page *),
1430                                          DRM_MEM_DRIVER);
1431         if (obj_priv->page_list == NULL) {
1432                 DRM_ERROR("Faled to allocate page list\n");
1433                 return -ENOMEM;
1434         }
1435
1436         inode = obj->filp->f_path.dentry->d_inode;
1437         mapping = inode->i_mapping;
1438         for (i = 0; i < page_count; i++) {
1439                 page = read_mapping_page(mapping, i, NULL);
1440                 if (IS_ERR(page)) {
1441                         ret = PTR_ERR(page);
1442                         DRM_ERROR("read_mapping_page failed: %d\n", ret);
1443                         i915_gem_object_free_page_list(obj);
1444                         return ret;
1445                 }
1446                 obj_priv->page_list[i] = page;
1447         }
1448         return 0;
1449 }
1450
1451 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
1452 {
1453         struct drm_gem_object *obj = reg->obj;
1454         struct drm_device *dev = obj->dev;
1455         drm_i915_private_t *dev_priv = dev->dev_private;
1456         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1457         int regnum = obj_priv->fence_reg;
1458         uint64_t val;
1459
1460         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
1461                     0xfffff000) << 32;
1462         val |= obj_priv->gtt_offset & 0xfffff000;
1463         val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
1464         if (obj_priv->tiling_mode == I915_TILING_Y)
1465                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
1466         val |= I965_FENCE_REG_VALID;
1467
1468         I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
1469 }
1470
1471 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
1472 {
1473         struct drm_gem_object *obj = reg->obj;
1474         struct drm_device *dev = obj->dev;
1475         drm_i915_private_t *dev_priv = dev->dev_private;
1476         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1477         int regnum = obj_priv->fence_reg;
1478         int tile_width;
1479         uint32_t fence_reg, val;
1480         uint32_t pitch_val;
1481
1482         if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
1483             (obj_priv->gtt_offset & (obj->size - 1))) {
1484                 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
1485                      __func__, obj_priv->gtt_offset, obj->size);
1486                 return;
1487         }
1488
1489         if (obj_priv->tiling_mode == I915_TILING_Y &&
1490             HAS_128_BYTE_Y_TILING(dev))
1491                 tile_width = 128;
1492         else
1493                 tile_width = 512;
1494
1495         /* Note: pitch better be a power of two tile widths */
1496         pitch_val = obj_priv->stride / tile_width;
1497         pitch_val = ffs(pitch_val) - 1;
1498
1499         val = obj_priv->gtt_offset;
1500         if (obj_priv->tiling_mode == I915_TILING_Y)
1501                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1502         val |= I915_FENCE_SIZE_BITS(obj->size);
1503         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1504         val |= I830_FENCE_REG_VALID;
1505
1506         if (regnum < 8)
1507                 fence_reg = FENCE_REG_830_0 + (regnum * 4);
1508         else
1509                 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
1510         I915_WRITE(fence_reg, val);
1511 }
1512
1513 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
1514 {
1515         struct drm_gem_object *obj = reg->obj;
1516         struct drm_device *dev = obj->dev;
1517         drm_i915_private_t *dev_priv = dev->dev_private;
1518         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1519         int regnum = obj_priv->fence_reg;
1520         uint32_t val;
1521         uint32_t pitch_val;
1522
1523         if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
1524             (obj_priv->gtt_offset & (obj->size - 1))) {
1525                 WARN(1, "%s: object 0x%08x not 1M or size aligned\n",
1526                      __func__, obj_priv->gtt_offset);
1527                 return;
1528         }
1529
1530         pitch_val = (obj_priv->stride / 128) - 1;
1531
1532         val = obj_priv->gtt_offset;
1533         if (obj_priv->tiling_mode == I915_TILING_Y)
1534                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1535         val |= I830_FENCE_SIZE_BITS(obj->size);
1536         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1537         val |= I830_FENCE_REG_VALID;
1538
1539         I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
1540
1541 }
1542
1543 /**
1544  * i915_gem_object_get_fence_reg - set up a fence reg for an object
1545  * @obj: object to map through a fence reg
1546  * @write: object is about to be written
1547  *
1548  * When mapping objects through the GTT, userspace wants to be able to write
1549  * to them without having to worry about swizzling if the object is tiled.
1550  *
1551  * This function walks the fence regs looking for a free one for @obj,
1552  * stealing one if it can't find any.
1553  *
1554  * It then sets up the reg based on the object's properties: address, pitch
1555  * and tiling format.
1556  */
1557 static int
1558 i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write)
1559 {
1560         struct drm_device *dev = obj->dev;
1561         struct drm_i915_private *dev_priv = dev->dev_private;
1562         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1563         struct drm_i915_fence_reg *reg = NULL;
1564         struct drm_i915_gem_object *old_obj_priv = NULL;
1565         int i, ret, avail;
1566
1567         switch (obj_priv->tiling_mode) {
1568         case I915_TILING_NONE:
1569                 WARN(1, "allocating a fence for non-tiled object?\n");
1570                 break;
1571         case I915_TILING_X:
1572                 if (!obj_priv->stride)
1573                         return -EINVAL;
1574                 WARN((obj_priv->stride & (512 - 1)),
1575                      "object 0x%08x is X tiled but has non-512B pitch\n",
1576                      obj_priv->gtt_offset);
1577                 break;
1578         case I915_TILING_Y:
1579                 if (!obj_priv->stride)
1580                         return -EINVAL;
1581                 WARN((obj_priv->stride & (128 - 1)),
1582                      "object 0x%08x is Y tiled but has non-128B pitch\n",
1583                      obj_priv->gtt_offset);
1584                 break;
1585         }
1586
1587         /* First try to find a free reg */
1588 try_again:
1589         avail = 0;
1590         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
1591                 reg = &dev_priv->fence_regs[i];
1592                 if (!reg->obj)
1593                         break;
1594
1595                 old_obj_priv = reg->obj->driver_private;
1596                 if (!old_obj_priv->pin_count)
1597                     avail++;
1598         }
1599
1600         /* None available, try to steal one or wait for a user to finish */
1601         if (i == dev_priv->num_fence_regs) {
1602                 uint32_t seqno = dev_priv->mm.next_gem_seqno;
1603                 loff_t offset;
1604
1605                 if (avail == 0)
1606                         return -ENOMEM;
1607
1608                 for (i = dev_priv->fence_reg_start;
1609                      i < dev_priv->num_fence_regs; i++) {
1610                         uint32_t this_seqno;
1611
1612                         reg = &dev_priv->fence_regs[i];
1613                         old_obj_priv = reg->obj->driver_private;
1614
1615                         if (old_obj_priv->pin_count)
1616                                 continue;
1617
1618                         /* i915 uses fences for GPU access to tiled buffers */
1619                         if (IS_I965G(dev) || !old_obj_priv->active)
1620                                 break;
1621
1622                         /* find the seqno of the first available fence */
1623                         this_seqno = old_obj_priv->last_rendering_seqno;
1624                         if (this_seqno != 0 &&
1625                             reg->obj->write_domain == 0 &&
1626                             i915_seqno_passed(seqno, this_seqno))
1627                                 seqno = this_seqno;
1628                 }
1629
1630                 /*
1631                  * Now things get ugly... we have to wait for one of the
1632                  * objects to finish before trying again.
1633                  */
1634                 if (i == dev_priv->num_fence_regs) {
1635                         if (seqno == dev_priv->mm.next_gem_seqno) {
1636                                 i915_gem_flush(dev,
1637                                                I915_GEM_GPU_DOMAINS,
1638                                                I915_GEM_GPU_DOMAINS);
1639                                 seqno = i915_add_request(dev,
1640                                                          I915_GEM_GPU_DOMAINS);
1641                                 if (seqno == 0)
1642                                         return -ENOMEM;
1643                         }
1644
1645                         ret = i915_wait_request(dev, seqno);
1646                         if (ret)
1647                                 return ret;
1648                         goto try_again;
1649                 }
1650
1651                 BUG_ON(old_obj_priv->active ||
1652                        (reg->obj->write_domain & I915_GEM_GPU_DOMAINS));
1653
1654                 /*
1655                  * Zap this virtual mapping so we can set up a fence again
1656                  * for this object next time we need it.
1657                  */
1658                 offset = ((loff_t) reg->obj->map_list.hash.key) << PAGE_SHIFT;
1659                 if (dev->dev_mapping)
1660                         unmap_mapping_range(dev->dev_mapping, offset,
1661                                             reg->obj->size, 1);
1662                 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
1663         }
1664
1665         obj_priv->fence_reg = i;
1666         reg->obj = obj;
1667
1668         if (IS_I965G(dev))
1669                 i965_write_fence_reg(reg);
1670         else if (IS_I9XX(dev))
1671                 i915_write_fence_reg(reg);
1672         else
1673                 i830_write_fence_reg(reg);
1674
1675         return 0;
1676 }
1677
1678 /**
1679  * i915_gem_clear_fence_reg - clear out fence register info
1680  * @obj: object to clear
1681  *
1682  * Zeroes out the fence register itself and clears out the associated
1683  * data structures in dev_priv and obj_priv.
1684  */
1685 static void
1686 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
1687 {
1688         struct drm_device *dev = obj->dev;
1689         drm_i915_private_t *dev_priv = dev->dev_private;
1690         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1691
1692         if (IS_I965G(dev))
1693                 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
1694         else {
1695                 uint32_t fence_reg;
1696
1697                 if (obj_priv->fence_reg < 8)
1698                         fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
1699                 else
1700                         fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
1701                                                        8) * 4;
1702
1703                 I915_WRITE(fence_reg, 0);
1704         }
1705
1706         dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
1707         obj_priv->fence_reg = I915_FENCE_REG_NONE;
1708 }
1709
1710 /**
1711  * Finds free space in the GTT aperture and binds the object there.
1712  */
1713 static int
1714 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
1715 {
1716         struct drm_device *dev = obj->dev;
1717         drm_i915_private_t *dev_priv = dev->dev_private;
1718         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1719         struct drm_mm_node *free_space;
1720         int page_count, ret;
1721
1722         if (dev_priv->mm.suspended)
1723                 return -EBUSY;
1724         if (alignment == 0)
1725                 alignment = i915_gem_get_gtt_alignment(obj);
1726         if (alignment & (PAGE_SIZE - 1)) {
1727                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
1728                 return -EINVAL;
1729         }
1730
1731  search_free:
1732         free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
1733                                         obj->size, alignment, 0);
1734         if (free_space != NULL) {
1735                 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
1736                                                        alignment);
1737                 if (obj_priv->gtt_space != NULL) {
1738                         obj_priv->gtt_space->private = obj;
1739                         obj_priv->gtt_offset = obj_priv->gtt_space->start;
1740                 }
1741         }
1742         if (obj_priv->gtt_space == NULL) {
1743                 /* If the gtt is empty and we're still having trouble
1744                  * fitting our object in, we're out of memory.
1745                  */
1746 #if WATCH_LRU
1747                 DRM_INFO("%s: GTT full, evicting something\n", __func__);
1748 #endif
1749                 if (list_empty(&dev_priv->mm.inactive_list) &&
1750                     list_empty(&dev_priv->mm.flushing_list) &&
1751                     list_empty(&dev_priv->mm.active_list)) {
1752                         DRM_ERROR("GTT full, but LRU list empty\n");
1753                         return -ENOMEM;
1754                 }
1755
1756                 ret = i915_gem_evict_something(dev);
1757                 if (ret != 0) {
1758                         if (ret != -ERESTARTSYS)
1759                                 DRM_ERROR("Failed to evict a buffer %d\n", ret);
1760                         return ret;
1761                 }
1762                 goto search_free;
1763         }
1764
1765 #if WATCH_BUF
1766         DRM_INFO("Binding object of size %d at 0x%08x\n",
1767                  obj->size, obj_priv->gtt_offset);
1768 #endif
1769         ret = i915_gem_object_get_page_list(obj);
1770         if (ret) {
1771                 drm_mm_put_block(obj_priv->gtt_space);
1772                 obj_priv->gtt_space = NULL;
1773                 return ret;
1774         }
1775
1776         page_count = obj->size / PAGE_SIZE;
1777         /* Create an AGP memory structure pointing at our pages, and bind it
1778          * into the GTT.
1779          */
1780         obj_priv->agp_mem = drm_agp_bind_pages(dev,
1781                                                obj_priv->page_list,
1782                                                page_count,
1783                                                obj_priv->gtt_offset,
1784                                                obj_priv->agp_type);
1785         if (obj_priv->agp_mem == NULL) {
1786                 i915_gem_object_free_page_list(obj);
1787                 drm_mm_put_block(obj_priv->gtt_space);
1788                 obj_priv->gtt_space = NULL;
1789                 return -ENOMEM;
1790         }
1791         atomic_inc(&dev->gtt_count);
1792         atomic_add(obj->size, &dev->gtt_memory);
1793
1794         /* Assert that the object is not currently in any GPU domain. As it
1795          * wasn't in the GTT, there shouldn't be any way it could have been in
1796          * a GPU cache
1797          */
1798         BUG_ON(obj->read_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1799         BUG_ON(obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1800
1801         return 0;
1802 }
1803
1804 void
1805 i915_gem_clflush_object(struct drm_gem_object *obj)
1806 {
1807         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
1808
1809         /* If we don't have a page list set up, then we're not pinned
1810          * to GPU, and we can ignore the cache flush because it'll happen
1811          * again at bind time.
1812          */
1813         if (obj_priv->page_list == NULL)
1814                 return;
1815
1816         drm_clflush_pages(obj_priv->page_list, obj->size / PAGE_SIZE);
1817 }
1818
1819 /** Flushes any GPU write domain for the object if it's dirty. */
1820 static void
1821 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
1822 {
1823         struct drm_device *dev = obj->dev;
1824         uint32_t seqno;
1825
1826         if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
1827                 return;
1828
1829         /* Queue the GPU write cache flushing we need. */
1830         i915_gem_flush(dev, 0, obj->write_domain);
1831         seqno = i915_add_request(dev, obj->write_domain);
1832         obj->write_domain = 0;
1833         i915_gem_object_move_to_active(obj, seqno);
1834 }
1835
1836 /** Flushes the GTT write domain for the object if it's dirty. */
1837 static void
1838 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
1839 {
1840         if (obj->write_domain != I915_GEM_DOMAIN_GTT)
1841                 return;
1842
1843         /* No actual flushing is required for the GTT write domain.   Writes
1844          * to it immediately go to main memory as far as we know, so there's
1845          * no chipset flush.  It also doesn't land in render cache.
1846          */
1847         obj->write_domain = 0;
1848 }
1849
1850 /** Flushes the CPU write domain for the object if it's dirty. */
1851 static void
1852 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
1853 {
1854         struct drm_device *dev = obj->dev;
1855
1856         if (obj->write_domain != I915_GEM_DOMAIN_CPU)
1857                 return;
1858
1859         i915_gem_clflush_object(obj);
1860         drm_agp_chipset_flush(dev);
1861         obj->write_domain = 0;
1862 }
1863
1864 /**
1865  * Moves a single object to the GTT read, and possibly write domain.
1866  *
1867  * This function returns when the move is complete, including waiting on
1868  * flushes to occur.
1869  */
1870 int
1871 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
1872 {
1873         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1874         int ret;
1875
1876         /* Not valid to be called on unbound objects. */
1877         if (obj_priv->gtt_space == NULL)
1878                 return -EINVAL;
1879
1880         i915_gem_object_flush_gpu_write_domain(obj);
1881         /* Wait on any GPU rendering and flushing to occur. */
1882         ret = i915_gem_object_wait_rendering(obj);
1883         if (ret != 0)
1884                 return ret;
1885
1886         /* If we're writing through the GTT domain, then CPU and GPU caches
1887          * will need to be invalidated at next use.
1888          */
1889         if (write)
1890                 obj->read_domains &= I915_GEM_DOMAIN_GTT;
1891
1892         i915_gem_object_flush_cpu_write_domain(obj);
1893
1894         /* It should now be out of any other write domains, and we can update
1895          * the domain values for our changes.
1896          */
1897         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
1898         obj->read_domains |= I915_GEM_DOMAIN_GTT;
1899         if (write) {
1900                 obj->write_domain = I915_GEM_DOMAIN_GTT;
1901                 obj_priv->dirty = 1;
1902         }
1903
1904         return 0;
1905 }
1906
1907 /**
1908  * Moves a single object to the CPU read, and possibly write domain.
1909  *
1910  * This function returns when the move is complete, including waiting on
1911  * flushes to occur.
1912  */
1913 static int
1914 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
1915 {
1916         struct drm_device *dev = obj->dev;
1917         int ret;
1918
1919         i915_gem_object_flush_gpu_write_domain(obj);
1920         /* Wait on any GPU rendering and flushing to occur. */
1921         ret = i915_gem_object_wait_rendering(obj);
1922         if (ret != 0)
1923                 return ret;
1924
1925         i915_gem_object_flush_gtt_write_domain(obj);
1926
1927         /* If we have a partially-valid cache of the object in the CPU,
1928          * finish invalidating it and free the per-page flags.
1929          */
1930         i915_gem_object_set_to_full_cpu_read_domain(obj);
1931
1932         /* Flush the CPU cache if it's still invalid. */
1933         if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
1934                 i915_gem_clflush_object(obj);
1935                 drm_agp_chipset_flush(dev);
1936
1937                 obj->read_domains |= I915_GEM_DOMAIN_CPU;
1938         }
1939
1940         /* It should now be out of any other write domains, and we can update
1941          * the domain values for our changes.
1942          */
1943         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
1944
1945         /* If we're writing through the CPU, then the GPU read domains will
1946          * need to be invalidated at next use.
1947          */
1948         if (write) {
1949                 obj->read_domains &= I915_GEM_DOMAIN_CPU;
1950                 obj->write_domain = I915_GEM_DOMAIN_CPU;
1951         }
1952
1953         return 0;
1954 }
1955
1956 /*
1957  * Set the next domain for the specified object. This
1958  * may not actually perform the necessary flushing/invaliding though,
1959  * as that may want to be batched with other set_domain operations
1960  *
1961  * This is (we hope) the only really tricky part of gem. The goal
1962  * is fairly simple -- track which caches hold bits of the object
1963  * and make sure they remain coherent. A few concrete examples may
1964  * help to explain how it works. For shorthand, we use the notation
1965  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
1966  * a pair of read and write domain masks.
1967  *
1968  * Case 1: the batch buffer
1969  *
1970  *      1. Allocated
1971  *      2. Written by CPU
1972  *      3. Mapped to GTT
1973  *      4. Read by GPU
1974  *      5. Unmapped from GTT
1975  *      6. Freed
1976  *
1977  *      Let's take these a step at a time
1978  *
1979  *      1. Allocated
1980  *              Pages allocated from the kernel may still have
1981  *              cache contents, so we set them to (CPU, CPU) always.
1982  *      2. Written by CPU (using pwrite)
1983  *              The pwrite function calls set_domain (CPU, CPU) and
1984  *              this function does nothing (as nothing changes)
1985  *      3. Mapped by GTT
1986  *              This function asserts that the object is not
1987  *              currently in any GPU-based read or write domains
1988  *      4. Read by GPU
1989  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
1990  *              As write_domain is zero, this function adds in the
1991  *              current read domains (CPU+COMMAND, 0).
1992  *              flush_domains is set to CPU.
1993  *              invalidate_domains is set to COMMAND
1994  *              clflush is run to get data out of the CPU caches
1995  *              then i915_dev_set_domain calls i915_gem_flush to
1996  *              emit an MI_FLUSH and drm_agp_chipset_flush
1997  *      5. Unmapped from GTT
1998  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
1999  *              flush_domains and invalidate_domains end up both zero
2000  *              so no flushing/invalidating happens
2001  *      6. Freed
2002  *              yay, done
2003  *
2004  * Case 2: The shared render buffer
2005  *
2006  *      1. Allocated
2007  *      2. Mapped to GTT
2008  *      3. Read/written by GPU
2009  *      4. set_domain to (CPU,CPU)
2010  *      5. Read/written by CPU
2011  *      6. Read/written by GPU
2012  *
2013  *      1. Allocated
2014  *              Same as last example, (CPU, CPU)
2015  *      2. Mapped to GTT
2016  *              Nothing changes (assertions find that it is not in the GPU)
2017  *      3. Read/written by GPU
2018  *              execbuffer calls set_domain (RENDER, RENDER)
2019  *              flush_domains gets CPU
2020  *              invalidate_domains gets GPU
2021  *              clflush (obj)
2022  *              MI_FLUSH and drm_agp_chipset_flush
2023  *      4. set_domain (CPU, CPU)
2024  *              flush_domains gets GPU
2025  *              invalidate_domains gets CPU
2026  *              wait_rendering (obj) to make sure all drawing is complete.
2027  *              This will include an MI_FLUSH to get the data from GPU
2028  *              to memory
2029  *              clflush (obj) to invalidate the CPU cache
2030  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2031  *      5. Read/written by CPU
2032  *              cache lines are loaded and dirtied
2033  *      6. Read written by GPU
2034  *              Same as last GPU access
2035  *
2036  * Case 3: The constant buffer
2037  *
2038  *      1. Allocated
2039  *      2. Written by CPU
2040  *      3. Read by GPU
2041  *      4. Updated (written) by CPU again
2042  *      5. Read by GPU
2043  *
2044  *      1. Allocated
2045  *              (CPU, CPU)
2046  *      2. Written by CPU
2047  *              (CPU, CPU)
2048  *      3. Read by GPU
2049  *              (CPU+RENDER, 0)
2050  *              flush_domains = CPU
2051  *              invalidate_domains = RENDER
2052  *              clflush (obj)
2053  *              MI_FLUSH
2054  *              drm_agp_chipset_flush
2055  *      4. Updated (written) by CPU again
2056  *              (CPU, CPU)
2057  *              flush_domains = 0 (no previous write domain)
2058  *              invalidate_domains = 0 (no new read domains)
2059  *      5. Read by GPU
2060  *              (CPU+RENDER, 0)
2061  *              flush_domains = CPU
2062  *              invalidate_domains = RENDER
2063  *              clflush (obj)
2064  *              MI_FLUSH
2065  *              drm_agp_chipset_flush
2066  */
2067 static void
2068 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2069 {
2070         struct drm_device               *dev = obj->dev;
2071         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
2072         uint32_t                        invalidate_domains = 0;
2073         uint32_t                        flush_domains = 0;
2074
2075         BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2076         BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
2077
2078 #if WATCH_BUF
2079         DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2080                  __func__, obj,
2081                  obj->read_domains, obj->pending_read_domains,
2082                  obj->write_domain, obj->pending_write_domain);
2083 #endif
2084         /*
2085          * If the object isn't moving to a new write domain,
2086          * let the object stay in multiple read domains
2087          */
2088         if (obj->pending_write_domain == 0)
2089                 obj->pending_read_domains |= obj->read_domains;
2090         else
2091                 obj_priv->dirty = 1;
2092
2093         /*
2094          * Flush the current write domain if
2095          * the new read domains don't match. Invalidate
2096          * any read domains which differ from the old
2097          * write domain
2098          */
2099         if (obj->write_domain &&
2100             obj->write_domain != obj->pending_read_domains) {
2101                 flush_domains |= obj->write_domain;
2102                 invalidate_domains |=
2103                         obj->pending_read_domains & ~obj->write_domain;
2104         }
2105         /*
2106          * Invalidate any read caches which may have
2107          * stale data. That is, any new read domains.
2108          */
2109         invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
2110         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
2111 #if WATCH_BUF
2112                 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
2113                          __func__, flush_domains, invalidate_domains);
2114 #endif
2115                 i915_gem_clflush_object(obj);
2116         }
2117
2118         /* The actual obj->write_domain will be updated with
2119          * pending_write_domain after we emit the accumulated flush for all
2120          * of our domain changes in execbuffers (which clears objects'
2121          * write_domains).  So if we have a current write domain that we
2122          * aren't changing, set pending_write_domain to that.
2123          */
2124         if (flush_domains == 0 && obj->pending_write_domain == 0)
2125                 obj->pending_write_domain = obj->write_domain;
2126         obj->read_domains = obj->pending_read_domains;
2127
2128         dev->invalidate_domains |= invalidate_domains;
2129         dev->flush_domains |= flush_domains;
2130 #if WATCH_BUF
2131         DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
2132                  __func__,
2133                  obj->read_domains, obj->write_domain,
2134                  dev->invalidate_domains, dev->flush_domains);
2135 #endif
2136 }
2137
2138 /**
2139  * Moves the object from a partially CPU read to a full one.
2140  *
2141  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
2142  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
2143  */
2144 static void
2145 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
2146 {
2147         struct drm_device *dev = obj->dev;
2148         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2149
2150         if (!obj_priv->page_cpu_valid)
2151                 return;
2152
2153         /* If we're partially in the CPU read domain, finish moving it in.
2154          */
2155         if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
2156                 int i;
2157
2158                 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
2159                         if (obj_priv->page_cpu_valid[i])
2160                                 continue;
2161                         drm_clflush_pages(obj_priv->page_list + i, 1);
2162                 }
2163                 drm_agp_chipset_flush(dev);
2164         }
2165
2166         /* Free the page_cpu_valid mappings which are now stale, whether
2167          * or not we've got I915_GEM_DOMAIN_CPU.
2168          */
2169         drm_free(obj_priv->page_cpu_valid, obj->size / PAGE_SIZE,
2170                  DRM_MEM_DRIVER);
2171         obj_priv->page_cpu_valid = NULL;
2172 }
2173
2174 /**
2175  * Set the CPU read domain on a range of the object.
2176  *
2177  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
2178  * not entirely valid.  The page_cpu_valid member of the object flags which
2179  * pages have been flushed, and will be respected by
2180  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
2181  * of the whole object.
2182  *
2183  * This function returns when the move is complete, including waiting on
2184  * flushes to occur.
2185  */
2186 static int
2187 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
2188                                           uint64_t offset, uint64_t size)
2189 {
2190         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2191         int i, ret;
2192
2193         if (offset == 0 && size == obj->size)
2194                 return i915_gem_object_set_to_cpu_domain(obj, 0);
2195
2196         i915_gem_object_flush_gpu_write_domain(obj);
2197         /* Wait on any GPU rendering and flushing to occur. */
2198         ret = i915_gem_object_wait_rendering(obj);
2199         if (ret != 0)
2200                 return ret;
2201         i915_gem_object_flush_gtt_write_domain(obj);
2202
2203         /* If we're already fully in the CPU read domain, we're done. */
2204         if (obj_priv->page_cpu_valid == NULL &&
2205             (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
2206                 return 0;
2207
2208         /* Otherwise, create/clear the per-page CPU read domain flag if we're
2209          * newly adding I915_GEM_DOMAIN_CPU
2210          */
2211         if (obj_priv->page_cpu_valid == NULL) {
2212                 obj_priv->page_cpu_valid = drm_calloc(1, obj->size / PAGE_SIZE,
2213                                                       DRM_MEM_DRIVER);
2214                 if (obj_priv->page_cpu_valid == NULL)
2215                         return -ENOMEM;
2216         } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
2217                 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
2218
2219         /* Flush the cache on any pages that are still invalid from the CPU's
2220          * perspective.
2221          */
2222         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
2223              i++) {
2224                 if (obj_priv->page_cpu_valid[i])
2225                         continue;
2226
2227                 drm_clflush_pages(obj_priv->page_list + i, 1);
2228
2229                 obj_priv->page_cpu_valid[i] = 1;
2230         }
2231
2232         /* It should now be out of any other write domains, and we can update
2233          * the domain values for our changes.
2234          */
2235         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2236
2237         obj->read_domains |= I915_GEM_DOMAIN_CPU;
2238
2239         return 0;
2240 }
2241
2242 /**
2243  * Pin an object to the GTT and evaluate the relocations landing in it.
2244  */
2245 static int
2246 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
2247                                  struct drm_file *file_priv,
2248                                  struct drm_i915_gem_exec_object *entry)
2249 {
2250         struct drm_device *dev = obj->dev;
2251         drm_i915_private_t *dev_priv = dev->dev_private;
2252         struct drm_i915_gem_relocation_entry reloc;
2253         struct drm_i915_gem_relocation_entry __user *relocs;
2254         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2255         int i, ret;
2256         void __iomem *reloc_page;
2257
2258         /* Choose the GTT offset for our buffer and put it there. */
2259         ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
2260         if (ret)
2261                 return ret;
2262
2263         entry->offset = obj_priv->gtt_offset;
2264
2265         relocs = (struct drm_i915_gem_relocation_entry __user *)
2266                  (uintptr_t) entry->relocs_ptr;
2267         /* Apply the relocations, using the GTT aperture to avoid cache
2268          * flushing requirements.
2269          */
2270         for (i = 0; i < entry->relocation_count; i++) {
2271                 struct drm_gem_object *target_obj;
2272                 struct drm_i915_gem_object *target_obj_priv;
2273                 uint32_t reloc_val, reloc_offset;
2274                 uint32_t __iomem *reloc_entry;
2275
2276                 ret = copy_from_user(&reloc, relocs + i, sizeof(reloc));
2277                 if (ret != 0) {
2278                         i915_gem_object_unpin(obj);
2279                         return ret;
2280                 }
2281
2282                 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
2283                                                    reloc.target_handle);
2284                 if (target_obj == NULL) {
2285                         i915_gem_object_unpin(obj);
2286                         return -EBADF;
2287                 }
2288                 target_obj_priv = target_obj->driver_private;
2289
2290                 /* The target buffer should have appeared before us in the
2291                  * exec_object list, so it should have a GTT space bound by now.
2292                  */
2293                 if (target_obj_priv->gtt_space == NULL) {
2294                         DRM_ERROR("No GTT space found for object %d\n",
2295                                   reloc.target_handle);
2296                         drm_gem_object_unreference(target_obj);
2297                         i915_gem_object_unpin(obj);
2298                         return -EINVAL;
2299                 }
2300
2301                 if (reloc.offset > obj->size - 4) {
2302                         DRM_ERROR("Relocation beyond object bounds: "
2303                                   "obj %p target %d offset %d size %d.\n",
2304                                   obj, reloc.target_handle,
2305                                   (int) reloc.offset, (int) obj->size);
2306                         drm_gem_object_unreference(target_obj);
2307                         i915_gem_object_unpin(obj);
2308                         return -EINVAL;
2309                 }
2310                 if (reloc.offset & 3) {
2311                         DRM_ERROR("Relocation not 4-byte aligned: "
2312                                   "obj %p target %d offset %d.\n",
2313                                   obj, reloc.target_handle,
2314                                   (int) reloc.offset);
2315                         drm_gem_object_unreference(target_obj);
2316                         i915_gem_object_unpin(obj);
2317                         return -EINVAL;
2318                 }
2319
2320                 if (reloc.write_domain & I915_GEM_DOMAIN_CPU ||
2321                     reloc.read_domains & I915_GEM_DOMAIN_CPU) {
2322                         DRM_ERROR("reloc with read/write CPU domains: "
2323                                   "obj %p target %d offset %d "
2324                                   "read %08x write %08x",
2325                                   obj, reloc.target_handle,
2326                                   (int) reloc.offset,
2327                                   reloc.read_domains,
2328                                   reloc.write_domain);
2329                         drm_gem_object_unreference(target_obj);
2330                         i915_gem_object_unpin(obj);
2331                         return -EINVAL;
2332                 }
2333
2334                 if (reloc.write_domain && target_obj->pending_write_domain &&
2335                     reloc.write_domain != target_obj->pending_write_domain) {
2336                         DRM_ERROR("Write domain conflict: "
2337                                   "obj %p target %d offset %d "
2338                                   "new %08x old %08x\n",
2339                                   obj, reloc.target_handle,
2340                                   (int) reloc.offset,
2341                                   reloc.write_domain,
2342                                   target_obj->pending_write_domain);
2343                         drm_gem_object_unreference(target_obj);
2344                         i915_gem_object_unpin(obj);
2345                         return -EINVAL;
2346                 }
2347
2348 #if WATCH_RELOC
2349                 DRM_INFO("%s: obj %p offset %08x target %d "
2350                          "read %08x write %08x gtt %08x "
2351                          "presumed %08x delta %08x\n",
2352                          __func__,
2353                          obj,
2354                          (int) reloc.offset,
2355                          (int) reloc.target_handle,
2356                          (int) reloc.read_domains,
2357                          (int) reloc.write_domain,
2358                          (int) target_obj_priv->gtt_offset,
2359                          (int) reloc.presumed_offset,
2360                          reloc.delta);
2361 #endif
2362
2363                 target_obj->pending_read_domains |= reloc.read_domains;
2364                 target_obj->pending_write_domain |= reloc.write_domain;
2365
2366                 /* If the relocation already has the right value in it, no
2367                  * more work needs to be done.
2368                  */
2369                 if (target_obj_priv->gtt_offset == reloc.presumed_offset) {
2370                         drm_gem_object_unreference(target_obj);
2371                         continue;
2372                 }
2373
2374                 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
2375                 if (ret != 0) {
2376                         drm_gem_object_unreference(target_obj);
2377                         i915_gem_object_unpin(obj);
2378                         return -EINVAL;
2379                 }
2380
2381                 /* Map the page containing the relocation we're going to
2382                  * perform.
2383                  */
2384                 reloc_offset = obj_priv->gtt_offset + reloc.offset;
2385                 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
2386                                                       (reloc_offset &
2387                                                        ~(PAGE_SIZE - 1)));
2388                 reloc_entry = (uint32_t __iomem *)(reloc_page +
2389                                                    (reloc_offset & (PAGE_SIZE - 1)));
2390                 reloc_val = target_obj_priv->gtt_offset + reloc.delta;
2391
2392 #if WATCH_BUF
2393                 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
2394                           obj, (unsigned int) reloc.offset,
2395                           readl(reloc_entry), reloc_val);
2396 #endif
2397                 writel(reloc_val, reloc_entry);
2398                 io_mapping_unmap_atomic(reloc_page);
2399
2400                 /* Write the updated presumed offset for this entry back out
2401                  * to the user.
2402                  */
2403                 reloc.presumed_offset = target_obj_priv->gtt_offset;
2404                 ret = copy_to_user(relocs + i, &reloc, sizeof(reloc));
2405                 if (ret != 0) {
2406                         drm_gem_object_unreference(target_obj);
2407                         i915_gem_object_unpin(obj);
2408                         return ret;
2409                 }
2410
2411                 drm_gem_object_unreference(target_obj);
2412         }
2413
2414 #if WATCH_BUF
2415         if (0)
2416                 i915_gem_dump_object(obj, 128, __func__, ~0);
2417 #endif
2418         return 0;
2419 }
2420
2421 /** Dispatch a batchbuffer to the ring
2422  */
2423 static int
2424 i915_dispatch_gem_execbuffer(struct drm_device *dev,
2425                               struct drm_i915_gem_execbuffer *exec,
2426                               uint64_t exec_offset)
2427 {
2428         drm_i915_private_t *dev_priv = dev->dev_private;
2429         struct drm_clip_rect __user *boxes = (struct drm_clip_rect __user *)
2430                                              (uintptr_t) exec->cliprects_ptr;
2431         int nbox = exec->num_cliprects;
2432         int i = 0, count;
2433         uint32_t        exec_start, exec_len;
2434         RING_LOCALS;
2435
2436         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
2437         exec_len = (uint32_t) exec->batch_len;
2438
2439         if ((exec_start | exec_len) & 0x7) {
2440                 DRM_ERROR("alignment\n");
2441                 return -EINVAL;
2442         }
2443
2444         if (!exec_start)
2445                 return -EINVAL;
2446
2447         count = nbox ? nbox : 1;
2448
2449         for (i = 0; i < count; i++) {
2450                 if (i < nbox) {
2451                         int ret = i915_emit_box(dev, boxes, i,
2452                                                 exec->DR1, exec->DR4);
2453                         if (ret)
2454                                 return ret;
2455                 }
2456
2457                 if (IS_I830(dev) || IS_845G(dev)) {
2458                         BEGIN_LP_RING(4);
2459                         OUT_RING(MI_BATCH_BUFFER);
2460                         OUT_RING(exec_start | MI_BATCH_NON_SECURE);
2461                         OUT_RING(exec_start + exec_len - 4);
2462                         OUT_RING(0);
2463                         ADVANCE_LP_RING();
2464                 } else {
2465                         BEGIN_LP_RING(2);
2466                         if (IS_I965G(dev)) {
2467                                 OUT_RING(MI_BATCH_BUFFER_START |
2468                                          (2 << 6) |
2469                                          MI_BATCH_NON_SECURE_I965);
2470                                 OUT_RING(exec_start);
2471                         } else {
2472                                 OUT_RING(MI_BATCH_BUFFER_START |
2473                                          (2 << 6));
2474                                 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
2475                         }
2476                         ADVANCE_LP_RING();
2477                 }
2478         }
2479
2480         /* XXX breadcrumb */
2481         return 0;
2482 }
2483
2484 /* Throttle our rendering by waiting until the ring has completed our requests
2485  * emitted over 20 msec ago.
2486  *
2487  * This should get us reasonable parallelism between CPU and GPU but also
2488  * relatively low latency when blocking on a particular request to finish.
2489  */
2490 static int
2491 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
2492 {
2493         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
2494         int ret = 0;
2495         uint32_t seqno;
2496
2497         mutex_lock(&dev->struct_mutex);
2498         seqno = i915_file_priv->mm.last_gem_throttle_seqno;
2499         i915_file_priv->mm.last_gem_throttle_seqno =
2500                 i915_file_priv->mm.last_gem_seqno;
2501         if (seqno)
2502                 ret = i915_wait_request(dev, seqno);
2503         mutex_unlock(&dev->struct_mutex);
2504         return ret;
2505 }
2506
2507 int
2508 i915_gem_execbuffer(struct drm_device *dev, void *data,
2509                     struct drm_file *file_priv)
2510 {
2511         drm_i915_private_t *dev_priv = dev->dev_private;
2512         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
2513         struct drm_i915_gem_execbuffer *args = data;
2514         struct drm_i915_gem_exec_object *exec_list = NULL;
2515         struct drm_gem_object **object_list = NULL;
2516         struct drm_gem_object *batch_obj;
2517         struct drm_i915_gem_object *obj_priv;
2518         int ret, i, pinned = 0;
2519         uint64_t exec_offset;
2520         uint32_t seqno, flush_domains;
2521         int pin_tries;
2522
2523 #if WATCH_EXEC
2524         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
2525                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
2526 #endif
2527
2528         if (args->buffer_count < 1) {
2529                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
2530                 return -EINVAL;
2531         }
2532         /* Copy in the exec list from userland */
2533         exec_list = drm_calloc(sizeof(*exec_list), args->buffer_count,
2534                                DRM_MEM_DRIVER);
2535         object_list = drm_calloc(sizeof(*object_list), args->buffer_count,
2536                                  DRM_MEM_DRIVER);
2537         if (exec_list == NULL || object_list == NULL) {
2538                 DRM_ERROR("Failed to allocate exec or object list "
2539                           "for %d buffers\n",
2540                           args->buffer_count);
2541                 ret = -ENOMEM;
2542                 goto pre_mutex_err;
2543         }
2544         ret = copy_from_user(exec_list,
2545                              (struct drm_i915_relocation_entry __user *)
2546                              (uintptr_t) args->buffers_ptr,
2547                              sizeof(*exec_list) * args->buffer_count);
2548         if (ret != 0) {
2549                 DRM_ERROR("copy %d exec entries failed %d\n",
2550                           args->buffer_count, ret);
2551                 goto pre_mutex_err;
2552         }
2553
2554         mutex_lock(&dev->struct_mutex);
2555
2556         i915_verify_inactive(dev, __FILE__, __LINE__);
2557
2558         if (dev_priv->mm.wedged) {
2559                 DRM_ERROR("Execbuf while wedged\n");
2560                 mutex_unlock(&dev->struct_mutex);
2561                 ret = -EIO;
2562                 goto pre_mutex_err;
2563         }
2564
2565         if (dev_priv->mm.suspended) {
2566                 DRM_ERROR("Execbuf while VT-switched.\n");
2567                 mutex_unlock(&dev->struct_mutex);
2568                 ret = -EBUSY;
2569                 goto pre_mutex_err;
2570         }
2571
2572         /* Look up object handles */
2573         for (i = 0; i < args->buffer_count; i++) {
2574                 object_list[i] = drm_gem_object_lookup(dev, file_priv,
2575                                                        exec_list[i].handle);
2576                 if (object_list[i] == NULL) {
2577                         DRM_ERROR("Invalid object handle %d at index %d\n",
2578                                    exec_list[i].handle, i);
2579                         ret = -EBADF;
2580                         goto err;
2581                 }
2582
2583                 obj_priv = object_list[i]->driver_private;
2584                 if (obj_priv->in_execbuffer) {
2585                         DRM_ERROR("Object %p appears more than once in object list\n",
2586                                    object_list[i]);
2587                         ret = -EBADF;
2588                         goto err;
2589                 }
2590                 obj_priv->in_execbuffer = true;
2591         }
2592
2593         /* Pin and relocate */
2594         for (pin_tries = 0; ; pin_tries++) {
2595                 ret = 0;
2596                 for (i = 0; i < args->buffer_count; i++) {
2597                         object_list[i]->pending_read_domains = 0;
2598                         object_list[i]->pending_write_domain = 0;
2599                         ret = i915_gem_object_pin_and_relocate(object_list[i],
2600                                                                file_priv,
2601                                                                &exec_list[i]);
2602                         if (ret)
2603                                 break;
2604                         pinned = i + 1;
2605                 }
2606                 /* success */
2607                 if (ret == 0)
2608                         break;
2609
2610                 /* error other than GTT full, or we've already tried again */
2611                 if (ret != -ENOMEM || pin_tries >= 1) {
2612                         if (ret != -ERESTARTSYS)
2613                                 DRM_ERROR("Failed to pin buffers %d\n", ret);
2614                         goto err;
2615                 }
2616
2617                 /* unpin all of our buffers */
2618                 for (i = 0; i < pinned; i++)
2619                         i915_gem_object_unpin(object_list[i]);
2620                 pinned = 0;
2621
2622                 /* evict everyone we can from the aperture */
2623                 ret = i915_gem_evict_everything(dev);
2624                 if (ret)
2625                         goto err;
2626         }
2627
2628         /* Set the pending read domains for the batch buffer to COMMAND */
2629         batch_obj = object_list[args->buffer_count-1];
2630         batch_obj->pending_read_domains = I915_GEM_DOMAIN_COMMAND;
2631         batch_obj->pending_write_domain = 0;
2632
2633         i915_verify_inactive(dev, __FILE__, __LINE__);
2634
2635         /* Zero the global flush/invalidate flags. These
2636          * will be modified as new domains are computed
2637          * for each object
2638          */
2639         dev->invalidate_domains = 0;
2640         dev->flush_domains = 0;
2641
2642         for (i = 0; i < args->buffer_count; i++) {
2643                 struct drm_gem_object *obj = object_list[i];
2644
2645                 /* Compute new gpu domains and update invalidate/flush */
2646                 i915_gem_object_set_to_gpu_domain(obj);
2647         }
2648
2649         i915_verify_inactive(dev, __FILE__, __LINE__);
2650
2651         if (dev->invalidate_domains | dev->flush_domains) {
2652 #if WATCH_EXEC
2653                 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
2654                           __func__,
2655                          dev->invalidate_domains,
2656                          dev->flush_domains);
2657 #endif
2658                 i915_gem_flush(dev,
2659                                dev->invalidate_domains,
2660                                dev->flush_domains);
2661                 if (dev->flush_domains)
2662                         (void)i915_add_request(dev, dev->flush_domains);
2663         }
2664
2665         for (i = 0; i < args->buffer_count; i++) {
2666                 struct drm_gem_object *obj = object_list[i];
2667
2668                 obj->write_domain = obj->pending_write_domain;
2669         }
2670
2671         i915_verify_inactive(dev, __FILE__, __LINE__);
2672
2673 #if WATCH_COHERENCY
2674         for (i = 0; i < args->buffer_count; i++) {
2675                 i915_gem_object_check_coherency(object_list[i],
2676                                                 exec_list[i].handle);
2677         }
2678 #endif
2679
2680         exec_offset = exec_list[args->buffer_count - 1].offset;
2681
2682 #if WATCH_EXEC
2683         i915_gem_dump_object(object_list[args->buffer_count - 1],
2684                               args->batch_len,
2685                               __func__,
2686                               ~0);
2687 #endif
2688
2689         /* Exec the batchbuffer */
2690         ret = i915_dispatch_gem_execbuffer(dev, args, exec_offset);
2691         if (ret) {
2692                 DRM_ERROR("dispatch failed %d\n", ret);
2693                 goto err;
2694         }
2695
2696         /*
2697          * Ensure that the commands in the batch buffer are
2698          * finished before the interrupt fires
2699          */
2700         flush_domains = i915_retire_commands(dev);
2701
2702         i915_verify_inactive(dev, __FILE__, __LINE__);
2703
2704         /*
2705          * Get a seqno representing the execution of the current buffer,
2706          * which we can wait on.  We would like to mitigate these interrupts,
2707          * likely by only creating seqnos occasionally (so that we have
2708          * *some* interrupts representing completion of buffers that we can
2709          * wait on when trying to clear up gtt space).
2710          */
2711         seqno = i915_add_request(dev, flush_domains);
2712         BUG_ON(seqno == 0);
2713         i915_file_priv->mm.last_gem_seqno = seqno;
2714         for (i = 0; i < args->buffer_count; i++) {
2715                 struct drm_gem_object *obj = object_list[i];
2716
2717                 i915_gem_object_move_to_active(obj, seqno);
2718 #if WATCH_LRU
2719                 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
2720 #endif
2721         }
2722 #if WATCH_LRU
2723         i915_dump_lru(dev, __func__);
2724 #endif
2725
2726         i915_verify_inactive(dev, __FILE__, __LINE__);
2727
2728 err:
2729         for (i = 0; i < pinned; i++)
2730                 i915_gem_object_unpin(object_list[i]);
2731
2732         for (i = 0; i < args->buffer_count; i++) {
2733                 if (object_list[i]) {
2734                         obj_priv = object_list[i]->driver_private;
2735                         obj_priv->in_execbuffer = false;
2736                 }
2737                 drm_gem_object_unreference(object_list[i]);
2738         }
2739
2740         mutex_unlock(&dev->struct_mutex);
2741
2742         if (!ret) {
2743                 /* Copy the new buffer offsets back to the user's exec list. */
2744                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
2745                                    (uintptr_t) args->buffers_ptr,
2746                                    exec_list,
2747                                    sizeof(*exec_list) * args->buffer_count);
2748                 if (ret)
2749                         DRM_ERROR("failed to copy %d exec entries "
2750                                   "back to user (%d)\n",
2751                                   args->buffer_count, ret);
2752         }
2753
2754 pre_mutex_err:
2755         drm_free(object_list, sizeof(*object_list) * args->buffer_count,
2756                  DRM_MEM_DRIVER);
2757         drm_free(exec_list, sizeof(*exec_list) * args->buffer_count,
2758                  DRM_MEM_DRIVER);
2759
2760         return ret;
2761 }
2762
2763 int
2764 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
2765 {
2766         struct drm_device *dev = obj->dev;
2767         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2768         int ret;
2769
2770         i915_verify_inactive(dev, __FILE__, __LINE__);
2771         if (obj_priv->gtt_space == NULL) {
2772                 ret = i915_gem_object_bind_to_gtt(obj, alignment);
2773                 if (ret != 0) {
2774                         if (ret != -EBUSY && ret != -ERESTARTSYS)
2775                                 DRM_ERROR("Failure to bind: %d\n", ret);
2776                         return ret;
2777                 }
2778         }
2779         /*
2780          * Pre-965 chips need a fence register set up in order to
2781          * properly handle tiled surfaces.
2782          */
2783         if (!IS_I965G(dev) &&
2784             obj_priv->fence_reg == I915_FENCE_REG_NONE &&
2785             obj_priv->tiling_mode != I915_TILING_NONE) {
2786                 ret = i915_gem_object_get_fence_reg(obj, true);
2787                 if (ret != 0) {
2788                         if (ret != -EBUSY && ret != -ERESTARTSYS)
2789                                 DRM_ERROR("Failure to install fence: %d\n",
2790                                           ret);
2791                         return ret;
2792                 }
2793         }
2794         obj_priv->pin_count++;
2795
2796         /* If the object is not active and not pending a flush,
2797          * remove it from the inactive list
2798          */
2799         if (obj_priv->pin_count == 1) {
2800                 atomic_inc(&dev->pin_count);
2801                 atomic_add(obj->size, &dev->pin_memory);
2802                 if (!obj_priv->active &&
2803                     (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
2804                                            I915_GEM_DOMAIN_GTT)) == 0 &&
2805                     !list_empty(&obj_priv->list))
2806                         list_del_init(&obj_priv->list);
2807         }
2808         i915_verify_inactive(dev, __FILE__, __LINE__);
2809
2810         return 0;
2811 }
2812
2813 void
2814 i915_gem_object_unpin(struct drm_gem_object *obj)
2815 {
2816         struct drm_device *dev = obj->dev;
2817         drm_i915_private_t *dev_priv = dev->dev_private;
2818         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2819
2820         i915_verify_inactive(dev, __FILE__, __LINE__);
2821         obj_priv->pin_count--;
2822         BUG_ON(obj_priv->pin_count < 0);
2823         BUG_ON(obj_priv->gtt_space == NULL);
2824
2825         /* If the object is no longer pinned, and is
2826          * neither active nor being flushed, then stick it on
2827          * the inactive list
2828          */
2829         if (obj_priv->pin_count == 0) {
2830                 if (!obj_priv->active &&
2831                     (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
2832                                            I915_GEM_DOMAIN_GTT)) == 0)
2833                         list_move_tail(&obj_priv->list,
2834                                        &dev_priv->mm.inactive_list);
2835                 atomic_dec(&dev->pin_count);
2836                 atomic_sub(obj->size, &dev->pin_memory);
2837         }
2838         i915_verify_inactive(dev, __FILE__, __LINE__);
2839 }
2840
2841 int
2842 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2843                    struct drm_file *file_priv)
2844 {
2845         struct drm_i915_gem_pin *args = data;
2846         struct drm_gem_object *obj;
2847         struct drm_i915_gem_object *obj_priv;
2848         int ret;
2849
2850         mutex_lock(&dev->struct_mutex);
2851
2852         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2853         if (obj == NULL) {
2854                 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
2855                           args->handle);
2856                 mutex_unlock(&dev->struct_mutex);
2857                 return -EBADF;
2858         }
2859         obj_priv = obj->driver_private;
2860
2861         if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
2862                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
2863                           args->handle);
2864                 drm_gem_object_unreference(obj);
2865                 mutex_unlock(&dev->struct_mutex);
2866                 return -EINVAL;
2867         }
2868
2869         obj_priv->user_pin_count++;
2870         obj_priv->pin_filp = file_priv;
2871         if (obj_priv->user_pin_count == 1) {
2872                 ret = i915_gem_object_pin(obj, args->alignment);
2873                 if (ret != 0) {
2874                         drm_gem_object_unreference(obj);
2875                         mutex_unlock(&dev->struct_mutex);
2876                         return ret;
2877                 }
2878         }
2879
2880         /* XXX - flush the CPU caches for pinned objects
2881          * as the X server doesn't manage domains yet
2882          */
2883         i915_gem_object_flush_cpu_write_domain(obj);
2884         args->offset = obj_priv->gtt_offset;
2885         drm_gem_object_unreference(obj);
2886         mutex_unlock(&dev->struct_mutex);
2887
2888         return 0;
2889 }
2890
2891 int
2892 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2893                      struct drm_file *file_priv)
2894 {
2895         struct drm_i915_gem_pin *args = data;
2896         struct drm_gem_object *obj;
2897         struct drm_i915_gem_object *obj_priv;
2898
2899         mutex_lock(&dev->struct_mutex);
2900
2901         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2902         if (obj == NULL) {
2903                 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
2904                           args->handle);
2905                 mutex_unlock(&dev->struct_mutex);
2906                 return -EBADF;
2907         }
2908
2909         obj_priv = obj->driver_private;
2910         if (obj_priv->pin_filp != file_priv) {
2911                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
2912                           args->handle);
2913                 drm_gem_object_unreference(obj);
2914                 mutex_unlock(&dev->struct_mutex);
2915                 return -EINVAL;
2916         }
2917         obj_priv->user_pin_count--;
2918         if (obj_priv->user_pin_count == 0) {
2919                 obj_priv->pin_filp = NULL;
2920                 i915_gem_object_unpin(obj);
2921         }
2922
2923         drm_gem_object_unreference(obj);
2924         mutex_unlock(&dev->struct_mutex);
2925         return 0;
2926 }
2927
2928 int
2929 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2930                     struct drm_file *file_priv)
2931 {
2932         struct drm_i915_gem_busy *args = data;
2933         struct drm_gem_object *obj;
2934         struct drm_i915_gem_object *obj_priv;
2935
2936         mutex_lock(&dev->struct_mutex);
2937         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2938         if (obj == NULL) {
2939                 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
2940                           args->handle);
2941                 mutex_unlock(&dev->struct_mutex);
2942                 return -EBADF;
2943         }
2944
2945         /* Update the active list for the hardware's current position.
2946          * Otherwise this only updates on a delayed timer or when irqs are
2947          * actually unmasked, and our working set ends up being larger than
2948          * required.
2949          */
2950         i915_gem_retire_requests(dev);
2951
2952         obj_priv = obj->driver_private;
2953         /* Don't count being on the flushing list against the object being
2954          * done.  Otherwise, a buffer left on the flushing list but not getting
2955          * flushed (because nobody's flushing that domain) won't ever return
2956          * unbusy and get reused by libdrm's bo cache.  The other expected
2957          * consumer of this interface, OpenGL's occlusion queries, also specs
2958          * that the objects get unbusy "eventually" without any interference.
2959          */
2960         args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
2961
2962         drm_gem_object_unreference(obj);
2963         mutex_unlock(&dev->struct_mutex);
2964         return 0;
2965 }
2966
2967 int
2968 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2969                         struct drm_file *file_priv)
2970 {
2971     return i915_gem_ring_throttle(dev, file_priv);
2972 }
2973
2974 int i915_gem_init_object(struct drm_gem_object *obj)
2975 {
2976         struct drm_i915_gem_object *obj_priv;
2977
2978         obj_priv = drm_calloc(1, sizeof(*obj_priv), DRM_MEM_DRIVER);
2979         if (obj_priv == NULL)
2980                 return -ENOMEM;
2981
2982         /*
2983          * We've just allocated pages from the kernel,
2984          * so they've just been written by the CPU with
2985          * zeros. They'll need to be clflushed before we
2986          * use them with the GPU.
2987          */
2988         obj->write_domain = I915_GEM_DOMAIN_CPU;
2989         obj->read_domains = I915_GEM_DOMAIN_CPU;
2990
2991         obj_priv->agp_type = AGP_USER_MEMORY;
2992
2993         obj->driver_private = obj_priv;
2994         obj_priv->obj = obj;
2995         obj_priv->fence_reg = I915_FENCE_REG_NONE;
2996         INIT_LIST_HEAD(&obj_priv->list);
2997
2998         return 0;
2999 }
3000
3001 void i915_gem_free_object(struct drm_gem_object *obj)
3002 {
3003         struct drm_device *dev = obj->dev;
3004         struct drm_i915_gem_object *obj_priv = obj->driver_private;
3005
3006         while (obj_priv->pin_count > 0)
3007                 i915_gem_object_unpin(obj);
3008
3009         if (obj_priv->phys_obj)
3010                 i915_gem_detach_phys_object(dev, obj);
3011
3012         i915_gem_object_unbind(obj);
3013
3014         i915_gem_free_mmap_offset(obj);
3015
3016         drm_free(obj_priv->page_cpu_valid, 1, DRM_MEM_DRIVER);
3017         drm_free(obj->driver_private, 1, DRM_MEM_DRIVER);
3018 }
3019
3020 /** Unbinds all objects that are on the given buffer list. */
3021 static int
3022 i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
3023 {
3024         struct drm_gem_object *obj;
3025         struct drm_i915_gem_object *obj_priv;
3026         int ret;
3027
3028         while (!list_empty(head)) {
3029                 obj_priv = list_first_entry(head,
3030                                             struct drm_i915_gem_object,
3031                                             list);
3032                 obj = obj_priv->obj;
3033
3034                 if (obj_priv->pin_count != 0) {
3035                         DRM_ERROR("Pinned object in unbind list\n");
3036                         mutex_unlock(&dev->struct_mutex);
3037                         return -EINVAL;
3038                 }
3039
3040                 ret = i915_gem_object_unbind(obj);
3041                 if (ret != 0) {
3042                         DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
3043                                   ret);
3044                         mutex_unlock(&dev->struct_mutex);
3045                         return ret;
3046                 }
3047         }
3048
3049
3050         return 0;
3051 }
3052
3053 int
3054 i915_gem_idle(struct drm_device *dev)
3055 {
3056         drm_i915_private_t *dev_priv = dev->dev_private;
3057         uint32_t seqno, cur_seqno, last_seqno;
3058         int stuck, ret;
3059
3060         mutex_lock(&dev->struct_mutex);
3061
3062         if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
3063                 mutex_unlock(&dev->struct_mutex);
3064                 return 0;
3065         }
3066
3067         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
3068          * We need to replace this with a semaphore, or something.
3069          */
3070         dev_priv->mm.suspended = 1;
3071
3072         /* Cancel the retire work handler, wait for it to finish if running
3073          */
3074         mutex_unlock(&dev->struct_mutex);
3075         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3076         mutex_lock(&dev->struct_mutex);
3077
3078         i915_kernel_lost_context(dev);
3079
3080         /* Flush the GPU along with all non-CPU write domains
3081          */
3082         i915_gem_flush(dev, ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT),
3083                        ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
3084         seqno = i915_add_request(dev, ~I915_GEM_DOMAIN_CPU);
3085
3086         if (seqno == 0) {
3087                 mutex_unlock(&dev->struct_mutex);
3088                 return -ENOMEM;
3089         }
3090
3091         dev_priv->mm.waiting_gem_seqno = seqno;
3092         last_seqno = 0;
3093         stuck = 0;
3094         for (;;) {
3095                 cur_seqno = i915_get_gem_seqno(dev);
3096                 if (i915_seqno_passed(cur_seqno, seqno))
3097                         break;
3098                 if (last_seqno == cur_seqno) {
3099                         if (stuck++ > 100) {
3100                                 DRM_ERROR("hardware wedged\n");
3101                                 dev_priv->mm.wedged = 1;
3102                                 DRM_WAKEUP(&dev_priv->irq_queue);
3103                                 break;
3104                         }
3105                 }
3106                 msleep(10);
3107                 last_seqno = cur_seqno;
3108         }
3109         dev_priv->mm.waiting_gem_seqno = 0;
3110
3111         i915_gem_retire_requests(dev);
3112
3113         if (!dev_priv->mm.wedged) {
3114                 /* Active and flushing should now be empty as we've
3115                  * waited for a sequence higher than any pending execbuffer
3116                  */
3117                 WARN_ON(!list_empty(&dev_priv->mm.active_list));
3118                 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
3119                 /* Request should now be empty as we've also waited
3120                  * for the last request in the list
3121                  */
3122                 WARN_ON(!list_empty(&dev_priv->mm.request_list));
3123         }
3124
3125         /* Empty the active and flushing lists to inactive.  If there's
3126          * anything left at this point, it means that we're wedged and
3127          * nothing good's going to happen by leaving them there.  So strip
3128          * the GPU domains and just stuff them onto inactive.
3129          */
3130         while (!list_empty(&dev_priv->mm.active_list)) {
3131                 struct drm_i915_gem_object *obj_priv;
3132
3133                 obj_priv = list_first_entry(&dev_priv->mm.active_list,
3134                                             struct drm_i915_gem_object,
3135                                             list);
3136                 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3137                 i915_gem_object_move_to_inactive(obj_priv->obj);
3138         }
3139
3140         while (!list_empty(&dev_priv->mm.flushing_list)) {
3141                 struct drm_i915_gem_object *obj_priv;
3142
3143                 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
3144                                             struct drm_i915_gem_object,
3145                                             list);
3146                 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3147                 i915_gem_object_move_to_inactive(obj_priv->obj);
3148         }
3149
3150
3151         /* Move all inactive buffers out of the GTT. */
3152         ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
3153         WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
3154         if (ret) {
3155                 mutex_unlock(&dev->struct_mutex);
3156                 return ret;
3157         }
3158
3159         i915_gem_cleanup_ringbuffer(dev);
3160         mutex_unlock(&dev->struct_mutex);
3161
3162         return 0;
3163 }
3164
3165 static int
3166 i915_gem_init_hws(struct drm_device *dev)
3167 {
3168         drm_i915_private_t *dev_priv = dev->dev_private;
3169         struct drm_gem_object *obj;
3170         struct drm_i915_gem_object *obj_priv;
3171         int ret;
3172
3173         /* If we need a physical address for the status page, it's already
3174          * initialized at driver load time.
3175          */
3176         if (!I915_NEED_GFX_HWS(dev))
3177                 return 0;
3178
3179         obj = drm_gem_object_alloc(dev, 4096);
3180         if (obj == NULL) {
3181                 DRM_ERROR("Failed to allocate status page\n");
3182                 return -ENOMEM;
3183         }
3184         obj_priv = obj->driver_private;
3185         obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
3186
3187         ret = i915_gem_object_pin(obj, 4096);
3188         if (ret != 0) {
3189                 drm_gem_object_unreference(obj);
3190                 return ret;
3191         }
3192
3193         dev_priv->status_gfx_addr = obj_priv->gtt_offset;
3194
3195         dev_priv->hw_status_page = kmap(obj_priv->page_list[0]);
3196         if (dev_priv->hw_status_page == NULL) {
3197                 DRM_ERROR("Failed to map status page.\n");
3198                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
3199                 i915_gem_object_unpin(obj);
3200                 drm_gem_object_unreference(obj);
3201                 return -EINVAL;
3202         }
3203         dev_priv->hws_obj = obj;
3204         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
3205         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
3206         I915_READ(HWS_PGA); /* posting read */
3207         DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
3208
3209         return 0;
3210 }
3211
3212 static void
3213 i915_gem_cleanup_hws(struct drm_device *dev)
3214 {
3215         drm_i915_private_t *dev_priv = dev->dev_private;
3216         struct drm_gem_object *obj;
3217         struct drm_i915_gem_object *obj_priv;
3218
3219         if (dev_priv->hws_obj == NULL)
3220                 return;
3221
3222         obj = dev_priv->hws_obj;
3223         obj_priv = obj->driver_private;
3224
3225         kunmap(obj_priv->page_list[0]);
3226         i915_gem_object_unpin(obj);
3227         drm_gem_object_unreference(obj);
3228         dev_priv->hws_obj = NULL;
3229
3230         memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
3231         dev_priv->hw_status_page = NULL;
3232
3233         /* Write high address into HWS_PGA when disabling. */
3234         I915_WRITE(HWS_PGA, 0x1ffff000);
3235 }
3236
3237 int
3238 i915_gem_init_ringbuffer(struct drm_device *dev)
3239 {
3240         drm_i915_private_t *dev_priv = dev->dev_private;
3241         struct drm_gem_object *obj;
3242         struct drm_i915_gem_object *obj_priv;
3243         drm_i915_ring_buffer_t *ring = &dev_priv->ring;
3244         int ret;
3245         u32 head;
3246
3247         ret = i915_gem_init_hws(dev);
3248         if (ret != 0)
3249                 return ret;
3250
3251         obj = drm_gem_object_alloc(dev, 128 * 1024);
3252         if (obj == NULL) {
3253                 DRM_ERROR("Failed to allocate ringbuffer\n");
3254                 i915_gem_cleanup_hws(dev);
3255                 return -ENOMEM;
3256         }
3257         obj_priv = obj->driver_private;
3258
3259         ret = i915_gem_object_pin(obj, 4096);
3260         if (ret != 0) {
3261                 drm_gem_object_unreference(obj);
3262                 i915_gem_cleanup_hws(dev);
3263                 return ret;
3264         }
3265
3266         /* Set up the kernel mapping for the ring. */
3267         ring->Size = obj->size;
3268         ring->tail_mask = obj->size - 1;
3269
3270         ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
3271         ring->map.size = obj->size;
3272         ring->map.type = 0;
3273         ring->map.flags = 0;
3274         ring->map.mtrr = 0;
3275
3276         drm_core_ioremap_wc(&ring->map, dev);
3277         if (ring->map.handle == NULL) {
3278                 DRM_ERROR("Failed to map ringbuffer.\n");
3279                 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
3280                 i915_gem_object_unpin(obj);
3281                 drm_gem_object_unreference(obj);
3282                 i915_gem_cleanup_hws(dev);
3283                 return -EINVAL;
3284         }
3285         ring->ring_obj = obj;
3286         ring->virtual_start = ring->map.handle;
3287
3288         /* Stop the ring if it's running. */
3289         I915_WRITE(PRB0_CTL, 0);
3290         I915_WRITE(PRB0_TAIL, 0);
3291         I915_WRITE(PRB0_HEAD, 0);
3292
3293         /* Initialize the ring. */
3294         I915_WRITE(PRB0_START, obj_priv->gtt_offset);
3295         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
3296
3297         /* G45 ring initialization fails to reset head to zero */
3298         if (head != 0) {
3299                 DRM_ERROR("Ring head not reset to zero "
3300                           "ctl %08x head %08x tail %08x start %08x\n",
3301                           I915_READ(PRB0_CTL),
3302                           I915_READ(PRB0_HEAD),
3303                           I915_READ(PRB0_TAIL),
3304                           I915_READ(PRB0_START));
3305                 I915_WRITE(PRB0_HEAD, 0);
3306
3307                 DRM_ERROR("Ring head forced to zero "
3308                           "ctl %08x head %08x tail %08x start %08x\n",
3309                           I915_READ(PRB0_CTL),
3310                           I915_READ(PRB0_HEAD),
3311                           I915_READ(PRB0_TAIL),
3312                           I915_READ(PRB0_START));
3313         }
3314
3315         I915_WRITE(PRB0_CTL,
3316                    ((obj->size - 4096) & RING_NR_PAGES) |
3317                    RING_NO_REPORT |
3318                    RING_VALID);
3319
3320         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
3321
3322         /* If the head is still not zero, the ring is dead */
3323         if (head != 0) {
3324                 DRM_ERROR("Ring initialization failed "
3325                           "ctl %08x head %08x tail %08x start %08x\n",
3326                           I915_READ(PRB0_CTL),
3327                           I915_READ(PRB0_HEAD),
3328                           I915_READ(PRB0_TAIL),
3329                           I915_READ(PRB0_START));
3330                 return -EIO;
3331         }
3332
3333         /* Update our cache of the ring state */
3334         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3335                 i915_kernel_lost_context(dev);
3336         else {
3337                 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
3338                 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
3339                 ring->space = ring->head - (ring->tail + 8);
3340                 if (ring->space < 0)
3341                         ring->space += ring->Size;
3342         }
3343
3344         return 0;
3345 }
3346
3347 void
3348 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3349 {
3350         drm_i915_private_t *dev_priv = dev->dev_private;
3351
3352         if (dev_priv->ring.ring_obj == NULL)
3353                 return;
3354
3355         drm_core_ioremapfree(&dev_priv->ring.map, dev);
3356
3357         i915_gem_object_unpin(dev_priv->ring.ring_obj);
3358         drm_gem_object_unreference(dev_priv->ring.ring_obj);
3359         dev_priv->ring.ring_obj = NULL;
3360         memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
3361
3362         i915_gem_cleanup_hws(dev);
3363 }
3364
3365 int
3366 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3367                        struct drm_file *file_priv)
3368 {
3369         drm_i915_private_t *dev_priv = dev->dev_private;
3370         int ret;
3371
3372         if (drm_core_check_feature(dev, DRIVER_MODESET))
3373                 return 0;
3374
3375         if (dev_priv->mm.wedged) {
3376                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3377                 dev_priv->mm.wedged = 0;
3378         }
3379
3380         mutex_lock(&dev->struct_mutex);
3381         dev_priv->mm.suspended = 0;
3382
3383         ret = i915_gem_init_ringbuffer(dev);
3384         if (ret != 0)
3385                 return ret;
3386
3387         BUG_ON(!list_empty(&dev_priv->mm.active_list));
3388         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3389         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3390         BUG_ON(!list_empty(&dev_priv->mm.request_list));
3391         mutex_unlock(&dev->struct_mutex);
3392
3393         drm_irq_install(dev);
3394
3395         return 0;
3396 }
3397
3398 int
3399 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3400                        struct drm_file *file_priv)
3401 {
3402         int ret;
3403
3404         if (drm_core_check_feature(dev, DRIVER_MODESET))
3405                 return 0;
3406
3407         ret = i915_gem_idle(dev);
3408         drm_irq_uninstall(dev);
3409
3410         return ret;
3411 }
3412
3413 void
3414 i915_gem_lastclose(struct drm_device *dev)
3415 {
3416         int ret;
3417
3418         if (drm_core_check_feature(dev, DRIVER_MODESET))
3419                 return;
3420
3421         ret = i915_gem_idle(dev);
3422         if (ret)
3423                 DRM_ERROR("failed to idle hardware: %d\n", ret);
3424 }
3425
3426 void
3427 i915_gem_load(struct drm_device *dev)
3428 {
3429         drm_i915_private_t *dev_priv = dev->dev_private;
3430
3431         INIT_LIST_HEAD(&dev_priv->mm.active_list);
3432         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3433         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3434         INIT_LIST_HEAD(&dev_priv->mm.request_list);
3435         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3436                           i915_gem_retire_work_handler);
3437         dev_priv->mm.next_gem_seqno = 1;
3438
3439         /* Old X drivers will take 0-2 for front, back, depth buffers */
3440         dev_priv->fence_reg_start = 3;
3441
3442         if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3443                 dev_priv->num_fence_regs = 16;
3444         else
3445                 dev_priv->num_fence_regs = 8;
3446
3447         i915_gem_detect_bit_6_swizzle(dev);
3448 }
3449
3450 /*
3451  * Create a physically contiguous memory object for this object
3452  * e.g. for cursor + overlay regs
3453  */
3454 int i915_gem_init_phys_object(struct drm_device *dev,
3455                               int id, int size)
3456 {
3457         drm_i915_private_t *dev_priv = dev->dev_private;
3458         struct drm_i915_gem_phys_object *phys_obj;
3459         int ret;
3460
3461         if (dev_priv->mm.phys_objs[id - 1] || !size)
3462                 return 0;
3463
3464         phys_obj = drm_calloc(1, sizeof(struct drm_i915_gem_phys_object), DRM_MEM_DRIVER);
3465         if (!phys_obj)
3466                 return -ENOMEM;
3467
3468         phys_obj->id = id;
3469
3470         phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
3471         if (!phys_obj->handle) {
3472                 ret = -ENOMEM;
3473                 goto kfree_obj;
3474         }
3475 #ifdef CONFIG_X86
3476         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3477 #endif
3478
3479         dev_priv->mm.phys_objs[id - 1] = phys_obj;
3480
3481         return 0;
3482 kfree_obj:
3483         drm_free(phys_obj, sizeof(struct drm_i915_gem_phys_object), DRM_MEM_DRIVER);
3484         return ret;
3485 }
3486
3487 void i915_gem_free_phys_object(struct drm_device *dev, int id)
3488 {
3489         drm_i915_private_t *dev_priv = dev->dev_private;
3490         struct drm_i915_gem_phys_object *phys_obj;
3491
3492         if (!dev_priv->mm.phys_objs[id - 1])
3493                 return;
3494
3495         phys_obj = dev_priv->mm.phys_objs[id - 1];
3496         if (phys_obj->cur_obj) {
3497                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3498         }
3499
3500 #ifdef CONFIG_X86
3501         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3502 #endif
3503         drm_pci_free(dev, phys_obj->handle);
3504         kfree(phys_obj);
3505         dev_priv->mm.phys_objs[id - 1] = NULL;
3506 }
3507
3508 void i915_gem_free_all_phys_object(struct drm_device *dev)
3509 {
3510         int i;
3511
3512         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3513                 i915_gem_free_phys_object(dev, i);
3514 }
3515
3516 void i915_gem_detach_phys_object(struct drm_device *dev,
3517                                  struct drm_gem_object *obj)
3518 {
3519         struct drm_i915_gem_object *obj_priv;
3520         int i;
3521         int ret;
3522         int page_count;
3523
3524         obj_priv = obj->driver_private;
3525         if (!obj_priv->phys_obj)
3526                 return;
3527
3528         ret = i915_gem_object_get_page_list(obj);
3529         if (ret)
3530                 goto out;
3531
3532         page_count = obj->size / PAGE_SIZE;
3533
3534         for (i = 0; i < page_count; i++) {
3535                 char *dst = kmap_atomic(obj_priv->page_list[i], KM_USER0);
3536                 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
3537
3538                 memcpy(dst, src, PAGE_SIZE);
3539                 kunmap_atomic(dst, KM_USER0);
3540         }
3541         drm_clflush_pages(obj_priv->page_list, page_count);
3542         drm_agp_chipset_flush(dev);
3543 out:
3544         obj_priv->phys_obj->cur_obj = NULL;
3545         obj_priv->phys_obj = NULL;
3546 }
3547
3548 int
3549 i915_gem_attach_phys_object(struct drm_device *dev,
3550                             struct drm_gem_object *obj, int id)
3551 {
3552         drm_i915_private_t *dev_priv = dev->dev_private;
3553         struct drm_i915_gem_object *obj_priv;
3554         int ret = 0;
3555         int page_count;
3556         int i;
3557
3558         if (id > I915_MAX_PHYS_OBJECT)
3559                 return -EINVAL;
3560
3561         obj_priv = obj->driver_private;
3562
3563         if (obj_priv->phys_obj) {
3564                 if (obj_priv->phys_obj->id == id)
3565                         return 0;
3566                 i915_gem_detach_phys_object(dev, obj);
3567         }
3568
3569
3570         /* create a new object */
3571         if (!dev_priv->mm.phys_objs[id - 1]) {
3572                 ret = i915_gem_init_phys_object(dev, id,
3573                                                 obj->size);
3574                 if (ret) {
3575                         DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
3576                         goto out;
3577                 }
3578         }
3579
3580         /* bind to the object */
3581         obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
3582         obj_priv->phys_obj->cur_obj = obj;
3583
3584         ret = i915_gem_object_get_page_list(obj);
3585         if (ret) {
3586                 DRM_ERROR("failed to get page list\n");
3587                 goto out;
3588         }
3589
3590         page_count = obj->size / PAGE_SIZE;
3591
3592         for (i = 0; i < page_count; i++) {
3593                 char *src = kmap_atomic(obj_priv->page_list[i], KM_USER0);
3594                 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
3595
3596                 memcpy(dst, src, PAGE_SIZE);
3597                 kunmap_atomic(src, KM_USER0);
3598         }
3599
3600         return 0;
3601 out:
3602         return ret;
3603 }
3604
3605 static int
3606 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
3607                      struct drm_i915_gem_pwrite *args,
3608                      struct drm_file *file_priv)
3609 {
3610         struct drm_i915_gem_object *obj_priv = obj->driver_private;
3611         void *obj_addr;
3612         int ret;
3613         char __user *user_data;
3614
3615         user_data = (char __user *) (uintptr_t) args->data_ptr;
3616         obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
3617
3618         DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size);
3619         ret = copy_from_user(obj_addr, user_data, args->size);
3620         if (ret)
3621                 return -EFAULT;
3622
3623         drm_agp_chipset_flush(dev);
3624         return 0;
3625 }