drm/i915: execbuf2 support
[linux-2.6.git] / drivers / gpu / drm / i915 / i915_gem.c
1 /*
2  * Copyright © 2008 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Eric Anholt <eric@anholt.net>
25  *
26  */
27
28 #include "drmP.h"
29 #include "drm.h"
30 #include "i915_drm.h"
31 #include "i915_drv.h"
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/swap.h>
35 #include <linux/pci.h>
36
37 #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
38
39 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
42 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
43                                              int write);
44 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
45                                                      uint64_t offset,
46                                                      uint64_t size);
47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
48 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
50                                            unsigned alignment);
51 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
52 static int i915_gem_evict_something(struct drm_device *dev, int min_size);
53 static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
54 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
55                                 struct drm_i915_gem_pwrite *args,
56                                 struct drm_file *file_priv);
57
58 static LIST_HEAD(shrink_list);
59 static DEFINE_SPINLOCK(shrink_list_lock);
60
61 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
62                      unsigned long end)
63 {
64         drm_i915_private_t *dev_priv = dev->dev_private;
65
66         if (start >= end ||
67             (start & (PAGE_SIZE - 1)) != 0 ||
68             (end & (PAGE_SIZE - 1)) != 0) {
69                 return -EINVAL;
70         }
71
72         drm_mm_init(&dev_priv->mm.gtt_space, start,
73                     end - start);
74
75         dev->gtt_total = (uint32_t) (end - start);
76
77         return 0;
78 }
79
80 int
81 i915_gem_init_ioctl(struct drm_device *dev, void *data,
82                     struct drm_file *file_priv)
83 {
84         struct drm_i915_gem_init *args = data;
85         int ret;
86
87         mutex_lock(&dev->struct_mutex);
88         ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
89         mutex_unlock(&dev->struct_mutex);
90
91         return ret;
92 }
93
94 int
95 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
96                             struct drm_file *file_priv)
97 {
98         struct drm_i915_gem_get_aperture *args = data;
99
100         if (!(dev->driver->driver_features & DRIVER_GEM))
101                 return -ENODEV;
102
103         args->aper_size = dev->gtt_total;
104         args->aper_available_size = (args->aper_size -
105                                      atomic_read(&dev->pin_memory));
106
107         return 0;
108 }
109
110
111 /**
112  * Creates a new mm object and returns a handle to it.
113  */
114 int
115 i915_gem_create_ioctl(struct drm_device *dev, void *data,
116                       struct drm_file *file_priv)
117 {
118         struct drm_i915_gem_create *args = data;
119         struct drm_gem_object *obj;
120         int ret;
121         u32 handle;
122
123         args->size = roundup(args->size, PAGE_SIZE);
124
125         /* Allocate the new object */
126         obj = drm_gem_object_alloc(dev, args->size);
127         if (obj == NULL)
128                 return -ENOMEM;
129
130         ret = drm_gem_handle_create(file_priv, obj, &handle);
131         mutex_lock(&dev->struct_mutex);
132         drm_gem_object_handle_unreference(obj);
133         mutex_unlock(&dev->struct_mutex);
134
135         if (ret)
136                 return ret;
137
138         args->handle = handle;
139
140         return 0;
141 }
142
143 static inline int
144 fast_shmem_read(struct page **pages,
145                 loff_t page_base, int page_offset,
146                 char __user *data,
147                 int length)
148 {
149         char __iomem *vaddr;
150         int unwritten;
151
152         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
153         if (vaddr == NULL)
154                 return -ENOMEM;
155         unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
156         kunmap_atomic(vaddr, KM_USER0);
157
158         if (unwritten)
159                 return -EFAULT;
160
161         return 0;
162 }
163
164 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
165 {
166         drm_i915_private_t *dev_priv = obj->dev->dev_private;
167         struct drm_i915_gem_object *obj_priv = obj->driver_private;
168
169         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
170                 obj_priv->tiling_mode != I915_TILING_NONE;
171 }
172
173 static inline int
174 slow_shmem_copy(struct page *dst_page,
175                 int dst_offset,
176                 struct page *src_page,
177                 int src_offset,
178                 int length)
179 {
180         char *dst_vaddr, *src_vaddr;
181
182         dst_vaddr = kmap_atomic(dst_page, KM_USER0);
183         if (dst_vaddr == NULL)
184                 return -ENOMEM;
185
186         src_vaddr = kmap_atomic(src_page, KM_USER1);
187         if (src_vaddr == NULL) {
188                 kunmap_atomic(dst_vaddr, KM_USER0);
189                 return -ENOMEM;
190         }
191
192         memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
193
194         kunmap_atomic(src_vaddr, KM_USER1);
195         kunmap_atomic(dst_vaddr, KM_USER0);
196
197         return 0;
198 }
199
200 static inline int
201 slow_shmem_bit17_copy(struct page *gpu_page,
202                       int gpu_offset,
203                       struct page *cpu_page,
204                       int cpu_offset,
205                       int length,
206                       int is_read)
207 {
208         char *gpu_vaddr, *cpu_vaddr;
209
210         /* Use the unswizzled path if this page isn't affected. */
211         if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
212                 if (is_read)
213                         return slow_shmem_copy(cpu_page, cpu_offset,
214                                                gpu_page, gpu_offset, length);
215                 else
216                         return slow_shmem_copy(gpu_page, gpu_offset,
217                                                cpu_page, cpu_offset, length);
218         }
219
220         gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
221         if (gpu_vaddr == NULL)
222                 return -ENOMEM;
223
224         cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
225         if (cpu_vaddr == NULL) {
226                 kunmap_atomic(gpu_vaddr, KM_USER0);
227                 return -ENOMEM;
228         }
229
230         /* Copy the data, XORing A6 with A17 (1). The user already knows he's
231          * XORing with the other bits (A9 for Y, A9 and A10 for X)
232          */
233         while (length > 0) {
234                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
235                 int this_length = min(cacheline_end - gpu_offset, length);
236                 int swizzled_gpu_offset = gpu_offset ^ 64;
237
238                 if (is_read) {
239                         memcpy(cpu_vaddr + cpu_offset,
240                                gpu_vaddr + swizzled_gpu_offset,
241                                this_length);
242                 } else {
243                         memcpy(gpu_vaddr + swizzled_gpu_offset,
244                                cpu_vaddr + cpu_offset,
245                                this_length);
246                 }
247                 cpu_offset += this_length;
248                 gpu_offset += this_length;
249                 length -= this_length;
250         }
251
252         kunmap_atomic(cpu_vaddr, KM_USER1);
253         kunmap_atomic(gpu_vaddr, KM_USER0);
254
255         return 0;
256 }
257
258 /**
259  * This is the fast shmem pread path, which attempts to copy_from_user directly
260  * from the backing pages of the object to the user's address space.  On a
261  * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
262  */
263 static int
264 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
265                           struct drm_i915_gem_pread *args,
266                           struct drm_file *file_priv)
267 {
268         struct drm_i915_gem_object *obj_priv = obj->driver_private;
269         ssize_t remain;
270         loff_t offset, page_base;
271         char __user *user_data;
272         int page_offset, page_length;
273         int ret;
274
275         user_data = (char __user *) (uintptr_t) args->data_ptr;
276         remain = args->size;
277
278         mutex_lock(&dev->struct_mutex);
279
280         ret = i915_gem_object_get_pages(obj);
281         if (ret != 0)
282                 goto fail_unlock;
283
284         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
285                                                         args->size);
286         if (ret != 0)
287                 goto fail_put_pages;
288
289         obj_priv = obj->driver_private;
290         offset = args->offset;
291
292         while (remain > 0) {
293                 /* Operation in this page
294                  *
295                  * page_base = page offset within aperture
296                  * page_offset = offset within page
297                  * page_length = bytes to copy for this page
298                  */
299                 page_base = (offset & ~(PAGE_SIZE-1));
300                 page_offset = offset & (PAGE_SIZE-1);
301                 page_length = remain;
302                 if ((page_offset + remain) > PAGE_SIZE)
303                         page_length = PAGE_SIZE - page_offset;
304
305                 ret = fast_shmem_read(obj_priv->pages,
306                                       page_base, page_offset,
307                                       user_data, page_length);
308                 if (ret)
309                         goto fail_put_pages;
310
311                 remain -= page_length;
312                 user_data += page_length;
313                 offset += page_length;
314         }
315
316 fail_put_pages:
317         i915_gem_object_put_pages(obj);
318 fail_unlock:
319         mutex_unlock(&dev->struct_mutex);
320
321         return ret;
322 }
323
324 static inline gfp_t
325 i915_gem_object_get_page_gfp_mask (struct drm_gem_object *obj)
326 {
327         return mapping_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping);
328 }
329
330 static inline void
331 i915_gem_object_set_page_gfp_mask (struct drm_gem_object *obj, gfp_t gfp)
332 {
333         mapping_set_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping, gfp);
334 }
335
336 static int
337 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
338 {
339         int ret;
340
341         ret = i915_gem_object_get_pages(obj);
342
343         /* If we've insufficient memory to map in the pages, attempt
344          * to make some space by throwing out some old buffers.
345          */
346         if (ret == -ENOMEM) {
347                 struct drm_device *dev = obj->dev;
348                 gfp_t gfp;
349
350                 ret = i915_gem_evict_something(dev, obj->size);
351                 if (ret)
352                         return ret;
353
354                 gfp = i915_gem_object_get_page_gfp_mask(obj);
355                 i915_gem_object_set_page_gfp_mask(obj, gfp & ~__GFP_NORETRY);
356                 ret = i915_gem_object_get_pages(obj);
357                 i915_gem_object_set_page_gfp_mask (obj, gfp);
358         }
359
360         return ret;
361 }
362
363 /**
364  * This is the fallback shmem pread path, which allocates temporary storage
365  * in kernel space to copy_to_user into outside of the struct_mutex, so we
366  * can copy out of the object's backing pages while holding the struct mutex
367  * and not take page faults.
368  */
369 static int
370 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
371                           struct drm_i915_gem_pread *args,
372                           struct drm_file *file_priv)
373 {
374         struct drm_i915_gem_object *obj_priv = obj->driver_private;
375         struct mm_struct *mm = current->mm;
376         struct page **user_pages;
377         ssize_t remain;
378         loff_t offset, pinned_pages, i;
379         loff_t first_data_page, last_data_page, num_pages;
380         int shmem_page_index, shmem_page_offset;
381         int data_page_index,  data_page_offset;
382         int page_length;
383         int ret;
384         uint64_t data_ptr = args->data_ptr;
385         int do_bit17_swizzling;
386
387         remain = args->size;
388
389         /* Pin the user pages containing the data.  We can't fault while
390          * holding the struct mutex, yet we want to hold it while
391          * dereferencing the user data.
392          */
393         first_data_page = data_ptr / PAGE_SIZE;
394         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
395         num_pages = last_data_page - first_data_page + 1;
396
397         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
398         if (user_pages == NULL)
399                 return -ENOMEM;
400
401         down_read(&mm->mmap_sem);
402         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
403                                       num_pages, 1, 0, user_pages, NULL);
404         up_read(&mm->mmap_sem);
405         if (pinned_pages < num_pages) {
406                 ret = -EFAULT;
407                 goto fail_put_user_pages;
408         }
409
410         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
411
412         mutex_lock(&dev->struct_mutex);
413
414         ret = i915_gem_object_get_pages_or_evict(obj);
415         if (ret)
416                 goto fail_unlock;
417
418         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
419                                                         args->size);
420         if (ret != 0)
421                 goto fail_put_pages;
422
423         obj_priv = obj->driver_private;
424         offset = args->offset;
425
426         while (remain > 0) {
427                 /* Operation in this page
428                  *
429                  * shmem_page_index = page number within shmem file
430                  * shmem_page_offset = offset within page in shmem file
431                  * data_page_index = page number in get_user_pages return
432                  * data_page_offset = offset with data_page_index page.
433                  * page_length = bytes to copy for this page
434                  */
435                 shmem_page_index = offset / PAGE_SIZE;
436                 shmem_page_offset = offset & ~PAGE_MASK;
437                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
438                 data_page_offset = data_ptr & ~PAGE_MASK;
439
440                 page_length = remain;
441                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
442                         page_length = PAGE_SIZE - shmem_page_offset;
443                 if ((data_page_offset + page_length) > PAGE_SIZE)
444                         page_length = PAGE_SIZE - data_page_offset;
445
446                 if (do_bit17_swizzling) {
447                         ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
448                                                     shmem_page_offset,
449                                                     user_pages[data_page_index],
450                                                     data_page_offset,
451                                                     page_length,
452                                                     1);
453                 } else {
454                         ret = slow_shmem_copy(user_pages[data_page_index],
455                                               data_page_offset,
456                                               obj_priv->pages[shmem_page_index],
457                                               shmem_page_offset,
458                                               page_length);
459                 }
460                 if (ret)
461                         goto fail_put_pages;
462
463                 remain -= page_length;
464                 data_ptr += page_length;
465                 offset += page_length;
466         }
467
468 fail_put_pages:
469         i915_gem_object_put_pages(obj);
470 fail_unlock:
471         mutex_unlock(&dev->struct_mutex);
472 fail_put_user_pages:
473         for (i = 0; i < pinned_pages; i++) {
474                 SetPageDirty(user_pages[i]);
475                 page_cache_release(user_pages[i]);
476         }
477         drm_free_large(user_pages);
478
479         return ret;
480 }
481
482 /**
483  * Reads data from the object referenced by handle.
484  *
485  * On error, the contents of *data are undefined.
486  */
487 int
488 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
489                      struct drm_file *file_priv)
490 {
491         struct drm_i915_gem_pread *args = data;
492         struct drm_gem_object *obj;
493         struct drm_i915_gem_object *obj_priv;
494         int ret;
495
496         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
497         if (obj == NULL)
498                 return -EBADF;
499         obj_priv = obj->driver_private;
500
501         /* Bounds check source.
502          *
503          * XXX: This could use review for overflow issues...
504          */
505         if (args->offset > obj->size || args->size > obj->size ||
506             args->offset + args->size > obj->size) {
507                 drm_gem_object_unreference(obj);
508                 return -EINVAL;
509         }
510
511         if (i915_gem_object_needs_bit17_swizzle(obj)) {
512                 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
513         } else {
514                 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
515                 if (ret != 0)
516                         ret = i915_gem_shmem_pread_slow(dev, obj, args,
517                                                         file_priv);
518         }
519
520         drm_gem_object_unreference(obj);
521
522         return ret;
523 }
524
525 /* This is the fast write path which cannot handle
526  * page faults in the source data
527  */
528
529 static inline int
530 fast_user_write(struct io_mapping *mapping,
531                 loff_t page_base, int page_offset,
532                 char __user *user_data,
533                 int length)
534 {
535         char *vaddr_atomic;
536         unsigned long unwritten;
537
538         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
539         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
540                                                       user_data, length);
541         io_mapping_unmap_atomic(vaddr_atomic);
542         if (unwritten)
543                 return -EFAULT;
544         return 0;
545 }
546
547 /* Here's the write path which can sleep for
548  * page faults
549  */
550
551 static inline int
552 slow_kernel_write(struct io_mapping *mapping,
553                   loff_t gtt_base, int gtt_offset,
554                   struct page *user_page, int user_offset,
555                   int length)
556 {
557         char *src_vaddr, *dst_vaddr;
558         unsigned long unwritten;
559
560         dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
561         src_vaddr = kmap_atomic(user_page, KM_USER1);
562         unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
563                                                       src_vaddr + user_offset,
564                                                       length);
565         kunmap_atomic(src_vaddr, KM_USER1);
566         io_mapping_unmap_atomic(dst_vaddr);
567         if (unwritten)
568                 return -EFAULT;
569         return 0;
570 }
571
572 static inline int
573 fast_shmem_write(struct page **pages,
574                  loff_t page_base, int page_offset,
575                  char __user *data,
576                  int length)
577 {
578         char __iomem *vaddr;
579         unsigned long unwritten;
580
581         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
582         if (vaddr == NULL)
583                 return -ENOMEM;
584         unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
585         kunmap_atomic(vaddr, KM_USER0);
586
587         if (unwritten)
588                 return -EFAULT;
589         return 0;
590 }
591
592 /**
593  * This is the fast pwrite path, where we copy the data directly from the
594  * user into the GTT, uncached.
595  */
596 static int
597 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
598                          struct drm_i915_gem_pwrite *args,
599                          struct drm_file *file_priv)
600 {
601         struct drm_i915_gem_object *obj_priv = obj->driver_private;
602         drm_i915_private_t *dev_priv = dev->dev_private;
603         ssize_t remain;
604         loff_t offset, page_base;
605         char __user *user_data;
606         int page_offset, page_length;
607         int ret;
608
609         user_data = (char __user *) (uintptr_t) args->data_ptr;
610         remain = args->size;
611         if (!access_ok(VERIFY_READ, user_data, remain))
612                 return -EFAULT;
613
614
615         mutex_lock(&dev->struct_mutex);
616         ret = i915_gem_object_pin(obj, 0);
617         if (ret) {
618                 mutex_unlock(&dev->struct_mutex);
619                 return ret;
620         }
621         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
622         if (ret)
623                 goto fail;
624
625         obj_priv = obj->driver_private;
626         offset = obj_priv->gtt_offset + args->offset;
627
628         while (remain > 0) {
629                 /* Operation in this page
630                  *
631                  * page_base = page offset within aperture
632                  * page_offset = offset within page
633                  * page_length = bytes to copy for this page
634                  */
635                 page_base = (offset & ~(PAGE_SIZE-1));
636                 page_offset = offset & (PAGE_SIZE-1);
637                 page_length = remain;
638                 if ((page_offset + remain) > PAGE_SIZE)
639                         page_length = PAGE_SIZE - page_offset;
640
641                 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
642                                        page_offset, user_data, page_length);
643
644                 /* If we get a fault while copying data, then (presumably) our
645                  * source page isn't available.  Return the error and we'll
646                  * retry in the slow path.
647                  */
648                 if (ret)
649                         goto fail;
650
651                 remain -= page_length;
652                 user_data += page_length;
653                 offset += page_length;
654         }
655
656 fail:
657         i915_gem_object_unpin(obj);
658         mutex_unlock(&dev->struct_mutex);
659
660         return ret;
661 }
662
663 /**
664  * This is the fallback GTT pwrite path, which uses get_user_pages to pin
665  * the memory and maps it using kmap_atomic for copying.
666  *
667  * This code resulted in x11perf -rgb10text consuming about 10% more CPU
668  * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
669  */
670 static int
671 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
672                          struct drm_i915_gem_pwrite *args,
673                          struct drm_file *file_priv)
674 {
675         struct drm_i915_gem_object *obj_priv = obj->driver_private;
676         drm_i915_private_t *dev_priv = dev->dev_private;
677         ssize_t remain;
678         loff_t gtt_page_base, offset;
679         loff_t first_data_page, last_data_page, num_pages;
680         loff_t pinned_pages, i;
681         struct page **user_pages;
682         struct mm_struct *mm = current->mm;
683         int gtt_page_offset, data_page_offset, data_page_index, page_length;
684         int ret;
685         uint64_t data_ptr = args->data_ptr;
686
687         remain = args->size;
688
689         /* Pin the user pages containing the data.  We can't fault while
690          * holding the struct mutex, and all of the pwrite implementations
691          * want to hold it while dereferencing the user data.
692          */
693         first_data_page = data_ptr / PAGE_SIZE;
694         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
695         num_pages = last_data_page - first_data_page + 1;
696
697         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
698         if (user_pages == NULL)
699                 return -ENOMEM;
700
701         down_read(&mm->mmap_sem);
702         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
703                                       num_pages, 0, 0, user_pages, NULL);
704         up_read(&mm->mmap_sem);
705         if (pinned_pages < num_pages) {
706                 ret = -EFAULT;
707                 goto out_unpin_pages;
708         }
709
710         mutex_lock(&dev->struct_mutex);
711         ret = i915_gem_object_pin(obj, 0);
712         if (ret)
713                 goto out_unlock;
714
715         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
716         if (ret)
717                 goto out_unpin_object;
718
719         obj_priv = obj->driver_private;
720         offset = obj_priv->gtt_offset + args->offset;
721
722         while (remain > 0) {
723                 /* Operation in this page
724                  *
725                  * gtt_page_base = page offset within aperture
726                  * gtt_page_offset = offset within page in aperture
727                  * data_page_index = page number in get_user_pages return
728                  * data_page_offset = offset with data_page_index page.
729                  * page_length = bytes to copy for this page
730                  */
731                 gtt_page_base = offset & PAGE_MASK;
732                 gtt_page_offset = offset & ~PAGE_MASK;
733                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
734                 data_page_offset = data_ptr & ~PAGE_MASK;
735
736                 page_length = remain;
737                 if ((gtt_page_offset + page_length) > PAGE_SIZE)
738                         page_length = PAGE_SIZE - gtt_page_offset;
739                 if ((data_page_offset + page_length) > PAGE_SIZE)
740                         page_length = PAGE_SIZE - data_page_offset;
741
742                 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
743                                         gtt_page_base, gtt_page_offset,
744                                         user_pages[data_page_index],
745                                         data_page_offset,
746                                         page_length);
747
748                 /* If we get a fault while copying data, then (presumably) our
749                  * source page isn't available.  Return the error and we'll
750                  * retry in the slow path.
751                  */
752                 if (ret)
753                         goto out_unpin_object;
754
755                 remain -= page_length;
756                 offset += page_length;
757                 data_ptr += page_length;
758         }
759
760 out_unpin_object:
761         i915_gem_object_unpin(obj);
762 out_unlock:
763         mutex_unlock(&dev->struct_mutex);
764 out_unpin_pages:
765         for (i = 0; i < pinned_pages; i++)
766                 page_cache_release(user_pages[i]);
767         drm_free_large(user_pages);
768
769         return ret;
770 }
771
772 /**
773  * This is the fast shmem pwrite path, which attempts to directly
774  * copy_from_user into the kmapped pages backing the object.
775  */
776 static int
777 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
778                            struct drm_i915_gem_pwrite *args,
779                            struct drm_file *file_priv)
780 {
781         struct drm_i915_gem_object *obj_priv = obj->driver_private;
782         ssize_t remain;
783         loff_t offset, page_base;
784         char __user *user_data;
785         int page_offset, page_length;
786         int ret;
787
788         user_data = (char __user *) (uintptr_t) args->data_ptr;
789         remain = args->size;
790
791         mutex_lock(&dev->struct_mutex);
792
793         ret = i915_gem_object_get_pages(obj);
794         if (ret != 0)
795                 goto fail_unlock;
796
797         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
798         if (ret != 0)
799                 goto fail_put_pages;
800
801         obj_priv = obj->driver_private;
802         offset = args->offset;
803         obj_priv->dirty = 1;
804
805         while (remain > 0) {
806                 /* Operation in this page
807                  *
808                  * page_base = page offset within aperture
809                  * page_offset = offset within page
810                  * page_length = bytes to copy for this page
811                  */
812                 page_base = (offset & ~(PAGE_SIZE-1));
813                 page_offset = offset & (PAGE_SIZE-1);
814                 page_length = remain;
815                 if ((page_offset + remain) > PAGE_SIZE)
816                         page_length = PAGE_SIZE - page_offset;
817
818                 ret = fast_shmem_write(obj_priv->pages,
819                                        page_base, page_offset,
820                                        user_data, page_length);
821                 if (ret)
822                         goto fail_put_pages;
823
824                 remain -= page_length;
825                 user_data += page_length;
826                 offset += page_length;
827         }
828
829 fail_put_pages:
830         i915_gem_object_put_pages(obj);
831 fail_unlock:
832         mutex_unlock(&dev->struct_mutex);
833
834         return ret;
835 }
836
837 /**
838  * This is the fallback shmem pwrite path, which uses get_user_pages to pin
839  * the memory and maps it using kmap_atomic for copying.
840  *
841  * This avoids taking mmap_sem for faulting on the user's address while the
842  * struct_mutex is held.
843  */
844 static int
845 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
846                            struct drm_i915_gem_pwrite *args,
847                            struct drm_file *file_priv)
848 {
849         struct drm_i915_gem_object *obj_priv = obj->driver_private;
850         struct mm_struct *mm = current->mm;
851         struct page **user_pages;
852         ssize_t remain;
853         loff_t offset, pinned_pages, i;
854         loff_t first_data_page, last_data_page, num_pages;
855         int shmem_page_index, shmem_page_offset;
856         int data_page_index,  data_page_offset;
857         int page_length;
858         int ret;
859         uint64_t data_ptr = args->data_ptr;
860         int do_bit17_swizzling;
861
862         remain = args->size;
863
864         /* Pin the user pages containing the data.  We can't fault while
865          * holding the struct mutex, and all of the pwrite implementations
866          * want to hold it while dereferencing the user data.
867          */
868         first_data_page = data_ptr / PAGE_SIZE;
869         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
870         num_pages = last_data_page - first_data_page + 1;
871
872         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
873         if (user_pages == NULL)
874                 return -ENOMEM;
875
876         down_read(&mm->mmap_sem);
877         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
878                                       num_pages, 0, 0, user_pages, NULL);
879         up_read(&mm->mmap_sem);
880         if (pinned_pages < num_pages) {
881                 ret = -EFAULT;
882                 goto fail_put_user_pages;
883         }
884
885         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
886
887         mutex_lock(&dev->struct_mutex);
888
889         ret = i915_gem_object_get_pages_or_evict(obj);
890         if (ret)
891                 goto fail_unlock;
892
893         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
894         if (ret != 0)
895                 goto fail_put_pages;
896
897         obj_priv = obj->driver_private;
898         offset = args->offset;
899         obj_priv->dirty = 1;
900
901         while (remain > 0) {
902                 /* Operation in this page
903                  *
904                  * shmem_page_index = page number within shmem file
905                  * shmem_page_offset = offset within page in shmem file
906                  * data_page_index = page number in get_user_pages return
907                  * data_page_offset = offset with data_page_index page.
908                  * page_length = bytes to copy for this page
909                  */
910                 shmem_page_index = offset / PAGE_SIZE;
911                 shmem_page_offset = offset & ~PAGE_MASK;
912                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
913                 data_page_offset = data_ptr & ~PAGE_MASK;
914
915                 page_length = remain;
916                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
917                         page_length = PAGE_SIZE - shmem_page_offset;
918                 if ((data_page_offset + page_length) > PAGE_SIZE)
919                         page_length = PAGE_SIZE - data_page_offset;
920
921                 if (do_bit17_swizzling) {
922                         ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
923                                                     shmem_page_offset,
924                                                     user_pages[data_page_index],
925                                                     data_page_offset,
926                                                     page_length,
927                                                     0);
928                 } else {
929                         ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
930                                               shmem_page_offset,
931                                               user_pages[data_page_index],
932                                               data_page_offset,
933                                               page_length);
934                 }
935                 if (ret)
936                         goto fail_put_pages;
937
938                 remain -= page_length;
939                 data_ptr += page_length;
940                 offset += page_length;
941         }
942
943 fail_put_pages:
944         i915_gem_object_put_pages(obj);
945 fail_unlock:
946         mutex_unlock(&dev->struct_mutex);
947 fail_put_user_pages:
948         for (i = 0; i < pinned_pages; i++)
949                 page_cache_release(user_pages[i]);
950         drm_free_large(user_pages);
951
952         return ret;
953 }
954
955 /**
956  * Writes data to the object referenced by handle.
957  *
958  * On error, the contents of the buffer that were to be modified are undefined.
959  */
960 int
961 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
962                       struct drm_file *file_priv)
963 {
964         struct drm_i915_gem_pwrite *args = data;
965         struct drm_gem_object *obj;
966         struct drm_i915_gem_object *obj_priv;
967         int ret = 0;
968
969         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
970         if (obj == NULL)
971                 return -EBADF;
972         obj_priv = obj->driver_private;
973
974         /* Bounds check destination.
975          *
976          * XXX: This could use review for overflow issues...
977          */
978         if (args->offset > obj->size || args->size > obj->size ||
979             args->offset + args->size > obj->size) {
980                 drm_gem_object_unreference(obj);
981                 return -EINVAL;
982         }
983
984         /* We can only do the GTT pwrite on untiled buffers, as otherwise
985          * it would end up going through the fenced access, and we'll get
986          * different detiling behavior between reading and writing.
987          * pread/pwrite currently are reading and writing from the CPU
988          * perspective, requiring manual detiling by the client.
989          */
990         if (obj_priv->phys_obj)
991                 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
992         else if (obj_priv->tiling_mode == I915_TILING_NONE &&
993                  dev->gtt_total != 0) {
994                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
995                 if (ret == -EFAULT) {
996                         ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
997                                                        file_priv);
998                 }
999         } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
1000                 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
1001         } else {
1002                 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
1003                 if (ret == -EFAULT) {
1004                         ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
1005                                                          file_priv);
1006                 }
1007         }
1008
1009 #if WATCH_PWRITE
1010         if (ret)
1011                 DRM_INFO("pwrite failed %d\n", ret);
1012 #endif
1013
1014         drm_gem_object_unreference(obj);
1015
1016         return ret;
1017 }
1018
1019 /**
1020  * Called when user space prepares to use an object with the CPU, either
1021  * through the mmap ioctl's mapping or a GTT mapping.
1022  */
1023 int
1024 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1025                           struct drm_file *file_priv)
1026 {
1027         struct drm_i915_private *dev_priv = dev->dev_private;
1028         struct drm_i915_gem_set_domain *args = data;
1029         struct drm_gem_object *obj;
1030         struct drm_i915_gem_object *obj_priv;
1031         uint32_t read_domains = args->read_domains;
1032         uint32_t write_domain = args->write_domain;
1033         int ret;
1034
1035         if (!(dev->driver->driver_features & DRIVER_GEM))
1036                 return -ENODEV;
1037
1038         /* Only handle setting domains to types used by the CPU. */
1039         if (write_domain & I915_GEM_GPU_DOMAINS)
1040                 return -EINVAL;
1041
1042         if (read_domains & I915_GEM_GPU_DOMAINS)
1043                 return -EINVAL;
1044
1045         /* Having something in the write domain implies it's in the read
1046          * domain, and only that read domain.  Enforce that in the request.
1047          */
1048         if (write_domain != 0 && read_domains != write_domain)
1049                 return -EINVAL;
1050
1051         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1052         if (obj == NULL)
1053                 return -EBADF;
1054         obj_priv = obj->driver_private;
1055
1056         mutex_lock(&dev->struct_mutex);
1057
1058         intel_mark_busy(dev, obj);
1059
1060 #if WATCH_BUF
1061         DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1062                  obj, obj->size, read_domains, write_domain);
1063 #endif
1064         if (read_domains & I915_GEM_DOMAIN_GTT) {
1065                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1066
1067                 /* Update the LRU on the fence for the CPU access that's
1068                  * about to occur.
1069                  */
1070                 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1071                         list_move_tail(&obj_priv->fence_list,
1072                                        &dev_priv->mm.fence_list);
1073                 }
1074
1075                 /* Silently promote "you're not bound, there was nothing to do"
1076                  * to success, since the client was just asking us to
1077                  * make sure everything was done.
1078                  */
1079                 if (ret == -EINVAL)
1080                         ret = 0;
1081         } else {
1082                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1083         }
1084
1085         drm_gem_object_unreference(obj);
1086         mutex_unlock(&dev->struct_mutex);
1087         return ret;
1088 }
1089
1090 /**
1091  * Called when user space has done writes to this buffer
1092  */
1093 int
1094 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1095                       struct drm_file *file_priv)
1096 {
1097         struct drm_i915_gem_sw_finish *args = data;
1098         struct drm_gem_object *obj;
1099         struct drm_i915_gem_object *obj_priv;
1100         int ret = 0;
1101
1102         if (!(dev->driver->driver_features & DRIVER_GEM))
1103                 return -ENODEV;
1104
1105         mutex_lock(&dev->struct_mutex);
1106         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1107         if (obj == NULL) {
1108                 mutex_unlock(&dev->struct_mutex);
1109                 return -EBADF;
1110         }
1111
1112 #if WATCH_BUF
1113         DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1114                  __func__, args->handle, obj, obj->size);
1115 #endif
1116         obj_priv = obj->driver_private;
1117
1118         /* Pinned buffers may be scanout, so flush the cache */
1119         if (obj_priv->pin_count)
1120                 i915_gem_object_flush_cpu_write_domain(obj);
1121
1122         drm_gem_object_unreference(obj);
1123         mutex_unlock(&dev->struct_mutex);
1124         return ret;
1125 }
1126
1127 /**
1128  * Maps the contents of an object, returning the address it is mapped
1129  * into.
1130  *
1131  * While the mapping holds a reference on the contents of the object, it doesn't
1132  * imply a ref on the object itself.
1133  */
1134 int
1135 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1136                    struct drm_file *file_priv)
1137 {
1138         struct drm_i915_gem_mmap *args = data;
1139         struct drm_gem_object *obj;
1140         loff_t offset;
1141         unsigned long addr;
1142
1143         if (!(dev->driver->driver_features & DRIVER_GEM))
1144                 return -ENODEV;
1145
1146         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1147         if (obj == NULL)
1148                 return -EBADF;
1149
1150         offset = args->offset;
1151
1152         down_write(&current->mm->mmap_sem);
1153         addr = do_mmap(obj->filp, 0, args->size,
1154                        PROT_READ | PROT_WRITE, MAP_SHARED,
1155                        args->offset);
1156         up_write(&current->mm->mmap_sem);
1157         mutex_lock(&dev->struct_mutex);
1158         drm_gem_object_unreference(obj);
1159         mutex_unlock(&dev->struct_mutex);
1160         if (IS_ERR((void *)addr))
1161                 return addr;
1162
1163         args->addr_ptr = (uint64_t) addr;
1164
1165         return 0;
1166 }
1167
1168 /**
1169  * i915_gem_fault - fault a page into the GTT
1170  * vma: VMA in question
1171  * vmf: fault info
1172  *
1173  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1174  * from userspace.  The fault handler takes care of binding the object to
1175  * the GTT (if needed), allocating and programming a fence register (again,
1176  * only if needed based on whether the old reg is still valid or the object
1177  * is tiled) and inserting a new PTE into the faulting process.
1178  *
1179  * Note that the faulting process may involve evicting existing objects
1180  * from the GTT and/or fence registers to make room.  So performance may
1181  * suffer if the GTT working set is large or there are few fence registers
1182  * left.
1183  */
1184 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1185 {
1186         struct drm_gem_object *obj = vma->vm_private_data;
1187         struct drm_device *dev = obj->dev;
1188         struct drm_i915_private *dev_priv = dev->dev_private;
1189         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1190         pgoff_t page_offset;
1191         unsigned long pfn;
1192         int ret = 0;
1193         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1194
1195         /* We don't use vmf->pgoff since that has the fake offset */
1196         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1197                 PAGE_SHIFT;
1198
1199         /* Now bind it into the GTT if needed */
1200         mutex_lock(&dev->struct_mutex);
1201         if (!obj_priv->gtt_space) {
1202                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1203                 if (ret)
1204                         goto unlock;
1205
1206                 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1207
1208                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1209                 if (ret)
1210                         goto unlock;
1211         }
1212
1213         /* Need a new fence register? */
1214         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1215                 ret = i915_gem_object_get_fence_reg(obj);
1216                 if (ret)
1217                         goto unlock;
1218         }
1219
1220         pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1221                 page_offset;
1222
1223         /* Finally, remap it using the new GTT offset */
1224         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1225 unlock:
1226         mutex_unlock(&dev->struct_mutex);
1227
1228         switch (ret) {
1229         case 0:
1230         case -ERESTARTSYS:
1231                 return VM_FAULT_NOPAGE;
1232         case -ENOMEM:
1233         case -EAGAIN:
1234                 return VM_FAULT_OOM;
1235         default:
1236                 return VM_FAULT_SIGBUS;
1237         }
1238 }
1239
1240 /**
1241  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1242  * @obj: obj in question
1243  *
1244  * GEM memory mapping works by handing back to userspace a fake mmap offset
1245  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
1246  * up the object based on the offset and sets up the various memory mapping
1247  * structures.
1248  *
1249  * This routine allocates and attaches a fake offset for @obj.
1250  */
1251 static int
1252 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1253 {
1254         struct drm_device *dev = obj->dev;
1255         struct drm_gem_mm *mm = dev->mm_private;
1256         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1257         struct drm_map_list *list;
1258         struct drm_local_map *map;
1259         int ret = 0;
1260
1261         /* Set the object up for mmap'ing */
1262         list = &obj->map_list;
1263         list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1264         if (!list->map)
1265                 return -ENOMEM;
1266
1267         map = list->map;
1268         map->type = _DRM_GEM;
1269         map->size = obj->size;
1270         map->handle = obj;
1271
1272         /* Get a DRM GEM mmap offset allocated... */
1273         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1274                                                     obj->size / PAGE_SIZE, 0, 0);
1275         if (!list->file_offset_node) {
1276                 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1277                 ret = -ENOMEM;
1278                 goto out_free_list;
1279         }
1280
1281         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1282                                                   obj->size / PAGE_SIZE, 0);
1283         if (!list->file_offset_node) {
1284                 ret = -ENOMEM;
1285                 goto out_free_list;
1286         }
1287
1288         list->hash.key = list->file_offset_node->start;
1289         if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1290                 DRM_ERROR("failed to add to map hash\n");
1291                 ret = -ENOMEM;
1292                 goto out_free_mm;
1293         }
1294
1295         /* By now we should be all set, any drm_mmap request on the offset
1296          * below will get to our mmap & fault handler */
1297         obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1298
1299         return 0;
1300
1301 out_free_mm:
1302         drm_mm_put_block(list->file_offset_node);
1303 out_free_list:
1304         kfree(list->map);
1305
1306         return ret;
1307 }
1308
1309 /**
1310  * i915_gem_release_mmap - remove physical page mappings
1311  * @obj: obj in question
1312  *
1313  * Preserve the reservation of the mmapping with the DRM core code, but
1314  * relinquish ownership of the pages back to the system.
1315  *
1316  * It is vital that we remove the page mapping if we have mapped a tiled
1317  * object through the GTT and then lose the fence register due to
1318  * resource pressure. Similarly if the object has been moved out of the
1319  * aperture, than pages mapped into userspace must be revoked. Removing the
1320  * mapping will then trigger a page fault on the next user access, allowing
1321  * fixup by i915_gem_fault().
1322  */
1323 void
1324 i915_gem_release_mmap(struct drm_gem_object *obj)
1325 {
1326         struct drm_device *dev = obj->dev;
1327         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1328
1329         if (dev->dev_mapping)
1330                 unmap_mapping_range(dev->dev_mapping,
1331                                     obj_priv->mmap_offset, obj->size, 1);
1332 }
1333
1334 static void
1335 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1336 {
1337         struct drm_device *dev = obj->dev;
1338         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1339         struct drm_gem_mm *mm = dev->mm_private;
1340         struct drm_map_list *list;
1341
1342         list = &obj->map_list;
1343         drm_ht_remove_item(&mm->offset_hash, &list->hash);
1344
1345         if (list->file_offset_node) {
1346                 drm_mm_put_block(list->file_offset_node);
1347                 list->file_offset_node = NULL;
1348         }
1349
1350         if (list->map) {
1351                 kfree(list->map);
1352                 list->map = NULL;
1353         }
1354
1355         obj_priv->mmap_offset = 0;
1356 }
1357
1358 /**
1359  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1360  * @obj: object to check
1361  *
1362  * Return the required GTT alignment for an object, taking into account
1363  * potential fence register mapping if needed.
1364  */
1365 static uint32_t
1366 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1367 {
1368         struct drm_device *dev = obj->dev;
1369         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1370         int start, i;
1371
1372         /*
1373          * Minimum alignment is 4k (GTT page size), but might be greater
1374          * if a fence register is needed for the object.
1375          */
1376         if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1377                 return 4096;
1378
1379         /*
1380          * Previous chips need to be aligned to the size of the smallest
1381          * fence register that can contain the object.
1382          */
1383         if (IS_I9XX(dev))
1384                 start = 1024*1024;
1385         else
1386                 start = 512*1024;
1387
1388         for (i = start; i < obj->size; i <<= 1)
1389                 ;
1390
1391         return i;
1392 }
1393
1394 /**
1395  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1396  * @dev: DRM device
1397  * @data: GTT mapping ioctl data
1398  * @file_priv: GEM object info
1399  *
1400  * Simply returns the fake offset to userspace so it can mmap it.
1401  * The mmap call will end up in drm_gem_mmap(), which will set things
1402  * up so we can get faults in the handler above.
1403  *
1404  * The fault handler will take care of binding the object into the GTT
1405  * (since it may have been evicted to make room for something), allocating
1406  * a fence register, and mapping the appropriate aperture address into
1407  * userspace.
1408  */
1409 int
1410 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1411                         struct drm_file *file_priv)
1412 {
1413         struct drm_i915_gem_mmap_gtt *args = data;
1414         struct drm_i915_private *dev_priv = dev->dev_private;
1415         struct drm_gem_object *obj;
1416         struct drm_i915_gem_object *obj_priv;
1417         int ret;
1418
1419         if (!(dev->driver->driver_features & DRIVER_GEM))
1420                 return -ENODEV;
1421
1422         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1423         if (obj == NULL)
1424                 return -EBADF;
1425
1426         mutex_lock(&dev->struct_mutex);
1427
1428         obj_priv = obj->driver_private;
1429
1430         if (obj_priv->madv != I915_MADV_WILLNEED) {
1431                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1432                 drm_gem_object_unreference(obj);
1433                 mutex_unlock(&dev->struct_mutex);
1434                 return -EINVAL;
1435         }
1436
1437
1438         if (!obj_priv->mmap_offset) {
1439                 ret = i915_gem_create_mmap_offset(obj);
1440                 if (ret) {
1441                         drm_gem_object_unreference(obj);
1442                         mutex_unlock(&dev->struct_mutex);
1443                         return ret;
1444                 }
1445         }
1446
1447         args->offset = obj_priv->mmap_offset;
1448
1449         /*
1450          * Pull it into the GTT so that we have a page list (makes the
1451          * initial fault faster and any subsequent flushing possible).
1452          */
1453         if (!obj_priv->agp_mem) {
1454                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1455                 if (ret) {
1456                         drm_gem_object_unreference(obj);
1457                         mutex_unlock(&dev->struct_mutex);
1458                         return ret;
1459                 }
1460                 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1461         }
1462
1463         drm_gem_object_unreference(obj);
1464         mutex_unlock(&dev->struct_mutex);
1465
1466         return 0;
1467 }
1468
1469 void
1470 i915_gem_object_put_pages(struct drm_gem_object *obj)
1471 {
1472         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1473         int page_count = obj->size / PAGE_SIZE;
1474         int i;
1475
1476         BUG_ON(obj_priv->pages_refcount == 0);
1477         BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1478
1479         if (--obj_priv->pages_refcount != 0)
1480                 return;
1481
1482         if (obj_priv->tiling_mode != I915_TILING_NONE)
1483                 i915_gem_object_save_bit_17_swizzle(obj);
1484
1485         if (obj_priv->madv == I915_MADV_DONTNEED)
1486                 obj_priv->dirty = 0;
1487
1488         for (i = 0; i < page_count; i++) {
1489                 if (obj_priv->pages[i] == NULL)
1490                         break;
1491
1492                 if (obj_priv->dirty)
1493                         set_page_dirty(obj_priv->pages[i]);
1494
1495                 if (obj_priv->madv == I915_MADV_WILLNEED)
1496                         mark_page_accessed(obj_priv->pages[i]);
1497
1498                 page_cache_release(obj_priv->pages[i]);
1499         }
1500         obj_priv->dirty = 0;
1501
1502         drm_free_large(obj_priv->pages);
1503         obj_priv->pages = NULL;
1504 }
1505
1506 static void
1507 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
1508 {
1509         struct drm_device *dev = obj->dev;
1510         drm_i915_private_t *dev_priv = dev->dev_private;
1511         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1512
1513         /* Add a reference if we're newly entering the active list. */
1514         if (!obj_priv->active) {
1515                 drm_gem_object_reference(obj);
1516                 obj_priv->active = 1;
1517         }
1518         /* Move from whatever list we were on to the tail of execution. */
1519         spin_lock(&dev_priv->mm.active_list_lock);
1520         list_move_tail(&obj_priv->list,
1521                        &dev_priv->mm.active_list);
1522         spin_unlock(&dev_priv->mm.active_list_lock);
1523         obj_priv->last_rendering_seqno = seqno;
1524 }
1525
1526 static void
1527 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1528 {
1529         struct drm_device *dev = obj->dev;
1530         drm_i915_private_t *dev_priv = dev->dev_private;
1531         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1532
1533         BUG_ON(!obj_priv->active);
1534         list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1535         obj_priv->last_rendering_seqno = 0;
1536 }
1537
1538 /* Immediately discard the backing storage */
1539 static void
1540 i915_gem_object_truncate(struct drm_gem_object *obj)
1541 {
1542         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1543         struct inode *inode;
1544
1545         inode = obj->filp->f_path.dentry->d_inode;
1546         if (inode->i_op->truncate)
1547                 inode->i_op->truncate (inode);
1548
1549         obj_priv->madv = __I915_MADV_PURGED;
1550 }
1551
1552 static inline int
1553 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1554 {
1555         return obj_priv->madv == I915_MADV_DONTNEED;
1556 }
1557
1558 static void
1559 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1560 {
1561         struct drm_device *dev = obj->dev;
1562         drm_i915_private_t *dev_priv = dev->dev_private;
1563         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1564
1565         i915_verify_inactive(dev, __FILE__, __LINE__);
1566         if (obj_priv->pin_count != 0)
1567                 list_del_init(&obj_priv->list);
1568         else
1569                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1570
1571         obj_priv->last_rendering_seqno = 0;
1572         if (obj_priv->active) {
1573                 obj_priv->active = 0;
1574                 drm_gem_object_unreference(obj);
1575         }
1576         i915_verify_inactive(dev, __FILE__, __LINE__);
1577 }
1578
1579 /**
1580  * Creates a new sequence number, emitting a write of it to the status page
1581  * plus an interrupt, which will trigger i915_user_interrupt_handler.
1582  *
1583  * Must be called with struct_lock held.
1584  *
1585  * Returned sequence numbers are nonzero on success.
1586  */
1587 uint32_t
1588 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1589                  uint32_t flush_domains)
1590 {
1591         drm_i915_private_t *dev_priv = dev->dev_private;
1592         struct drm_i915_file_private *i915_file_priv = NULL;
1593         struct drm_i915_gem_request *request;
1594         uint32_t seqno;
1595         int was_empty;
1596         RING_LOCALS;
1597
1598         if (file_priv != NULL)
1599                 i915_file_priv = file_priv->driver_priv;
1600
1601         request = kzalloc(sizeof(*request), GFP_KERNEL);
1602         if (request == NULL)
1603                 return 0;
1604
1605         /* Grab the seqno we're going to make this request be, and bump the
1606          * next (skipping 0 so it can be the reserved no-seqno value).
1607          */
1608         seqno = dev_priv->mm.next_gem_seqno;
1609         dev_priv->mm.next_gem_seqno++;
1610         if (dev_priv->mm.next_gem_seqno == 0)
1611                 dev_priv->mm.next_gem_seqno++;
1612
1613         BEGIN_LP_RING(4);
1614         OUT_RING(MI_STORE_DWORD_INDEX);
1615         OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1616         OUT_RING(seqno);
1617
1618         OUT_RING(MI_USER_INTERRUPT);
1619         ADVANCE_LP_RING();
1620
1621         DRM_DEBUG_DRIVER("%d\n", seqno);
1622
1623         request->seqno = seqno;
1624         request->emitted_jiffies = jiffies;
1625         was_empty = list_empty(&dev_priv->mm.request_list);
1626         list_add_tail(&request->list, &dev_priv->mm.request_list);
1627         if (i915_file_priv) {
1628                 list_add_tail(&request->client_list,
1629                               &i915_file_priv->mm.request_list);
1630         } else {
1631                 INIT_LIST_HEAD(&request->client_list);
1632         }
1633
1634         /* Associate any objects on the flushing list matching the write
1635          * domain we're flushing with our flush.
1636          */
1637         if (flush_domains != 0) {
1638                 struct drm_i915_gem_object *obj_priv, *next;
1639
1640                 list_for_each_entry_safe(obj_priv, next,
1641                                          &dev_priv->mm.flushing_list, list) {
1642                         struct drm_gem_object *obj = obj_priv->obj;
1643
1644                         if ((obj->write_domain & flush_domains) ==
1645                             obj->write_domain) {
1646                                 uint32_t old_write_domain = obj->write_domain;
1647
1648                                 obj->write_domain = 0;
1649                                 i915_gem_object_move_to_active(obj, seqno);
1650
1651                                 trace_i915_gem_object_change_domain(obj,
1652                                                                     obj->read_domains,
1653                                                                     old_write_domain);
1654                         }
1655                 }
1656
1657         }
1658
1659         if (!dev_priv->mm.suspended) {
1660                 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1661                 if (was_empty)
1662                         queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1663         }
1664         return seqno;
1665 }
1666
1667 /**
1668  * Command execution barrier
1669  *
1670  * Ensures that all commands in the ring are finished
1671  * before signalling the CPU
1672  */
1673 static uint32_t
1674 i915_retire_commands(struct drm_device *dev)
1675 {
1676         drm_i915_private_t *dev_priv = dev->dev_private;
1677         uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1678         uint32_t flush_domains = 0;
1679         RING_LOCALS;
1680
1681         /* The sampler always gets flushed on i965 (sigh) */
1682         if (IS_I965G(dev))
1683                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1684         BEGIN_LP_RING(2);
1685         OUT_RING(cmd);
1686         OUT_RING(0); /* noop */
1687         ADVANCE_LP_RING();
1688         return flush_domains;
1689 }
1690
1691 /**
1692  * Moves buffers associated only with the given active seqno from the active
1693  * to inactive list, potentially freeing them.
1694  */
1695 static void
1696 i915_gem_retire_request(struct drm_device *dev,
1697                         struct drm_i915_gem_request *request)
1698 {
1699         drm_i915_private_t *dev_priv = dev->dev_private;
1700
1701         trace_i915_gem_request_retire(dev, request->seqno);
1702
1703         /* Move any buffers on the active list that are no longer referenced
1704          * by the ringbuffer to the flushing/inactive lists as appropriate.
1705          */
1706         spin_lock(&dev_priv->mm.active_list_lock);
1707         while (!list_empty(&dev_priv->mm.active_list)) {
1708                 struct drm_gem_object *obj;
1709                 struct drm_i915_gem_object *obj_priv;
1710
1711                 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1712                                             struct drm_i915_gem_object,
1713                                             list);
1714                 obj = obj_priv->obj;
1715
1716                 /* If the seqno being retired doesn't match the oldest in the
1717                  * list, then the oldest in the list must still be newer than
1718                  * this seqno.
1719                  */
1720                 if (obj_priv->last_rendering_seqno != request->seqno)
1721                         goto out;
1722
1723 #if WATCH_LRU
1724                 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1725                          __func__, request->seqno, obj);
1726 #endif
1727
1728                 if (obj->write_domain != 0)
1729                         i915_gem_object_move_to_flushing(obj);
1730                 else {
1731                         /* Take a reference on the object so it won't be
1732                          * freed while the spinlock is held.  The list
1733                          * protection for this spinlock is safe when breaking
1734                          * the lock like this since the next thing we do
1735                          * is just get the head of the list again.
1736                          */
1737                         drm_gem_object_reference(obj);
1738                         i915_gem_object_move_to_inactive(obj);
1739                         spin_unlock(&dev_priv->mm.active_list_lock);
1740                         drm_gem_object_unreference(obj);
1741                         spin_lock(&dev_priv->mm.active_list_lock);
1742                 }
1743         }
1744 out:
1745         spin_unlock(&dev_priv->mm.active_list_lock);
1746 }
1747
1748 /**
1749  * Returns true if seq1 is later than seq2.
1750  */
1751 bool
1752 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1753 {
1754         return (int32_t)(seq1 - seq2) >= 0;
1755 }
1756
1757 uint32_t
1758 i915_get_gem_seqno(struct drm_device *dev)
1759 {
1760         drm_i915_private_t *dev_priv = dev->dev_private;
1761
1762         return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1763 }
1764
1765 /**
1766  * This function clears the request list as sequence numbers are passed.
1767  */
1768 void
1769 i915_gem_retire_requests(struct drm_device *dev)
1770 {
1771         drm_i915_private_t *dev_priv = dev->dev_private;
1772         uint32_t seqno;
1773
1774         if (!dev_priv->hw_status_page || list_empty(&dev_priv->mm.request_list))
1775                 return;
1776
1777         seqno = i915_get_gem_seqno(dev);
1778
1779         while (!list_empty(&dev_priv->mm.request_list)) {
1780                 struct drm_i915_gem_request *request;
1781                 uint32_t retiring_seqno;
1782
1783                 request = list_first_entry(&dev_priv->mm.request_list,
1784                                            struct drm_i915_gem_request,
1785                                            list);
1786                 retiring_seqno = request->seqno;
1787
1788                 if (i915_seqno_passed(seqno, retiring_seqno) ||
1789                     atomic_read(&dev_priv->mm.wedged)) {
1790                         i915_gem_retire_request(dev, request);
1791
1792                         list_del(&request->list);
1793                         list_del(&request->client_list);
1794                         kfree(request);
1795                 } else
1796                         break;
1797         }
1798
1799         if (unlikely (dev_priv->trace_irq_seqno &&
1800                       i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1801                 i915_user_irq_put(dev);
1802                 dev_priv->trace_irq_seqno = 0;
1803         }
1804 }
1805
1806 void
1807 i915_gem_retire_work_handler(struct work_struct *work)
1808 {
1809         drm_i915_private_t *dev_priv;
1810         struct drm_device *dev;
1811
1812         dev_priv = container_of(work, drm_i915_private_t,
1813                                 mm.retire_work.work);
1814         dev = dev_priv->dev;
1815
1816         mutex_lock(&dev->struct_mutex);
1817         i915_gem_retire_requests(dev);
1818         if (!dev_priv->mm.suspended &&
1819             !list_empty(&dev_priv->mm.request_list))
1820                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1821         mutex_unlock(&dev->struct_mutex);
1822 }
1823
1824 int
1825 i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible)
1826 {
1827         drm_i915_private_t *dev_priv = dev->dev_private;
1828         u32 ier;
1829         int ret = 0;
1830
1831         BUG_ON(seqno == 0);
1832
1833         if (atomic_read(&dev_priv->mm.wedged))
1834                 return -EIO;
1835
1836         if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1837                 if (IS_IRONLAKE(dev))
1838                         ier = I915_READ(DEIER) | I915_READ(GTIER);
1839                 else
1840                         ier = I915_READ(IER);
1841                 if (!ier) {
1842                         DRM_ERROR("something (likely vbetool) disabled "
1843                                   "interrupts, re-enabling\n");
1844                         i915_driver_irq_preinstall(dev);
1845                         i915_driver_irq_postinstall(dev);
1846                 }
1847
1848                 trace_i915_gem_request_wait_begin(dev, seqno);
1849
1850                 dev_priv->mm.waiting_gem_seqno = seqno;
1851                 i915_user_irq_get(dev);
1852                 if (interruptible)
1853                         ret = wait_event_interruptible(dev_priv->irq_queue,
1854                                 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1855                                 atomic_read(&dev_priv->mm.wedged));
1856                 else
1857                         wait_event(dev_priv->irq_queue,
1858                                 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1859                                 atomic_read(&dev_priv->mm.wedged));
1860
1861                 i915_user_irq_put(dev);
1862                 dev_priv->mm.waiting_gem_seqno = 0;
1863
1864                 trace_i915_gem_request_wait_end(dev, seqno);
1865         }
1866         if (atomic_read(&dev_priv->mm.wedged))
1867                 ret = -EIO;
1868
1869         if (ret && ret != -ERESTARTSYS)
1870                 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1871                           __func__, ret, seqno, i915_get_gem_seqno(dev));
1872
1873         /* Directly dispatch request retiring.  While we have the work queue
1874          * to handle this, the waiter on a request often wants an associated
1875          * buffer to have made it to the inactive list, and we would need
1876          * a separate wait queue to handle that.
1877          */
1878         if (ret == 0)
1879                 i915_gem_retire_requests(dev);
1880
1881         return ret;
1882 }
1883
1884 /**
1885  * Waits for a sequence number to be signaled, and cleans up the
1886  * request and object lists appropriately for that event.
1887  */
1888 static int
1889 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1890 {
1891         return i915_do_wait_request(dev, seqno, 1);
1892 }
1893
1894 static void
1895 i915_gem_flush(struct drm_device *dev,
1896                uint32_t invalidate_domains,
1897                uint32_t flush_domains)
1898 {
1899         drm_i915_private_t *dev_priv = dev->dev_private;
1900         uint32_t cmd;
1901         RING_LOCALS;
1902
1903 #if WATCH_EXEC
1904         DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1905                   invalidate_domains, flush_domains);
1906 #endif
1907         trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
1908                                      invalidate_domains, flush_domains);
1909
1910         if (flush_domains & I915_GEM_DOMAIN_CPU)
1911                 drm_agp_chipset_flush(dev);
1912
1913         if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
1914                 /*
1915                  * read/write caches:
1916                  *
1917                  * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1918                  * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
1919                  * also flushed at 2d versus 3d pipeline switches.
1920                  *
1921                  * read-only caches:
1922                  *
1923                  * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1924                  * MI_READ_FLUSH is set, and is always flushed on 965.
1925                  *
1926                  * I915_GEM_DOMAIN_COMMAND may not exist?
1927                  *
1928                  * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1929                  * invalidated when MI_EXE_FLUSH is set.
1930                  *
1931                  * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1932                  * invalidated with every MI_FLUSH.
1933                  *
1934                  * TLBs:
1935                  *
1936                  * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1937                  * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1938                  * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1939                  * are flushed at any MI_FLUSH.
1940                  */
1941
1942                 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1943                 if ((invalidate_domains|flush_domains) &
1944                     I915_GEM_DOMAIN_RENDER)
1945                         cmd &= ~MI_NO_WRITE_FLUSH;
1946                 if (!IS_I965G(dev)) {
1947                         /*
1948                          * On the 965, the sampler cache always gets flushed
1949                          * and this bit is reserved.
1950                          */
1951                         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1952                                 cmd |= MI_READ_FLUSH;
1953                 }
1954                 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1955                         cmd |= MI_EXE_FLUSH;
1956
1957 #if WATCH_EXEC
1958                 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1959 #endif
1960                 BEGIN_LP_RING(2);
1961                 OUT_RING(cmd);
1962                 OUT_RING(MI_NOOP);
1963                 ADVANCE_LP_RING();
1964         }
1965 }
1966
1967 /**
1968  * Ensures that all rendering to the object has completed and the object is
1969  * safe to unbind from the GTT or access from the CPU.
1970  */
1971 static int
1972 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1973 {
1974         struct drm_device *dev = obj->dev;
1975         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1976         int ret;
1977
1978         /* This function only exists to support waiting for existing rendering,
1979          * not for emitting required flushes.
1980          */
1981         BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1982
1983         /* If there is rendering queued on the buffer being evicted, wait for
1984          * it.
1985          */
1986         if (obj_priv->active) {
1987 #if WATCH_BUF
1988                 DRM_INFO("%s: object %p wait for seqno %08x\n",
1989                           __func__, obj, obj_priv->last_rendering_seqno);
1990 #endif
1991                 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1992                 if (ret != 0)
1993                         return ret;
1994         }
1995
1996         return 0;
1997 }
1998
1999 /**
2000  * Unbinds an object from the GTT aperture.
2001  */
2002 int
2003 i915_gem_object_unbind(struct drm_gem_object *obj)
2004 {
2005         struct drm_device *dev = obj->dev;
2006         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2007         int ret = 0;
2008
2009 #if WATCH_BUF
2010         DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
2011         DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
2012 #endif
2013         if (obj_priv->gtt_space == NULL)
2014                 return 0;
2015
2016         if (obj_priv->pin_count != 0) {
2017                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2018                 return -EINVAL;
2019         }
2020
2021         /* blow away mappings if mapped through GTT */
2022         i915_gem_release_mmap(obj);
2023
2024         /* Move the object to the CPU domain to ensure that
2025          * any possible CPU writes while it's not in the GTT
2026          * are flushed when we go to remap it. This will
2027          * also ensure that all pending GPU writes are finished
2028          * before we unbind.
2029          */
2030         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2031         if (ret) {
2032                 if (ret != -ERESTARTSYS)
2033                         DRM_ERROR("set_domain failed: %d\n", ret);
2034                 return ret;
2035         }
2036
2037         BUG_ON(obj_priv->active);
2038
2039         /* release the fence reg _after_ flushing */
2040         if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2041                 i915_gem_clear_fence_reg(obj);
2042
2043         if (obj_priv->agp_mem != NULL) {
2044                 drm_unbind_agp(obj_priv->agp_mem);
2045                 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2046                 obj_priv->agp_mem = NULL;
2047         }
2048
2049         i915_gem_object_put_pages(obj);
2050         BUG_ON(obj_priv->pages_refcount);
2051
2052         if (obj_priv->gtt_space) {
2053                 atomic_dec(&dev->gtt_count);
2054                 atomic_sub(obj->size, &dev->gtt_memory);
2055
2056                 drm_mm_put_block(obj_priv->gtt_space);
2057                 obj_priv->gtt_space = NULL;
2058         }
2059
2060         /* Remove ourselves from the LRU list if present. */
2061         if (!list_empty(&obj_priv->list))
2062                 list_del_init(&obj_priv->list);
2063
2064         if (i915_gem_object_is_purgeable(obj_priv))
2065                 i915_gem_object_truncate(obj);
2066
2067         trace_i915_gem_object_unbind(obj);
2068
2069         return 0;
2070 }
2071
2072 static struct drm_gem_object *
2073 i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2074 {
2075         drm_i915_private_t *dev_priv = dev->dev_private;
2076         struct drm_i915_gem_object *obj_priv;
2077         struct drm_gem_object *best = NULL;
2078         struct drm_gem_object *first = NULL;
2079
2080         /* Try to find the smallest clean object */
2081         list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2082                 struct drm_gem_object *obj = obj_priv->obj;
2083                 if (obj->size >= min_size) {
2084                         if ((!obj_priv->dirty ||
2085                              i915_gem_object_is_purgeable(obj_priv)) &&
2086                             (!best || obj->size < best->size)) {
2087                                 best = obj;
2088                                 if (best->size == min_size)
2089                                         return best;
2090                         }
2091                         if (!first)
2092                             first = obj;
2093                 }
2094         }
2095
2096         return best ? best : first;
2097 }
2098
2099 static int
2100 i915_gem_evict_everything(struct drm_device *dev)
2101 {
2102         drm_i915_private_t *dev_priv = dev->dev_private;
2103         uint32_t seqno;
2104         int ret;
2105         bool lists_empty;
2106
2107         spin_lock(&dev_priv->mm.active_list_lock);
2108         lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2109                        list_empty(&dev_priv->mm.flushing_list) &&
2110                        list_empty(&dev_priv->mm.active_list));
2111         spin_unlock(&dev_priv->mm.active_list_lock);
2112
2113         if (lists_empty)
2114                 return -ENOSPC;
2115
2116         /* Flush everything (on to the inactive lists) and evict */
2117         i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2118         seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2119         if (seqno == 0)
2120                 return -ENOMEM;
2121
2122         ret = i915_wait_request(dev, seqno);
2123         if (ret)
2124                 return ret;
2125
2126         ret = i915_gem_evict_from_inactive_list(dev);
2127         if (ret)
2128                 return ret;
2129
2130         spin_lock(&dev_priv->mm.active_list_lock);
2131         lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2132                        list_empty(&dev_priv->mm.flushing_list) &&
2133                        list_empty(&dev_priv->mm.active_list));
2134         spin_unlock(&dev_priv->mm.active_list_lock);
2135         BUG_ON(!lists_empty);
2136
2137         return 0;
2138 }
2139
2140 static int
2141 i915_gem_evict_something(struct drm_device *dev, int min_size)
2142 {
2143         drm_i915_private_t *dev_priv = dev->dev_private;
2144         struct drm_gem_object *obj;
2145         int ret;
2146
2147         for (;;) {
2148                 i915_gem_retire_requests(dev);
2149
2150                 /* If there's an inactive buffer available now, grab it
2151                  * and be done.
2152                  */
2153                 obj = i915_gem_find_inactive_object(dev, min_size);
2154                 if (obj) {
2155                         struct drm_i915_gem_object *obj_priv;
2156
2157 #if WATCH_LRU
2158                         DRM_INFO("%s: evicting %p\n", __func__, obj);
2159 #endif
2160                         obj_priv = obj->driver_private;
2161                         BUG_ON(obj_priv->pin_count != 0);
2162                         BUG_ON(obj_priv->active);
2163
2164                         /* Wait on the rendering and unbind the buffer. */
2165                         return i915_gem_object_unbind(obj);
2166                 }
2167
2168                 /* If we didn't get anything, but the ring is still processing
2169                  * things, wait for the next to finish and hopefully leave us
2170                  * a buffer to evict.
2171                  */
2172                 if (!list_empty(&dev_priv->mm.request_list)) {
2173                         struct drm_i915_gem_request *request;
2174
2175                         request = list_first_entry(&dev_priv->mm.request_list,
2176                                                    struct drm_i915_gem_request,
2177                                                    list);
2178
2179                         ret = i915_wait_request(dev, request->seqno);
2180                         if (ret)
2181                                 return ret;
2182
2183                         continue;
2184                 }
2185
2186                 /* If we didn't have anything on the request list but there
2187                  * are buffers awaiting a flush, emit one and try again.
2188                  * When we wait on it, those buffers waiting for that flush
2189                  * will get moved to inactive.
2190                  */
2191                 if (!list_empty(&dev_priv->mm.flushing_list)) {
2192                         struct drm_i915_gem_object *obj_priv;
2193
2194                         /* Find an object that we can immediately reuse */
2195                         list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2196                                 obj = obj_priv->obj;
2197                                 if (obj->size >= min_size)
2198                                         break;
2199
2200                                 obj = NULL;
2201                         }
2202
2203                         if (obj != NULL) {
2204                                 uint32_t seqno;
2205
2206                                 i915_gem_flush(dev,
2207                                                obj->write_domain,
2208                                                obj->write_domain);
2209                                 seqno = i915_add_request(dev, NULL, obj->write_domain);
2210                                 if (seqno == 0)
2211                                         return -ENOMEM;
2212
2213                                 ret = i915_wait_request(dev, seqno);
2214                                 if (ret)
2215                                         return ret;
2216
2217                                 continue;
2218                         }
2219                 }
2220
2221                 /* If we didn't do any of the above, there's no single buffer
2222                  * large enough to swap out for the new one, so just evict
2223                  * everything and start again. (This should be rare.)
2224                  */
2225                 if (!list_empty (&dev_priv->mm.inactive_list))
2226                         return i915_gem_evict_from_inactive_list(dev);
2227                 else
2228                         return i915_gem_evict_everything(dev);
2229         }
2230 }
2231
2232 int
2233 i915_gem_object_get_pages(struct drm_gem_object *obj)
2234 {
2235         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2236         int page_count, i;
2237         struct address_space *mapping;
2238         struct inode *inode;
2239         struct page *page;
2240         int ret;
2241
2242         if (obj_priv->pages_refcount++ != 0)
2243                 return 0;
2244
2245         /* Get the list of pages out of our struct file.  They'll be pinned
2246          * at this point until we release them.
2247          */
2248         page_count = obj->size / PAGE_SIZE;
2249         BUG_ON(obj_priv->pages != NULL);
2250         obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2251         if (obj_priv->pages == NULL) {
2252                 obj_priv->pages_refcount--;
2253                 return -ENOMEM;
2254         }
2255
2256         inode = obj->filp->f_path.dentry->d_inode;
2257         mapping = inode->i_mapping;
2258         for (i = 0; i < page_count; i++) {
2259                 page = read_mapping_page(mapping, i, NULL);
2260                 if (IS_ERR(page)) {
2261                         ret = PTR_ERR(page);
2262                         i915_gem_object_put_pages(obj);
2263                         return ret;
2264                 }
2265                 obj_priv->pages[i] = page;
2266         }
2267
2268         if (obj_priv->tiling_mode != I915_TILING_NONE)
2269                 i915_gem_object_do_bit_17_swizzle(obj);
2270
2271         return 0;
2272 }
2273
2274 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2275 {
2276         struct drm_gem_object *obj = reg->obj;
2277         struct drm_device *dev = obj->dev;
2278         drm_i915_private_t *dev_priv = dev->dev_private;
2279         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2280         int regnum = obj_priv->fence_reg;
2281         uint64_t val;
2282
2283         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2284                     0xfffff000) << 32;
2285         val |= obj_priv->gtt_offset & 0xfffff000;
2286         val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2287         if (obj_priv->tiling_mode == I915_TILING_Y)
2288                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2289         val |= I965_FENCE_REG_VALID;
2290
2291         I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2292 }
2293
2294 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2295 {
2296         struct drm_gem_object *obj = reg->obj;
2297         struct drm_device *dev = obj->dev;
2298         drm_i915_private_t *dev_priv = dev->dev_private;
2299         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2300         int regnum = obj_priv->fence_reg;
2301         int tile_width;
2302         uint32_t fence_reg, val;
2303         uint32_t pitch_val;
2304
2305         if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2306             (obj_priv->gtt_offset & (obj->size - 1))) {
2307                 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2308                      __func__, obj_priv->gtt_offset, obj->size);
2309                 return;
2310         }
2311
2312         if (obj_priv->tiling_mode == I915_TILING_Y &&
2313             HAS_128_BYTE_Y_TILING(dev))
2314                 tile_width = 128;
2315         else
2316                 tile_width = 512;
2317
2318         /* Note: pitch better be a power of two tile widths */
2319         pitch_val = obj_priv->stride / tile_width;
2320         pitch_val = ffs(pitch_val) - 1;
2321
2322         val = obj_priv->gtt_offset;
2323         if (obj_priv->tiling_mode == I915_TILING_Y)
2324                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2325         val |= I915_FENCE_SIZE_BITS(obj->size);
2326         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2327         val |= I830_FENCE_REG_VALID;
2328
2329         if (regnum < 8)
2330                 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2331         else
2332                 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2333         I915_WRITE(fence_reg, val);
2334 }
2335
2336 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2337 {
2338         struct drm_gem_object *obj = reg->obj;
2339         struct drm_device *dev = obj->dev;
2340         drm_i915_private_t *dev_priv = dev->dev_private;
2341         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2342         int regnum = obj_priv->fence_reg;
2343         uint32_t val;
2344         uint32_t pitch_val;
2345         uint32_t fence_size_bits;
2346
2347         if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2348             (obj_priv->gtt_offset & (obj->size - 1))) {
2349                 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2350                      __func__, obj_priv->gtt_offset);
2351                 return;
2352         }
2353
2354         pitch_val = obj_priv->stride / 128;
2355         pitch_val = ffs(pitch_val) - 1;
2356         WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2357
2358         val = obj_priv->gtt_offset;
2359         if (obj_priv->tiling_mode == I915_TILING_Y)
2360                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2361         fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2362         WARN_ON(fence_size_bits & ~0x00000f00);
2363         val |= fence_size_bits;
2364         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2365         val |= I830_FENCE_REG_VALID;
2366
2367         I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2368 }
2369
2370 /**
2371  * i915_gem_object_get_fence_reg - set up a fence reg for an object
2372  * @obj: object to map through a fence reg
2373  *
2374  * When mapping objects through the GTT, userspace wants to be able to write
2375  * to them without having to worry about swizzling if the object is tiled.
2376  *
2377  * This function walks the fence regs looking for a free one for @obj,
2378  * stealing one if it can't find any.
2379  *
2380  * It then sets up the reg based on the object's properties: address, pitch
2381  * and tiling format.
2382  */
2383 int
2384 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2385 {
2386         struct drm_device *dev = obj->dev;
2387         struct drm_i915_private *dev_priv = dev->dev_private;
2388         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2389         struct drm_i915_fence_reg *reg = NULL;
2390         struct drm_i915_gem_object *old_obj_priv = NULL;
2391         int i, ret, avail;
2392
2393         /* Just update our place in the LRU if our fence is getting used. */
2394         if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2395                 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2396                 return 0;
2397         }
2398
2399         switch (obj_priv->tiling_mode) {
2400         case I915_TILING_NONE:
2401                 WARN(1, "allocating a fence for non-tiled object?\n");
2402                 break;
2403         case I915_TILING_X:
2404                 if (!obj_priv->stride)
2405                         return -EINVAL;
2406                 WARN((obj_priv->stride & (512 - 1)),
2407                      "object 0x%08x is X tiled but has non-512B pitch\n",
2408                      obj_priv->gtt_offset);
2409                 break;
2410         case I915_TILING_Y:
2411                 if (!obj_priv->stride)
2412                         return -EINVAL;
2413                 WARN((obj_priv->stride & (128 - 1)),
2414                      "object 0x%08x is Y tiled but has non-128B pitch\n",
2415                      obj_priv->gtt_offset);
2416                 break;
2417         }
2418
2419         /* First try to find a free reg */
2420         avail = 0;
2421         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2422                 reg = &dev_priv->fence_regs[i];
2423                 if (!reg->obj)
2424                         break;
2425
2426                 old_obj_priv = reg->obj->driver_private;
2427                 if (!old_obj_priv->pin_count)
2428                     avail++;
2429         }
2430
2431         /* None available, try to steal one or wait for a user to finish */
2432         if (i == dev_priv->num_fence_regs) {
2433                 struct drm_gem_object *old_obj = NULL;
2434
2435                 if (avail == 0)
2436                         return -ENOSPC;
2437
2438                 list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list,
2439                                     fence_list) {
2440                         old_obj = old_obj_priv->obj;
2441
2442                         if (old_obj_priv->pin_count)
2443                                 continue;
2444
2445                         /* Take a reference, as otherwise the wait_rendering
2446                          * below may cause the object to get freed out from
2447                          * under us.
2448                          */
2449                         drm_gem_object_reference(old_obj);
2450
2451                         /* i915 uses fences for GPU access to tiled buffers */
2452                         if (IS_I965G(dev) || !old_obj_priv->active)
2453                                 break;
2454
2455                         /* This brings the object to the head of the LRU if it
2456                          * had been written to.  The only way this should
2457                          * result in us waiting longer than the expected
2458                          * optimal amount of time is if there was a
2459                          * fence-using buffer later that was read-only.
2460                          */
2461                         i915_gem_object_flush_gpu_write_domain(old_obj);
2462                         ret = i915_gem_object_wait_rendering(old_obj);
2463                         if (ret != 0) {
2464                                 drm_gem_object_unreference(old_obj);
2465                                 return ret;
2466                         }
2467
2468                         break;
2469                 }
2470
2471                 /*
2472                  * Zap this virtual mapping so we can set up a fence again
2473                  * for this object next time we need it.
2474                  */
2475                 i915_gem_release_mmap(old_obj);
2476
2477                 i = old_obj_priv->fence_reg;
2478                 reg = &dev_priv->fence_regs[i];
2479
2480                 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
2481                 list_del_init(&old_obj_priv->fence_list);
2482
2483                 drm_gem_object_unreference(old_obj);
2484         }
2485
2486         obj_priv->fence_reg = i;
2487         list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2488
2489         reg->obj = obj;
2490
2491         if (IS_I965G(dev))
2492                 i965_write_fence_reg(reg);
2493         else if (IS_I9XX(dev))
2494                 i915_write_fence_reg(reg);
2495         else
2496                 i830_write_fence_reg(reg);
2497
2498         trace_i915_gem_object_get_fence(obj, i, obj_priv->tiling_mode);
2499
2500         return 0;
2501 }
2502
2503 /**
2504  * i915_gem_clear_fence_reg - clear out fence register info
2505  * @obj: object to clear
2506  *
2507  * Zeroes out the fence register itself and clears out the associated
2508  * data structures in dev_priv and obj_priv.
2509  */
2510 static void
2511 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2512 {
2513         struct drm_device *dev = obj->dev;
2514         drm_i915_private_t *dev_priv = dev->dev_private;
2515         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2516
2517         if (IS_I965G(dev))
2518                 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2519         else {
2520                 uint32_t fence_reg;
2521
2522                 if (obj_priv->fence_reg < 8)
2523                         fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2524                 else
2525                         fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2526                                                        8) * 4;
2527
2528                 I915_WRITE(fence_reg, 0);
2529         }
2530
2531         dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2532         obj_priv->fence_reg = I915_FENCE_REG_NONE;
2533         list_del_init(&obj_priv->fence_list);
2534 }
2535
2536 /**
2537  * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2538  * to the buffer to finish, and then resets the fence register.
2539  * @obj: tiled object holding a fence register.
2540  *
2541  * Zeroes out the fence register itself and clears out the associated
2542  * data structures in dev_priv and obj_priv.
2543  */
2544 int
2545 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2546 {
2547         struct drm_device *dev = obj->dev;
2548         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2549
2550         if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2551                 return 0;
2552
2553         /* On the i915, GPU access to tiled buffers is via a fence,
2554          * therefore we must wait for any outstanding access to complete
2555          * before clearing the fence.
2556          */
2557         if (!IS_I965G(dev)) {
2558                 int ret;
2559
2560                 i915_gem_object_flush_gpu_write_domain(obj);
2561                 i915_gem_object_flush_gtt_write_domain(obj);
2562                 ret = i915_gem_object_wait_rendering(obj);
2563                 if (ret != 0)
2564                         return ret;
2565         }
2566
2567         i915_gem_clear_fence_reg (obj);
2568
2569         return 0;
2570 }
2571
2572 /**
2573  * Finds free space in the GTT aperture and binds the object there.
2574  */
2575 static int
2576 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2577 {
2578         struct drm_device *dev = obj->dev;
2579         drm_i915_private_t *dev_priv = dev->dev_private;
2580         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2581         struct drm_mm_node *free_space;
2582         bool retry_alloc = false;
2583         int ret;
2584
2585         if (dev_priv->mm.suspended)
2586                 return -EBUSY;
2587
2588         if (obj_priv->madv != I915_MADV_WILLNEED) {
2589                 DRM_ERROR("Attempting to bind a purgeable object\n");
2590                 return -EINVAL;
2591         }
2592
2593         if (alignment == 0)
2594                 alignment = i915_gem_get_gtt_alignment(obj);
2595         if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2596                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2597                 return -EINVAL;
2598         }
2599
2600  search_free:
2601         free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2602                                         obj->size, alignment, 0);
2603         if (free_space != NULL) {
2604                 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2605                                                        alignment);
2606                 if (obj_priv->gtt_space != NULL) {
2607                         obj_priv->gtt_space->private = obj;
2608                         obj_priv->gtt_offset = obj_priv->gtt_space->start;
2609                 }
2610         }
2611         if (obj_priv->gtt_space == NULL) {
2612                 /* If the gtt is empty and we're still having trouble
2613                  * fitting our object in, we're out of memory.
2614                  */
2615 #if WATCH_LRU
2616                 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2617 #endif
2618                 ret = i915_gem_evict_something(dev, obj->size);
2619                 if (ret)
2620                         return ret;
2621
2622                 goto search_free;
2623         }
2624
2625 #if WATCH_BUF
2626         DRM_INFO("Binding object of size %zd at 0x%08x\n",
2627                  obj->size, obj_priv->gtt_offset);
2628 #endif
2629         if (retry_alloc) {
2630                 i915_gem_object_set_page_gfp_mask (obj,
2631                                                    i915_gem_object_get_page_gfp_mask (obj) & ~__GFP_NORETRY);
2632         }
2633         ret = i915_gem_object_get_pages(obj);
2634         if (retry_alloc) {
2635                 i915_gem_object_set_page_gfp_mask (obj,
2636                                                    i915_gem_object_get_page_gfp_mask (obj) | __GFP_NORETRY);
2637         }
2638         if (ret) {
2639                 drm_mm_put_block(obj_priv->gtt_space);
2640                 obj_priv->gtt_space = NULL;
2641
2642                 if (ret == -ENOMEM) {
2643                         /* first try to clear up some space from the GTT */
2644                         ret = i915_gem_evict_something(dev, obj->size);
2645                         if (ret) {
2646                                 /* now try to shrink everyone else */
2647                                 if (! retry_alloc) {
2648                                     retry_alloc = true;
2649                                     goto search_free;
2650                                 }
2651
2652                                 return ret;
2653                         }
2654
2655                         goto search_free;
2656                 }
2657
2658                 return ret;
2659         }
2660
2661         /* Create an AGP memory structure pointing at our pages, and bind it
2662          * into the GTT.
2663          */
2664         obj_priv->agp_mem = drm_agp_bind_pages(dev,
2665                                                obj_priv->pages,
2666                                                obj->size >> PAGE_SHIFT,
2667                                                obj_priv->gtt_offset,
2668                                                obj_priv->agp_type);
2669         if (obj_priv->agp_mem == NULL) {
2670                 i915_gem_object_put_pages(obj);
2671                 drm_mm_put_block(obj_priv->gtt_space);
2672                 obj_priv->gtt_space = NULL;
2673
2674                 ret = i915_gem_evict_something(dev, obj->size);
2675                 if (ret)
2676                         return ret;
2677
2678                 goto search_free;
2679         }
2680         atomic_inc(&dev->gtt_count);
2681         atomic_add(obj->size, &dev->gtt_memory);
2682
2683         /* Assert that the object is not currently in any GPU domain. As it
2684          * wasn't in the GTT, there shouldn't be any way it could have been in
2685          * a GPU cache
2686          */
2687         BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2688         BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2689
2690         trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2691
2692         return 0;
2693 }
2694
2695 void
2696 i915_gem_clflush_object(struct drm_gem_object *obj)
2697 {
2698         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
2699
2700         /* If we don't have a page list set up, then we're not pinned
2701          * to GPU, and we can ignore the cache flush because it'll happen
2702          * again at bind time.
2703          */
2704         if (obj_priv->pages == NULL)
2705                 return;
2706
2707         trace_i915_gem_object_clflush(obj);
2708
2709         drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2710 }
2711
2712 /** Flushes any GPU write domain for the object if it's dirty. */
2713 static void
2714 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2715 {
2716         struct drm_device *dev = obj->dev;
2717         uint32_t seqno;
2718         uint32_t old_write_domain;
2719
2720         if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2721                 return;
2722
2723         /* Queue the GPU write cache flushing we need. */
2724         old_write_domain = obj->write_domain;
2725         i915_gem_flush(dev, 0, obj->write_domain);
2726         seqno = i915_add_request(dev, NULL, obj->write_domain);
2727         obj->write_domain = 0;
2728         i915_gem_object_move_to_active(obj, seqno);
2729
2730         trace_i915_gem_object_change_domain(obj,
2731                                             obj->read_domains,
2732                                             old_write_domain);
2733 }
2734
2735 /** Flushes the GTT write domain for the object if it's dirty. */
2736 static void
2737 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2738 {
2739         uint32_t old_write_domain;
2740
2741         if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2742                 return;
2743
2744         /* No actual flushing is required for the GTT write domain.   Writes
2745          * to it immediately go to main memory as far as we know, so there's
2746          * no chipset flush.  It also doesn't land in render cache.
2747          */
2748         old_write_domain = obj->write_domain;
2749         obj->write_domain = 0;
2750
2751         trace_i915_gem_object_change_domain(obj,
2752                                             obj->read_domains,
2753                                             old_write_domain);
2754 }
2755
2756 /** Flushes the CPU write domain for the object if it's dirty. */
2757 static void
2758 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2759 {
2760         struct drm_device *dev = obj->dev;
2761         uint32_t old_write_domain;
2762
2763         if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2764                 return;
2765
2766         i915_gem_clflush_object(obj);
2767         drm_agp_chipset_flush(dev);
2768         old_write_domain = obj->write_domain;
2769         obj->write_domain = 0;
2770
2771         trace_i915_gem_object_change_domain(obj,
2772                                             obj->read_domains,
2773                                             old_write_domain);
2774 }
2775
2776 void
2777 i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2778 {
2779         switch (obj->write_domain) {
2780         case I915_GEM_DOMAIN_GTT:
2781                 i915_gem_object_flush_gtt_write_domain(obj);
2782                 break;
2783         case I915_GEM_DOMAIN_CPU:
2784                 i915_gem_object_flush_cpu_write_domain(obj);
2785                 break;
2786         default:
2787                 i915_gem_object_flush_gpu_write_domain(obj);
2788                 break;
2789         }
2790 }
2791
2792 /**
2793  * Moves a single object to the GTT read, and possibly write domain.
2794  *
2795  * This function returns when the move is complete, including waiting on
2796  * flushes to occur.
2797  */
2798 int
2799 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2800 {
2801         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2802         uint32_t old_write_domain, old_read_domains;
2803         int ret;
2804
2805         /* Not valid to be called on unbound objects. */
2806         if (obj_priv->gtt_space == NULL)
2807                 return -EINVAL;
2808
2809         i915_gem_object_flush_gpu_write_domain(obj);
2810         /* Wait on any GPU rendering and flushing to occur. */
2811         ret = i915_gem_object_wait_rendering(obj);
2812         if (ret != 0)
2813                 return ret;
2814
2815         old_write_domain = obj->write_domain;
2816         old_read_domains = obj->read_domains;
2817
2818         /* If we're writing through the GTT domain, then CPU and GPU caches
2819          * will need to be invalidated at next use.
2820          */
2821         if (write)
2822                 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2823
2824         i915_gem_object_flush_cpu_write_domain(obj);
2825
2826         /* It should now be out of any other write domains, and we can update
2827          * the domain values for our changes.
2828          */
2829         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2830         obj->read_domains |= I915_GEM_DOMAIN_GTT;
2831         if (write) {
2832                 obj->write_domain = I915_GEM_DOMAIN_GTT;
2833                 obj_priv->dirty = 1;
2834         }
2835
2836         trace_i915_gem_object_change_domain(obj,
2837                                             old_read_domains,
2838                                             old_write_domain);
2839
2840         return 0;
2841 }
2842
2843 /**
2844  * Moves a single object to the CPU read, and possibly write domain.
2845  *
2846  * This function returns when the move is complete, including waiting on
2847  * flushes to occur.
2848  */
2849 static int
2850 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2851 {
2852         uint32_t old_write_domain, old_read_domains;
2853         int ret;
2854
2855         i915_gem_object_flush_gpu_write_domain(obj);
2856         /* Wait on any GPU rendering and flushing to occur. */
2857         ret = i915_gem_object_wait_rendering(obj);
2858         if (ret != 0)
2859                 return ret;
2860
2861         i915_gem_object_flush_gtt_write_domain(obj);
2862
2863         /* If we have a partially-valid cache of the object in the CPU,
2864          * finish invalidating it and free the per-page flags.
2865          */
2866         i915_gem_object_set_to_full_cpu_read_domain(obj);
2867
2868         old_write_domain = obj->write_domain;
2869         old_read_domains = obj->read_domains;
2870
2871         /* Flush the CPU cache if it's still invalid. */
2872         if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2873                 i915_gem_clflush_object(obj);
2874
2875                 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2876         }
2877
2878         /* It should now be out of any other write domains, and we can update
2879          * the domain values for our changes.
2880          */
2881         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2882
2883         /* If we're writing through the CPU, then the GPU read domains will
2884          * need to be invalidated at next use.
2885          */
2886         if (write) {
2887                 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2888                 obj->write_domain = I915_GEM_DOMAIN_CPU;
2889         }
2890
2891         trace_i915_gem_object_change_domain(obj,
2892                                             old_read_domains,
2893                                             old_write_domain);
2894
2895         return 0;
2896 }
2897
2898 /*
2899  * Set the next domain for the specified object. This
2900  * may not actually perform the necessary flushing/invaliding though,
2901  * as that may want to be batched with other set_domain operations
2902  *
2903  * This is (we hope) the only really tricky part of gem. The goal
2904  * is fairly simple -- track which caches hold bits of the object
2905  * and make sure they remain coherent. A few concrete examples may
2906  * help to explain how it works. For shorthand, we use the notation
2907  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2908  * a pair of read and write domain masks.
2909  *
2910  * Case 1: the batch buffer
2911  *
2912  *      1. Allocated
2913  *      2. Written by CPU
2914  *      3. Mapped to GTT
2915  *      4. Read by GPU
2916  *      5. Unmapped from GTT
2917  *      6. Freed
2918  *
2919  *      Let's take these a step at a time
2920  *
2921  *      1. Allocated
2922  *              Pages allocated from the kernel may still have
2923  *              cache contents, so we set them to (CPU, CPU) always.
2924  *      2. Written by CPU (using pwrite)
2925  *              The pwrite function calls set_domain (CPU, CPU) and
2926  *              this function does nothing (as nothing changes)
2927  *      3. Mapped by GTT
2928  *              This function asserts that the object is not
2929  *              currently in any GPU-based read or write domains
2930  *      4. Read by GPU
2931  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
2932  *              As write_domain is zero, this function adds in the
2933  *              current read domains (CPU+COMMAND, 0).
2934  *              flush_domains is set to CPU.
2935  *              invalidate_domains is set to COMMAND
2936  *              clflush is run to get data out of the CPU caches
2937  *              then i915_dev_set_domain calls i915_gem_flush to
2938  *              emit an MI_FLUSH and drm_agp_chipset_flush
2939  *      5. Unmapped from GTT
2940  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
2941  *              flush_domains and invalidate_domains end up both zero
2942  *              so no flushing/invalidating happens
2943  *      6. Freed
2944  *              yay, done
2945  *
2946  * Case 2: The shared render buffer
2947  *
2948  *      1. Allocated
2949  *      2. Mapped to GTT
2950  *      3. Read/written by GPU
2951  *      4. set_domain to (CPU,CPU)
2952  *      5. Read/written by CPU
2953  *      6. Read/written by GPU
2954  *
2955  *      1. Allocated
2956  *              Same as last example, (CPU, CPU)
2957  *      2. Mapped to GTT
2958  *              Nothing changes (assertions find that it is not in the GPU)
2959  *      3. Read/written by GPU
2960  *              execbuffer calls set_domain (RENDER, RENDER)
2961  *              flush_domains gets CPU
2962  *              invalidate_domains gets GPU
2963  *              clflush (obj)
2964  *              MI_FLUSH and drm_agp_chipset_flush
2965  *      4. set_domain (CPU, CPU)
2966  *              flush_domains gets GPU
2967  *              invalidate_domains gets CPU
2968  *              wait_rendering (obj) to make sure all drawing is complete.
2969  *              This will include an MI_FLUSH to get the data from GPU
2970  *              to memory
2971  *              clflush (obj) to invalidate the CPU cache
2972  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2973  *      5. Read/written by CPU
2974  *              cache lines are loaded and dirtied
2975  *      6. Read written by GPU
2976  *              Same as last GPU access
2977  *
2978  * Case 3: The constant buffer
2979  *
2980  *      1. Allocated
2981  *      2. Written by CPU
2982  *      3. Read by GPU
2983  *      4. Updated (written) by CPU again
2984  *      5. Read by GPU
2985  *
2986  *      1. Allocated
2987  *              (CPU, CPU)
2988  *      2. Written by CPU
2989  *              (CPU, CPU)
2990  *      3. Read by GPU
2991  *              (CPU+RENDER, 0)
2992  *              flush_domains = CPU
2993  *              invalidate_domains = RENDER
2994  *              clflush (obj)
2995  *              MI_FLUSH
2996  *              drm_agp_chipset_flush
2997  *      4. Updated (written) by CPU again
2998  *              (CPU, CPU)
2999  *              flush_domains = 0 (no previous write domain)
3000  *              invalidate_domains = 0 (no new read domains)
3001  *      5. Read by GPU
3002  *              (CPU+RENDER, 0)
3003  *              flush_domains = CPU
3004  *              invalidate_domains = RENDER
3005  *              clflush (obj)
3006  *              MI_FLUSH
3007  *              drm_agp_chipset_flush
3008  */
3009 static void
3010 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
3011 {
3012         struct drm_device               *dev = obj->dev;
3013         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
3014         uint32_t                        invalidate_domains = 0;
3015         uint32_t                        flush_domains = 0;
3016         uint32_t                        old_read_domains;
3017
3018         BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3019         BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
3020
3021         intel_mark_busy(dev, obj);
3022
3023 #if WATCH_BUF
3024         DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3025                  __func__, obj,
3026                  obj->read_domains, obj->pending_read_domains,
3027                  obj->write_domain, obj->pending_write_domain);
3028 #endif
3029         /*
3030          * If the object isn't moving to a new write domain,
3031          * let the object stay in multiple read domains
3032          */
3033         if (obj->pending_write_domain == 0)
3034                 obj->pending_read_domains |= obj->read_domains;
3035         else
3036                 obj_priv->dirty = 1;
3037
3038         /*
3039          * Flush the current write domain if
3040          * the new read domains don't match. Invalidate
3041          * any read domains which differ from the old
3042          * write domain
3043          */
3044         if (obj->write_domain &&
3045             obj->write_domain != obj->pending_read_domains) {
3046                 flush_domains |= obj->write_domain;
3047                 invalidate_domains |=
3048                         obj->pending_read_domains & ~obj->write_domain;
3049         }
3050         /*
3051          * Invalidate any read caches which may have
3052          * stale data. That is, any new read domains.
3053          */
3054         invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3055         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3056 #if WATCH_BUF
3057                 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3058                          __func__, flush_domains, invalidate_domains);
3059 #endif
3060                 i915_gem_clflush_object(obj);
3061         }
3062
3063         old_read_domains = obj->read_domains;
3064
3065         /* The actual obj->write_domain will be updated with
3066          * pending_write_domain after we emit the accumulated flush for all
3067          * of our domain changes in execbuffers (which clears objects'
3068          * write_domains).  So if we have a current write domain that we
3069          * aren't changing, set pending_write_domain to that.
3070          */
3071         if (flush_domains == 0 && obj->pending_write_domain == 0)
3072                 obj->pending_write_domain = obj->write_domain;
3073         obj->read_domains = obj->pending_read_domains;
3074
3075         dev->invalidate_domains |= invalidate_domains;
3076         dev->flush_domains |= flush_domains;
3077 #if WATCH_BUF
3078         DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3079                  __func__,
3080                  obj->read_domains, obj->write_domain,
3081                  dev->invalidate_domains, dev->flush_domains);
3082 #endif
3083
3084         trace_i915_gem_object_change_domain(obj,
3085                                             old_read_domains,
3086                                             obj->write_domain);
3087 }
3088
3089 /**
3090  * Moves the object from a partially CPU read to a full one.
3091  *
3092  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3093  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3094  */
3095 static void
3096 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3097 {
3098         struct drm_i915_gem_object *obj_priv = obj->driver_private;
3099
3100         if (!obj_priv->page_cpu_valid)
3101                 return;
3102
3103         /* If we're partially in the CPU read domain, finish moving it in.
3104          */
3105         if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3106                 int i;
3107
3108                 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3109                         if (obj_priv->page_cpu_valid[i])
3110                                 continue;
3111                         drm_clflush_pages(obj_priv->pages + i, 1);
3112                 }
3113         }
3114
3115         /* Free the page_cpu_valid mappings which are now stale, whether
3116          * or not we've got I915_GEM_DOMAIN_CPU.
3117          */
3118         kfree(obj_priv->page_cpu_valid);
3119         obj_priv->page_cpu_valid = NULL;
3120 }
3121
3122 /**
3123  * Set the CPU read domain on a range of the object.
3124  *
3125  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3126  * not entirely valid.  The page_cpu_valid member of the object flags which
3127  * pages have been flushed, and will be respected by
3128  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3129  * of the whole object.
3130  *
3131  * This function returns when the move is complete, including waiting on
3132  * flushes to occur.
3133  */
3134 static int
3135 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3136                                           uint64_t offset, uint64_t size)
3137 {
3138         struct drm_i915_gem_object *obj_priv = obj->driver_private;
3139         uint32_t old_read_domains;
3140         int i, ret;
3141
3142         if (offset == 0 && size == obj->size)
3143                 return i915_gem_object_set_to_cpu_domain(obj, 0);
3144
3145         i915_gem_object_flush_gpu_write_domain(obj);
3146         /* Wait on any GPU rendering and flushing to occur. */
3147         ret = i915_gem_object_wait_rendering(obj);
3148         if (ret != 0)
3149                 return ret;
3150         i915_gem_object_flush_gtt_write_domain(obj);
3151
3152         /* If we're already fully in the CPU read domain, we're done. */
3153         if (obj_priv->page_cpu_valid == NULL &&
3154             (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3155                 return 0;
3156
3157         /* Otherwise, create/clear the per-page CPU read domain flag if we're
3158          * newly adding I915_GEM_DOMAIN_CPU
3159          */
3160         if (obj_priv->page_cpu_valid == NULL) {
3161                 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3162                                                    GFP_KERNEL);
3163                 if (obj_priv->page_cpu_valid == NULL)
3164                         return -ENOMEM;
3165         } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3166                 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3167
3168         /* Flush the cache on any pages that are still invalid from the CPU's
3169          * perspective.
3170          */
3171         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3172              i++) {
3173                 if (obj_priv->page_cpu_valid[i])
3174                         continue;
3175
3176                 drm_clflush_pages(obj_priv->pages + i, 1);
3177
3178                 obj_priv->page_cpu_valid[i] = 1;
3179         }
3180
3181         /* It should now be out of any other write domains, and we can update
3182          * the domain values for our changes.
3183          */
3184         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3185
3186         old_read_domains = obj->read_domains;
3187         obj->read_domains |= I915_GEM_DOMAIN_CPU;
3188
3189         trace_i915_gem_object_change_domain(obj,
3190                                             old_read_domains,
3191                                             obj->write_domain);
3192
3193         return 0;
3194 }
3195
3196 /**
3197  * Pin an object to the GTT and evaluate the relocations landing in it.
3198  */
3199 static int
3200 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3201                                  struct drm_file *file_priv,
3202                                  struct drm_i915_gem_exec_object2 *entry,
3203                                  struct drm_i915_gem_relocation_entry *relocs)
3204 {
3205         struct drm_device *dev = obj->dev;
3206         drm_i915_private_t *dev_priv = dev->dev_private;
3207         struct drm_i915_gem_object *obj_priv = obj->driver_private;
3208         int i, ret;
3209         void __iomem *reloc_page;
3210         bool need_fence;
3211
3212         need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3213                      obj_priv->tiling_mode != I915_TILING_NONE;
3214
3215         /* Check fence reg constraints and rebind if necessary */
3216         if (need_fence && !i915_obj_fenceable(dev, obj))
3217                 i915_gem_object_unbind(obj);
3218
3219         /* Choose the GTT offset for our buffer and put it there. */
3220         ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3221         if (ret)
3222                 return ret;
3223
3224         /*
3225          * Pre-965 chips need a fence register set up in order to
3226          * properly handle blits to/from tiled surfaces.
3227          */
3228         if (need_fence) {
3229                 ret = i915_gem_object_get_fence_reg(obj);
3230                 if (ret != 0) {
3231                         if (ret != -EBUSY && ret != -ERESTARTSYS)
3232                                 DRM_ERROR("Failure to install fence: %d\n",
3233                                           ret);
3234                         i915_gem_object_unpin(obj);
3235                         return ret;
3236                 }
3237         }
3238
3239         entry->offset = obj_priv->gtt_offset;
3240
3241         /* Apply the relocations, using the GTT aperture to avoid cache
3242          * flushing requirements.
3243          */
3244         for (i = 0; i < entry->relocation_count; i++) {
3245                 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3246                 struct drm_gem_object *target_obj;
3247                 struct drm_i915_gem_object *target_obj_priv;
3248                 uint32_t reloc_val, reloc_offset;
3249                 uint32_t __iomem *reloc_entry;
3250
3251                 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3252                                                    reloc->target_handle);
3253                 if (target_obj == NULL) {
3254                         i915_gem_object_unpin(obj);
3255                         return -EBADF;
3256                 }
3257                 target_obj_priv = target_obj->driver_private;
3258
3259 #if WATCH_RELOC
3260                 DRM_INFO("%s: obj %p offset %08x target %d "
3261                          "read %08x write %08x gtt %08x "
3262                          "presumed %08x delta %08x\n",
3263                          __func__,
3264                          obj,
3265                          (int) reloc->offset,
3266                          (int) reloc->target_handle,
3267                          (int) reloc->read_domains,
3268                          (int) reloc->write_domain,
3269                          (int) target_obj_priv->gtt_offset,
3270                          (int) reloc->presumed_offset,
3271                          reloc->delta);
3272 #endif
3273
3274                 /* The target buffer should have appeared before us in the
3275                  * exec_object list, so it should have a GTT space bound by now.
3276                  */
3277                 if (target_obj_priv->gtt_space == NULL) {
3278                         DRM_ERROR("No GTT space found for object %d\n",
3279                                   reloc->target_handle);
3280                         drm_gem_object_unreference(target_obj);
3281                         i915_gem_object_unpin(obj);
3282                         return -EINVAL;
3283                 }
3284
3285                 /* Validate that the target is in a valid r/w GPU domain */
3286                 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3287                     reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3288                         DRM_ERROR("reloc with read/write CPU domains: "
3289                                   "obj %p target %d offset %d "
3290                                   "read %08x write %08x",
3291                                   obj, reloc->target_handle,
3292                                   (int) reloc->offset,
3293                                   reloc->read_domains,
3294                                   reloc->write_domain);
3295                         drm_gem_object_unreference(target_obj);
3296                         i915_gem_object_unpin(obj);
3297                         return -EINVAL;
3298                 }
3299                 if (reloc->write_domain && target_obj->pending_write_domain &&
3300                     reloc->write_domain != target_obj->pending_write_domain) {
3301                         DRM_ERROR("Write domain conflict: "
3302                                   "obj %p target %d offset %d "
3303                                   "new %08x old %08x\n",
3304                                   obj, reloc->target_handle,
3305                                   (int) reloc->offset,
3306                                   reloc->write_domain,
3307                                   target_obj->pending_write_domain);
3308                         drm_gem_object_unreference(target_obj);
3309                         i915_gem_object_unpin(obj);
3310                         return -EINVAL;
3311                 }
3312
3313                 target_obj->pending_read_domains |= reloc->read_domains;
3314                 target_obj->pending_write_domain |= reloc->write_domain;
3315
3316                 /* If the relocation already has the right value in it, no
3317                  * more work needs to be done.
3318                  */
3319                 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3320                         drm_gem_object_unreference(target_obj);
3321                         continue;
3322                 }
3323
3324                 /* Check that the relocation address is valid... */
3325                 if (reloc->offset > obj->size - 4) {
3326                         DRM_ERROR("Relocation beyond object bounds: "
3327                                   "obj %p target %d offset %d size %d.\n",
3328                                   obj, reloc->target_handle,
3329                                   (int) reloc->offset, (int) obj->size);
3330                         drm_gem_object_unreference(target_obj);
3331                         i915_gem_object_unpin(obj);
3332                         return -EINVAL;
3333                 }
3334                 if (reloc->offset & 3) {
3335                         DRM_ERROR("Relocation not 4-byte aligned: "
3336                                   "obj %p target %d offset %d.\n",
3337                                   obj, reloc->target_handle,
3338                                   (int) reloc->offset);
3339                         drm_gem_object_unreference(target_obj);
3340                         i915_gem_object_unpin(obj);
3341                         return -EINVAL;
3342                 }
3343
3344                 /* and points to somewhere within the target object. */
3345                 if (reloc->delta >= target_obj->size) {
3346                         DRM_ERROR("Relocation beyond target object bounds: "
3347                                   "obj %p target %d delta %d size %d.\n",
3348                                   obj, reloc->target_handle,
3349                                   (int) reloc->delta, (int) target_obj->size);
3350                         drm_gem_object_unreference(target_obj);
3351                         i915_gem_object_unpin(obj);
3352                         return -EINVAL;
3353                 }
3354
3355                 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3356                 if (ret != 0) {
3357                         drm_gem_object_unreference(target_obj);
3358                         i915_gem_object_unpin(obj);
3359                         return -EINVAL;
3360                 }
3361
3362                 /* Map the page containing the relocation we're going to
3363                  * perform.
3364                  */
3365                 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3366                 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3367                                                       (reloc_offset &
3368                                                        ~(PAGE_SIZE - 1)));
3369                 reloc_entry = (uint32_t __iomem *)(reloc_page +
3370                                                    (reloc_offset & (PAGE_SIZE - 1)));
3371                 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3372
3373 #if WATCH_BUF
3374                 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3375                           obj, (unsigned int) reloc->offset,
3376                           readl(reloc_entry), reloc_val);
3377 #endif
3378                 writel(reloc_val, reloc_entry);
3379                 io_mapping_unmap_atomic(reloc_page);
3380
3381                 /* The updated presumed offset for this entry will be
3382                  * copied back out to the user.
3383                  */
3384                 reloc->presumed_offset = target_obj_priv->gtt_offset;
3385
3386                 drm_gem_object_unreference(target_obj);
3387         }
3388
3389 #if WATCH_BUF
3390         if (0)
3391                 i915_gem_dump_object(obj, 128, __func__, ~0);
3392 #endif
3393         return 0;
3394 }
3395
3396 /** Dispatch a batchbuffer to the ring
3397  */
3398 static int
3399 i915_dispatch_gem_execbuffer(struct drm_device *dev,
3400                               struct drm_i915_gem_execbuffer2 *exec,
3401                               struct drm_clip_rect *cliprects,
3402                               uint64_t exec_offset)
3403 {
3404         drm_i915_private_t *dev_priv = dev->dev_private;
3405         int nbox = exec->num_cliprects;
3406         int i = 0, count;
3407         uint32_t exec_start, exec_len;
3408         RING_LOCALS;
3409
3410         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3411         exec_len = (uint32_t) exec->batch_len;
3412
3413         trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno + 1);
3414
3415         count = nbox ? nbox : 1;
3416
3417         for (i = 0; i < count; i++) {
3418                 if (i < nbox) {
3419                         int ret = i915_emit_box(dev, cliprects, i,
3420                                                 exec->DR1, exec->DR4);
3421                         if (ret)
3422                                 return ret;
3423                 }
3424
3425                 if (IS_I830(dev) || IS_845G(dev)) {
3426                         BEGIN_LP_RING(4);
3427                         OUT_RING(MI_BATCH_BUFFER);
3428                         OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3429                         OUT_RING(exec_start + exec_len - 4);
3430                         OUT_RING(0);
3431                         ADVANCE_LP_RING();
3432                 } else {
3433                         BEGIN_LP_RING(2);
3434                         if (IS_I965G(dev)) {
3435                                 OUT_RING(MI_BATCH_BUFFER_START |
3436                                          (2 << 6) |
3437                                          MI_BATCH_NON_SECURE_I965);
3438                                 OUT_RING(exec_start);
3439                         } else {
3440                                 OUT_RING(MI_BATCH_BUFFER_START |
3441                                          (2 << 6));
3442                                 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3443                         }
3444                         ADVANCE_LP_RING();
3445                 }
3446         }
3447
3448         /* XXX breadcrumb */
3449         return 0;
3450 }
3451
3452 /* Throttle our rendering by waiting until the ring has completed our requests
3453  * emitted over 20 msec ago.
3454  *
3455  * Note that if we were to use the current jiffies each time around the loop,
3456  * we wouldn't escape the function with any frames outstanding if the time to
3457  * render a frame was over 20ms.
3458  *
3459  * This should get us reasonable parallelism between CPU and GPU but also
3460  * relatively low latency when blocking on a particular request to finish.
3461  */
3462 static int
3463 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3464 {
3465         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3466         int ret = 0;
3467         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3468
3469         mutex_lock(&dev->struct_mutex);
3470         while (!list_empty(&i915_file_priv->mm.request_list)) {
3471                 struct drm_i915_gem_request *request;
3472
3473                 request = list_first_entry(&i915_file_priv->mm.request_list,
3474                                            struct drm_i915_gem_request,
3475                                            client_list);
3476
3477                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3478                         break;
3479
3480                 ret = i915_wait_request(dev, request->seqno);
3481                 if (ret != 0)
3482                         break;
3483         }
3484         mutex_unlock(&dev->struct_mutex);
3485
3486         return ret;
3487 }
3488
3489 static int
3490 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
3491                               uint32_t buffer_count,
3492                               struct drm_i915_gem_relocation_entry **relocs)
3493 {
3494         uint32_t reloc_count = 0, reloc_index = 0, i;
3495         int ret;
3496
3497         *relocs = NULL;
3498         for (i = 0; i < buffer_count; i++) {
3499                 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3500                         return -EINVAL;
3501                 reloc_count += exec_list[i].relocation_count;
3502         }
3503
3504         *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3505         if (*relocs == NULL) {
3506                 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
3507                 return -ENOMEM;
3508         }
3509
3510         for (i = 0; i < buffer_count; i++) {
3511                 struct drm_i915_gem_relocation_entry __user *user_relocs;
3512
3513                 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3514
3515                 ret = copy_from_user(&(*relocs)[reloc_index],
3516                                      user_relocs,
3517                                      exec_list[i].relocation_count *
3518                                      sizeof(**relocs));
3519                 if (ret != 0) {
3520                         drm_free_large(*relocs);
3521                         *relocs = NULL;
3522                         return -EFAULT;
3523                 }
3524
3525                 reloc_index += exec_list[i].relocation_count;
3526         }
3527
3528         return 0;
3529 }
3530
3531 static int
3532 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
3533                             uint32_t buffer_count,
3534                             struct drm_i915_gem_relocation_entry *relocs)
3535 {
3536         uint32_t reloc_count = 0, i;
3537         int ret = 0;
3538
3539         for (i = 0; i < buffer_count; i++) {
3540                 struct drm_i915_gem_relocation_entry __user *user_relocs;
3541                 int unwritten;
3542
3543                 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3544
3545                 unwritten = copy_to_user(user_relocs,
3546                                          &relocs[reloc_count],
3547                                          exec_list[i].relocation_count *
3548                                          sizeof(*relocs));
3549
3550                 if (unwritten) {
3551                         ret = -EFAULT;
3552                         goto err;
3553                 }
3554
3555                 reloc_count += exec_list[i].relocation_count;
3556         }
3557
3558 err:
3559         drm_free_large(relocs);
3560
3561         return ret;
3562 }
3563
3564 static int
3565 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
3566                            uint64_t exec_offset)
3567 {
3568         uint32_t exec_start, exec_len;
3569
3570         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3571         exec_len = (uint32_t) exec->batch_len;
3572
3573         if ((exec_start | exec_len) & 0x7)
3574                 return -EINVAL;
3575
3576         if (!exec_start)
3577                 return -EINVAL;
3578
3579         return 0;
3580 }
3581
3582 static int
3583 i915_gem_wait_for_pending_flip(struct drm_device *dev,
3584                                struct drm_gem_object **object_list,
3585                                int count)
3586 {
3587         drm_i915_private_t *dev_priv = dev->dev_private;
3588         struct drm_i915_gem_object *obj_priv;
3589         DEFINE_WAIT(wait);
3590         int i, ret = 0;
3591
3592         for (;;) {
3593                 prepare_to_wait(&dev_priv->pending_flip_queue,
3594                                 &wait, TASK_INTERRUPTIBLE);
3595                 for (i = 0; i < count; i++) {
3596                         obj_priv = object_list[i]->driver_private;
3597                         if (atomic_read(&obj_priv->pending_flip) > 0)
3598                                 break;
3599                 }
3600                 if (i == count)
3601                         break;
3602
3603                 if (!signal_pending(current)) {
3604                         mutex_unlock(&dev->struct_mutex);
3605                         schedule();
3606                         mutex_lock(&dev->struct_mutex);
3607                         continue;
3608                 }
3609                 ret = -ERESTARTSYS;
3610                 break;
3611         }
3612         finish_wait(&dev_priv->pending_flip_queue, &wait);
3613
3614         return ret;
3615 }
3616
3617 int
3618 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3619                        struct drm_file *file_priv,
3620                        struct drm_i915_gem_execbuffer2 *args,
3621                        struct drm_i915_gem_exec_object2 *exec_list)
3622 {
3623         drm_i915_private_t *dev_priv = dev->dev_private;
3624         struct drm_gem_object **object_list = NULL;
3625         struct drm_gem_object *batch_obj;
3626         struct drm_i915_gem_object *obj_priv;
3627         struct drm_clip_rect *cliprects = NULL;
3628         struct drm_i915_gem_relocation_entry *relocs;
3629         int ret = 0, ret2, i, pinned = 0;
3630         uint64_t exec_offset;
3631         uint32_t seqno, flush_domains, reloc_index;
3632         int pin_tries, flips;
3633
3634 #if WATCH_EXEC
3635         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3636                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3637 #endif
3638
3639         if (args->buffer_count < 1) {
3640                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3641                 return -EINVAL;
3642         }
3643         object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3644         if (object_list == NULL) {
3645                 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3646                           args->buffer_count);
3647                 ret = -ENOMEM;
3648                 goto pre_mutex_err;
3649         }
3650
3651         if (args->num_cliprects != 0) {
3652                 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3653                                     GFP_KERNEL);
3654                 if (cliprects == NULL)
3655                         goto pre_mutex_err;
3656
3657                 ret = copy_from_user(cliprects,
3658                                      (struct drm_clip_rect __user *)
3659                                      (uintptr_t) args->cliprects_ptr,
3660                                      sizeof(*cliprects) * args->num_cliprects);
3661                 if (ret != 0) {
3662                         DRM_ERROR("copy %d cliprects failed: %d\n",
3663                                   args->num_cliprects, ret);
3664                         goto pre_mutex_err;
3665                 }
3666         }
3667
3668         ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3669                                             &relocs);
3670         if (ret != 0)
3671                 goto pre_mutex_err;
3672
3673         mutex_lock(&dev->struct_mutex);
3674
3675         i915_verify_inactive(dev, __FILE__, __LINE__);
3676
3677         if (atomic_read(&dev_priv->mm.wedged)) {
3678                 mutex_unlock(&dev->struct_mutex);
3679                 ret = -EIO;
3680                 goto pre_mutex_err;
3681         }
3682
3683         if (dev_priv->mm.suspended) {
3684                 mutex_unlock(&dev->struct_mutex);
3685                 ret = -EBUSY;
3686                 goto pre_mutex_err;
3687         }
3688
3689         /* Look up object handles */
3690         flips = 0;
3691         for (i = 0; i < args->buffer_count; i++) {
3692                 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3693                                                        exec_list[i].handle);
3694                 if (object_list[i] == NULL) {
3695                         DRM_ERROR("Invalid object handle %d at index %d\n",
3696                                    exec_list[i].handle, i);
3697                         ret = -EBADF;
3698                         goto err;
3699                 }
3700
3701                 obj_priv = object_list[i]->driver_private;
3702                 if (obj_priv->in_execbuffer) {
3703                         DRM_ERROR("Object %p appears more than once in object list\n",
3704                                    object_list[i]);
3705                         ret = -EBADF;
3706                         goto err;
3707                 }
3708                 obj_priv->in_execbuffer = true;
3709                 flips += atomic_read(&obj_priv->pending_flip);
3710         }
3711
3712         if (flips > 0) {
3713                 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3714                                                      args->buffer_count);
3715                 if (ret)
3716                         goto err;
3717         }
3718
3719         /* Pin and relocate */
3720         for (pin_tries = 0; ; pin_tries++) {
3721                 ret = 0;
3722                 reloc_index = 0;
3723
3724                 for (i = 0; i < args->buffer_count; i++) {
3725                         object_list[i]->pending_read_domains = 0;
3726                         object_list[i]->pending_write_domain = 0;
3727                         ret = i915_gem_object_pin_and_relocate(object_list[i],
3728                                                                file_priv,
3729                                                                &exec_list[i],
3730                                                                &relocs[reloc_index]);
3731                         if (ret)
3732                                 break;
3733                         pinned = i + 1;
3734                         reloc_index += exec_list[i].relocation_count;
3735                 }
3736                 /* success */
3737                 if (ret == 0)
3738                         break;
3739
3740                 /* error other than GTT full, or we've already tried again */
3741                 if (ret != -ENOSPC || pin_tries >= 1) {
3742                         if (ret != -ERESTARTSYS) {
3743                                 unsigned long long total_size = 0;
3744                                 for (i = 0; i < args->buffer_count; i++)
3745                                         total_size += object_list[i]->size;
3746                                 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3747                                           pinned+1, args->buffer_count,
3748                                           total_size, ret);
3749                                 DRM_ERROR("%d objects [%d pinned], "
3750                                           "%d object bytes [%d pinned], "
3751                                           "%d/%d gtt bytes\n",
3752                                           atomic_read(&dev->object_count),
3753                                           atomic_read(&dev->pin_count),
3754                                           atomic_read(&dev->object_memory),
3755                                           atomic_read(&dev->pin_memory),
3756                                           atomic_read(&dev->gtt_memory),
3757                                           dev->gtt_total);
3758                         }
3759                         goto err;
3760                 }
3761
3762                 /* unpin all of our buffers */
3763                 for (i = 0; i < pinned; i++)
3764                         i915_gem_object_unpin(object_list[i]);
3765                 pinned = 0;
3766
3767                 /* evict everyone we can from the aperture */
3768                 ret = i915_gem_evict_everything(dev);
3769                 if (ret && ret != -ENOSPC)
3770                         goto err;
3771         }
3772
3773         /* Set the pending read domains for the batch buffer to COMMAND */
3774         batch_obj = object_list[args->buffer_count-1];
3775         if (batch_obj->pending_write_domain) {
3776                 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3777                 ret = -EINVAL;
3778                 goto err;
3779         }
3780         batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3781
3782         /* Sanity check the batch buffer, prior to moving objects */
3783         exec_offset = exec_list[args->buffer_count - 1].offset;
3784         ret = i915_gem_check_execbuffer (args, exec_offset);
3785         if (ret != 0) {
3786                 DRM_ERROR("execbuf with invalid offset/length\n");
3787                 goto err;
3788         }
3789
3790         i915_verify_inactive(dev, __FILE__, __LINE__);
3791
3792         /* Zero the global flush/invalidate flags. These
3793          * will be modified as new domains are computed
3794          * for each object
3795          */
3796         dev->invalidate_domains = 0;
3797         dev->flush_domains = 0;
3798
3799         for (i = 0; i < args->buffer_count; i++) {
3800                 struct drm_gem_object *obj = object_list[i];
3801
3802                 /* Compute new gpu domains and update invalidate/flush */
3803                 i915_gem_object_set_to_gpu_domain(obj);
3804         }
3805
3806         i915_verify_inactive(dev, __FILE__, __LINE__);
3807
3808         if (dev->invalidate_domains | dev->flush_domains) {
3809 #if WATCH_EXEC
3810                 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3811                           __func__,
3812                          dev->invalidate_domains,
3813                          dev->flush_domains);
3814 #endif
3815                 i915_gem_flush(dev,
3816                                dev->invalidate_domains,
3817                                dev->flush_domains);
3818                 if (dev->flush_domains)
3819                         (void)i915_add_request(dev, file_priv,
3820                                                dev->flush_domains);
3821         }
3822
3823         for (i = 0; i < args->buffer_count; i++) {
3824                 struct drm_gem_object *obj = object_list[i];
3825                 uint32_t old_write_domain = obj->write_domain;
3826
3827                 obj->write_domain = obj->pending_write_domain;
3828                 trace_i915_gem_object_change_domain(obj,
3829                                                     obj->read_domains,
3830                                                     old_write_domain);
3831         }
3832
3833         i915_verify_inactive(dev, __FILE__, __LINE__);
3834
3835 #if WATCH_COHERENCY
3836         for (i = 0; i < args->buffer_count; i++) {
3837                 i915_gem_object_check_coherency(object_list[i],
3838                                                 exec_list[i].handle);
3839         }
3840 #endif
3841
3842 #if WATCH_EXEC
3843         i915_gem_dump_object(batch_obj,
3844                               args->batch_len,
3845                               __func__,
3846                               ~0);
3847 #endif
3848
3849         /* Exec the batchbuffer */
3850         ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
3851         if (ret) {
3852                 DRM_ERROR("dispatch failed %d\n", ret);
3853                 goto err;
3854         }
3855
3856         /*
3857          * Ensure that the commands in the batch buffer are
3858          * finished before the interrupt fires
3859          */
3860         flush_domains = i915_retire_commands(dev);
3861
3862         i915_verify_inactive(dev, __FILE__, __LINE__);
3863
3864         /*
3865          * Get a seqno representing the execution of the current buffer,
3866          * which we can wait on.  We would like to mitigate these interrupts,
3867          * likely by only creating seqnos occasionally (so that we have
3868          * *some* interrupts representing completion of buffers that we can
3869          * wait on when trying to clear up gtt space).
3870          */
3871         seqno = i915_add_request(dev, file_priv, flush_domains);
3872         BUG_ON(seqno == 0);
3873         for (i = 0; i < args->buffer_count; i++) {
3874                 struct drm_gem_object *obj = object_list[i];
3875
3876                 i915_gem_object_move_to_active(obj, seqno);
3877 #if WATCH_LRU
3878                 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3879 #endif
3880         }
3881 #if WATCH_LRU
3882         i915_dump_lru(dev, __func__);
3883 #endif
3884
3885         i915_verify_inactive(dev, __FILE__, __LINE__);
3886
3887 err:
3888         for (i = 0; i < pinned; i++)
3889                 i915_gem_object_unpin(object_list[i]);
3890
3891         for (i = 0; i < args->buffer_count; i++) {
3892                 if (object_list[i]) {
3893                         obj_priv = object_list[i]->driver_private;
3894                         obj_priv->in_execbuffer = false;
3895                 }
3896                 drm_gem_object_unreference(object_list[i]);
3897         }
3898
3899         mutex_unlock(&dev->struct_mutex);
3900
3901         /* Copy the updated relocations out regardless of current error
3902          * state.  Failure to update the relocs would mean that the next
3903          * time userland calls execbuf, it would do so with presumed offset
3904          * state that didn't match the actual object state.
3905          */
3906         ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3907                                            relocs);
3908         if (ret2 != 0) {
3909                 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3910
3911                 if (ret == 0)
3912                         ret = ret2;
3913         }
3914
3915 pre_mutex_err:
3916         drm_free_large(object_list);
3917         kfree(cliprects);
3918
3919         return ret;
3920 }
3921
3922 /*
3923  * Legacy execbuffer just creates an exec2 list from the original exec object
3924  * list array and passes it to the real function.
3925  */
3926 int
3927 i915_gem_execbuffer(struct drm_device *dev, void *data,
3928                     struct drm_file *file_priv)
3929 {
3930         struct drm_i915_gem_execbuffer *args = data;
3931         struct drm_i915_gem_execbuffer2 exec2;
3932         struct drm_i915_gem_exec_object *exec_list = NULL;
3933         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3934         int ret, i;
3935
3936 #if WATCH_EXEC
3937         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3938                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3939 #endif
3940
3941         if (args->buffer_count < 1) {
3942                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3943                 return -EINVAL;
3944         }
3945
3946         /* Copy in the exec list from userland */
3947         exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
3948         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3949         if (exec_list == NULL || exec2_list == NULL) {
3950                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3951                           args->buffer_count);
3952                 drm_free_large(exec_list);
3953                 drm_free_large(exec2_list);
3954                 return -ENOMEM;
3955         }
3956         ret = copy_from_user(exec_list,
3957                              (struct drm_i915_relocation_entry __user *)
3958                              (uintptr_t) args->buffers_ptr,
3959                              sizeof(*exec_list) * args->buffer_count);
3960         if (ret != 0) {
3961                 DRM_ERROR("copy %d exec entries failed %d\n",
3962                           args->buffer_count, ret);
3963                 drm_free_large(exec_list);
3964                 drm_free_large(exec2_list);
3965                 return -EFAULT;
3966         }
3967
3968         for (i = 0; i < args->buffer_count; i++) {
3969                 exec2_list[i].handle = exec_list[i].handle;
3970                 exec2_list[i].relocation_count = exec_list[i].relocation_count;
3971                 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
3972                 exec2_list[i].alignment = exec_list[i].alignment;
3973                 exec2_list[i].offset = exec_list[i].offset;
3974                 if (!IS_I965G(dev))
3975                         exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
3976                 else
3977                         exec2_list[i].flags = 0;
3978         }
3979
3980         exec2.buffers_ptr = args->buffers_ptr;
3981         exec2.buffer_count = args->buffer_count;
3982         exec2.batch_start_offset = args->batch_start_offset;
3983         exec2.batch_len = args->batch_len;
3984         exec2.DR1 = args->DR1;
3985         exec2.DR4 = args->DR4;
3986         exec2.num_cliprects = args->num_cliprects;
3987         exec2.cliprects_ptr = args->cliprects_ptr;
3988         exec2.flags = 0;
3989
3990         ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
3991         if (!ret) {
3992                 /* Copy the new buffer offsets back to the user's exec list. */
3993                 for (i = 0; i < args->buffer_count; i++)
3994                         exec_list[i].offset = exec2_list[i].offset;
3995                 /* ... and back out to userspace */
3996                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3997                                    (uintptr_t) args->buffers_ptr,
3998                                    exec_list,
3999                                    sizeof(*exec_list) * args->buffer_count);
4000                 if (ret) {
4001                         ret = -EFAULT;
4002                         DRM_ERROR("failed to copy %d exec entries "
4003                                   "back to user (%d)\n",
4004                                   args->buffer_count, ret);
4005                 }
4006         } else {
4007                 DRM_ERROR("i915_gem_do_execbuffer returns %d\n", ret);
4008         }
4009
4010         drm_free_large(exec_list);
4011         drm_free_large(exec2_list);
4012         return ret;
4013 }
4014
4015 int
4016 i915_gem_execbuffer2(struct drm_device *dev, void *data,
4017                      struct drm_file *file_priv)
4018 {
4019         struct drm_i915_gem_execbuffer2 *args = data;
4020         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4021         int ret;
4022
4023 #if WATCH_EXEC
4024         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4025                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4026 #endif
4027
4028         if (args->buffer_count < 1) {
4029                 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4030                 return -EINVAL;
4031         }
4032
4033         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4034         if (exec2_list == NULL) {
4035                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4036                           args->buffer_count);
4037                 return -ENOMEM;
4038         }
4039         ret = copy_from_user(exec2_list,
4040                              (struct drm_i915_relocation_entry __user *)
4041                              (uintptr_t) args->buffers_ptr,
4042                              sizeof(*exec2_list) * args->buffer_count);
4043         if (ret != 0) {
4044                 DRM_ERROR("copy %d exec entries failed %d\n",
4045                           args->buffer_count, ret);
4046                 drm_free_large(exec2_list);
4047                 return -EFAULT;
4048         }
4049
4050         ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4051         if (!ret) {
4052                 /* Copy the new buffer offsets back to the user's exec list. */
4053                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4054                                    (uintptr_t) args->buffers_ptr,
4055                                    exec2_list,
4056                                    sizeof(*exec2_list) * args->buffer_count);
4057                 if (ret) {
4058                         ret = -EFAULT;
4059                         DRM_ERROR("failed to copy %d exec entries "
4060                                   "back to user (%d)\n",
4061                                   args->buffer_count, ret);
4062                 }
4063         }
4064
4065         drm_free_large(exec2_list);
4066         return ret;
4067 }
4068
4069 int
4070 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4071 {
4072         struct drm_device *dev = obj->dev;
4073         struct drm_i915_gem_object *obj_priv = obj->driver_private;
4074         int ret;
4075
4076         i915_verify_inactive(dev, __FILE__, __LINE__);
4077         if (obj_priv->gtt_space == NULL) {
4078                 ret = i915_gem_object_bind_to_gtt(obj, alignment);
4079                 if (ret)
4080                         return ret;
4081         }
4082
4083         obj_priv->pin_count++;
4084
4085         /* If the object is not active and not pending a flush,
4086          * remove it from the inactive list
4087          */
4088         if (obj_priv->pin_count == 1) {
4089                 atomic_inc(&dev->pin_count);
4090                 atomic_add(obj->size, &dev->pin_memory);
4091                 if (!obj_priv->active &&
4092                     (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
4093                     !list_empty(&obj_priv->list))
4094                         list_del_init(&obj_priv->list);
4095         }
4096         i915_verify_inactive(dev, __FILE__, __LINE__);
4097
4098         return 0;
4099 }
4100
4101 void
4102 i915_gem_object_unpin(struct drm_gem_object *obj)
4103 {
4104         struct drm_device *dev = obj->dev;
4105         drm_i915_private_t *dev_priv = dev->dev_private;
4106         struct drm_i915_gem_object *obj_priv = obj->driver_private;
4107
4108         i915_verify_inactive(dev, __FILE__, __LINE__);
4109         obj_priv->pin_count--;
4110         BUG_ON(obj_priv->pin_count < 0);
4111         BUG_ON(obj_priv->gtt_space == NULL);
4112
4113         /* If the object is no longer pinned, and is
4114          * neither active nor being flushed, then stick it on
4115          * the inactive list
4116          */
4117         if (obj_priv->pin_count == 0) {
4118                 if (!obj_priv->active &&
4119                     (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4120                         list_move_tail(&obj_priv->list,
4121                                        &dev_priv->mm.inactive_list);
4122                 atomic_dec(&dev->pin_count);
4123                 atomic_sub(obj->size, &dev->pin_memory);
4124         }
4125         i915_verify_inactive(dev, __FILE__, __LINE__);
4126 }
4127
4128 int
4129 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4130                    struct drm_file *file_priv)
4131 {
4132         struct drm_i915_gem_pin *args = data;
4133         struct drm_gem_object *obj;
4134         struct drm_i915_gem_object *obj_priv;
4135         int ret;
4136
4137         mutex_lock(&dev->struct_mutex);
4138
4139         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4140         if (obj == NULL) {
4141                 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4142                           args->handle);
4143                 mutex_unlock(&dev->struct_mutex);
4144                 return -EBADF;
4145         }
4146         obj_priv = obj->driver_private;
4147
4148         if (obj_priv->madv != I915_MADV_WILLNEED) {
4149                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4150                 drm_gem_object_unreference(obj);
4151                 mutex_unlock(&dev->struct_mutex);
4152                 return -EINVAL;
4153         }
4154
4155         if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4156                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4157                           args->handle);
4158                 drm_gem_object_unreference(obj);
4159                 mutex_unlock(&dev->struct_mutex);
4160                 return -EINVAL;
4161         }
4162
4163         obj_priv->user_pin_count++;
4164         obj_priv->pin_filp = file_priv;
4165         if (obj_priv->user_pin_count == 1) {
4166                 ret = i915_gem_object_pin(obj, args->alignment);
4167                 if (ret != 0) {
4168                         drm_gem_object_unreference(obj);
4169                         mutex_unlock(&dev->struct_mutex);
4170                         return ret;
4171                 }
4172         }
4173
4174         /* XXX - flush the CPU caches for pinned objects
4175          * as the X server doesn't manage domains yet
4176          */
4177         i915_gem_object_flush_cpu_write_domain(obj);
4178         args->offset = obj_priv->gtt_offset;
4179         drm_gem_object_unreference(obj);
4180         mutex_unlock(&dev->struct_mutex);
4181
4182         return 0;
4183 }
4184
4185 int
4186 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4187                      struct drm_file *file_priv)
4188 {
4189         struct drm_i915_gem_pin *args = data;
4190         struct drm_gem_object *obj;
4191         struct drm_i915_gem_object *obj_priv;
4192
4193         mutex_lock(&dev->struct_mutex);
4194
4195         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4196         if (obj == NULL) {
4197                 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4198                           args->handle);
4199                 mutex_unlock(&dev->struct_mutex);
4200                 return -EBADF;
4201         }
4202
4203         obj_priv = obj->driver_private;
4204         if (obj_priv->pin_filp != file_priv) {
4205                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4206                           args->handle);
4207                 drm_gem_object_unreference(obj);
4208                 mutex_unlock(&dev->struct_mutex);
4209                 return -EINVAL;
4210         }
4211         obj_priv->user_pin_count--;
4212         if (obj_priv->user_pin_count == 0) {
4213                 obj_priv->pin_filp = NULL;
4214                 i915_gem_object_unpin(obj);
4215         }
4216
4217         drm_gem_object_unreference(obj);
4218         mutex_unlock(&dev->struct_mutex);
4219         return 0;
4220 }
4221
4222 int
4223 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4224                     struct drm_file *file_priv)
4225 {
4226         struct drm_i915_gem_busy *args = data;
4227         struct drm_gem_object *obj;
4228         struct drm_i915_gem_object *obj_priv;
4229
4230         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4231         if (obj == NULL) {
4232                 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4233                           args->handle);
4234                 return -EBADF;
4235         }
4236
4237         mutex_lock(&dev->struct_mutex);
4238         /* Update the active list for the hardware's current position.
4239          * Otherwise this only updates on a delayed timer or when irqs are
4240          * actually unmasked, and our working set ends up being larger than
4241          * required.
4242          */
4243         i915_gem_retire_requests(dev);
4244
4245         obj_priv = obj->driver_private;
4246         /* Don't count being on the flushing list against the object being
4247          * done.  Otherwise, a buffer left on the flushing list but not getting
4248          * flushed (because nobody's flushing that domain) won't ever return
4249          * unbusy and get reused by libdrm's bo cache.  The other expected
4250          * consumer of this interface, OpenGL's occlusion queries, also specs
4251          * that the objects get unbusy "eventually" without any interference.
4252          */
4253         args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
4254
4255         drm_gem_object_unreference(obj);
4256         mutex_unlock(&dev->struct_mutex);
4257         return 0;
4258 }
4259
4260 int
4261 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4262                         struct drm_file *file_priv)
4263 {
4264     return i915_gem_ring_throttle(dev, file_priv);
4265 }
4266
4267 int
4268 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4269                        struct drm_file *file_priv)
4270 {
4271         struct drm_i915_gem_madvise *args = data;
4272         struct drm_gem_object *obj;
4273         struct drm_i915_gem_object *obj_priv;
4274
4275         switch (args->madv) {
4276         case I915_MADV_DONTNEED:
4277         case I915_MADV_WILLNEED:
4278             break;
4279         default:
4280             return -EINVAL;
4281         }
4282
4283         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4284         if (obj == NULL) {
4285                 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4286                           args->handle);
4287                 return -EBADF;
4288         }
4289
4290         mutex_lock(&dev->struct_mutex);
4291         obj_priv = obj->driver_private;
4292
4293         if (obj_priv->pin_count) {
4294                 drm_gem_object_unreference(obj);
4295                 mutex_unlock(&dev->struct_mutex);
4296
4297                 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4298                 return -EINVAL;
4299         }
4300
4301         if (obj_priv->madv != __I915_MADV_PURGED)
4302                 obj_priv->madv = args->madv;
4303
4304         /* if the object is no longer bound, discard its backing storage */
4305         if (i915_gem_object_is_purgeable(obj_priv) &&
4306             obj_priv->gtt_space == NULL)
4307                 i915_gem_object_truncate(obj);
4308
4309         args->retained = obj_priv->madv != __I915_MADV_PURGED;
4310
4311         drm_gem_object_unreference(obj);
4312         mutex_unlock(&dev->struct_mutex);
4313
4314         return 0;
4315 }
4316
4317 int i915_gem_init_object(struct drm_gem_object *obj)
4318 {
4319         struct drm_i915_gem_object *obj_priv;
4320
4321         obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL);
4322         if (obj_priv == NULL)
4323                 return -ENOMEM;
4324
4325         /*
4326          * We've just allocated pages from the kernel,
4327          * so they've just been written by the CPU with
4328          * zeros. They'll need to be clflushed before we
4329          * use them with the GPU.
4330          */
4331         obj->write_domain = I915_GEM_DOMAIN_CPU;
4332         obj->read_domains = I915_GEM_DOMAIN_CPU;
4333
4334         obj_priv->agp_type = AGP_USER_MEMORY;
4335
4336         obj->driver_private = obj_priv;
4337         obj_priv->obj = obj;
4338         obj_priv->fence_reg = I915_FENCE_REG_NONE;
4339         INIT_LIST_HEAD(&obj_priv->list);
4340         INIT_LIST_HEAD(&obj_priv->fence_list);
4341         obj_priv->madv = I915_MADV_WILLNEED;
4342
4343         trace_i915_gem_object_create(obj);
4344
4345         return 0;
4346 }
4347
4348 void i915_gem_free_object(struct drm_gem_object *obj)
4349 {
4350         struct drm_device *dev = obj->dev;
4351         struct drm_i915_gem_object *obj_priv = obj->driver_private;
4352
4353         trace_i915_gem_object_destroy(obj);
4354
4355         while (obj_priv->pin_count > 0)
4356                 i915_gem_object_unpin(obj);
4357
4358         if (obj_priv->phys_obj)
4359                 i915_gem_detach_phys_object(dev, obj);
4360
4361         i915_gem_object_unbind(obj);
4362
4363         if (obj_priv->mmap_offset)
4364                 i915_gem_free_mmap_offset(obj);
4365
4366         kfree(obj_priv->page_cpu_valid);
4367         kfree(obj_priv->bit_17);
4368         kfree(obj->driver_private);
4369 }
4370
4371 /** Unbinds all inactive objects. */
4372 static int
4373 i915_gem_evict_from_inactive_list(struct drm_device *dev)
4374 {
4375         drm_i915_private_t *dev_priv = dev->dev_private;
4376
4377         while (!list_empty(&dev_priv->mm.inactive_list)) {
4378                 struct drm_gem_object *obj;
4379                 int ret;
4380
4381                 obj = list_first_entry(&dev_priv->mm.inactive_list,
4382                                        struct drm_i915_gem_object,
4383                                        list)->obj;
4384
4385                 ret = i915_gem_object_unbind(obj);
4386                 if (ret != 0) {
4387                         DRM_ERROR("Error unbinding object: %d\n", ret);
4388                         return ret;
4389                 }
4390         }
4391
4392         return 0;
4393 }
4394
4395 int
4396 i915_gem_idle(struct drm_device *dev)
4397 {
4398         drm_i915_private_t *dev_priv = dev->dev_private;
4399         uint32_t seqno, cur_seqno, last_seqno;
4400         int stuck, ret;
4401
4402         mutex_lock(&dev->struct_mutex);
4403
4404         if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
4405                 mutex_unlock(&dev->struct_mutex);
4406                 return 0;
4407         }
4408
4409         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
4410          * We need to replace this with a semaphore, or something.
4411          */
4412         dev_priv->mm.suspended = 1;
4413         del_timer(&dev_priv->hangcheck_timer);
4414
4415         /* Cancel the retire work handler, wait for it to finish if running
4416          */
4417         mutex_unlock(&dev->struct_mutex);
4418         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4419         mutex_lock(&dev->struct_mutex);
4420
4421         i915_kernel_lost_context(dev);
4422
4423         /* Flush the GPU along with all non-CPU write domains
4424          */
4425         i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
4426         seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
4427
4428         if (seqno == 0) {
4429                 mutex_unlock(&dev->struct_mutex);
4430                 return -ENOMEM;
4431         }
4432
4433         dev_priv->mm.waiting_gem_seqno = seqno;
4434         last_seqno = 0;
4435         stuck = 0;
4436         for (;;) {
4437                 cur_seqno = i915_get_gem_seqno(dev);
4438                 if (i915_seqno_passed(cur_seqno, seqno))
4439                         break;
4440                 if (last_seqno == cur_seqno) {
4441                         if (stuck++ > 100) {
4442                                 DRM_ERROR("hardware wedged\n");
4443                                 atomic_set(&dev_priv->mm.wedged, 1);
4444                                 DRM_WAKEUP(&dev_priv->irq_queue);
4445                                 break;
4446                         }
4447                 }
4448                 msleep(10);
4449                 last_seqno = cur_seqno;
4450         }
4451         dev_priv->mm.waiting_gem_seqno = 0;
4452
4453         i915_gem_retire_requests(dev);
4454
4455         spin_lock(&dev_priv->mm.active_list_lock);
4456         if (!atomic_read(&dev_priv->mm.wedged)) {
4457                 /* Active and flushing should now be empty as we've
4458                  * waited for a sequence higher than any pending execbuffer
4459                  */
4460                 WARN_ON(!list_empty(&dev_priv->mm.active_list));
4461                 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
4462                 /* Request should now be empty as we've also waited
4463                  * for the last request in the list
4464                  */
4465                 WARN_ON(!list_empty(&dev_priv->mm.request_list));
4466         }
4467
4468         /* Empty the active and flushing lists to inactive.  If there's
4469          * anything left at this point, it means that we're wedged and
4470          * nothing good's going to happen by leaving them there.  So strip
4471          * the GPU domains and just stuff them onto inactive.
4472          */
4473         while (!list_empty(&dev_priv->mm.active_list)) {
4474                 struct drm_gem_object *obj;
4475                 uint32_t old_write_domain;
4476
4477                 obj = list_first_entry(&dev_priv->mm.active_list,
4478                                        struct drm_i915_gem_object,
4479                                        list)->obj;
4480                 old_write_domain = obj->write_domain;
4481                 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4482                 i915_gem_object_move_to_inactive(obj);
4483
4484                 trace_i915_gem_object_change_domain(obj,
4485                                                     obj->read_domains,
4486                                                     old_write_domain);
4487         }
4488         spin_unlock(&dev_priv->mm.active_list_lock);
4489
4490         while (!list_empty(&dev_priv->mm.flushing_list)) {
4491                 struct drm_gem_object *obj;
4492                 uint32_t old_write_domain;
4493
4494                 obj = list_first_entry(&dev_priv->mm.flushing_list,
4495                                        struct drm_i915_gem_object,
4496                                        list)->obj;
4497                 old_write_domain = obj->write_domain;
4498                 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4499                 i915_gem_object_move_to_inactive(obj);
4500
4501                 trace_i915_gem_object_change_domain(obj,
4502                                                     obj->read_domains,
4503                                                     old_write_domain);
4504         }
4505
4506
4507         /* Move all inactive buffers out of the GTT. */
4508         ret = i915_gem_evict_from_inactive_list(dev);
4509         WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
4510         if (ret) {
4511                 mutex_unlock(&dev->struct_mutex);
4512                 return ret;
4513         }
4514
4515         i915_gem_cleanup_ringbuffer(dev);
4516         mutex_unlock(&dev->struct_mutex);
4517
4518         return 0;
4519 }
4520
4521 static int
4522 i915_gem_init_hws(struct drm_device *dev)
4523 {
4524         drm_i915_private_t *dev_priv = dev->dev_private;
4525         struct drm_gem_object *obj;
4526         struct drm_i915_gem_object *obj_priv;
4527         int ret;
4528
4529         /* If we need a physical address for the status page, it's already
4530          * initialized at driver load time.
4531          */
4532         if (!I915_NEED_GFX_HWS(dev))
4533                 return 0;
4534
4535         obj = drm_gem_object_alloc(dev, 4096);
4536         if (obj == NULL) {
4537                 DRM_ERROR("Failed to allocate status page\n");
4538                 return -ENOMEM;
4539         }
4540         obj_priv = obj->driver_private;
4541         obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4542
4543         ret = i915_gem_object_pin(obj, 4096);
4544         if (ret != 0) {
4545                 drm_gem_object_unreference(obj);
4546                 return ret;
4547         }
4548
4549         dev_priv->status_gfx_addr = obj_priv->gtt_offset;
4550
4551         dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
4552         if (dev_priv->hw_status_page == NULL) {
4553                 DRM_ERROR("Failed to map status page.\n");
4554                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4555                 i915_gem_object_unpin(obj);
4556                 drm_gem_object_unreference(obj);
4557                 return -EINVAL;
4558         }
4559         dev_priv->hws_obj = obj;
4560         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4561         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
4562         I915_READ(HWS_PGA); /* posting read */
4563         DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
4564
4565         return 0;
4566 }
4567
4568 static void
4569 i915_gem_cleanup_hws(struct drm_device *dev)
4570 {
4571         drm_i915_private_t *dev_priv = dev->dev_private;
4572         struct drm_gem_object *obj;
4573         struct drm_i915_gem_object *obj_priv;
4574
4575         if (dev_priv->hws_obj == NULL)
4576                 return;
4577
4578         obj = dev_priv->hws_obj;
4579         obj_priv = obj->driver_private;
4580
4581         kunmap(obj_priv->pages[0]);
4582         i915_gem_object_unpin(obj);
4583         drm_gem_object_unreference(obj);
4584         dev_priv->hws_obj = NULL;
4585
4586         memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4587         dev_priv->hw_status_page = NULL;
4588
4589         /* Write high address into HWS_PGA when disabling. */
4590         I915_WRITE(HWS_PGA, 0x1ffff000);
4591 }
4592
4593 int
4594 i915_gem_init_ringbuffer(struct drm_device *dev)
4595 {
4596         drm_i915_private_t *dev_priv = dev->dev_private;
4597         struct drm_gem_object *obj;
4598         struct drm_i915_gem_object *obj_priv;
4599         drm_i915_ring_buffer_t *ring = &dev_priv->ring;
4600         int ret;
4601         u32 head;
4602
4603         ret = i915_gem_init_hws(dev);
4604         if (ret != 0)
4605                 return ret;
4606
4607         obj = drm_gem_object_alloc(dev, 128 * 1024);
4608         if (obj == NULL) {
4609                 DRM_ERROR("Failed to allocate ringbuffer\n");
4610                 i915_gem_cleanup_hws(dev);
4611                 return -ENOMEM;
4612         }
4613         obj_priv = obj->driver_private;
4614
4615         ret = i915_gem_object_pin(obj, 4096);
4616         if (ret != 0) {
4617                 drm_gem_object_unreference(obj);
4618                 i915_gem_cleanup_hws(dev);
4619                 return ret;
4620         }
4621
4622         /* Set up the kernel mapping for the ring. */
4623         ring->Size = obj->size;
4624
4625         ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4626         ring->map.size = obj->size;
4627         ring->map.type = 0;
4628         ring->map.flags = 0;
4629         ring->map.mtrr = 0;
4630
4631         drm_core_ioremap_wc(&ring->map, dev);
4632         if (ring->map.handle == NULL) {
4633                 DRM_ERROR("Failed to map ringbuffer.\n");
4634                 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4635                 i915_gem_object_unpin(obj);
4636                 drm_gem_object_unreference(obj);
4637                 i915_gem_cleanup_hws(dev);
4638                 return -EINVAL;
4639         }
4640         ring->ring_obj = obj;
4641         ring->virtual_start = ring->map.handle;
4642
4643         /* Stop the ring if it's running. */
4644         I915_WRITE(PRB0_CTL, 0);
4645         I915_WRITE(PRB0_TAIL, 0);
4646         I915_WRITE(PRB0_HEAD, 0);
4647
4648         /* Initialize the ring. */
4649         I915_WRITE(PRB0_START, obj_priv->gtt_offset);
4650         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4651
4652         /* G45 ring initialization fails to reset head to zero */
4653         if (head != 0) {
4654                 DRM_ERROR("Ring head not reset to zero "
4655                           "ctl %08x head %08x tail %08x start %08x\n",
4656                           I915_READ(PRB0_CTL),
4657                           I915_READ(PRB0_HEAD),
4658                           I915_READ(PRB0_TAIL),
4659                           I915_READ(PRB0_START));
4660                 I915_WRITE(PRB0_HEAD, 0);
4661
4662                 DRM_ERROR("Ring head forced to zero "
4663                           "ctl %08x head %08x tail %08x start %08x\n",
4664                           I915_READ(PRB0_CTL),
4665                           I915_READ(PRB0_HEAD),
4666                           I915_READ(PRB0_TAIL),
4667                           I915_READ(PRB0_START));
4668         }
4669
4670         I915_WRITE(PRB0_CTL,
4671                    ((obj->size - 4096) & RING_NR_PAGES) |
4672                    RING_NO_REPORT |
4673                    RING_VALID);
4674
4675         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4676
4677         /* If the head is still not zero, the ring is dead */
4678         if (head != 0) {
4679                 DRM_ERROR("Ring initialization failed "
4680                           "ctl %08x head %08x tail %08x start %08x\n",
4681                           I915_READ(PRB0_CTL),
4682                           I915_READ(PRB0_HEAD),
4683                           I915_READ(PRB0_TAIL),
4684                           I915_READ(PRB0_START));
4685                 return -EIO;
4686         }
4687
4688         /* Update our cache of the ring state */
4689         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4690                 i915_kernel_lost_context(dev);
4691         else {
4692                 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4693                 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4694                 ring->space = ring->head - (ring->tail + 8);
4695                 if (ring->space < 0)
4696                         ring->space += ring->Size;
4697         }
4698
4699         return 0;
4700 }
4701
4702 void
4703 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4704 {
4705         drm_i915_private_t *dev_priv = dev->dev_private;
4706
4707         if (dev_priv->ring.ring_obj == NULL)
4708                 return;
4709
4710         drm_core_ioremapfree(&dev_priv->ring.map, dev);
4711
4712         i915_gem_object_unpin(dev_priv->ring.ring_obj);
4713         drm_gem_object_unreference(dev_priv->ring.ring_obj);
4714         dev_priv->ring.ring_obj = NULL;
4715         memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4716
4717         i915_gem_cleanup_hws(dev);
4718 }
4719
4720 int
4721 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4722                        struct drm_file *file_priv)
4723 {
4724         drm_i915_private_t *dev_priv = dev->dev_private;
4725         int ret;
4726
4727         if (drm_core_check_feature(dev, DRIVER_MODESET))
4728                 return 0;
4729
4730         if (atomic_read(&dev_priv->mm.wedged)) {
4731                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4732                 atomic_set(&dev_priv->mm.wedged, 0);
4733         }
4734
4735         mutex_lock(&dev->struct_mutex);
4736         dev_priv->mm.suspended = 0;
4737
4738         ret = i915_gem_init_ringbuffer(dev);
4739         if (ret != 0) {
4740                 mutex_unlock(&dev->struct_mutex);
4741                 return ret;
4742         }
4743
4744         spin_lock(&dev_priv->mm.active_list_lock);
4745         BUG_ON(!list_empty(&dev_priv->mm.active_list));
4746         spin_unlock(&dev_priv->mm.active_list_lock);
4747
4748         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4749         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4750         BUG_ON(!list_empty(&dev_priv->mm.request_list));
4751         mutex_unlock(&dev->struct_mutex);
4752
4753         drm_irq_install(dev);
4754
4755         return 0;
4756 }
4757
4758 int
4759 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4760                        struct drm_file *file_priv)
4761 {
4762         if (drm_core_check_feature(dev, DRIVER_MODESET))
4763                 return 0;
4764
4765         drm_irq_uninstall(dev);
4766         return i915_gem_idle(dev);
4767 }
4768
4769 void
4770 i915_gem_lastclose(struct drm_device *dev)
4771 {
4772         int ret;
4773
4774         if (drm_core_check_feature(dev, DRIVER_MODESET))
4775                 return;
4776
4777         ret = i915_gem_idle(dev);
4778         if (ret)
4779                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4780 }
4781
4782 void
4783 i915_gem_load(struct drm_device *dev)
4784 {
4785         int i;
4786         drm_i915_private_t *dev_priv = dev->dev_private;
4787
4788         spin_lock_init(&dev_priv->mm.active_list_lock);
4789         INIT_LIST_HEAD(&dev_priv->mm.active_list);
4790         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4791         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4792         INIT_LIST_HEAD(&dev_priv->mm.request_list);
4793         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4794         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4795                           i915_gem_retire_work_handler);
4796         dev_priv->mm.next_gem_seqno = 1;
4797
4798         spin_lock(&shrink_list_lock);
4799         list_add(&dev_priv->mm.shrink_list, &shrink_list);
4800         spin_unlock(&shrink_list_lock);
4801
4802         /* Old X drivers will take 0-2 for front, back, depth buffers */
4803         dev_priv->fence_reg_start = 3;
4804
4805         if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4806                 dev_priv->num_fence_regs = 16;
4807         else
4808                 dev_priv->num_fence_regs = 8;
4809
4810         /* Initialize fence registers to zero */
4811         if (IS_I965G(dev)) {
4812                 for (i = 0; i < 16; i++)
4813                         I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4814         } else {
4815                 for (i = 0; i < 8; i++)
4816                         I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4817                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4818                         for (i = 0; i < 8; i++)
4819                                 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4820         }
4821         i915_gem_detect_bit_6_swizzle(dev);
4822         init_waitqueue_head(&dev_priv->pending_flip_queue);
4823 }
4824
4825 /*
4826  * Create a physically contiguous memory object for this object
4827  * e.g. for cursor + overlay regs
4828  */
4829 int i915_gem_init_phys_object(struct drm_device *dev,
4830                               int id, int size)
4831 {
4832         drm_i915_private_t *dev_priv = dev->dev_private;
4833         struct drm_i915_gem_phys_object *phys_obj;
4834         int ret;
4835
4836         if (dev_priv->mm.phys_objs[id - 1] || !size)
4837                 return 0;
4838
4839         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4840         if (!phys_obj)
4841                 return -ENOMEM;
4842
4843         phys_obj->id = id;
4844
4845         phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
4846         if (!phys_obj->handle) {
4847                 ret = -ENOMEM;
4848                 goto kfree_obj;
4849         }
4850 #ifdef CONFIG_X86
4851         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4852 #endif
4853
4854         dev_priv->mm.phys_objs[id - 1] = phys_obj;
4855
4856         return 0;
4857 kfree_obj:
4858         kfree(phys_obj);
4859         return ret;
4860 }
4861
4862 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4863 {
4864         drm_i915_private_t *dev_priv = dev->dev_private;
4865         struct drm_i915_gem_phys_object *phys_obj;
4866
4867         if (!dev_priv->mm.phys_objs[id - 1])
4868                 return;
4869
4870         phys_obj = dev_priv->mm.phys_objs[id - 1];
4871         if (phys_obj->cur_obj) {
4872                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4873         }
4874
4875 #ifdef CONFIG_X86
4876         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4877 #endif
4878         drm_pci_free(dev, phys_obj->handle);
4879         kfree(phys_obj);
4880         dev_priv->mm.phys_objs[id - 1] = NULL;
4881 }
4882
4883 void i915_gem_free_all_phys_object(struct drm_device *dev)
4884 {
4885         int i;
4886
4887         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4888                 i915_gem_free_phys_object(dev, i);
4889 }
4890
4891 void i915_gem_detach_phys_object(struct drm_device *dev,
4892                                  struct drm_gem_object *obj)
4893 {
4894         struct drm_i915_gem_object *obj_priv;
4895         int i;
4896         int ret;
4897         int page_count;
4898
4899         obj_priv = obj->driver_private;
4900         if (!obj_priv->phys_obj)
4901                 return;
4902
4903         ret = i915_gem_object_get_pages(obj);
4904         if (ret)
4905                 goto out;
4906
4907         page_count = obj->size / PAGE_SIZE;
4908
4909         for (i = 0; i < page_count; i++) {
4910                 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4911                 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4912
4913                 memcpy(dst, src, PAGE_SIZE);
4914                 kunmap_atomic(dst, KM_USER0);
4915         }
4916         drm_clflush_pages(obj_priv->pages, page_count);
4917         drm_agp_chipset_flush(dev);
4918
4919         i915_gem_object_put_pages(obj);
4920 out:
4921         obj_priv->phys_obj->cur_obj = NULL;
4922         obj_priv->phys_obj = NULL;
4923 }
4924
4925 int
4926 i915_gem_attach_phys_object(struct drm_device *dev,
4927                             struct drm_gem_object *obj, int id)
4928 {
4929         drm_i915_private_t *dev_priv = dev->dev_private;
4930         struct drm_i915_gem_object *obj_priv;
4931         int ret = 0;
4932         int page_count;
4933         int i;
4934
4935         if (id > I915_MAX_PHYS_OBJECT)
4936                 return -EINVAL;
4937
4938         obj_priv = obj->driver_private;
4939
4940         if (obj_priv->phys_obj) {
4941                 if (obj_priv->phys_obj->id == id)
4942                         return 0;
4943                 i915_gem_detach_phys_object(dev, obj);
4944         }
4945
4946
4947         /* create a new object */
4948         if (!dev_priv->mm.phys_objs[id - 1]) {
4949                 ret = i915_gem_init_phys_object(dev, id,
4950                                                 obj->size);
4951                 if (ret) {
4952                         DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4953                         goto out;
4954                 }
4955         }
4956
4957         /* bind to the object */
4958         obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4959         obj_priv->phys_obj->cur_obj = obj;
4960
4961         ret = i915_gem_object_get_pages(obj);
4962         if (ret) {
4963                 DRM_ERROR("failed to get page list\n");
4964                 goto out;
4965         }
4966
4967         page_count = obj->size / PAGE_SIZE;
4968
4969         for (i = 0; i < page_count; i++) {
4970                 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4971                 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4972
4973                 memcpy(dst, src, PAGE_SIZE);
4974                 kunmap_atomic(src, KM_USER0);
4975         }
4976
4977         i915_gem_object_put_pages(obj);
4978
4979         return 0;
4980 out:
4981         return ret;
4982 }
4983
4984 static int
4985 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4986                      struct drm_i915_gem_pwrite *args,
4987                      struct drm_file *file_priv)
4988 {
4989         struct drm_i915_gem_object *obj_priv = obj->driver_private;
4990         void *obj_addr;
4991         int ret;
4992         char __user *user_data;
4993
4994         user_data = (char __user *) (uintptr_t) args->data_ptr;
4995         obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4996
4997         DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
4998         ret = copy_from_user(obj_addr, user_data, args->size);
4999         if (ret)
5000                 return -EFAULT;
5001
5002         drm_agp_chipset_flush(dev);
5003         return 0;
5004 }
5005
5006 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
5007 {
5008         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
5009
5010         /* Clean up our request list when the client is going away, so that
5011          * later retire_requests won't dereference our soon-to-be-gone
5012          * file_priv.
5013          */
5014         mutex_lock(&dev->struct_mutex);
5015         while (!list_empty(&i915_file_priv->mm.request_list))
5016                 list_del_init(i915_file_priv->mm.request_list.next);
5017         mutex_unlock(&dev->struct_mutex);
5018 }
5019
5020 static int
5021 i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
5022 {
5023         drm_i915_private_t *dev_priv, *next_dev;
5024         struct drm_i915_gem_object *obj_priv, *next_obj;
5025         int cnt = 0;
5026         int would_deadlock = 1;
5027
5028         /* "fast-path" to count number of available objects */
5029         if (nr_to_scan == 0) {
5030                 spin_lock(&shrink_list_lock);
5031                 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5032                         struct drm_device *dev = dev_priv->dev;
5033
5034                         if (mutex_trylock(&dev->struct_mutex)) {
5035                                 list_for_each_entry(obj_priv,
5036                                                     &dev_priv->mm.inactive_list,
5037                                                     list)
5038                                         cnt++;
5039                                 mutex_unlock(&dev->struct_mutex);
5040                         }
5041                 }
5042                 spin_unlock(&shrink_list_lock);
5043
5044                 return (cnt / 100) * sysctl_vfs_cache_pressure;
5045         }
5046
5047         spin_lock(&shrink_list_lock);
5048
5049         /* first scan for clean buffers */
5050         list_for_each_entry_safe(dev_priv, next_dev,
5051                                  &shrink_list, mm.shrink_list) {
5052                 struct drm_device *dev = dev_priv->dev;
5053
5054                 if (! mutex_trylock(&dev->struct_mutex))
5055                         continue;
5056
5057                 spin_unlock(&shrink_list_lock);
5058
5059                 i915_gem_retire_requests(dev);
5060
5061                 list_for_each_entry_safe(obj_priv, next_obj,
5062                                          &dev_priv->mm.inactive_list,
5063                                          list) {
5064                         if (i915_gem_object_is_purgeable(obj_priv)) {
5065                                 i915_gem_object_unbind(obj_priv->obj);
5066                                 if (--nr_to_scan <= 0)
5067                                         break;
5068                         }
5069                 }
5070
5071                 spin_lock(&shrink_list_lock);
5072                 mutex_unlock(&dev->struct_mutex);
5073
5074                 would_deadlock = 0;
5075
5076                 if (nr_to_scan <= 0)
5077                         break;
5078         }
5079
5080         /* second pass, evict/count anything still on the inactive list */
5081         list_for_each_entry_safe(dev_priv, next_dev,
5082                                  &shrink_list, mm.shrink_list) {
5083                 struct drm_device *dev = dev_priv->dev;
5084
5085                 if (! mutex_trylock(&dev->struct_mutex))
5086                         continue;
5087
5088                 spin_unlock(&shrink_list_lock);
5089
5090                 list_for_each_entry_safe(obj_priv, next_obj,
5091                                          &dev_priv->mm.inactive_list,
5092                                          list) {
5093                         if (nr_to_scan > 0) {
5094                                 i915_gem_object_unbind(obj_priv->obj);
5095                                 nr_to_scan--;
5096                         } else
5097                                 cnt++;
5098                 }
5099
5100                 spin_lock(&shrink_list_lock);
5101                 mutex_unlock(&dev->struct_mutex);
5102
5103                 would_deadlock = 0;
5104         }
5105
5106         spin_unlock(&shrink_list_lock);
5107
5108         if (would_deadlock)
5109                 return -1;
5110         else if (cnt > 0)
5111                 return (cnt / 100) * sysctl_vfs_cache_pressure;
5112         else
5113                 return 0;
5114 }
5115
5116 static struct shrinker shrinker = {
5117         .shrink = i915_gem_shrink,
5118         .seeks = DEFAULT_SEEKS,
5119 };
5120
5121 __init void
5122 i915_gem_shrinker_init(void)
5123 {
5124     register_shrinker(&shrinker);
5125 }
5126
5127 __exit void
5128 i915_gem_shrinker_exit(void)
5129 {
5130     unregister_shrinker(&shrinker);
5131 }