drm/i915: hold forcewake around ring hw init
[linux-2.6.git] / drivers / gpu / drm / i915 / i915_drv.c
1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2  */
3 /*
4  *
5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6  * All Rights Reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the
10  * "Software"), to deal in the Software without restriction, including
11  * without limitation the rights to use, copy, modify, merge, publish,
12  * distribute, sub license, and/or sell copies of the Software, and to
13  * permit persons to whom the Software is furnished to do so, subject to
14  * the following conditions:
15  *
16  * The above copyright notice and this permission notice (including the
17  * next paragraph) shall be included in all copies or substantial portions
18  * of the Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27  *
28  */
29
30 #include <linux/device.h>
31 #include "drmP.h"
32 #include "drm.h"
33 #include "i915_drm.h"
34 #include "i915_drv.h"
35 #include "intel_drv.h"
36
37 #include <linux/console.h>
38 #include <linux/module.h>
39 #include "drm_crtc_helper.h"
40
41 static int i915_modeset __read_mostly = -1;
42 module_param_named(modeset, i915_modeset, int, 0400);
43 MODULE_PARM_DESC(modeset,
44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
45                 "1=on, -1=force vga console preference [default])");
46
47 unsigned int i915_fbpercrtc __always_unused = 0;
48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
49
50 int i915_panel_ignore_lid __read_mostly = 0;
51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
52 MODULE_PARM_DESC(panel_ignore_lid,
53                 "Override lid status (0=autodetect [default], 1=lid open, "
54                 "-1=lid closed)");
55
56 unsigned int i915_powersave __read_mostly = 1;
57 module_param_named(powersave, i915_powersave, int, 0600);
58 MODULE_PARM_DESC(powersave,
59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
60
61 int i915_semaphores __read_mostly = -1;
62 module_param_named(semaphores, i915_semaphores, int, 0600);
63 MODULE_PARM_DESC(semaphores,
64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
65
66 int i915_enable_rc6 __read_mostly = -1;
67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
68 MODULE_PARM_DESC(i915_enable_rc6,
69                 "Enable power-saving render C-state 6. "
70                 "Different stages can be selected via bitmask values "
71                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
72                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
73                 "default: -1 (use per-chip default)");
74
75 int i915_enable_fbc __read_mostly = -1;
76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
77 MODULE_PARM_DESC(i915_enable_fbc,
78                 "Enable frame buffer compression for power savings "
79                 "(default: -1 (use per-chip default))");
80
81 unsigned int i915_lvds_downclock __read_mostly = 0;
82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
83 MODULE_PARM_DESC(lvds_downclock,
84                 "Use panel (LVDS/eDP) downclocking for power savings "
85                 "(default: false)");
86
87 int i915_panel_use_ssc __read_mostly = -1;
88 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
89 MODULE_PARM_DESC(lvds_use_ssc,
90                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
91                 "(default: auto from VBT)");
92
93 int i915_vbt_sdvo_panel_type __read_mostly = -1;
94 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
95 MODULE_PARM_DESC(vbt_sdvo_panel_type,
96                 "Override selection of SDVO panel mode in the VBT "
97                 "(default: auto)");
98
99 static bool i915_try_reset __read_mostly = true;
100 module_param_named(reset, i915_try_reset, bool, 0600);
101 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
102
103 bool i915_enable_hangcheck __read_mostly = true;
104 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
105 MODULE_PARM_DESC(enable_hangcheck,
106                 "Periodically check GPU activity for detecting hangs. "
107                 "WARNING: Disabling this can cause system wide hangs. "
108                 "(default: true)");
109
110 int i915_enable_ppgtt __read_mostly = -1;
111 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
112 MODULE_PARM_DESC(i915_enable_ppgtt,
113                 "Enable PPGTT (default: true)");
114
115 static struct drm_driver driver;
116 extern int intel_agp_enabled;
117
118 #define INTEL_VGA_DEVICE(id, info) {            \
119         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
120         .class_mask = 0xff0000,                 \
121         .vendor = 0x8086,                       \
122         .device = id,                           \
123         .subvendor = PCI_ANY_ID,                \
124         .subdevice = PCI_ANY_ID,                \
125         .driver_data = (unsigned long) info }
126
127 static const struct intel_device_info intel_i830_info = {
128         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
129         .has_overlay = 1, .overlay_needs_physical = 1,
130 };
131
132 static const struct intel_device_info intel_845g_info = {
133         .gen = 2,
134         .has_overlay = 1, .overlay_needs_physical = 1,
135 };
136
137 static const struct intel_device_info intel_i85x_info = {
138         .gen = 2, .is_i85x = 1, .is_mobile = 1,
139         .cursor_needs_physical = 1,
140         .has_overlay = 1, .overlay_needs_physical = 1,
141 };
142
143 static const struct intel_device_info intel_i865g_info = {
144         .gen = 2,
145         .has_overlay = 1, .overlay_needs_physical = 1,
146 };
147
148 static const struct intel_device_info intel_i915g_info = {
149         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
150         .has_overlay = 1, .overlay_needs_physical = 1,
151 };
152 static const struct intel_device_info intel_i915gm_info = {
153         .gen = 3, .is_mobile = 1,
154         .cursor_needs_physical = 1,
155         .has_overlay = 1, .overlay_needs_physical = 1,
156         .supports_tv = 1,
157 };
158 static const struct intel_device_info intel_i945g_info = {
159         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
160         .has_overlay = 1, .overlay_needs_physical = 1,
161 };
162 static const struct intel_device_info intel_i945gm_info = {
163         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
164         .has_hotplug = 1, .cursor_needs_physical = 1,
165         .has_overlay = 1, .overlay_needs_physical = 1,
166         .supports_tv = 1,
167 };
168
169 static const struct intel_device_info intel_i965g_info = {
170         .gen = 4, .is_broadwater = 1,
171         .has_hotplug = 1,
172         .has_overlay = 1,
173 };
174
175 static const struct intel_device_info intel_i965gm_info = {
176         .gen = 4, .is_crestline = 1,
177         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
178         .has_overlay = 1,
179         .supports_tv = 1,
180 };
181
182 static const struct intel_device_info intel_g33_info = {
183         .gen = 3, .is_g33 = 1,
184         .need_gfx_hws = 1, .has_hotplug = 1,
185         .has_overlay = 1,
186 };
187
188 static const struct intel_device_info intel_g45_info = {
189         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
190         .has_pipe_cxsr = 1, .has_hotplug = 1,
191         .has_bsd_ring = 1,
192 };
193
194 static const struct intel_device_info intel_gm45_info = {
195         .gen = 4, .is_g4x = 1,
196         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
197         .has_pipe_cxsr = 1, .has_hotplug = 1,
198         .supports_tv = 1,
199         .has_bsd_ring = 1,
200 };
201
202 static const struct intel_device_info intel_pineview_info = {
203         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
204         .need_gfx_hws = 1, .has_hotplug = 1,
205         .has_overlay = 1,
206 };
207
208 static const struct intel_device_info intel_ironlake_d_info = {
209         .gen = 5,
210         .need_gfx_hws = 1, .has_hotplug = 1,
211         .has_bsd_ring = 1,
212 };
213
214 static const struct intel_device_info intel_ironlake_m_info = {
215         .gen = 5, .is_mobile = 1,
216         .need_gfx_hws = 1, .has_hotplug = 1,
217         .has_fbc = 1,
218         .has_bsd_ring = 1,
219 };
220
221 static const struct intel_device_info intel_sandybridge_d_info = {
222         .gen = 6,
223         .need_gfx_hws = 1, .has_hotplug = 1,
224         .has_bsd_ring = 1,
225         .has_blt_ring = 1,
226         .has_llc = 1,
227         .has_force_wake = 1,
228 };
229
230 static const struct intel_device_info intel_sandybridge_m_info = {
231         .gen = 6, .is_mobile = 1,
232         .need_gfx_hws = 1, .has_hotplug = 1,
233         .has_fbc = 1,
234         .has_bsd_ring = 1,
235         .has_blt_ring = 1,
236         .has_llc = 1,
237         .has_force_wake = 1,
238 };
239
240 static const struct intel_device_info intel_ivybridge_d_info = {
241         .is_ivybridge = 1, .gen = 7,
242         .need_gfx_hws = 1, .has_hotplug = 1,
243         .has_bsd_ring = 1,
244         .has_blt_ring = 1,
245         .has_llc = 1,
246         .has_force_wake = 1,
247 };
248
249 static const struct intel_device_info intel_ivybridge_m_info = {
250         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
251         .need_gfx_hws = 1, .has_hotplug = 1,
252         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
253         .has_bsd_ring = 1,
254         .has_blt_ring = 1,
255         .has_llc = 1,
256         .has_force_wake = 1,
257 };
258
259 static const struct pci_device_id pciidlist[] = {               /* aka */
260         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
261         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
262         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
263         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
264         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
265         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
266         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
267         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
268         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
269         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
270         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
271         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
272         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
273         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
274         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
275         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
276         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
277         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
278         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
279         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
280         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
281         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
282         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
283         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
284         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
285         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
286         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
287         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
288         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
289         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
290         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
291         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
292         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
293         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
294         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
295         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
296         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
297         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
298         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
299         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
300         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
301         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
302         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
303         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
304         {0, 0, 0}
305 };
306
307 #if defined(CONFIG_DRM_I915_KMS)
308 MODULE_DEVICE_TABLE(pci, pciidlist);
309 #endif
310
311 #define INTEL_PCH_DEVICE_ID_MASK        0xff00
312 #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
313 #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
314 #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
315
316 void intel_detect_pch(struct drm_device *dev)
317 {
318         struct drm_i915_private *dev_priv = dev->dev_private;
319         struct pci_dev *pch;
320
321         /*
322          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
323          * make graphics device passthrough work easy for VMM, that only
324          * need to expose ISA bridge to let driver know the real hardware
325          * underneath. This is a requirement from virtualization team.
326          */
327         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
328         if (pch) {
329                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
330                         int id;
331                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
332
333                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
334                                 dev_priv->pch_type = PCH_IBX;
335                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
336                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
337                                 dev_priv->pch_type = PCH_CPT;
338                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
339                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
340                                 /* PantherPoint is CPT compatible */
341                                 dev_priv->pch_type = PCH_CPT;
342                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
343                         }
344                 }
345                 pci_dev_put(pch);
346         }
347 }
348
349 void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
350 {
351         int count;
352
353         count = 0;
354         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
355                 udelay(10);
356
357         I915_WRITE_NOTRACE(FORCEWAKE, 1);
358         POSTING_READ(FORCEWAKE);
359
360         count = 0;
361         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
362                 udelay(10);
363 }
364
365 void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
366 {
367         int count;
368
369         count = 0;
370         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
371                 udelay(10);
372
373         I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1);
374         POSTING_READ(FORCEWAKE_MT);
375
376         count = 0;
377         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
378                 udelay(10);
379 }
380
381 /*
382  * Generally this is called implicitly by the register read function. However,
383  * if some sequence requires the GT to not power down then this function should
384  * be called at the beginning of the sequence followed by a call to
385  * gen6_gt_force_wake_put() at the end of the sequence.
386  */
387 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
388 {
389         unsigned long irqflags;
390
391         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
392         if (dev_priv->forcewake_count++ == 0)
393                 dev_priv->display.force_wake_get(dev_priv);
394         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
395 }
396
397 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
398 {
399         u32 gtfifodbg;
400         gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
401         if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
402              "MMIO read or write has been dropped %x\n", gtfifodbg))
403                 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
404 }
405
406 void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
407 {
408         I915_WRITE_NOTRACE(FORCEWAKE, 0);
409         /* The below doubles as a POSTING_READ */
410         gen6_gt_check_fifodbg(dev_priv);
411 }
412
413 void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
414 {
415         I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0);
416         /* The below doubles as a POSTING_READ */
417         gen6_gt_check_fifodbg(dev_priv);
418 }
419
420 /*
421  * see gen6_gt_force_wake_get()
422  */
423 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
424 {
425         unsigned long irqflags;
426
427         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
428         if (--dev_priv->forcewake_count == 0)
429                 dev_priv->display.force_wake_put(dev_priv);
430         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
431 }
432
433 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
434 {
435         int ret = 0;
436
437         if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
438                 int loop = 500;
439                 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
440                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
441                         udelay(10);
442                         fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
443                 }
444                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
445                         ++ret;
446                 dev_priv->gt_fifo_count = fifo;
447         }
448         dev_priv->gt_fifo_count--;
449
450         return ret;
451 }
452
453 static int i915_drm_freeze(struct drm_device *dev)
454 {
455         struct drm_i915_private *dev_priv = dev->dev_private;
456
457         drm_kms_helper_poll_disable(dev);
458
459         pci_save_state(dev->pdev);
460
461         /* If KMS is active, we do the leavevt stuff here */
462         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
463                 int error = i915_gem_idle(dev);
464                 if (error) {
465                         dev_err(&dev->pdev->dev,
466                                 "GEM idle failed, resume might fail\n");
467                         return error;
468                 }
469                 drm_irq_uninstall(dev);
470         }
471
472         i915_save_state(dev);
473
474         intel_opregion_fini(dev);
475
476         /* Modeset on resume, not lid events */
477         dev_priv->modeset_on_lid = 0;
478
479         console_lock();
480         intel_fbdev_set_suspend(dev, 1);
481         console_unlock();
482
483         return 0;
484 }
485
486 int i915_suspend(struct drm_device *dev, pm_message_t state)
487 {
488         int error;
489
490         if (!dev || !dev->dev_private) {
491                 DRM_ERROR("dev: %p\n", dev);
492                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
493                 return -ENODEV;
494         }
495
496         if (state.event == PM_EVENT_PRETHAW)
497                 return 0;
498
499
500         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
501                 return 0;
502
503         error = i915_drm_freeze(dev);
504         if (error)
505                 return error;
506
507         if (state.event == PM_EVENT_SUSPEND) {
508                 /* Shut down the device */
509                 pci_disable_device(dev->pdev);
510                 pci_set_power_state(dev->pdev, PCI_D3hot);
511         }
512
513         return 0;
514 }
515
516 static int i915_drm_thaw(struct drm_device *dev)
517 {
518         struct drm_i915_private *dev_priv = dev->dev_private;
519         int error = 0;
520
521         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
522                 mutex_lock(&dev->struct_mutex);
523                 i915_gem_restore_gtt_mappings(dev);
524                 mutex_unlock(&dev->struct_mutex);
525         }
526
527         i915_restore_state(dev);
528         intel_opregion_setup(dev);
529
530         /* KMS EnterVT equivalent */
531         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
532                 mutex_lock(&dev->struct_mutex);
533                 dev_priv->mm.suspended = 0;
534
535                 error = i915_gem_init_hw(dev);
536                 mutex_unlock(&dev->struct_mutex);
537
538                 if (HAS_PCH_SPLIT(dev))
539                         ironlake_init_pch_refclk(dev);
540
541                 drm_mode_config_reset(dev);
542                 drm_irq_install(dev);
543
544                 /* Resume the modeset for every activated CRTC */
545                 mutex_lock(&dev->mode_config.mutex);
546                 drm_helper_resume_force_mode(dev);
547                 mutex_unlock(&dev->mode_config.mutex);
548
549                 if (IS_IRONLAKE_M(dev))
550                         ironlake_enable_rc6(dev);
551         }
552
553         intel_opregion_init(dev);
554
555         dev_priv->modeset_on_lid = 0;
556
557         console_lock();
558         intel_fbdev_set_suspend(dev, 0);
559         console_unlock();
560         return error;
561 }
562
563 int i915_resume(struct drm_device *dev)
564 {
565         int ret;
566
567         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
568                 return 0;
569
570         if (pci_enable_device(dev->pdev))
571                 return -EIO;
572
573         pci_set_master(dev->pdev);
574
575         ret = i915_drm_thaw(dev);
576         if (ret)
577                 return ret;
578
579         drm_kms_helper_poll_enable(dev);
580         return 0;
581 }
582
583 static int i8xx_do_reset(struct drm_device *dev, u8 flags)
584 {
585         struct drm_i915_private *dev_priv = dev->dev_private;
586
587         if (IS_I85X(dev))
588                 return -ENODEV;
589
590         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
591         POSTING_READ(D_STATE);
592
593         if (IS_I830(dev) || IS_845G(dev)) {
594                 I915_WRITE(DEBUG_RESET_I830,
595                            DEBUG_RESET_DISPLAY |
596                            DEBUG_RESET_RENDER |
597                            DEBUG_RESET_FULL);
598                 POSTING_READ(DEBUG_RESET_I830);
599                 msleep(1);
600
601                 I915_WRITE(DEBUG_RESET_I830, 0);
602                 POSTING_READ(DEBUG_RESET_I830);
603         }
604
605         msleep(1);
606
607         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
608         POSTING_READ(D_STATE);
609
610         return 0;
611 }
612
613 static int i965_reset_complete(struct drm_device *dev)
614 {
615         u8 gdrst;
616         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
617         return gdrst & 0x1;
618 }
619
620 static int i965_do_reset(struct drm_device *dev, u8 flags)
621 {
622         u8 gdrst;
623
624         /*
625          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
626          * well as the reset bit (GR/bit 0).  Setting the GR bit
627          * triggers the reset; when done, the hardware will clear it.
628          */
629         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
630         pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
631
632         return wait_for(i965_reset_complete(dev), 500);
633 }
634
635 static int ironlake_do_reset(struct drm_device *dev, u8 flags)
636 {
637         struct drm_i915_private *dev_priv = dev->dev_private;
638         u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
639         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
640         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
641 }
642
643 static int gen6_do_reset(struct drm_device *dev, u8 flags)
644 {
645         struct drm_i915_private *dev_priv = dev->dev_private;
646         int     ret;
647         unsigned long irqflags;
648
649         /* Hold gt_lock across reset to prevent any register access
650          * with forcewake not set correctly
651          */
652         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
653
654         /* Reset the chip */
655
656         /* GEN6_GDRST is not in the gt power well, no need to check
657          * for fifo space for the write or forcewake the chip for
658          * the read
659          */
660         I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
661
662         /* Spin waiting for the device to ack the reset request */
663         ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
664
665         /* If reset with a user forcewake, try to restore, otherwise turn it off */
666         if (dev_priv->forcewake_count)
667                 dev_priv->display.force_wake_get(dev_priv);
668         else
669                 dev_priv->display.force_wake_put(dev_priv);
670
671         /* Restore fifo count */
672         dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
673
674         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
675         return ret;
676 }
677
678 /**
679  * i915_reset - reset chip after a hang
680  * @dev: drm device to reset
681  * @flags: reset domains
682  *
683  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
684  * reset or otherwise an error code.
685  *
686  * Procedure is fairly simple:
687  *   - reset the chip using the reset reg
688  *   - re-init context state
689  *   - re-init hardware status page
690  *   - re-init ring buffer
691  *   - re-init interrupt state
692  *   - re-init display
693  */
694 int i915_reset(struct drm_device *dev, u8 flags)
695 {
696         drm_i915_private_t *dev_priv = dev->dev_private;
697         /*
698          * We really should only reset the display subsystem if we actually
699          * need to
700          */
701         bool need_display = true;
702         int ret;
703
704         if (!i915_try_reset)
705                 return 0;
706
707         if (!mutex_trylock(&dev->struct_mutex))
708                 return -EBUSY;
709
710         i915_gem_reset(dev);
711
712         ret = -ENODEV;
713         if (get_seconds() - dev_priv->last_gpu_reset < 5) {
714                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
715         } else switch (INTEL_INFO(dev)->gen) {
716         case 7:
717         case 6:
718                 ret = gen6_do_reset(dev, flags);
719                 break;
720         case 5:
721                 ret = ironlake_do_reset(dev, flags);
722                 break;
723         case 4:
724                 ret = i965_do_reset(dev, flags);
725                 break;
726         case 2:
727                 ret = i8xx_do_reset(dev, flags);
728                 break;
729         }
730         dev_priv->last_gpu_reset = get_seconds();
731         if (ret) {
732                 DRM_ERROR("Failed to reset chip.\n");
733                 mutex_unlock(&dev->struct_mutex);
734                 return ret;
735         }
736
737         /* Ok, now get things going again... */
738
739         /*
740          * Everything depends on having the GTT running, so we need to start
741          * there.  Fortunately we don't need to do this unless we reset the
742          * chip at a PCI level.
743          *
744          * Next we need to restore the context, but we don't use those
745          * yet either...
746          *
747          * Ring buffer needs to be re-initialized in the KMS case, or if X
748          * was running at the time of the reset (i.e. we weren't VT
749          * switched away).
750          */
751         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
752                         !dev_priv->mm.suspended) {
753                 dev_priv->mm.suspended = 0;
754
755                 i915_gem_init_swizzling(dev);
756
757                 dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
758                 if (HAS_BSD(dev))
759                     dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
760                 if (HAS_BLT(dev))
761                     dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
762
763                 i915_gem_init_ppgtt(dev);
764
765                 mutex_unlock(&dev->struct_mutex);
766                 drm_irq_uninstall(dev);
767                 drm_mode_config_reset(dev);
768                 drm_irq_install(dev);
769                 mutex_lock(&dev->struct_mutex);
770         }
771
772         mutex_unlock(&dev->struct_mutex);
773
774         /*
775          * Perform a full modeset as on later generations, e.g. Ironlake, we may
776          * need to retrain the display link and cannot just restore the register
777          * values.
778          */
779         if (need_display) {
780                 mutex_lock(&dev->mode_config.mutex);
781                 drm_helper_resume_force_mode(dev);
782                 mutex_unlock(&dev->mode_config.mutex);
783         }
784
785         return 0;
786 }
787
788
789 static int __devinit
790 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
791 {
792         /* Only bind to function 0 of the device. Early generations
793          * used function 1 as a placeholder for multi-head. This causes
794          * us confusion instead, especially on the systems where both
795          * functions have the same PCI-ID!
796          */
797         if (PCI_FUNC(pdev->devfn))
798                 return -ENODEV;
799
800         return drm_get_pci_dev(pdev, ent, &driver);
801 }
802
803 static void
804 i915_pci_remove(struct pci_dev *pdev)
805 {
806         struct drm_device *dev = pci_get_drvdata(pdev);
807
808         drm_put_dev(dev);
809 }
810
811 static int i915_pm_suspend(struct device *dev)
812 {
813         struct pci_dev *pdev = to_pci_dev(dev);
814         struct drm_device *drm_dev = pci_get_drvdata(pdev);
815         int error;
816
817         if (!drm_dev || !drm_dev->dev_private) {
818                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
819                 return -ENODEV;
820         }
821
822         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
823                 return 0;
824
825         error = i915_drm_freeze(drm_dev);
826         if (error)
827                 return error;
828
829         pci_disable_device(pdev);
830         pci_set_power_state(pdev, PCI_D3hot);
831
832         return 0;
833 }
834
835 static int i915_pm_resume(struct device *dev)
836 {
837         struct pci_dev *pdev = to_pci_dev(dev);
838         struct drm_device *drm_dev = pci_get_drvdata(pdev);
839
840         return i915_resume(drm_dev);
841 }
842
843 static int i915_pm_freeze(struct device *dev)
844 {
845         struct pci_dev *pdev = to_pci_dev(dev);
846         struct drm_device *drm_dev = pci_get_drvdata(pdev);
847
848         if (!drm_dev || !drm_dev->dev_private) {
849                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
850                 return -ENODEV;
851         }
852
853         return i915_drm_freeze(drm_dev);
854 }
855
856 static int i915_pm_thaw(struct device *dev)
857 {
858         struct pci_dev *pdev = to_pci_dev(dev);
859         struct drm_device *drm_dev = pci_get_drvdata(pdev);
860
861         return i915_drm_thaw(drm_dev);
862 }
863
864 static int i915_pm_poweroff(struct device *dev)
865 {
866         struct pci_dev *pdev = to_pci_dev(dev);
867         struct drm_device *drm_dev = pci_get_drvdata(pdev);
868
869         return i915_drm_freeze(drm_dev);
870 }
871
872 static const struct dev_pm_ops i915_pm_ops = {
873         .suspend = i915_pm_suspend,
874         .resume = i915_pm_resume,
875         .freeze = i915_pm_freeze,
876         .thaw = i915_pm_thaw,
877         .poweroff = i915_pm_poweroff,
878         .restore = i915_pm_resume,
879 };
880
881 static struct vm_operations_struct i915_gem_vm_ops = {
882         .fault = i915_gem_fault,
883         .open = drm_gem_vm_open,
884         .close = drm_gem_vm_close,
885 };
886
887 static const struct file_operations i915_driver_fops = {
888         .owner = THIS_MODULE,
889         .open = drm_open,
890         .release = drm_release,
891         .unlocked_ioctl = drm_ioctl,
892         .mmap = drm_gem_mmap,
893         .poll = drm_poll,
894         .fasync = drm_fasync,
895         .read = drm_read,
896 #ifdef CONFIG_COMPAT
897         .compat_ioctl = i915_compat_ioctl,
898 #endif
899         .llseek = noop_llseek,
900 };
901
902 static struct drm_driver driver = {
903         /* Don't use MTRRs here; the Xserver or userspace app should
904          * deal with them for Intel hardware.
905          */
906         .driver_features =
907             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
908             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
909         .load = i915_driver_load,
910         .unload = i915_driver_unload,
911         .open = i915_driver_open,
912         .lastclose = i915_driver_lastclose,
913         .preclose = i915_driver_preclose,
914         .postclose = i915_driver_postclose,
915
916         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
917         .suspend = i915_suspend,
918         .resume = i915_resume,
919
920         .device_is_agp = i915_driver_device_is_agp,
921         .reclaim_buffers = drm_core_reclaim_buffers,
922         .master_create = i915_master_create,
923         .master_destroy = i915_master_destroy,
924 #if defined(CONFIG_DEBUG_FS)
925         .debugfs_init = i915_debugfs_init,
926         .debugfs_cleanup = i915_debugfs_cleanup,
927 #endif
928         .gem_init_object = i915_gem_init_object,
929         .gem_free_object = i915_gem_free_object,
930         .gem_vm_ops = &i915_gem_vm_ops,
931         .dumb_create = i915_gem_dumb_create,
932         .dumb_map_offset = i915_gem_mmap_gtt,
933         .dumb_destroy = i915_gem_dumb_destroy,
934         .ioctls = i915_ioctls,
935         .fops = &i915_driver_fops,
936         .name = DRIVER_NAME,
937         .desc = DRIVER_DESC,
938         .date = DRIVER_DATE,
939         .major = DRIVER_MAJOR,
940         .minor = DRIVER_MINOR,
941         .patchlevel = DRIVER_PATCHLEVEL,
942 };
943
944 static struct pci_driver i915_pci_driver = {
945         .name = DRIVER_NAME,
946         .id_table = pciidlist,
947         .probe = i915_pci_probe,
948         .remove = i915_pci_remove,
949         .driver.pm = &i915_pm_ops,
950 };
951
952 static int __init i915_init(void)
953 {
954         if (!intel_agp_enabled) {
955                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
956                 return -ENODEV;
957         }
958
959         driver.num_ioctls = i915_max_ioctl;
960
961         /*
962          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
963          * explicitly disabled with the module pararmeter.
964          *
965          * Otherwise, just follow the parameter (defaulting to off).
966          *
967          * Allow optional vga_text_mode_force boot option to override
968          * the default behavior.
969          */
970 #if defined(CONFIG_DRM_I915_KMS)
971         if (i915_modeset != 0)
972                 driver.driver_features |= DRIVER_MODESET;
973 #endif
974         if (i915_modeset == 1)
975                 driver.driver_features |= DRIVER_MODESET;
976
977 #ifdef CONFIG_VGA_CONSOLE
978         if (vgacon_text_force() && i915_modeset == -1)
979                 driver.driver_features &= ~DRIVER_MODESET;
980 #endif
981
982         if (!(driver.driver_features & DRIVER_MODESET))
983                 driver.get_vblank_timestamp = NULL;
984
985         return drm_pci_init(&driver, &i915_pci_driver);
986 }
987
988 static void __exit i915_exit(void)
989 {
990         drm_pci_exit(&driver, &i915_pci_driver);
991 }
992
993 module_init(i915_init);
994 module_exit(i915_exit);
995
996 MODULE_AUTHOR(DRIVER_AUTHOR);
997 MODULE_DESCRIPTION(DRIVER_DESC);
998 MODULE_LICENSE("GPL and additional rights");
999
1000 /* We give fast paths for the really cool registers */
1001 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1002         ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1003         ((reg) < 0x40000) &&            \
1004         ((reg) != FORCEWAKE))
1005
1006 #define __i915_read(x, y) \
1007 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1008         u##x val = 0; \
1009         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1010                 unsigned long irqflags; \
1011                 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1012                 if (dev_priv->forcewake_count == 0) \
1013                         dev_priv->display.force_wake_get(dev_priv); \
1014                 val = read##y(dev_priv->regs + reg); \
1015                 if (dev_priv->forcewake_count == 0) \
1016                         dev_priv->display.force_wake_put(dev_priv); \
1017                 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1018         } else { \
1019                 val = read##y(dev_priv->regs + reg); \
1020         } \
1021         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1022         return val; \
1023 }
1024
1025 __i915_read(8, b)
1026 __i915_read(16, w)
1027 __i915_read(32, l)
1028 __i915_read(64, q)
1029 #undef __i915_read
1030
1031 #define __i915_write(x, y) \
1032 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1033         u32 __fifo_ret = 0; \
1034         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1035         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1036                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1037         } \
1038         write##y(val, dev_priv->regs + reg); \
1039         if (unlikely(__fifo_ret)) { \
1040                 gen6_gt_check_fifodbg(dev_priv); \
1041         } \
1042 }
1043 __i915_write(8, b)
1044 __i915_write(16, w)
1045 __i915_write(32, l)
1046 __i915_write(64, q)
1047 #undef __i915_write