e6800819bca846f6a3fd102ef37e2632858247f8
[linux-2.6.git] / drivers / gpu / drm / i915 / i915_dma.c
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2  */
3 /*
4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5  * All Rights Reserved.
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a
8  * copy of this software and associated documentation files (the
9  * "Software"), to deal in the Software without restriction, including
10  * without limitation the rights to use, copy, modify, merge, publish,
11  * distribute, sub license, and/or sell copies of the Software, and to
12  * permit persons to whom the Software is furnished to do so, subject to
13  * the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the
16  * next paragraph) shall be included in all copies or substantial portions
17  * of the Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26  *
27  */
28
29 #include "drmP.h"
30 #include "drm.h"
31 #include "drm_crtc_helper.h"
32 #include "drm_fb_helper.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "i915_trace.h"
37 #include <linux/pci.h>
38 #include <linux/vgaarb.h>
39 #include <linux/acpi.h>
40 #include <linux/pnp.h>
41 #include <linux/vga_switcheroo.h>
42 #include <linux/slab.h>
43 #include <acpi/video.h>
44
45 /**
46  * Sets up the hardware status page for devices that need a physical address
47  * in the register.
48  */
49 static int i915_init_phys_hws(struct drm_device *dev)
50 {
51         drm_i915_private_t *dev_priv = dev->dev_private;
52         /* Program Hardware Status Page */
53         dev_priv->status_page_dmah =
54                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
55
56         if (!dev_priv->status_page_dmah) {
57                 DRM_ERROR("Can not allocate hardware status page\n");
58                 return -ENOMEM;
59         }
60         dev_priv->render_ring.status_page.page_addr
61                 = dev_priv->status_page_dmah->vaddr;
62         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
63
64         memset(dev_priv->render_ring.status_page.page_addr, 0, PAGE_SIZE);
65
66         if (INTEL_INFO(dev)->gen >= 4)
67                 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
68                                              0xf0;
69
70         I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
71         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
72         return 0;
73 }
74
75 /**
76  * Frees the hardware status page, whether it's a physical address or a virtual
77  * address set up by the X Server.
78  */
79 static void i915_free_hws(struct drm_device *dev)
80 {
81         drm_i915_private_t *dev_priv = dev->dev_private;
82         if (dev_priv->status_page_dmah) {
83                 drm_pci_free(dev, dev_priv->status_page_dmah);
84                 dev_priv->status_page_dmah = NULL;
85         }
86
87         if (dev_priv->render_ring.status_page.gfx_addr) {
88                 dev_priv->render_ring.status_page.gfx_addr = 0;
89                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
90         }
91
92         /* Need to rewrite hardware status page */
93         I915_WRITE(HWS_PGA, 0x1ffff000);
94 }
95
96 void i915_kernel_lost_context(struct drm_device * dev)
97 {
98         drm_i915_private_t *dev_priv = dev->dev_private;
99         struct drm_i915_master_private *master_priv;
100         struct intel_ring_buffer *ring = &dev_priv->render_ring;
101
102         /*
103          * We should never lose context on the ring with modesetting
104          * as we don't expose it to userspace
105          */
106         if (drm_core_check_feature(dev, DRIVER_MODESET))
107                 return;
108
109         ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
110         ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
111         ring->space = ring->head - (ring->tail + 8);
112         if (ring->space < 0)
113                 ring->space += ring->size;
114
115         if (!dev->primary->master)
116                 return;
117
118         master_priv = dev->primary->master->driver_priv;
119         if (ring->head == ring->tail && master_priv->sarea_priv)
120                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
121 }
122
123 static int i915_dma_cleanup(struct drm_device * dev)
124 {
125         drm_i915_private_t *dev_priv = dev->dev_private;
126         /* Make sure interrupts are disabled here because the uninstall ioctl
127          * may not have been called from userspace and after dev_private
128          * is freed, it's too late.
129          */
130         if (dev->irq_enabled)
131                 drm_irq_uninstall(dev);
132
133         mutex_lock(&dev->struct_mutex);
134         intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
135         intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
136         intel_cleanup_ring_buffer(dev, &dev_priv->blt_ring);
137         mutex_unlock(&dev->struct_mutex);
138
139         /* Clear the HWS virtual address at teardown */
140         if (I915_NEED_GFX_HWS(dev))
141                 i915_free_hws(dev);
142
143         return 0;
144 }
145
146 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
147 {
148         drm_i915_private_t *dev_priv = dev->dev_private;
149         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
150
151         master_priv->sarea = drm_getsarea(dev);
152         if (master_priv->sarea) {
153                 master_priv->sarea_priv = (drm_i915_sarea_t *)
154                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
155         } else {
156                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
157         }
158
159         if (init->ring_size != 0) {
160                 if (dev_priv->render_ring.gem_object != NULL) {
161                         i915_dma_cleanup(dev);
162                         DRM_ERROR("Client tried to initialize ringbuffer in "
163                                   "GEM mode\n");
164                         return -EINVAL;
165                 }
166
167                 dev_priv->render_ring.size = init->ring_size;
168
169                 dev_priv->render_ring.map.offset = init->ring_start;
170                 dev_priv->render_ring.map.size = init->ring_size;
171                 dev_priv->render_ring.map.type = 0;
172                 dev_priv->render_ring.map.flags = 0;
173                 dev_priv->render_ring.map.mtrr = 0;
174
175                 drm_core_ioremap_wc(&dev_priv->render_ring.map, dev);
176
177                 if (dev_priv->render_ring.map.handle == NULL) {
178                         i915_dma_cleanup(dev);
179                         DRM_ERROR("can not ioremap virtual address for"
180                                   " ring buffer\n");
181                         return -ENOMEM;
182                 }
183         }
184
185         dev_priv->render_ring.virtual_start = dev_priv->render_ring.map.handle;
186
187         dev_priv->cpp = init->cpp;
188         dev_priv->back_offset = init->back_offset;
189         dev_priv->front_offset = init->front_offset;
190         dev_priv->current_page = 0;
191         if (master_priv->sarea_priv)
192                 master_priv->sarea_priv->pf_current_page = 0;
193
194         /* Allow hardware batchbuffers unless told otherwise.
195          */
196         dev_priv->allow_batchbuffer = 1;
197
198         return 0;
199 }
200
201 static int i915_dma_resume(struct drm_device * dev)
202 {
203         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
204
205         struct intel_ring_buffer *ring;
206         DRM_DEBUG_DRIVER("%s\n", __func__);
207
208         ring = &dev_priv->render_ring;
209
210         if (ring->map.handle == NULL) {
211                 DRM_ERROR("can not ioremap virtual address for"
212                           " ring buffer\n");
213                 return -ENOMEM;
214         }
215
216         /* Program Hardware Status Page */
217         if (!ring->status_page.page_addr) {
218                 DRM_ERROR("Can not find hardware status page\n");
219                 return -EINVAL;
220         }
221         DRM_DEBUG_DRIVER("hw status page @ %p\n",
222                                 ring->status_page.page_addr);
223         if (ring->status_page.gfx_addr != 0)
224                 intel_ring_setup_status_page(dev, ring);
225         else
226                 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
227
228         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
229
230         return 0;
231 }
232
233 static int i915_dma_init(struct drm_device *dev, void *data,
234                          struct drm_file *file_priv)
235 {
236         drm_i915_init_t *init = data;
237         int retcode = 0;
238
239         switch (init->func) {
240         case I915_INIT_DMA:
241                 retcode = i915_initialize(dev, init);
242                 break;
243         case I915_CLEANUP_DMA:
244                 retcode = i915_dma_cleanup(dev);
245                 break;
246         case I915_RESUME_DMA:
247                 retcode = i915_dma_resume(dev);
248                 break;
249         default:
250                 retcode = -EINVAL;
251                 break;
252         }
253
254         return retcode;
255 }
256
257 /* Implement basically the same security restrictions as hardware does
258  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
259  *
260  * Most of the calculations below involve calculating the size of a
261  * particular instruction.  It's important to get the size right as
262  * that tells us where the next instruction to check is.  Any illegal
263  * instruction detected will be given a size of zero, which is a
264  * signal to abort the rest of the buffer.
265  */
266 static int do_validate_cmd(int cmd)
267 {
268         switch (((cmd >> 29) & 0x7)) {
269         case 0x0:
270                 switch ((cmd >> 23) & 0x3f) {
271                 case 0x0:
272                         return 1;       /* MI_NOOP */
273                 case 0x4:
274                         return 1;       /* MI_FLUSH */
275                 default:
276                         return 0;       /* disallow everything else */
277                 }
278                 break;
279         case 0x1:
280                 return 0;       /* reserved */
281         case 0x2:
282                 return (cmd & 0xff) + 2;        /* 2d commands */
283         case 0x3:
284                 if (((cmd >> 24) & 0x1f) <= 0x18)
285                         return 1;
286
287                 switch ((cmd >> 24) & 0x1f) {
288                 case 0x1c:
289                         return 1;
290                 case 0x1d:
291                         switch ((cmd >> 16) & 0xff) {
292                         case 0x3:
293                                 return (cmd & 0x1f) + 2;
294                         case 0x4:
295                                 return (cmd & 0xf) + 2;
296                         default:
297                                 return (cmd & 0xffff) + 2;
298                         }
299                 case 0x1e:
300                         if (cmd & (1 << 23))
301                                 return (cmd & 0xffff) + 1;
302                         else
303                                 return 1;
304                 case 0x1f:
305                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
306                                 return (cmd & 0x1ffff) + 2;
307                         else if (cmd & (1 << 17))       /* indirect random */
308                                 if ((cmd & 0xffff) == 0)
309                                         return 0;       /* unknown length, too hard */
310                                 else
311                                         return (((cmd & 0xffff) + 1) / 2) + 1;
312                         else
313                                 return 2;       /* indirect sequential */
314                 default:
315                         return 0;
316                 }
317         default:
318                 return 0;
319         }
320
321         return 0;
322 }
323
324 static int validate_cmd(int cmd)
325 {
326         int ret = do_validate_cmd(cmd);
327
328 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
329
330         return ret;
331 }
332
333 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
334 {
335         drm_i915_private_t *dev_priv = dev->dev_private;
336         int i;
337
338         if ((dwords+1) * sizeof(int) >= dev_priv->render_ring.size - 8)
339                 return -EINVAL;
340
341         BEGIN_LP_RING((dwords+1)&~1);
342
343         for (i = 0; i < dwords;) {
344                 int cmd, sz;
345
346                 cmd = buffer[i];
347
348                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
349                         return -EINVAL;
350
351                 OUT_RING(cmd);
352
353                 while (++i, --sz) {
354                         OUT_RING(buffer[i]);
355                 }
356         }
357
358         if (dwords & 1)
359                 OUT_RING(0);
360
361         ADVANCE_LP_RING();
362
363         return 0;
364 }
365
366 int
367 i915_emit_box(struct drm_device *dev,
368               struct drm_clip_rect *boxes,
369               int i, int DR1, int DR4)
370 {
371         struct drm_clip_rect box = boxes[i];
372
373         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
374                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
375                           box.x1, box.y1, box.x2, box.y2);
376                 return -EINVAL;
377         }
378
379         if (INTEL_INFO(dev)->gen >= 4) {
380                 BEGIN_LP_RING(4);
381                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
382                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
383                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
384                 OUT_RING(DR4);
385                 ADVANCE_LP_RING();
386         } else {
387                 BEGIN_LP_RING(6);
388                 OUT_RING(GFX_OP_DRAWRECT_INFO);
389                 OUT_RING(DR1);
390                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
391                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
392                 OUT_RING(DR4);
393                 OUT_RING(0);
394                 ADVANCE_LP_RING();
395         }
396
397         return 0;
398 }
399
400 /* XXX: Emitting the counter should really be moved to part of the IRQ
401  * emit. For now, do it in both places:
402  */
403
404 static void i915_emit_breadcrumb(struct drm_device *dev)
405 {
406         drm_i915_private_t *dev_priv = dev->dev_private;
407         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
408
409         dev_priv->counter++;
410         if (dev_priv->counter > 0x7FFFFFFFUL)
411                 dev_priv->counter = 0;
412         if (master_priv->sarea_priv)
413                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
414
415         BEGIN_LP_RING(4);
416         OUT_RING(MI_STORE_DWORD_INDEX);
417         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
418         OUT_RING(dev_priv->counter);
419         OUT_RING(0);
420         ADVANCE_LP_RING();
421 }
422
423 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
424                                    drm_i915_cmdbuffer_t *cmd,
425                                    struct drm_clip_rect *cliprects,
426                                    void *cmdbuf)
427 {
428         int nbox = cmd->num_cliprects;
429         int i = 0, count, ret;
430
431         if (cmd->sz & 0x3) {
432                 DRM_ERROR("alignment");
433                 return -EINVAL;
434         }
435
436         i915_kernel_lost_context(dev);
437
438         count = nbox ? nbox : 1;
439
440         for (i = 0; i < count; i++) {
441                 if (i < nbox) {
442                         ret = i915_emit_box(dev, cliprects, i,
443                                             cmd->DR1, cmd->DR4);
444                         if (ret)
445                                 return ret;
446                 }
447
448                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
449                 if (ret)
450                         return ret;
451         }
452
453         i915_emit_breadcrumb(dev);
454         return 0;
455 }
456
457 static int i915_dispatch_batchbuffer(struct drm_device * dev,
458                                      drm_i915_batchbuffer_t * batch,
459                                      struct drm_clip_rect *cliprects)
460 {
461         int nbox = batch->num_cliprects;
462         int i = 0, count;
463
464         if ((batch->start | batch->used) & 0x7) {
465                 DRM_ERROR("alignment");
466                 return -EINVAL;
467         }
468
469         i915_kernel_lost_context(dev);
470
471         count = nbox ? nbox : 1;
472
473         for (i = 0; i < count; i++) {
474                 if (i < nbox) {
475                         int ret = i915_emit_box(dev, cliprects, i,
476                                                 batch->DR1, batch->DR4);
477                         if (ret)
478                                 return ret;
479                 }
480
481                 if (!IS_I830(dev) && !IS_845G(dev)) {
482                         BEGIN_LP_RING(2);
483                         if (INTEL_INFO(dev)->gen >= 4) {
484                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
485                                 OUT_RING(batch->start);
486                         } else {
487                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
488                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
489                         }
490                         ADVANCE_LP_RING();
491                 } else {
492                         BEGIN_LP_RING(4);
493                         OUT_RING(MI_BATCH_BUFFER);
494                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
495                         OUT_RING(batch->start + batch->used - 4);
496                         OUT_RING(0);
497                         ADVANCE_LP_RING();
498                 }
499         }
500
501
502         if (IS_G4X(dev) || IS_GEN5(dev)) {
503                 BEGIN_LP_RING(2);
504                 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
505                 OUT_RING(MI_NOOP);
506                 ADVANCE_LP_RING();
507         }
508         i915_emit_breadcrumb(dev);
509
510         return 0;
511 }
512
513 static int i915_dispatch_flip(struct drm_device * dev)
514 {
515         drm_i915_private_t *dev_priv = dev->dev_private;
516         struct drm_i915_master_private *master_priv =
517                 dev->primary->master->driver_priv;
518
519         if (!master_priv->sarea_priv)
520                 return -EINVAL;
521
522         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
523                           __func__,
524                          dev_priv->current_page,
525                          master_priv->sarea_priv->pf_current_page);
526
527         i915_kernel_lost_context(dev);
528
529         BEGIN_LP_RING(2);
530         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
531         OUT_RING(0);
532         ADVANCE_LP_RING();
533
534         BEGIN_LP_RING(6);
535         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
536         OUT_RING(0);
537         if (dev_priv->current_page == 0) {
538                 OUT_RING(dev_priv->back_offset);
539                 dev_priv->current_page = 1;
540         } else {
541                 OUT_RING(dev_priv->front_offset);
542                 dev_priv->current_page = 0;
543         }
544         OUT_RING(0);
545         ADVANCE_LP_RING();
546
547         BEGIN_LP_RING(2);
548         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
549         OUT_RING(0);
550         ADVANCE_LP_RING();
551
552         master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
553
554         BEGIN_LP_RING(4);
555         OUT_RING(MI_STORE_DWORD_INDEX);
556         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
557         OUT_RING(dev_priv->counter);
558         OUT_RING(0);
559         ADVANCE_LP_RING();
560
561         master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
562         return 0;
563 }
564
565 static int i915_quiescent(struct drm_device * dev)
566 {
567         drm_i915_private_t *dev_priv = dev->dev_private;
568
569         i915_kernel_lost_context(dev);
570         return intel_wait_ring_buffer(dev, &dev_priv->render_ring,
571                                       dev_priv->render_ring.size - 8);
572 }
573
574 static int i915_flush_ioctl(struct drm_device *dev, void *data,
575                             struct drm_file *file_priv)
576 {
577         int ret;
578
579         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
580
581         mutex_lock(&dev->struct_mutex);
582         ret = i915_quiescent(dev);
583         mutex_unlock(&dev->struct_mutex);
584
585         return ret;
586 }
587
588 static int i915_batchbuffer(struct drm_device *dev, void *data,
589                             struct drm_file *file_priv)
590 {
591         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
592         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
593         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
594             master_priv->sarea_priv;
595         drm_i915_batchbuffer_t *batch = data;
596         int ret;
597         struct drm_clip_rect *cliprects = NULL;
598
599         if (!dev_priv->allow_batchbuffer) {
600                 DRM_ERROR("Batchbuffer ioctl disabled\n");
601                 return -EINVAL;
602         }
603
604         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
605                         batch->start, batch->used, batch->num_cliprects);
606
607         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
608
609         if (batch->num_cliprects < 0)
610                 return -EINVAL;
611
612         if (batch->num_cliprects) {
613                 cliprects = kcalloc(batch->num_cliprects,
614                                     sizeof(struct drm_clip_rect),
615                                     GFP_KERNEL);
616                 if (cliprects == NULL)
617                         return -ENOMEM;
618
619                 ret = copy_from_user(cliprects, batch->cliprects,
620                                      batch->num_cliprects *
621                                      sizeof(struct drm_clip_rect));
622                 if (ret != 0) {
623                         ret = -EFAULT;
624                         goto fail_free;
625                 }
626         }
627
628         mutex_lock(&dev->struct_mutex);
629         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
630         mutex_unlock(&dev->struct_mutex);
631
632         if (sarea_priv)
633                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
634
635 fail_free:
636         kfree(cliprects);
637
638         return ret;
639 }
640
641 static int i915_cmdbuffer(struct drm_device *dev, void *data,
642                           struct drm_file *file_priv)
643 {
644         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
645         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
646         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
647             master_priv->sarea_priv;
648         drm_i915_cmdbuffer_t *cmdbuf = data;
649         struct drm_clip_rect *cliprects = NULL;
650         void *batch_data;
651         int ret;
652
653         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
654                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
655
656         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
657
658         if (cmdbuf->num_cliprects < 0)
659                 return -EINVAL;
660
661         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
662         if (batch_data == NULL)
663                 return -ENOMEM;
664
665         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
666         if (ret != 0) {
667                 ret = -EFAULT;
668                 goto fail_batch_free;
669         }
670
671         if (cmdbuf->num_cliprects) {
672                 cliprects = kcalloc(cmdbuf->num_cliprects,
673                                     sizeof(struct drm_clip_rect), GFP_KERNEL);
674                 if (cliprects == NULL) {
675                         ret = -ENOMEM;
676                         goto fail_batch_free;
677                 }
678
679                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
680                                      cmdbuf->num_cliprects *
681                                      sizeof(struct drm_clip_rect));
682                 if (ret != 0) {
683                         ret = -EFAULT;
684                         goto fail_clip_free;
685                 }
686         }
687
688         mutex_lock(&dev->struct_mutex);
689         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
690         mutex_unlock(&dev->struct_mutex);
691         if (ret) {
692                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
693                 goto fail_clip_free;
694         }
695
696         if (sarea_priv)
697                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
698
699 fail_clip_free:
700         kfree(cliprects);
701 fail_batch_free:
702         kfree(batch_data);
703
704         return ret;
705 }
706
707 static int i915_flip_bufs(struct drm_device *dev, void *data,
708                           struct drm_file *file_priv)
709 {
710         int ret;
711
712         DRM_DEBUG_DRIVER("%s\n", __func__);
713
714         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
715
716         mutex_lock(&dev->struct_mutex);
717         ret = i915_dispatch_flip(dev);
718         mutex_unlock(&dev->struct_mutex);
719
720         return ret;
721 }
722
723 static int i915_getparam(struct drm_device *dev, void *data,
724                          struct drm_file *file_priv)
725 {
726         drm_i915_private_t *dev_priv = dev->dev_private;
727         drm_i915_getparam_t *param = data;
728         int value;
729
730         if (!dev_priv) {
731                 DRM_ERROR("called with no initialization\n");
732                 return -EINVAL;
733         }
734
735         switch (param->param) {
736         case I915_PARAM_IRQ_ACTIVE:
737                 value = dev->pdev->irq ? 1 : 0;
738                 break;
739         case I915_PARAM_ALLOW_BATCHBUFFER:
740                 value = dev_priv->allow_batchbuffer ? 1 : 0;
741                 break;
742         case I915_PARAM_LAST_DISPATCH:
743                 value = READ_BREADCRUMB(dev_priv);
744                 break;
745         case I915_PARAM_CHIPSET_ID:
746                 value = dev->pci_device;
747                 break;
748         case I915_PARAM_HAS_GEM:
749                 value = dev_priv->has_gem;
750                 break;
751         case I915_PARAM_NUM_FENCES_AVAIL:
752                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
753                 break;
754         case I915_PARAM_HAS_OVERLAY:
755                 value = dev_priv->overlay ? 1 : 0;
756                 break;
757         case I915_PARAM_HAS_PAGEFLIPPING:
758                 value = 1;
759                 break;
760         case I915_PARAM_HAS_EXECBUF2:
761                 /* depends on GEM */
762                 value = dev_priv->has_gem;
763                 break;
764         case I915_PARAM_HAS_BSD:
765                 value = HAS_BSD(dev);
766                 break;
767         case I915_PARAM_HAS_BLT:
768                 value = HAS_BLT(dev);
769                 break;
770         case I915_PARAM_HAS_COHERENT_RINGS:
771                 value = 1;
772                 break;
773         default:
774                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
775                                  param->param);
776                 return -EINVAL;
777         }
778
779         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
780                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
781                 return -EFAULT;
782         }
783
784         return 0;
785 }
786
787 static int i915_setparam(struct drm_device *dev, void *data,
788                          struct drm_file *file_priv)
789 {
790         drm_i915_private_t *dev_priv = dev->dev_private;
791         drm_i915_setparam_t *param = data;
792
793         if (!dev_priv) {
794                 DRM_ERROR("called with no initialization\n");
795                 return -EINVAL;
796         }
797
798         switch (param->param) {
799         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
800                 break;
801         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
802                 dev_priv->tex_lru_log_granularity = param->value;
803                 break;
804         case I915_SETPARAM_ALLOW_BATCHBUFFER:
805                 dev_priv->allow_batchbuffer = param->value;
806                 break;
807         case I915_SETPARAM_NUM_USED_FENCES:
808                 if (param->value > dev_priv->num_fence_regs ||
809                     param->value < 0)
810                         return -EINVAL;
811                 /* Userspace can use first N regs */
812                 dev_priv->fence_reg_start = param->value;
813                 break;
814         default:
815                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
816                                         param->param);
817                 return -EINVAL;
818         }
819
820         return 0;
821 }
822
823 static int i915_set_status_page(struct drm_device *dev, void *data,
824                                 struct drm_file *file_priv)
825 {
826         drm_i915_private_t *dev_priv = dev->dev_private;
827         drm_i915_hws_addr_t *hws = data;
828         struct intel_ring_buffer *ring = &dev_priv->render_ring;
829
830         if (!I915_NEED_GFX_HWS(dev))
831                 return -EINVAL;
832
833         if (!dev_priv) {
834                 DRM_ERROR("called with no initialization\n");
835                 return -EINVAL;
836         }
837
838         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
839                 WARN(1, "tried to set status page when mode setting active\n");
840                 return 0;
841         }
842
843         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
844
845         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
846
847         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
848         dev_priv->hws_map.size = 4*1024;
849         dev_priv->hws_map.type = 0;
850         dev_priv->hws_map.flags = 0;
851         dev_priv->hws_map.mtrr = 0;
852
853         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
854         if (dev_priv->hws_map.handle == NULL) {
855                 i915_dma_cleanup(dev);
856                 ring->status_page.gfx_addr = 0;
857                 DRM_ERROR("can not ioremap virtual address for"
858                                 " G33 hw status page\n");
859                 return -ENOMEM;
860         }
861         ring->status_page.page_addr = dev_priv->hws_map.handle;
862         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
863         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
864
865         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
866                          ring->status_page.gfx_addr);
867         DRM_DEBUG_DRIVER("load hws at %p\n",
868                          ring->status_page.page_addr);
869         return 0;
870 }
871
872 static int i915_get_bridge_dev(struct drm_device *dev)
873 {
874         struct drm_i915_private *dev_priv = dev->dev_private;
875
876         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
877         if (!dev_priv->bridge_dev) {
878                 DRM_ERROR("bridge device not found\n");
879                 return -1;
880         }
881         return 0;
882 }
883
884 #define MCHBAR_I915 0x44
885 #define MCHBAR_I965 0x48
886 #define MCHBAR_SIZE (4*4096)
887
888 #define DEVEN_REG 0x54
889 #define   DEVEN_MCHBAR_EN (1 << 28)
890
891 /* Allocate space for the MCH regs if needed, return nonzero on error */
892 static int
893 intel_alloc_mchbar_resource(struct drm_device *dev)
894 {
895         drm_i915_private_t *dev_priv = dev->dev_private;
896         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
897         u32 temp_lo, temp_hi = 0;
898         u64 mchbar_addr;
899         int ret;
900
901         if (INTEL_INFO(dev)->gen >= 4)
902                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
903         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
904         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
905
906         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
907 #ifdef CONFIG_PNP
908         if (mchbar_addr &&
909             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
910                 return 0;
911 #endif
912
913         /* Get some space for it */
914         dev_priv->mch_res.name = "i915 MCHBAR";
915         dev_priv->mch_res.flags = IORESOURCE_MEM;
916         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
917                                      &dev_priv->mch_res,
918                                      MCHBAR_SIZE, MCHBAR_SIZE,
919                                      PCIBIOS_MIN_MEM,
920                                      0, pcibios_align_resource,
921                                      dev_priv->bridge_dev);
922         if (ret) {
923                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
924                 dev_priv->mch_res.start = 0;
925                 return ret;
926         }
927
928         if (INTEL_INFO(dev)->gen >= 4)
929                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
930                                        upper_32_bits(dev_priv->mch_res.start));
931
932         pci_write_config_dword(dev_priv->bridge_dev, reg,
933                                lower_32_bits(dev_priv->mch_res.start));
934         return 0;
935 }
936
937 /* Setup MCHBAR if possible, return true if we should disable it again */
938 static void
939 intel_setup_mchbar(struct drm_device *dev)
940 {
941         drm_i915_private_t *dev_priv = dev->dev_private;
942         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
943         u32 temp;
944         bool enabled;
945
946         dev_priv->mchbar_need_disable = false;
947
948         if (IS_I915G(dev) || IS_I915GM(dev)) {
949                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
950                 enabled = !!(temp & DEVEN_MCHBAR_EN);
951         } else {
952                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
953                 enabled = temp & 1;
954         }
955
956         /* If it's already enabled, don't have to do anything */
957         if (enabled)
958                 return;
959
960         if (intel_alloc_mchbar_resource(dev))
961                 return;
962
963         dev_priv->mchbar_need_disable = true;
964
965         /* Space is allocated or reserved, so enable it. */
966         if (IS_I915G(dev) || IS_I915GM(dev)) {
967                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
968                                        temp | DEVEN_MCHBAR_EN);
969         } else {
970                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
971                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
972         }
973 }
974
975 static void
976 intel_teardown_mchbar(struct drm_device *dev)
977 {
978         drm_i915_private_t *dev_priv = dev->dev_private;
979         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
980         u32 temp;
981
982         if (dev_priv->mchbar_need_disable) {
983                 if (IS_I915G(dev) || IS_I915GM(dev)) {
984                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
985                         temp &= ~DEVEN_MCHBAR_EN;
986                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
987                 } else {
988                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
989                         temp &= ~1;
990                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
991                 }
992         }
993
994         if (dev_priv->mch_res.start)
995                 release_resource(&dev_priv->mch_res);
996 }
997
998 #define PTE_ADDRESS_MASK                0xfffff000
999 #define PTE_ADDRESS_MASK_HIGH           0x000000f0 /* i915+ */
1000 #define PTE_MAPPING_TYPE_UNCACHED       (0 << 1)
1001 #define PTE_MAPPING_TYPE_DCACHE         (1 << 1) /* i830 only */
1002 #define PTE_MAPPING_TYPE_CACHED         (3 << 1)
1003 #define PTE_MAPPING_TYPE_MASK           (3 << 1)
1004 #define PTE_VALID                       (1 << 0)
1005
1006 /**
1007  * i915_gtt_to_phys - take a GTT address and turn it into a physical one
1008  * @dev: drm device
1009  * @gtt_addr: address to translate
1010  *
1011  * Some chip functions require allocations from stolen space but need the
1012  * physical address of the memory in question.  We use this routine
1013  * to get a physical address suitable for register programming from a given
1014  * GTT address.
1015  */
1016 static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1017                                       unsigned long gtt_addr)
1018 {
1019         unsigned long *gtt;
1020         unsigned long entry, phys;
1021         int gtt_bar = IS_GEN2(dev) ? 1 : 0;
1022         int gtt_offset, gtt_size;
1023
1024         if (INTEL_INFO(dev)->gen >= 4) {
1025                 if (IS_G4X(dev) || INTEL_INFO(dev)->gen > 4) {
1026                         gtt_offset = 2*1024*1024;
1027                         gtt_size = 2*1024*1024;
1028                 } else {
1029                         gtt_offset = 512*1024;
1030                         gtt_size = 512*1024;
1031                 }
1032         } else {
1033                 gtt_bar = 3;
1034                 gtt_offset = 0;
1035                 gtt_size = pci_resource_len(dev->pdev, gtt_bar);
1036         }
1037
1038         gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
1039                          gtt_size);
1040         if (!gtt) {
1041                 DRM_ERROR("ioremap of GTT failed\n");
1042                 return 0;
1043         }
1044
1045         entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
1046
1047         DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
1048
1049         /* Mask out these reserved bits on this hardware. */
1050         if (INTEL_INFO(dev)->gen < 4 && !IS_G33(dev))
1051                 entry &= ~PTE_ADDRESS_MASK_HIGH;
1052
1053         /* If it's not a mapping type we know, then bail. */
1054         if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
1055             (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
1056                 iounmap(gtt);
1057                 return 0;
1058         }
1059
1060         if (!(entry & PTE_VALID)) {
1061                 DRM_ERROR("bad GTT entry in stolen space\n");
1062                 iounmap(gtt);
1063                 return 0;
1064         }
1065
1066         iounmap(gtt);
1067
1068         phys =(entry & PTE_ADDRESS_MASK) |
1069                 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
1070
1071         DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
1072
1073         return phys;
1074 }
1075
1076 static void i915_warn_stolen(struct drm_device *dev)
1077 {
1078         DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1079         DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1080 }
1081
1082 static void i915_setup_compression(struct drm_device *dev, int size)
1083 {
1084         struct drm_i915_private *dev_priv = dev->dev_private;
1085         struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
1086         unsigned long cfb_base;
1087         unsigned long ll_base = 0;
1088
1089         /* Leave 1M for line length buffer & misc. */
1090         compressed_fb = drm_mm_search_free(&dev_priv->mm.vram, size, 4096, 0);
1091         if (!compressed_fb) {
1092                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1093                 i915_warn_stolen(dev);
1094                 return;
1095         }
1096
1097         compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1098         if (!compressed_fb) {
1099                 i915_warn_stolen(dev);
1100                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1101                 return;
1102         }
1103
1104         cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
1105         if (!cfb_base) {
1106                 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1107                 drm_mm_put_block(compressed_fb);
1108         }
1109
1110         if (!(IS_GM45(dev) || IS_IRONLAKE_M(dev))) {
1111                 compressed_llb = drm_mm_search_free(&dev_priv->mm.vram, 4096,
1112                                                     4096, 0);
1113                 if (!compressed_llb) {
1114                         i915_warn_stolen(dev);
1115                         return;
1116                 }
1117
1118                 compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
1119                 if (!compressed_llb) {
1120                         i915_warn_stolen(dev);
1121                         return;
1122                 }
1123
1124                 ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
1125                 if (!ll_base) {
1126                         DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1127                         drm_mm_put_block(compressed_fb);
1128                         drm_mm_put_block(compressed_llb);
1129                 }
1130         }
1131
1132         dev_priv->cfb_size = size;
1133
1134         intel_disable_fbc(dev);
1135         dev_priv->compressed_fb = compressed_fb;
1136         if (IS_IRONLAKE_M(dev))
1137                 I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
1138         else if (IS_GM45(dev)) {
1139                 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1140         } else {
1141                 I915_WRITE(FBC_CFB_BASE, cfb_base);
1142                 I915_WRITE(FBC_LL_BASE, ll_base);
1143                 dev_priv->compressed_llb = compressed_llb;
1144         }
1145
1146         DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
1147                   ll_base, size >> 20);
1148 }
1149
1150 static void i915_cleanup_compression(struct drm_device *dev)
1151 {
1152         struct drm_i915_private *dev_priv = dev->dev_private;
1153
1154         drm_mm_put_block(dev_priv->compressed_fb);
1155         if (dev_priv->compressed_llb)
1156                 drm_mm_put_block(dev_priv->compressed_llb);
1157 }
1158
1159 /* true = enable decode, false = disable decoder */
1160 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1161 {
1162         struct drm_device *dev = cookie;
1163
1164         intel_modeset_vga_set_state(dev, state);
1165         if (state)
1166                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1167                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1168         else
1169                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1170 }
1171
1172 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1173 {
1174         struct drm_device *dev = pci_get_drvdata(pdev);
1175         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1176         if (state == VGA_SWITCHEROO_ON) {
1177                 printk(KERN_INFO "i915: switched on\n");
1178                 /* i915 resume handler doesn't set to D0 */
1179                 pci_set_power_state(dev->pdev, PCI_D0);
1180                 i915_resume(dev);
1181         } else {
1182                 printk(KERN_ERR "i915: switched off\n");
1183                 i915_suspend(dev, pmm);
1184         }
1185 }
1186
1187 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1188 {
1189         struct drm_device *dev = pci_get_drvdata(pdev);
1190         bool can_switch;
1191
1192         spin_lock(&dev->count_lock);
1193         can_switch = (dev->open_count == 0);
1194         spin_unlock(&dev->count_lock);
1195         return can_switch;
1196 }
1197
1198 static int i915_load_modeset_init(struct drm_device *dev,
1199                                   unsigned long prealloc_size,
1200                                   unsigned long agp_size)
1201 {
1202         struct drm_i915_private *dev_priv = dev->dev_private;
1203         int ret = 0;
1204
1205         /* Basic memrange allocator for stolen space (aka mm.vram) */
1206         drm_mm_init(&dev_priv->mm.vram, 0, prealloc_size);
1207
1208         /* Let GEM Manage from end of prealloc space to end of aperture.
1209          *
1210          * However, leave one page at the end still bound to the scratch page.
1211          * There are a number of places where the hardware apparently
1212          * prefetches past the end of the object, and we've seen multiple
1213          * hangs with the GPU head pointer stuck in a batchbuffer bound
1214          * at the last page of the aperture.  One page should be enough to
1215          * keep any prefetching inside of the aperture.
1216          */
1217         i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
1218
1219         mutex_lock(&dev->struct_mutex);
1220         ret = i915_gem_init_ringbuffer(dev);
1221         mutex_unlock(&dev->struct_mutex);
1222         if (ret)
1223                 goto out;
1224
1225         /* Try to set up FBC with a reasonable compressed buffer size */
1226         if (I915_HAS_FBC(dev) && i915_powersave) {
1227                 int cfb_size;
1228
1229                 /* Try to get an 8M buffer... */
1230                 if (prealloc_size > (9*1024*1024))
1231                         cfb_size = 8*1024*1024;
1232                 else /* fall back to 7/8 of the stolen space */
1233                         cfb_size = prealloc_size * 7 / 8;
1234                 i915_setup_compression(dev, cfb_size);
1235         }
1236
1237         /* Allow hardware batchbuffers unless told otherwise.
1238          */
1239         dev_priv->allow_batchbuffer = 1;
1240
1241         ret = intel_parse_bios(dev);
1242         if (ret)
1243                 DRM_INFO("failed to find VBIOS tables\n");
1244
1245         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1246         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1247         if (ret)
1248                 goto cleanup_ringbuffer;
1249
1250         intel_register_dsm_handler();
1251
1252         ret = vga_switcheroo_register_client(dev->pdev,
1253                                              i915_switcheroo_set_state,
1254                                              i915_switcheroo_can_switch);
1255         if (ret)
1256                 goto cleanup_vga_client;
1257
1258         /* IIR "flip pending" bit means done if this bit is set */
1259         if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1260                 dev_priv->flip_pending_is_done = true;
1261
1262         intel_modeset_init(dev);
1263
1264         ret = drm_irq_install(dev);
1265         if (ret)
1266                 goto cleanup_vga_switcheroo;
1267
1268         /* Always safe in the mode setting case. */
1269         /* FIXME: do pre/post-mode set stuff in core KMS code */
1270         dev->vblank_disable_allowed = 1;
1271
1272         ret = intel_fbdev_init(dev);
1273         if (ret)
1274                 goto cleanup_irq;
1275
1276         drm_kms_helper_poll_init(dev);
1277
1278         /* We're off and running w/KMS */
1279         dev_priv->mm.suspended = 0;
1280
1281         return 0;
1282
1283 cleanup_irq:
1284         drm_irq_uninstall(dev);
1285 cleanup_vga_switcheroo:
1286         vga_switcheroo_unregister_client(dev->pdev);
1287 cleanup_vga_client:
1288         vga_client_register(dev->pdev, NULL, NULL, NULL);
1289 cleanup_ringbuffer:
1290         mutex_lock(&dev->struct_mutex);
1291         i915_gem_cleanup_ringbuffer(dev);
1292         mutex_unlock(&dev->struct_mutex);
1293 out:
1294         return ret;
1295 }
1296
1297 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1298 {
1299         struct drm_i915_master_private *master_priv;
1300
1301         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1302         if (!master_priv)
1303                 return -ENOMEM;
1304
1305         master->driver_priv = master_priv;
1306         return 0;
1307 }
1308
1309 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1310 {
1311         struct drm_i915_master_private *master_priv = master->driver_priv;
1312
1313         if (!master_priv)
1314                 return;
1315
1316         kfree(master_priv);
1317
1318         master->driver_priv = NULL;
1319 }
1320
1321 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1322 {
1323         drm_i915_private_t *dev_priv = dev->dev_private;
1324         u32 tmp;
1325
1326         tmp = I915_READ(CLKCFG);
1327
1328         switch (tmp & CLKCFG_FSB_MASK) {
1329         case CLKCFG_FSB_533:
1330                 dev_priv->fsb_freq = 533; /* 133*4 */
1331                 break;
1332         case CLKCFG_FSB_800:
1333                 dev_priv->fsb_freq = 800; /* 200*4 */
1334                 break;
1335         case CLKCFG_FSB_667:
1336                 dev_priv->fsb_freq =  667; /* 167*4 */
1337                 break;
1338         case CLKCFG_FSB_400:
1339                 dev_priv->fsb_freq = 400; /* 100*4 */
1340                 break;
1341         }
1342
1343         switch (tmp & CLKCFG_MEM_MASK) {
1344         case CLKCFG_MEM_533:
1345                 dev_priv->mem_freq = 533;
1346                 break;
1347         case CLKCFG_MEM_667:
1348                 dev_priv->mem_freq = 667;
1349                 break;
1350         case CLKCFG_MEM_800:
1351                 dev_priv->mem_freq = 800;
1352                 break;
1353         }
1354
1355         /* detect pineview DDR3 setting */
1356         tmp = I915_READ(CSHRDDR3CTL);
1357         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1358 }
1359
1360 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1361 {
1362         drm_i915_private_t *dev_priv = dev->dev_private;
1363         u16 ddrpll, csipll;
1364
1365         ddrpll = I915_READ16(DDRMPLL1);
1366         csipll = I915_READ16(CSIPLL0);
1367
1368         switch (ddrpll & 0xff) {
1369         case 0xc:
1370                 dev_priv->mem_freq = 800;
1371                 break;
1372         case 0x10:
1373                 dev_priv->mem_freq = 1066;
1374                 break;
1375         case 0x14:
1376                 dev_priv->mem_freq = 1333;
1377                 break;
1378         case 0x18:
1379                 dev_priv->mem_freq = 1600;
1380                 break;
1381         default:
1382                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1383                                  ddrpll & 0xff);
1384                 dev_priv->mem_freq = 0;
1385                 break;
1386         }
1387
1388         dev_priv->r_t = dev_priv->mem_freq;
1389
1390         switch (csipll & 0x3ff) {
1391         case 0x00c:
1392                 dev_priv->fsb_freq = 3200;
1393                 break;
1394         case 0x00e:
1395                 dev_priv->fsb_freq = 3733;
1396                 break;
1397         case 0x010:
1398                 dev_priv->fsb_freq = 4266;
1399                 break;
1400         case 0x012:
1401                 dev_priv->fsb_freq = 4800;
1402                 break;
1403         case 0x014:
1404                 dev_priv->fsb_freq = 5333;
1405                 break;
1406         case 0x016:
1407                 dev_priv->fsb_freq = 5866;
1408                 break;
1409         case 0x018:
1410                 dev_priv->fsb_freq = 6400;
1411                 break;
1412         default:
1413                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1414                                  csipll & 0x3ff);
1415                 dev_priv->fsb_freq = 0;
1416                 break;
1417         }
1418
1419         if (dev_priv->fsb_freq == 3200) {
1420                 dev_priv->c_m = 0;
1421         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1422                 dev_priv->c_m = 1;
1423         } else {
1424                 dev_priv->c_m = 2;
1425         }
1426 }
1427
1428 struct v_table {
1429         u8 vid;
1430         unsigned long vd; /* in .1 mil */
1431         unsigned long vm; /* in .1 mil */
1432         u8 pvid;
1433 };
1434
1435 static struct v_table v_table[] = {
1436         { 0, 16125, 15000, 0x7f, },
1437         { 1, 16000, 14875, 0x7e, },
1438         { 2, 15875, 14750, 0x7d, },
1439         { 3, 15750, 14625, 0x7c, },
1440         { 4, 15625, 14500, 0x7b, },
1441         { 5, 15500, 14375, 0x7a, },
1442         { 6, 15375, 14250, 0x79, },
1443         { 7, 15250, 14125, 0x78, },
1444         { 8, 15125, 14000, 0x77, },
1445         { 9, 15000, 13875, 0x76, },
1446         { 10, 14875, 13750, 0x75, },
1447         { 11, 14750, 13625, 0x74, },
1448         { 12, 14625, 13500, 0x73, },
1449         { 13, 14500, 13375, 0x72, },
1450         { 14, 14375, 13250, 0x71, },
1451         { 15, 14250, 13125, 0x70, },
1452         { 16, 14125, 13000, 0x6f, },
1453         { 17, 14000, 12875, 0x6e, },
1454         { 18, 13875, 12750, 0x6d, },
1455         { 19, 13750, 12625, 0x6c, },
1456         { 20, 13625, 12500, 0x6b, },
1457         { 21, 13500, 12375, 0x6a, },
1458         { 22, 13375, 12250, 0x69, },
1459         { 23, 13250, 12125, 0x68, },
1460         { 24, 13125, 12000, 0x67, },
1461         { 25, 13000, 11875, 0x66, },
1462         { 26, 12875, 11750, 0x65, },
1463         { 27, 12750, 11625, 0x64, },
1464         { 28, 12625, 11500, 0x63, },
1465         { 29, 12500, 11375, 0x62, },
1466         { 30, 12375, 11250, 0x61, },
1467         { 31, 12250, 11125, 0x60, },
1468         { 32, 12125, 11000, 0x5f, },
1469         { 33, 12000, 10875, 0x5e, },
1470         { 34, 11875, 10750, 0x5d, },
1471         { 35, 11750, 10625, 0x5c, },
1472         { 36, 11625, 10500, 0x5b, },
1473         { 37, 11500, 10375, 0x5a, },
1474         { 38, 11375, 10250, 0x59, },
1475         { 39, 11250, 10125, 0x58, },
1476         { 40, 11125, 10000, 0x57, },
1477         { 41, 11000, 9875, 0x56, },
1478         { 42, 10875, 9750, 0x55, },
1479         { 43, 10750, 9625, 0x54, },
1480         { 44, 10625, 9500, 0x53, },
1481         { 45, 10500, 9375, 0x52, },
1482         { 46, 10375, 9250, 0x51, },
1483         { 47, 10250, 9125, 0x50, },
1484         { 48, 10125, 9000, 0x4f, },
1485         { 49, 10000, 8875, 0x4e, },
1486         { 50, 9875, 8750, 0x4d, },
1487         { 51, 9750, 8625, 0x4c, },
1488         { 52, 9625, 8500, 0x4b, },
1489         { 53, 9500, 8375, 0x4a, },
1490         { 54, 9375, 8250, 0x49, },
1491         { 55, 9250, 8125, 0x48, },
1492         { 56, 9125, 8000, 0x47, },
1493         { 57, 9000, 7875, 0x46, },
1494         { 58, 8875, 7750, 0x45, },
1495         { 59, 8750, 7625, 0x44, },
1496         { 60, 8625, 7500, 0x43, },
1497         { 61, 8500, 7375, 0x42, },
1498         { 62, 8375, 7250, 0x41, },
1499         { 63, 8250, 7125, 0x40, },
1500         { 64, 8125, 7000, 0x3f, },
1501         { 65, 8000, 6875, 0x3e, },
1502         { 66, 7875, 6750, 0x3d, },
1503         { 67, 7750, 6625, 0x3c, },
1504         { 68, 7625, 6500, 0x3b, },
1505         { 69, 7500, 6375, 0x3a, },
1506         { 70, 7375, 6250, 0x39, },
1507         { 71, 7250, 6125, 0x38, },
1508         { 72, 7125, 6000, 0x37, },
1509         { 73, 7000, 5875, 0x36, },
1510         { 74, 6875, 5750, 0x35, },
1511         { 75, 6750, 5625, 0x34, },
1512         { 76, 6625, 5500, 0x33, },
1513         { 77, 6500, 5375, 0x32, },
1514         { 78, 6375, 5250, 0x31, },
1515         { 79, 6250, 5125, 0x30, },
1516         { 80, 6125, 5000, 0x2f, },
1517         { 81, 6000, 4875, 0x2e, },
1518         { 82, 5875, 4750, 0x2d, },
1519         { 83, 5750, 4625, 0x2c, },
1520         { 84, 5625, 4500, 0x2b, },
1521         { 85, 5500, 4375, 0x2a, },
1522         { 86, 5375, 4250, 0x29, },
1523         { 87, 5250, 4125, 0x28, },
1524         { 88, 5125, 4000, 0x27, },
1525         { 89, 5000, 3875, 0x26, },
1526         { 90, 4875, 3750, 0x25, },
1527         { 91, 4750, 3625, 0x24, },
1528         { 92, 4625, 3500, 0x23, },
1529         { 93, 4500, 3375, 0x22, },
1530         { 94, 4375, 3250, 0x21, },
1531         { 95, 4250, 3125, 0x20, },
1532         { 96, 4125, 3000, 0x1f, },
1533         { 97, 4125, 3000, 0x1e, },
1534         { 98, 4125, 3000, 0x1d, },
1535         { 99, 4125, 3000, 0x1c, },
1536         { 100, 4125, 3000, 0x1b, },
1537         { 101, 4125, 3000, 0x1a, },
1538         { 102, 4125, 3000, 0x19, },
1539         { 103, 4125, 3000, 0x18, },
1540         { 104, 4125, 3000, 0x17, },
1541         { 105, 4125, 3000, 0x16, },
1542         { 106, 4125, 3000, 0x15, },
1543         { 107, 4125, 3000, 0x14, },
1544         { 108, 4125, 3000, 0x13, },
1545         { 109, 4125, 3000, 0x12, },
1546         { 110, 4125, 3000, 0x11, },
1547         { 111, 4125, 3000, 0x10, },
1548         { 112, 4125, 3000, 0x0f, },
1549         { 113, 4125, 3000, 0x0e, },
1550         { 114, 4125, 3000, 0x0d, },
1551         { 115, 4125, 3000, 0x0c, },
1552         { 116, 4125, 3000, 0x0b, },
1553         { 117, 4125, 3000, 0x0a, },
1554         { 118, 4125, 3000, 0x09, },
1555         { 119, 4125, 3000, 0x08, },
1556         { 120, 1125, 0, 0x07, },
1557         { 121, 1000, 0, 0x06, },
1558         { 122, 875, 0, 0x05, },
1559         { 123, 750, 0, 0x04, },
1560         { 124, 625, 0, 0x03, },
1561         { 125, 500, 0, 0x02, },
1562         { 126, 375, 0, 0x01, },
1563         { 127, 0, 0, 0x00, },
1564 };
1565
1566 struct cparams {
1567         int i;
1568         int t;
1569         int m;
1570         int c;
1571 };
1572
1573 static struct cparams cparams[] = {
1574         { 1, 1333, 301, 28664 },
1575         { 1, 1066, 294, 24460 },
1576         { 1, 800, 294, 25192 },
1577         { 0, 1333, 276, 27605 },
1578         { 0, 1066, 276, 27605 },
1579         { 0, 800, 231, 23784 },
1580 };
1581
1582 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1583 {
1584         u64 total_count, diff, ret;
1585         u32 count1, count2, count3, m = 0, c = 0;
1586         unsigned long now = jiffies_to_msecs(jiffies), diff1;
1587         int i;
1588
1589         diff1 = now - dev_priv->last_time1;
1590
1591         count1 = I915_READ(DMIEC);
1592         count2 = I915_READ(DDREC);
1593         count3 = I915_READ(CSIEC);
1594
1595         total_count = count1 + count2 + count3;
1596
1597         /* FIXME: handle per-counter overflow */
1598         if (total_count < dev_priv->last_count1) {
1599                 diff = ~0UL - dev_priv->last_count1;
1600                 diff += total_count;
1601         } else {
1602                 diff = total_count - dev_priv->last_count1;
1603         }
1604
1605         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1606                 if (cparams[i].i == dev_priv->c_m &&
1607                     cparams[i].t == dev_priv->r_t) {
1608                         m = cparams[i].m;
1609                         c = cparams[i].c;
1610                         break;
1611                 }
1612         }
1613
1614         diff = div_u64(diff, diff1);
1615         ret = ((m * diff) + c);
1616         ret = div_u64(ret, 10);
1617
1618         dev_priv->last_count1 = total_count;
1619         dev_priv->last_time1 = now;
1620
1621         return ret;
1622 }
1623
1624 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1625 {
1626         unsigned long m, x, b;
1627         u32 tsfs;
1628
1629         tsfs = I915_READ(TSFS);
1630
1631         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1632         x = I915_READ8(TR1);
1633
1634         b = tsfs & TSFS_INTR_MASK;
1635
1636         return ((m * x) / 127) - b;
1637 }
1638
1639 static unsigned long pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1640 {
1641         unsigned long val = 0;
1642         int i;
1643
1644         for (i = 0; i < ARRAY_SIZE(v_table); i++) {
1645                 if (v_table[i].pvid == pxvid) {
1646                         if (IS_MOBILE(dev_priv->dev))
1647                                 val = v_table[i].vm;
1648                         else
1649                                 val = v_table[i].vd;
1650                 }
1651         }
1652
1653         return val;
1654 }
1655
1656 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1657 {
1658         struct timespec now, diff1;
1659         u64 diff;
1660         unsigned long diffms;
1661         u32 count;
1662
1663         getrawmonotonic(&now);
1664         diff1 = timespec_sub(now, dev_priv->last_time2);
1665
1666         /* Don't divide by 0 */
1667         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1668         if (!diffms)
1669                 return;
1670
1671         count = I915_READ(GFXEC);
1672
1673         if (count < dev_priv->last_count2) {
1674                 diff = ~0UL - dev_priv->last_count2;
1675                 diff += count;
1676         } else {
1677                 diff = count - dev_priv->last_count2;
1678         }
1679
1680         dev_priv->last_count2 = count;
1681         dev_priv->last_time2 = now;
1682
1683         /* More magic constants... */
1684         diff = diff * 1181;
1685         diff = div_u64(diff, diffms * 10);
1686         dev_priv->gfx_power = diff;
1687 }
1688
1689 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1690 {
1691         unsigned long t, corr, state1, corr2, state2;
1692         u32 pxvid, ext_v;
1693
1694         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1695         pxvid = (pxvid >> 24) & 0x7f;
1696         ext_v = pvid_to_extvid(dev_priv, pxvid);
1697
1698         state1 = ext_v;
1699
1700         t = i915_mch_val(dev_priv);
1701
1702         /* Revel in the empirically derived constants */
1703
1704         /* Correction factor in 1/100000 units */
1705         if (t > 80)
1706                 corr = ((t * 2349) + 135940);
1707         else if (t >= 50)
1708                 corr = ((t * 964) + 29317);
1709         else /* < 50 */
1710                 corr = ((t * 301) + 1004);
1711
1712         corr = corr * ((150142 * state1) / 10000 - 78642);
1713         corr /= 100000;
1714         corr2 = (corr * dev_priv->corr);
1715
1716         state2 = (corr2 * state1) / 10000;
1717         state2 /= 100; /* convert to mW */
1718
1719         i915_update_gfx_val(dev_priv);
1720
1721         return dev_priv->gfx_power + state2;
1722 }
1723
1724 /* Global for IPS driver to get at the current i915 device */
1725 static struct drm_i915_private *i915_mch_dev;
1726 /*
1727  * Lock protecting IPS related data structures
1728  *   - i915_mch_dev
1729  *   - dev_priv->max_delay
1730  *   - dev_priv->min_delay
1731  *   - dev_priv->fmax
1732  *   - dev_priv->gpu_busy
1733  */
1734 static DEFINE_SPINLOCK(mchdev_lock);
1735
1736 /**
1737  * i915_read_mch_val - return value for IPS use
1738  *
1739  * Calculate and return a value for the IPS driver to use when deciding whether
1740  * we have thermal and power headroom to increase CPU or GPU power budget.
1741  */
1742 unsigned long i915_read_mch_val(void)
1743 {
1744         struct drm_i915_private *dev_priv;
1745         unsigned long chipset_val, graphics_val, ret = 0;
1746
1747         spin_lock(&mchdev_lock);
1748         if (!i915_mch_dev)
1749                 goto out_unlock;
1750         dev_priv = i915_mch_dev;
1751
1752         chipset_val = i915_chipset_val(dev_priv);
1753         graphics_val = i915_gfx_val(dev_priv);
1754
1755         ret = chipset_val + graphics_val;
1756
1757 out_unlock:
1758         spin_unlock(&mchdev_lock);
1759
1760         return ret;
1761 }
1762 EXPORT_SYMBOL_GPL(i915_read_mch_val);
1763
1764 /**
1765  * i915_gpu_raise - raise GPU frequency limit
1766  *
1767  * Raise the limit; IPS indicates we have thermal headroom.
1768  */
1769 bool i915_gpu_raise(void)
1770 {
1771         struct drm_i915_private *dev_priv;
1772         bool ret = true;
1773
1774         spin_lock(&mchdev_lock);
1775         if (!i915_mch_dev) {
1776                 ret = false;
1777                 goto out_unlock;
1778         }
1779         dev_priv = i915_mch_dev;
1780
1781         if (dev_priv->max_delay > dev_priv->fmax)
1782                 dev_priv->max_delay--;
1783
1784 out_unlock:
1785         spin_unlock(&mchdev_lock);
1786
1787         return ret;
1788 }
1789 EXPORT_SYMBOL_GPL(i915_gpu_raise);
1790
1791 /**
1792  * i915_gpu_lower - lower GPU frequency limit
1793  *
1794  * IPS indicates we're close to a thermal limit, so throttle back the GPU
1795  * frequency maximum.
1796  */
1797 bool i915_gpu_lower(void)
1798 {
1799         struct drm_i915_private *dev_priv;
1800         bool ret = true;
1801
1802         spin_lock(&mchdev_lock);
1803         if (!i915_mch_dev) {
1804                 ret = false;
1805                 goto out_unlock;
1806         }
1807         dev_priv = i915_mch_dev;
1808
1809         if (dev_priv->max_delay < dev_priv->min_delay)
1810                 dev_priv->max_delay++;
1811
1812 out_unlock:
1813         spin_unlock(&mchdev_lock);
1814
1815         return ret;
1816 }
1817 EXPORT_SYMBOL_GPL(i915_gpu_lower);
1818
1819 /**
1820  * i915_gpu_busy - indicate GPU business to IPS
1821  *
1822  * Tell the IPS driver whether or not the GPU is busy.
1823  */
1824 bool i915_gpu_busy(void)
1825 {
1826         struct drm_i915_private *dev_priv;
1827         bool ret = false;
1828
1829         spin_lock(&mchdev_lock);
1830         if (!i915_mch_dev)
1831                 goto out_unlock;
1832         dev_priv = i915_mch_dev;
1833
1834         ret = dev_priv->busy;
1835
1836 out_unlock:
1837         spin_unlock(&mchdev_lock);
1838
1839         return ret;
1840 }
1841 EXPORT_SYMBOL_GPL(i915_gpu_busy);
1842
1843 /**
1844  * i915_gpu_turbo_disable - disable graphics turbo
1845  *
1846  * Disable graphics turbo by resetting the max frequency and setting the
1847  * current frequency to the default.
1848  */
1849 bool i915_gpu_turbo_disable(void)
1850 {
1851         struct drm_i915_private *dev_priv;
1852         bool ret = true;
1853
1854         spin_lock(&mchdev_lock);
1855         if (!i915_mch_dev) {
1856                 ret = false;
1857                 goto out_unlock;
1858         }
1859         dev_priv = i915_mch_dev;
1860
1861         dev_priv->max_delay = dev_priv->fstart;
1862
1863         if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
1864                 ret = false;
1865
1866 out_unlock:
1867         spin_unlock(&mchdev_lock);
1868
1869         return ret;
1870 }
1871 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
1872
1873 /**
1874  * i915_driver_load - setup chip and create an initial config
1875  * @dev: DRM device
1876  * @flags: startup flags
1877  *
1878  * The driver load routine has to do several things:
1879  *   - drive output discovery via intel_modeset_init()
1880  *   - initialize the memory manager
1881  *   - allocate initial config memory
1882  *   - setup the DRM framebuffer with the allocated memory
1883  */
1884 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1885 {
1886         struct drm_i915_private *dev_priv;
1887         resource_size_t base, size;
1888         int ret = 0, mmio_bar;
1889         uint32_t agp_size, prealloc_size;
1890         /* i915 has 4 more counters */
1891         dev->counters += 4;
1892         dev->types[6] = _DRM_STAT_IRQ;
1893         dev->types[7] = _DRM_STAT_PRIMARY;
1894         dev->types[8] = _DRM_STAT_SECONDARY;
1895         dev->types[9] = _DRM_STAT_DMA;
1896
1897         dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1898         if (dev_priv == NULL)
1899                 return -ENOMEM;
1900
1901         dev->dev_private = (void *)dev_priv;
1902         dev_priv->dev = dev;
1903         dev_priv->info = (struct intel_device_info *) flags;
1904
1905         /* Add register map (needed for suspend/resume) */
1906         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1907         base = pci_resource_start(dev->pdev, mmio_bar);
1908         size = pci_resource_len(dev->pdev, mmio_bar);
1909
1910         if (i915_get_bridge_dev(dev)) {
1911                 ret = -EIO;
1912                 goto free_priv;
1913         }
1914
1915         /* overlay on gen2 is broken and can't address above 1G */
1916         if (IS_GEN2(dev))
1917                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1918
1919         dev_priv->regs = ioremap(base, size);
1920         if (!dev_priv->regs) {
1921                 DRM_ERROR("failed to map registers\n");
1922                 ret = -EIO;
1923                 goto put_bridge;
1924         }
1925
1926         dev_priv->mm.gtt_mapping =
1927                 io_mapping_create_wc(dev->agp->base,
1928                                      dev->agp->agp_info.aper_size * 1024*1024);
1929         if (dev_priv->mm.gtt_mapping == NULL) {
1930                 ret = -EIO;
1931                 goto out_rmmap;
1932         }
1933
1934         /* Set up a WC MTRR for non-PAT systems.  This is more common than
1935          * one would think, because the kernel disables PAT on first
1936          * generation Core chips because WC PAT gets overridden by a UC
1937          * MTRR if present.  Even if a UC MTRR isn't present.
1938          */
1939         dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
1940                                          dev->agp->agp_info.aper_size *
1941                                          1024 * 1024,
1942                                          MTRR_TYPE_WRCOMB, 1);
1943         if (dev_priv->mm.gtt_mtrr < 0) {
1944                 DRM_INFO("MTRR allocation failed.  Graphics "
1945                          "performance may suffer.\n");
1946         }
1947
1948         dev_priv->mm.gtt = intel_gtt_get();
1949         if (!dev_priv->mm.gtt) {
1950                 DRM_ERROR("Failed to initialize GTT\n");
1951                 ret = -ENODEV;
1952                 goto out_iomapfree;
1953         }
1954
1955         prealloc_size = dev_priv->mm.gtt->gtt_stolen_entries << PAGE_SHIFT;
1956         agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1957
1958         /* The i915 workqueue is primarily used for batched retirement of
1959          * requests (and thus managing bo) once the task has been completed
1960          * by the GPU. i915_gem_retire_requests() is called directly when we
1961          * need high-priority retirement, such as waiting for an explicit
1962          * bo.
1963          *
1964          * It is also used for periodic low-priority events, such as
1965          * idle-timers and hangcheck.
1966          *
1967          * All tasks on the workqueue are expected to acquire the dev mutex
1968          * so there is no point in running more than one instance of the
1969          * workqueue at any time: max_active = 1 and NON_REENTRANT.
1970          */
1971         dev_priv->wq = alloc_workqueue("i915",
1972                                        WQ_UNBOUND | WQ_NON_REENTRANT,
1973                                        1);
1974         if (dev_priv->wq == NULL) {
1975                 DRM_ERROR("Failed to create our workqueue.\n");
1976                 ret = -ENOMEM;
1977                 goto out_iomapfree;
1978         }
1979
1980         /* enable GEM by default */
1981         dev_priv->has_gem = 1;
1982
1983         if (prealloc_size > agp_size * 3 / 4) {
1984                 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
1985                           "memory stolen.\n",
1986                           prealloc_size / 1024, agp_size / 1024);
1987                 DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
1988                           "updating the BIOS to fix).\n");
1989                 dev_priv->has_gem = 0;
1990         }
1991
1992         if (dev_priv->has_gem == 0 &&
1993             drm_core_check_feature(dev, DRIVER_MODESET)) {
1994                 DRM_ERROR("kernel modesetting requires GEM, disabling driver.\n");
1995                 ret = -ENODEV;
1996                 goto out_iomapfree;
1997         }
1998
1999         dev->driver->get_vblank_counter = i915_get_vblank_counter;
2000         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2001         if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
2002                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2003                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2004         }
2005
2006         /* Try to make sure MCHBAR is enabled before poking at it */
2007         intel_setup_mchbar(dev);
2008         intel_setup_gmbus(dev);
2009         intel_opregion_setup(dev);
2010
2011         /* Make sure the bios did its job and set up vital registers */
2012         intel_setup_bios(dev);
2013
2014         i915_gem_load(dev);
2015
2016         /* Init HWS */
2017         if (!I915_NEED_GFX_HWS(dev)) {
2018                 ret = i915_init_phys_hws(dev);
2019                 if (ret != 0)
2020                         goto out_workqueue_free;
2021         }
2022
2023         if (IS_PINEVIEW(dev))
2024                 i915_pineview_get_mem_freq(dev);
2025         else if (IS_GEN5(dev))
2026                 i915_ironlake_get_mem_freq(dev);
2027
2028         /* On the 945G/GM, the chipset reports the MSI capability on the
2029          * integrated graphics even though the support isn't actually there
2030          * according to the published specs.  It doesn't appear to function
2031          * correctly in testing on 945G.
2032          * This may be a side effect of MSI having been made available for PEG
2033          * and the registers being closely associated.
2034          *
2035          * According to chipset errata, on the 965GM, MSI interrupts may
2036          * be lost or delayed, but we use them anyways to avoid
2037          * stuck interrupts on some machines.
2038          */
2039         if (!IS_I945G(dev) && !IS_I945GM(dev))
2040                 pci_enable_msi(dev->pdev);
2041
2042         spin_lock_init(&dev_priv->user_irq_lock);
2043         spin_lock_init(&dev_priv->error_lock);
2044         dev_priv->trace_irq_seqno = 0;
2045
2046         ret = drm_vblank_init(dev, I915_NUM_PIPE);
2047
2048         if (ret) {
2049                 (void) i915_driver_unload(dev);
2050                 return ret;
2051         }
2052
2053         /* Start out suspended */
2054         dev_priv->mm.suspended = 1;
2055
2056         intel_detect_pch(dev);
2057
2058         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2059                 ret = i915_load_modeset_init(dev, prealloc_size, agp_size);
2060                 if (ret < 0) {
2061                         DRM_ERROR("failed to init modeset\n");
2062                         goto out_workqueue_free;
2063                 }
2064         }
2065
2066         /* Must be done after probing outputs */
2067         intel_opregion_init(dev);
2068         acpi_video_register();
2069
2070         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2071                     (unsigned long) dev);
2072
2073         spin_lock(&mchdev_lock);
2074         i915_mch_dev = dev_priv;
2075         dev_priv->mchdev_lock = &mchdev_lock;
2076         spin_unlock(&mchdev_lock);
2077
2078         return 0;
2079
2080 out_workqueue_free:
2081         destroy_workqueue(dev_priv->wq);
2082 out_iomapfree:
2083         io_mapping_free(dev_priv->mm.gtt_mapping);
2084 out_rmmap:
2085         iounmap(dev_priv->regs);
2086 put_bridge:
2087         pci_dev_put(dev_priv->bridge_dev);
2088 free_priv:
2089         kfree(dev_priv);
2090         return ret;
2091 }
2092
2093 int i915_driver_unload(struct drm_device *dev)
2094 {
2095         struct drm_i915_private *dev_priv = dev->dev_private;
2096         int ret;
2097
2098         spin_lock(&mchdev_lock);
2099         i915_mch_dev = NULL;
2100         spin_unlock(&mchdev_lock);
2101
2102         mutex_lock(&dev->struct_mutex);
2103         ret = i915_gpu_idle(dev);
2104         if (ret)
2105                 DRM_ERROR("failed to idle hardware: %d\n", ret);
2106         mutex_unlock(&dev->struct_mutex);
2107
2108         /* Cancel the retire work handler, which should be idle now. */
2109         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2110
2111         io_mapping_free(dev_priv->mm.gtt_mapping);
2112         if (dev_priv->mm.gtt_mtrr >= 0) {
2113                 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2114                          dev->agp->agp_info.aper_size * 1024 * 1024);
2115                 dev_priv->mm.gtt_mtrr = -1;
2116         }
2117
2118         acpi_video_unregister();
2119
2120         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2121                 intel_fbdev_fini(dev);
2122                 intel_modeset_cleanup(dev);
2123
2124                 /*
2125                  * free the memory space allocated for the child device
2126                  * config parsed from VBT
2127                  */
2128                 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2129                         kfree(dev_priv->child_dev);
2130                         dev_priv->child_dev = NULL;
2131                         dev_priv->child_dev_num = 0;
2132                 }
2133
2134                 vga_switcheroo_unregister_client(dev->pdev);
2135                 vga_client_register(dev->pdev, NULL, NULL, NULL);
2136         }
2137
2138         /* Free error state after interrupts are fully disabled. */
2139         del_timer_sync(&dev_priv->hangcheck_timer);
2140         cancel_work_sync(&dev_priv->error_work);
2141         i915_destroy_error_state(dev);
2142
2143         if (dev->pdev->msi_enabled)
2144                 pci_disable_msi(dev->pdev);
2145
2146         intel_opregion_fini(dev);
2147
2148         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2149                 /* Flush any outstanding unpin_work. */
2150                 flush_workqueue(dev_priv->wq);
2151
2152                 i915_gem_free_all_phys_object(dev);
2153
2154                 mutex_lock(&dev->struct_mutex);
2155                 i915_gem_cleanup_ringbuffer(dev);
2156                 mutex_unlock(&dev->struct_mutex);
2157                 if (I915_HAS_FBC(dev) && i915_powersave)
2158                         i915_cleanup_compression(dev);
2159                 drm_mm_takedown(&dev_priv->mm.vram);
2160
2161                 intel_cleanup_overlay(dev);
2162
2163                 if (!I915_NEED_GFX_HWS(dev))
2164                         i915_free_hws(dev);
2165         }
2166
2167         if (dev_priv->regs != NULL)
2168                 iounmap(dev_priv->regs);
2169
2170         intel_teardown_gmbus(dev);
2171         intel_teardown_mchbar(dev);
2172
2173         destroy_workqueue(dev_priv->wq);
2174
2175         pci_dev_put(dev_priv->bridge_dev);
2176         kfree(dev->dev_private);
2177
2178         return 0;
2179 }
2180
2181 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2182 {
2183         struct drm_i915_file_private *file_priv;
2184
2185         DRM_DEBUG_DRIVER("\n");
2186         file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
2187         if (!file_priv)
2188                 return -ENOMEM;
2189
2190         file->driver_priv = file_priv;
2191
2192         spin_lock_init(&file_priv->mm.lock);
2193         INIT_LIST_HEAD(&file_priv->mm.request_list);
2194
2195         return 0;
2196 }
2197
2198 /**
2199  * i915_driver_lastclose - clean up after all DRM clients have exited
2200  * @dev: DRM device
2201  *
2202  * Take care of cleaning up after all DRM clients have exited.  In the
2203  * mode setting case, we want to restore the kernel's initial mode (just
2204  * in case the last client left us in a bad state).
2205  *
2206  * Additionally, in the non-mode setting case, we'll tear down the AGP
2207  * and DMA structures, since the kernel won't be using them, and clea
2208  * up any GEM state.
2209  */
2210 void i915_driver_lastclose(struct drm_device * dev)
2211 {
2212         drm_i915_private_t *dev_priv = dev->dev_private;
2213
2214         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
2215                 drm_fb_helper_restore();
2216                 vga_switcheroo_process_delayed_switch();
2217                 return;
2218         }
2219
2220         i915_gem_lastclose(dev);
2221
2222         if (dev_priv->agp_heap)
2223                 i915_mem_takedown(&(dev_priv->agp_heap));
2224
2225         i915_dma_cleanup(dev);
2226 }
2227
2228 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
2229 {
2230         drm_i915_private_t *dev_priv = dev->dev_private;
2231         i915_gem_release(dev, file_priv);
2232         if (!drm_core_check_feature(dev, DRIVER_MODESET))
2233                 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
2234 }
2235
2236 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
2237 {
2238         struct drm_i915_file_private *file_priv = file->driver_priv;
2239
2240         kfree(file_priv);
2241 }
2242
2243 struct drm_ioctl_desc i915_ioctls[] = {
2244         DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2245         DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2246         DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2247         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2248         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2249         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2250         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
2251         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2252         DRM_IOCTL_DEF_DRV(I915_ALLOC, i915_mem_alloc, DRM_AUTH),
2253         DRM_IOCTL_DEF_DRV(I915_FREE, i915_mem_free, DRM_AUTH),
2254         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2255         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2256         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2257         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2258         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
2259         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2260         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2261         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2262         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2263         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2264         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2265         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2266         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2267         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2268         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2269         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2270         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2271         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2272         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2273         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2274         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2275         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2276         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2277         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2278         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2279         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2280         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2281         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2282         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2283         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2284 };
2285
2286 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
2287
2288 /**
2289  * Determine if the device really is AGP or not.
2290  *
2291  * All Intel graphics chipsets are treated as AGP, even if they are really
2292  * PCI-e.
2293  *
2294  * \param dev   The device to be tested.
2295  *
2296  * \returns
2297  * A value of 1 is always retured to indictate every i9x5 is AGP.
2298  */
2299 int i915_driver_device_is_agp(struct drm_device * dev)
2300 {
2301         return 1;
2302 }