e3e5d50942325a4ec35c6f5ecce3a39dced82769
[linux-2.6.git] / drivers / gpu / drm / i915 / i915_dma.c
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2  */
3 /*
4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5  * All Rights Reserved.
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a
8  * copy of this software and associated documentation files (the
9  * "Software"), to deal in the Software without restriction, including
10  * without limitation the rights to use, copy, modify, merge, publish,
11  * distribute, sub license, and/or sell copies of the Software, and to
12  * permit persons to whom the Software is furnished to do so, subject to
13  * the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the
16  * next paragraph) shall be included in all copies or substantial portions
17  * of the Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26  *
27  */
28
29 #include "drmP.h"
30 #include "drm.h"
31 #include "drm_crtc_helper.h"
32 #include "drm_fb_helper.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "i915_trace.h"
37 #include <linux/vgaarb.h>
38
39 /* Really want an OS-independent resettable timer.  Would like to have
40  * this loop run for (eg) 3 sec, but have the timer reset every time
41  * the head pointer changes, so that EBUSY only happens if the ring
42  * actually stalls for (eg) 3 seconds.
43  */
44 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
45 {
46         drm_i915_private_t *dev_priv = dev->dev_private;
47         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
48         u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
49         u32 last_acthd = I915_READ(acthd_reg);
50         u32 acthd;
51         u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
52         int i;
53
54         trace_i915_ring_wait_begin (dev);
55
56         for (i = 0; i < 100000; i++) {
57                 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
58                 acthd = I915_READ(acthd_reg);
59                 ring->space = ring->head - (ring->tail + 8);
60                 if (ring->space < 0)
61                         ring->space += ring->Size;
62                 if (ring->space >= n) {
63                         trace_i915_ring_wait_end (dev);
64                         return 0;
65                 }
66
67                 if (dev->primary->master) {
68                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
69                         if (master_priv->sarea_priv)
70                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
71                 }
72
73
74                 if (ring->head != last_head)
75                         i = 0;
76                 if (acthd != last_acthd)
77                         i = 0;
78
79                 last_head = ring->head;
80                 last_acthd = acthd;
81                 msleep_interruptible(10);
82
83         }
84
85         trace_i915_ring_wait_end (dev);
86         return -EBUSY;
87 }
88
89 /* As a ringbuffer is only allowed to wrap between instructions, fill
90  * the tail with NOOPs.
91  */
92 int i915_wrap_ring(struct drm_device *dev)
93 {
94         drm_i915_private_t *dev_priv = dev->dev_private;
95         volatile unsigned int *virt;
96         int rem;
97
98         rem = dev_priv->ring.Size - dev_priv->ring.tail;
99         if (dev_priv->ring.space < rem) {
100                 int ret = i915_wait_ring(dev, rem, __func__);
101                 if (ret)
102                         return ret;
103         }
104         dev_priv->ring.space -= rem;
105
106         virt = (unsigned int *)
107                 (dev_priv->ring.virtual_start + dev_priv->ring.tail);
108         rem /= 4;
109         while (rem--)
110                 *virt++ = MI_NOOP;
111
112         dev_priv->ring.tail = 0;
113
114         return 0;
115 }
116
117 /**
118  * Sets up the hardware status page for devices that need a physical address
119  * in the register.
120  */
121 static int i915_init_phys_hws(struct drm_device *dev)
122 {
123         drm_i915_private_t *dev_priv = dev->dev_private;
124         /* Program Hardware Status Page */
125         dev_priv->status_page_dmah =
126                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
127
128         if (!dev_priv->status_page_dmah) {
129                 DRM_ERROR("Can not allocate hardware status page\n");
130                 return -ENOMEM;
131         }
132         dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
133         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
134
135         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
136
137         I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
138         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
139         return 0;
140 }
141
142 /**
143  * Frees the hardware status page, whether it's a physical address or a virtual
144  * address set up by the X Server.
145  */
146 static void i915_free_hws(struct drm_device *dev)
147 {
148         drm_i915_private_t *dev_priv = dev->dev_private;
149         if (dev_priv->status_page_dmah) {
150                 drm_pci_free(dev, dev_priv->status_page_dmah);
151                 dev_priv->status_page_dmah = NULL;
152         }
153
154         if (dev_priv->status_gfx_addr) {
155                 dev_priv->status_gfx_addr = 0;
156                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
157         }
158
159         /* Need to rewrite hardware status page */
160         I915_WRITE(HWS_PGA, 0x1ffff000);
161 }
162
163 void i915_kernel_lost_context(struct drm_device * dev)
164 {
165         drm_i915_private_t *dev_priv = dev->dev_private;
166         struct drm_i915_master_private *master_priv;
167         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
168
169         /*
170          * We should never lose context on the ring with modesetting
171          * as we don't expose it to userspace
172          */
173         if (drm_core_check_feature(dev, DRIVER_MODESET))
174                 return;
175
176         ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
177         ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
178         ring->space = ring->head - (ring->tail + 8);
179         if (ring->space < 0)
180                 ring->space += ring->Size;
181
182         if (!dev->primary->master)
183                 return;
184
185         master_priv = dev->primary->master->driver_priv;
186         if (ring->head == ring->tail && master_priv->sarea_priv)
187                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
188 }
189
190 static int i915_dma_cleanup(struct drm_device * dev)
191 {
192         drm_i915_private_t *dev_priv = dev->dev_private;
193         /* Make sure interrupts are disabled here because the uninstall ioctl
194          * may not have been called from userspace and after dev_private
195          * is freed, it's too late.
196          */
197         if (dev->irq_enabled)
198                 drm_irq_uninstall(dev);
199
200         if (dev_priv->ring.virtual_start) {
201                 drm_core_ioremapfree(&dev_priv->ring.map, dev);
202                 dev_priv->ring.virtual_start = NULL;
203                 dev_priv->ring.map.handle = NULL;
204                 dev_priv->ring.map.size = 0;
205         }
206
207         /* Clear the HWS virtual address at teardown */
208         if (I915_NEED_GFX_HWS(dev))
209                 i915_free_hws(dev);
210
211         return 0;
212 }
213
214 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
215 {
216         drm_i915_private_t *dev_priv = dev->dev_private;
217         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
218
219         master_priv->sarea = drm_getsarea(dev);
220         if (master_priv->sarea) {
221                 master_priv->sarea_priv = (drm_i915_sarea_t *)
222                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
223         } else {
224                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
225         }
226
227         if (init->ring_size != 0) {
228                 if (dev_priv->ring.ring_obj != NULL) {
229                         i915_dma_cleanup(dev);
230                         DRM_ERROR("Client tried to initialize ringbuffer in "
231                                   "GEM mode\n");
232                         return -EINVAL;
233                 }
234
235                 dev_priv->ring.Size = init->ring_size;
236
237                 dev_priv->ring.map.offset = init->ring_start;
238                 dev_priv->ring.map.size = init->ring_size;
239                 dev_priv->ring.map.type = 0;
240                 dev_priv->ring.map.flags = 0;
241                 dev_priv->ring.map.mtrr = 0;
242
243                 drm_core_ioremap_wc(&dev_priv->ring.map, dev);
244
245                 if (dev_priv->ring.map.handle == NULL) {
246                         i915_dma_cleanup(dev);
247                         DRM_ERROR("can not ioremap virtual address for"
248                                   " ring buffer\n");
249                         return -ENOMEM;
250                 }
251         }
252
253         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
254
255         dev_priv->cpp = init->cpp;
256         dev_priv->back_offset = init->back_offset;
257         dev_priv->front_offset = init->front_offset;
258         dev_priv->current_page = 0;
259         if (master_priv->sarea_priv)
260                 master_priv->sarea_priv->pf_current_page = 0;
261
262         /* Allow hardware batchbuffers unless told otherwise.
263          */
264         dev_priv->allow_batchbuffer = 1;
265
266         return 0;
267 }
268
269 static int i915_dma_resume(struct drm_device * dev)
270 {
271         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
272
273         DRM_DEBUG_DRIVER("%s\n", __func__);
274
275         if (dev_priv->ring.map.handle == NULL) {
276                 DRM_ERROR("can not ioremap virtual address for"
277                           " ring buffer\n");
278                 return -ENOMEM;
279         }
280
281         /* Program Hardware Status Page */
282         if (!dev_priv->hw_status_page) {
283                 DRM_ERROR("Can not find hardware status page\n");
284                 return -EINVAL;
285         }
286         DRM_DEBUG_DRIVER("hw status page @ %p\n",
287                                 dev_priv->hw_status_page);
288
289         if (dev_priv->status_gfx_addr != 0)
290                 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
291         else
292                 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
293         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
294
295         return 0;
296 }
297
298 static int i915_dma_init(struct drm_device *dev, void *data,
299                          struct drm_file *file_priv)
300 {
301         drm_i915_init_t *init = data;
302         int retcode = 0;
303
304         switch (init->func) {
305         case I915_INIT_DMA:
306                 retcode = i915_initialize(dev, init);
307                 break;
308         case I915_CLEANUP_DMA:
309                 retcode = i915_dma_cleanup(dev);
310                 break;
311         case I915_RESUME_DMA:
312                 retcode = i915_dma_resume(dev);
313                 break;
314         default:
315                 retcode = -EINVAL;
316                 break;
317         }
318
319         return retcode;
320 }
321
322 /* Implement basically the same security restrictions as hardware does
323  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
324  *
325  * Most of the calculations below involve calculating the size of a
326  * particular instruction.  It's important to get the size right as
327  * that tells us where the next instruction to check is.  Any illegal
328  * instruction detected will be given a size of zero, which is a
329  * signal to abort the rest of the buffer.
330  */
331 static int do_validate_cmd(int cmd)
332 {
333         switch (((cmd >> 29) & 0x7)) {
334         case 0x0:
335                 switch ((cmd >> 23) & 0x3f) {
336                 case 0x0:
337                         return 1;       /* MI_NOOP */
338                 case 0x4:
339                         return 1;       /* MI_FLUSH */
340                 default:
341                         return 0;       /* disallow everything else */
342                 }
343                 break;
344         case 0x1:
345                 return 0;       /* reserved */
346         case 0x2:
347                 return (cmd & 0xff) + 2;        /* 2d commands */
348         case 0x3:
349                 if (((cmd >> 24) & 0x1f) <= 0x18)
350                         return 1;
351
352                 switch ((cmd >> 24) & 0x1f) {
353                 case 0x1c:
354                         return 1;
355                 case 0x1d:
356                         switch ((cmd >> 16) & 0xff) {
357                         case 0x3:
358                                 return (cmd & 0x1f) + 2;
359                         case 0x4:
360                                 return (cmd & 0xf) + 2;
361                         default:
362                                 return (cmd & 0xffff) + 2;
363                         }
364                 case 0x1e:
365                         if (cmd & (1 << 23))
366                                 return (cmd & 0xffff) + 1;
367                         else
368                                 return 1;
369                 case 0x1f:
370                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
371                                 return (cmd & 0x1ffff) + 2;
372                         else if (cmd & (1 << 17))       /* indirect random */
373                                 if ((cmd & 0xffff) == 0)
374                                         return 0;       /* unknown length, too hard */
375                                 else
376                                         return (((cmd & 0xffff) + 1) / 2) + 1;
377                         else
378                                 return 2;       /* indirect sequential */
379                 default:
380                         return 0;
381                 }
382         default:
383                 return 0;
384         }
385
386         return 0;
387 }
388
389 static int validate_cmd(int cmd)
390 {
391         int ret = do_validate_cmd(cmd);
392
393 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
394
395         return ret;
396 }
397
398 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
399 {
400         drm_i915_private_t *dev_priv = dev->dev_private;
401         int i;
402         RING_LOCALS;
403
404         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
405                 return -EINVAL;
406
407         BEGIN_LP_RING((dwords+1)&~1);
408
409         for (i = 0; i < dwords;) {
410                 int cmd, sz;
411
412                 cmd = buffer[i];
413
414                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
415                         return -EINVAL;
416
417                 OUT_RING(cmd);
418
419                 while (++i, --sz) {
420                         OUT_RING(buffer[i]);
421                 }
422         }
423
424         if (dwords & 1)
425                 OUT_RING(0);
426
427         ADVANCE_LP_RING();
428
429         return 0;
430 }
431
432 int
433 i915_emit_box(struct drm_device *dev,
434               struct drm_clip_rect *boxes,
435               int i, int DR1, int DR4)
436 {
437         drm_i915_private_t *dev_priv = dev->dev_private;
438         struct drm_clip_rect box = boxes[i];
439         RING_LOCALS;
440
441         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
442                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
443                           box.x1, box.y1, box.x2, box.y2);
444                 return -EINVAL;
445         }
446
447         if (IS_I965G(dev)) {
448                 BEGIN_LP_RING(4);
449                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
450                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
451                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
452                 OUT_RING(DR4);
453                 ADVANCE_LP_RING();
454         } else {
455                 BEGIN_LP_RING(6);
456                 OUT_RING(GFX_OP_DRAWRECT_INFO);
457                 OUT_RING(DR1);
458                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
459                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
460                 OUT_RING(DR4);
461                 OUT_RING(0);
462                 ADVANCE_LP_RING();
463         }
464
465         return 0;
466 }
467
468 /* XXX: Emitting the counter should really be moved to part of the IRQ
469  * emit. For now, do it in both places:
470  */
471
472 static void i915_emit_breadcrumb(struct drm_device *dev)
473 {
474         drm_i915_private_t *dev_priv = dev->dev_private;
475         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
476         RING_LOCALS;
477
478         dev_priv->counter++;
479         if (dev_priv->counter > 0x7FFFFFFFUL)
480                 dev_priv->counter = 0;
481         if (master_priv->sarea_priv)
482                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
483
484         BEGIN_LP_RING(4);
485         OUT_RING(MI_STORE_DWORD_INDEX);
486         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
487         OUT_RING(dev_priv->counter);
488         OUT_RING(0);
489         ADVANCE_LP_RING();
490 }
491
492 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
493                                    drm_i915_cmdbuffer_t *cmd,
494                                    struct drm_clip_rect *cliprects,
495                                    void *cmdbuf)
496 {
497         int nbox = cmd->num_cliprects;
498         int i = 0, count, ret;
499
500         if (cmd->sz & 0x3) {
501                 DRM_ERROR("alignment");
502                 return -EINVAL;
503         }
504
505         i915_kernel_lost_context(dev);
506
507         count = nbox ? nbox : 1;
508
509         for (i = 0; i < count; i++) {
510                 if (i < nbox) {
511                         ret = i915_emit_box(dev, cliprects, i,
512                                             cmd->DR1, cmd->DR4);
513                         if (ret)
514                                 return ret;
515                 }
516
517                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
518                 if (ret)
519                         return ret;
520         }
521
522         i915_emit_breadcrumb(dev);
523         return 0;
524 }
525
526 static int i915_dispatch_batchbuffer(struct drm_device * dev,
527                                      drm_i915_batchbuffer_t * batch,
528                                      struct drm_clip_rect *cliprects)
529 {
530         drm_i915_private_t *dev_priv = dev->dev_private;
531         int nbox = batch->num_cliprects;
532         int i = 0, count;
533         RING_LOCALS;
534
535         if ((batch->start | batch->used) & 0x7) {
536                 DRM_ERROR("alignment");
537                 return -EINVAL;
538         }
539
540         i915_kernel_lost_context(dev);
541
542         count = nbox ? nbox : 1;
543
544         for (i = 0; i < count; i++) {
545                 if (i < nbox) {
546                         int ret = i915_emit_box(dev, cliprects, i,
547                                                 batch->DR1, batch->DR4);
548                         if (ret)
549                                 return ret;
550                 }
551
552                 if (!IS_I830(dev) && !IS_845G(dev)) {
553                         BEGIN_LP_RING(2);
554                         if (IS_I965G(dev)) {
555                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
556                                 OUT_RING(batch->start);
557                         } else {
558                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
559                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
560                         }
561                         ADVANCE_LP_RING();
562                 } else {
563                         BEGIN_LP_RING(4);
564                         OUT_RING(MI_BATCH_BUFFER);
565                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
566                         OUT_RING(batch->start + batch->used - 4);
567                         OUT_RING(0);
568                         ADVANCE_LP_RING();
569                 }
570         }
571
572         i915_emit_breadcrumb(dev);
573
574         return 0;
575 }
576
577 static int i915_dispatch_flip(struct drm_device * dev)
578 {
579         drm_i915_private_t *dev_priv = dev->dev_private;
580         struct drm_i915_master_private *master_priv =
581                 dev->primary->master->driver_priv;
582         RING_LOCALS;
583
584         if (!master_priv->sarea_priv)
585                 return -EINVAL;
586
587         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
588                           __func__,
589                          dev_priv->current_page,
590                          master_priv->sarea_priv->pf_current_page);
591
592         i915_kernel_lost_context(dev);
593
594         BEGIN_LP_RING(2);
595         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
596         OUT_RING(0);
597         ADVANCE_LP_RING();
598
599         BEGIN_LP_RING(6);
600         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
601         OUT_RING(0);
602         if (dev_priv->current_page == 0) {
603                 OUT_RING(dev_priv->back_offset);
604                 dev_priv->current_page = 1;
605         } else {
606                 OUT_RING(dev_priv->front_offset);
607                 dev_priv->current_page = 0;
608         }
609         OUT_RING(0);
610         ADVANCE_LP_RING();
611
612         BEGIN_LP_RING(2);
613         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
614         OUT_RING(0);
615         ADVANCE_LP_RING();
616
617         master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
618
619         BEGIN_LP_RING(4);
620         OUT_RING(MI_STORE_DWORD_INDEX);
621         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
622         OUT_RING(dev_priv->counter);
623         OUT_RING(0);
624         ADVANCE_LP_RING();
625
626         master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
627         return 0;
628 }
629
630 static int i915_quiescent(struct drm_device * dev)
631 {
632         drm_i915_private_t *dev_priv = dev->dev_private;
633
634         i915_kernel_lost_context(dev);
635         return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
636 }
637
638 static int i915_flush_ioctl(struct drm_device *dev, void *data,
639                             struct drm_file *file_priv)
640 {
641         int ret;
642
643         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
644
645         mutex_lock(&dev->struct_mutex);
646         ret = i915_quiescent(dev);
647         mutex_unlock(&dev->struct_mutex);
648
649         return ret;
650 }
651
652 static int i915_batchbuffer(struct drm_device *dev, void *data,
653                             struct drm_file *file_priv)
654 {
655         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
656         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
657         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
658             master_priv->sarea_priv;
659         drm_i915_batchbuffer_t *batch = data;
660         int ret;
661         struct drm_clip_rect *cliprects = NULL;
662
663         if (!dev_priv->allow_batchbuffer) {
664                 DRM_ERROR("Batchbuffer ioctl disabled\n");
665                 return -EINVAL;
666         }
667
668         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
669                         batch->start, batch->used, batch->num_cliprects);
670
671         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
672
673         if (batch->num_cliprects < 0)
674                 return -EINVAL;
675
676         if (batch->num_cliprects) {
677                 cliprects = kcalloc(batch->num_cliprects,
678                                     sizeof(struct drm_clip_rect),
679                                     GFP_KERNEL);
680                 if (cliprects == NULL)
681                         return -ENOMEM;
682
683                 ret = copy_from_user(cliprects, batch->cliprects,
684                                      batch->num_cliprects *
685                                      sizeof(struct drm_clip_rect));
686                 if (ret != 0)
687                         goto fail_free;
688         }
689
690         mutex_lock(&dev->struct_mutex);
691         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
692         mutex_unlock(&dev->struct_mutex);
693
694         if (sarea_priv)
695                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
696
697 fail_free:
698         kfree(cliprects);
699
700         return ret;
701 }
702
703 static int i915_cmdbuffer(struct drm_device *dev, void *data,
704                           struct drm_file *file_priv)
705 {
706         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
707         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
708         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
709             master_priv->sarea_priv;
710         drm_i915_cmdbuffer_t *cmdbuf = data;
711         struct drm_clip_rect *cliprects = NULL;
712         void *batch_data;
713         int ret;
714
715         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
716                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
717
718         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
719
720         if (cmdbuf->num_cliprects < 0)
721                 return -EINVAL;
722
723         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
724         if (batch_data == NULL)
725                 return -ENOMEM;
726
727         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
728         if (ret != 0)
729                 goto fail_batch_free;
730
731         if (cmdbuf->num_cliprects) {
732                 cliprects = kcalloc(cmdbuf->num_cliprects,
733                                     sizeof(struct drm_clip_rect), GFP_KERNEL);
734                 if (cliprects == NULL)
735                         goto fail_batch_free;
736
737                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
738                                      cmdbuf->num_cliprects *
739                                      sizeof(struct drm_clip_rect));
740                 if (ret != 0)
741                         goto fail_clip_free;
742         }
743
744         mutex_lock(&dev->struct_mutex);
745         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
746         mutex_unlock(&dev->struct_mutex);
747         if (ret) {
748                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
749                 goto fail_clip_free;
750         }
751
752         if (sarea_priv)
753                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
754
755 fail_clip_free:
756         kfree(cliprects);
757 fail_batch_free:
758         kfree(batch_data);
759
760         return ret;
761 }
762
763 static int i915_flip_bufs(struct drm_device *dev, void *data,
764                           struct drm_file *file_priv)
765 {
766         int ret;
767
768         DRM_DEBUG_DRIVER("%s\n", __func__);
769
770         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
771
772         mutex_lock(&dev->struct_mutex);
773         ret = i915_dispatch_flip(dev);
774         mutex_unlock(&dev->struct_mutex);
775
776         return ret;
777 }
778
779 static int i915_getparam(struct drm_device *dev, void *data,
780                          struct drm_file *file_priv)
781 {
782         drm_i915_private_t *dev_priv = dev->dev_private;
783         drm_i915_getparam_t *param = data;
784         int value;
785
786         if (!dev_priv) {
787                 DRM_ERROR("called with no initialization\n");
788                 return -EINVAL;
789         }
790
791         switch (param->param) {
792         case I915_PARAM_IRQ_ACTIVE:
793                 value = dev->pdev->irq ? 1 : 0;
794                 break;
795         case I915_PARAM_ALLOW_BATCHBUFFER:
796                 value = dev_priv->allow_batchbuffer ? 1 : 0;
797                 break;
798         case I915_PARAM_LAST_DISPATCH:
799                 value = READ_BREADCRUMB(dev_priv);
800                 break;
801         case I915_PARAM_CHIPSET_ID:
802                 value = dev->pci_device;
803                 break;
804         case I915_PARAM_HAS_GEM:
805                 value = dev_priv->has_gem;
806                 break;
807         case I915_PARAM_NUM_FENCES_AVAIL:
808                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
809                 break;
810         case I915_PARAM_HAS_OVERLAY:
811                 value = dev_priv->overlay ? 1 : 0;
812                 break;
813         case I915_PARAM_HAS_PAGEFLIPPING:
814                 value = 1;
815                 break;
816         default:
817                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
818                                         param->param);
819                 return -EINVAL;
820         }
821
822         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
823                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
824                 return -EFAULT;
825         }
826
827         return 0;
828 }
829
830 static int i915_setparam(struct drm_device *dev, void *data,
831                          struct drm_file *file_priv)
832 {
833         drm_i915_private_t *dev_priv = dev->dev_private;
834         drm_i915_setparam_t *param = data;
835
836         if (!dev_priv) {
837                 DRM_ERROR("called with no initialization\n");
838                 return -EINVAL;
839         }
840
841         switch (param->param) {
842         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
843                 break;
844         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
845                 dev_priv->tex_lru_log_granularity = param->value;
846                 break;
847         case I915_SETPARAM_ALLOW_BATCHBUFFER:
848                 dev_priv->allow_batchbuffer = param->value;
849                 break;
850         case I915_SETPARAM_NUM_USED_FENCES:
851                 if (param->value > dev_priv->num_fence_regs ||
852                     param->value < 0)
853                         return -EINVAL;
854                 /* Userspace can use first N regs */
855                 dev_priv->fence_reg_start = param->value;
856                 break;
857         default:
858                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
859                                         param->param);
860                 return -EINVAL;
861         }
862
863         return 0;
864 }
865
866 static int i915_set_status_page(struct drm_device *dev, void *data,
867                                 struct drm_file *file_priv)
868 {
869         drm_i915_private_t *dev_priv = dev->dev_private;
870         drm_i915_hws_addr_t *hws = data;
871
872         if (!I915_NEED_GFX_HWS(dev))
873                 return -EINVAL;
874
875         if (!dev_priv) {
876                 DRM_ERROR("called with no initialization\n");
877                 return -EINVAL;
878         }
879
880         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
881                 WARN(1, "tried to set status page when mode setting active\n");
882                 return 0;
883         }
884
885         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
886
887         dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
888
889         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
890         dev_priv->hws_map.size = 4*1024;
891         dev_priv->hws_map.type = 0;
892         dev_priv->hws_map.flags = 0;
893         dev_priv->hws_map.mtrr = 0;
894
895         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
896         if (dev_priv->hws_map.handle == NULL) {
897                 i915_dma_cleanup(dev);
898                 dev_priv->status_gfx_addr = 0;
899                 DRM_ERROR("can not ioremap virtual address for"
900                                 " G33 hw status page\n");
901                 return -ENOMEM;
902         }
903         dev_priv->hw_status_page = dev_priv->hws_map.handle;
904
905         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
906         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
907         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
908                                 dev_priv->status_gfx_addr);
909         DRM_DEBUG_DRIVER("load hws at %p\n",
910                                 dev_priv->hw_status_page);
911         return 0;
912 }
913
914 static int i915_get_bridge_dev(struct drm_device *dev)
915 {
916         struct drm_i915_private *dev_priv = dev->dev_private;
917
918         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
919         if (!dev_priv->bridge_dev) {
920                 DRM_ERROR("bridge device not found\n");
921                 return -1;
922         }
923         return 0;
924 }
925
926 /**
927  * i915_probe_agp - get AGP bootup configuration
928  * @pdev: PCI device
929  * @aperture_size: returns AGP aperture configured size
930  * @preallocated_size: returns size of BIOS preallocated AGP space
931  *
932  * Since Intel integrated graphics are UMA, the BIOS has to set aside
933  * some RAM for the framebuffer at early boot.  This code figures out
934  * how much was set aside so we can use it for our own purposes.
935  */
936 static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
937                           uint32_t *preallocated_size,
938                           uint32_t *start)
939 {
940         struct drm_i915_private *dev_priv = dev->dev_private;
941         u16 tmp = 0;
942         unsigned long overhead;
943         unsigned long stolen;
944
945         /* Get the fb aperture size and "stolen" memory amount. */
946         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
947
948         *aperture_size = 1024 * 1024;
949         *preallocated_size = 1024 * 1024;
950
951         switch (dev->pdev->device) {
952         case PCI_DEVICE_ID_INTEL_82830_CGC:
953         case PCI_DEVICE_ID_INTEL_82845G_IG:
954         case PCI_DEVICE_ID_INTEL_82855GM_IG:
955         case PCI_DEVICE_ID_INTEL_82865_IG:
956                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
957                         *aperture_size *= 64;
958                 else
959                         *aperture_size *= 128;
960                 break;
961         default:
962                 /* 9xx supports large sizes, just look at the length */
963                 *aperture_size = pci_resource_len(dev->pdev, 2);
964                 break;
965         }
966
967         /*
968          * Some of the preallocated space is taken by the GTT
969          * and popup.  GTT is 1K per MB of aperture size, and popup is 4K.
970          */
971         if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev))
972                 overhead = 4096;
973         else
974                 overhead = (*aperture_size / 1024) + 4096;
975
976         switch (tmp & INTEL_GMCH_GMS_MASK) {
977         case INTEL_855_GMCH_GMS_DISABLED:
978                 DRM_ERROR("video memory is disabled\n");
979                 return -1;
980         case INTEL_855_GMCH_GMS_STOLEN_1M:
981                 stolen = 1 * 1024 * 1024;
982                 break;
983         case INTEL_855_GMCH_GMS_STOLEN_4M:
984                 stolen = 4 * 1024 * 1024;
985                 break;
986         case INTEL_855_GMCH_GMS_STOLEN_8M:
987                 stolen = 8 * 1024 * 1024;
988                 break;
989         case INTEL_855_GMCH_GMS_STOLEN_16M:
990                 stolen = 16 * 1024 * 1024;
991                 break;
992         case INTEL_855_GMCH_GMS_STOLEN_32M:
993                 stolen = 32 * 1024 * 1024;
994                 break;
995         case INTEL_915G_GMCH_GMS_STOLEN_48M:
996                 stolen = 48 * 1024 * 1024;
997                 break;
998         case INTEL_915G_GMCH_GMS_STOLEN_64M:
999                 stolen = 64 * 1024 * 1024;
1000                 break;
1001         case INTEL_GMCH_GMS_STOLEN_128M:
1002                 stolen = 128 * 1024 * 1024;
1003                 break;
1004         case INTEL_GMCH_GMS_STOLEN_256M:
1005                 stolen = 256 * 1024 * 1024;
1006                 break;
1007         case INTEL_GMCH_GMS_STOLEN_96M:
1008                 stolen = 96 * 1024 * 1024;
1009                 break;
1010         case INTEL_GMCH_GMS_STOLEN_160M:
1011                 stolen = 160 * 1024 * 1024;
1012                 break;
1013         case INTEL_GMCH_GMS_STOLEN_224M:
1014                 stolen = 224 * 1024 * 1024;
1015                 break;
1016         case INTEL_GMCH_GMS_STOLEN_352M:
1017                 stolen = 352 * 1024 * 1024;
1018                 break;
1019         default:
1020                 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1021                         tmp & INTEL_GMCH_GMS_MASK);
1022                 return -1;
1023         }
1024         *preallocated_size = stolen - overhead;
1025         *start = overhead;
1026
1027         return 0;
1028 }
1029
1030 #define PTE_ADDRESS_MASK                0xfffff000
1031 #define PTE_ADDRESS_MASK_HIGH           0x000000f0 /* i915+ */
1032 #define PTE_MAPPING_TYPE_UNCACHED       (0 << 1)
1033 #define PTE_MAPPING_TYPE_DCACHE         (1 << 1) /* i830 only */
1034 #define PTE_MAPPING_TYPE_CACHED         (3 << 1)
1035 #define PTE_MAPPING_TYPE_MASK           (3 << 1)
1036 #define PTE_VALID                       (1 << 0)
1037
1038 /**
1039  * i915_gtt_to_phys - take a GTT address and turn it into a physical one
1040  * @dev: drm device
1041  * @gtt_addr: address to translate
1042  *
1043  * Some chip functions require allocations from stolen space but need the
1044  * physical address of the memory in question.  We use this routine
1045  * to get a physical address suitable for register programming from a given
1046  * GTT address.
1047  */
1048 static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1049                                       unsigned long gtt_addr)
1050 {
1051         unsigned long *gtt;
1052         unsigned long entry, phys;
1053         int gtt_bar = IS_I9XX(dev) ? 0 : 1;
1054         int gtt_offset, gtt_size;
1055
1056         if (IS_I965G(dev)) {
1057                 if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
1058                         gtt_offset = 2*1024*1024;
1059                         gtt_size = 2*1024*1024;
1060                 } else {
1061                         gtt_offset = 512*1024;
1062                         gtt_size = 512*1024;
1063                 }
1064         } else {
1065                 gtt_bar = 3;
1066                 gtt_offset = 0;
1067                 gtt_size = pci_resource_len(dev->pdev, gtt_bar);
1068         }
1069
1070         gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
1071                          gtt_size);
1072         if (!gtt) {
1073                 DRM_ERROR("ioremap of GTT failed\n");
1074                 return 0;
1075         }
1076
1077         entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
1078
1079         DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
1080
1081         /* Mask out these reserved bits on this hardware. */
1082         if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
1083             IS_I945G(dev) || IS_I945GM(dev)) {
1084                 entry &= ~PTE_ADDRESS_MASK_HIGH;
1085         }
1086
1087         /* If it's not a mapping type we know, then bail. */
1088         if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
1089             (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
1090                 iounmap(gtt);
1091                 return 0;
1092         }
1093
1094         if (!(entry & PTE_VALID)) {
1095                 DRM_ERROR("bad GTT entry in stolen space\n");
1096                 iounmap(gtt);
1097                 return 0;
1098         }
1099
1100         iounmap(gtt);
1101
1102         phys =(entry & PTE_ADDRESS_MASK) |
1103                 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
1104
1105         DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
1106
1107         return phys;
1108 }
1109
1110 static void i915_warn_stolen(struct drm_device *dev)
1111 {
1112         DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1113         DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1114 }
1115
1116 static void i915_setup_compression(struct drm_device *dev, int size)
1117 {
1118         struct drm_i915_private *dev_priv = dev->dev_private;
1119         struct drm_mm_node *compressed_fb, *compressed_llb;
1120         unsigned long cfb_base, ll_base;
1121
1122         /* Leave 1M for line length buffer & misc. */
1123         compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
1124         if (!compressed_fb) {
1125                 i915_warn_stolen(dev);
1126                 return;
1127         }
1128
1129         compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1130         if (!compressed_fb) {
1131                 i915_warn_stolen(dev);
1132                 return;
1133         }
1134
1135         cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
1136         if (!cfb_base) {
1137                 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1138                 drm_mm_put_block(compressed_fb);
1139         }
1140
1141         if (!IS_GM45(dev)) {
1142                 compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096,
1143                                                     4096, 0);
1144                 if (!compressed_llb) {
1145                         i915_warn_stolen(dev);
1146                         return;
1147                 }
1148
1149                 compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
1150                 if (!compressed_llb) {
1151                         i915_warn_stolen(dev);
1152                         return;
1153                 }
1154
1155                 ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
1156                 if (!ll_base) {
1157                         DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1158                         drm_mm_put_block(compressed_fb);
1159                         drm_mm_put_block(compressed_llb);
1160                 }
1161         }
1162
1163         dev_priv->cfb_size = size;
1164
1165         if (IS_GM45(dev)) {
1166                 g4x_disable_fbc(dev);
1167                 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1168         } else {
1169                 i8xx_disable_fbc(dev);
1170                 I915_WRITE(FBC_CFB_BASE, cfb_base);
1171                 I915_WRITE(FBC_LL_BASE, ll_base);
1172         }
1173
1174         DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
1175                   ll_base, size >> 20);
1176 }
1177
1178 /* true = enable decode, false = disable decoder */
1179 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1180 {
1181         struct drm_device *dev = cookie;
1182
1183         intel_modeset_vga_set_state(dev, state);
1184         if (state)
1185                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1186                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1187         else
1188                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1189 }
1190
1191 static int i915_load_modeset_init(struct drm_device *dev,
1192                                   unsigned long prealloc_start,
1193                                   unsigned long prealloc_size,
1194                                   unsigned long agp_size)
1195 {
1196         struct drm_i915_private *dev_priv = dev->dev_private;
1197         int fb_bar = IS_I9XX(dev) ? 2 : 0;
1198         int ret = 0;
1199
1200         dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) &
1201                 0xff000000;
1202
1203         /* Basic memrange allocator for stolen space (aka vram) */
1204         drm_mm_init(&dev_priv->vram, 0, prealloc_size);
1205         DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
1206
1207         /* We're off and running w/KMS */
1208         dev_priv->mm.suspended = 0;
1209
1210         /* Let GEM Manage from end of prealloc space to end of aperture.
1211          *
1212          * However, leave one page at the end still bound to the scratch page.
1213          * There are a number of places where the hardware apparently
1214          * prefetches past the end of the object, and we've seen multiple
1215          * hangs with the GPU head pointer stuck in a batchbuffer bound
1216          * at the last page of the aperture.  One page should be enough to
1217          * keep any prefetching inside of the aperture.
1218          */
1219         i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
1220
1221         mutex_lock(&dev->struct_mutex);
1222         ret = i915_gem_init_ringbuffer(dev);
1223         mutex_unlock(&dev->struct_mutex);
1224         if (ret)
1225                 goto out;
1226
1227         /* Try to set up FBC with a reasonable compressed buffer size */
1228         if (I915_HAS_FBC(dev) && i915_powersave) {
1229                 int cfb_size;
1230
1231                 /* Try to get an 8M buffer... */
1232                 if (prealloc_size > (9*1024*1024))
1233                         cfb_size = 8*1024*1024;
1234                 else /* fall back to 7/8 of the stolen space */
1235                         cfb_size = prealloc_size * 7 / 8;
1236                 i915_setup_compression(dev, cfb_size);
1237         }
1238
1239         /* Allow hardware batchbuffers unless told otherwise.
1240          */
1241         dev_priv->allow_batchbuffer = 1;
1242
1243         ret = intel_init_bios(dev);
1244         if (ret)
1245                 DRM_INFO("failed to find VBIOS tables\n");
1246
1247         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1248         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1249         if (ret)
1250                 goto destroy_ringbuffer;
1251
1252         intel_modeset_init(dev);
1253
1254         ret = drm_irq_install(dev);
1255         if (ret)
1256                 goto destroy_ringbuffer;
1257
1258         /* Always safe in the mode setting case. */
1259         /* FIXME: do pre/post-mode set stuff in core KMS code */
1260         dev->vblank_disable_allowed = 1;
1261
1262         /*
1263          * Initialize the hardware status page IRQ location.
1264          */
1265
1266         I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
1267
1268         drm_helper_initial_config(dev);
1269
1270         return 0;
1271
1272 destroy_ringbuffer:
1273         i915_gem_cleanup_ringbuffer(dev);
1274 out:
1275         return ret;
1276 }
1277
1278 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1279 {
1280         struct drm_i915_master_private *master_priv;
1281
1282         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1283         if (!master_priv)
1284                 return -ENOMEM;
1285
1286         master->driver_priv = master_priv;
1287         return 0;
1288 }
1289
1290 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1291 {
1292         struct drm_i915_master_private *master_priv = master->driver_priv;
1293
1294         if (!master_priv)
1295                 return;
1296
1297         kfree(master_priv);
1298
1299         master->driver_priv = NULL;
1300 }
1301
1302 static void i915_get_mem_freq(struct drm_device *dev)
1303 {
1304         drm_i915_private_t *dev_priv = dev->dev_private;
1305         u32 tmp;
1306
1307         if (!IS_PINEVIEW(dev))
1308                 return;
1309
1310         tmp = I915_READ(CLKCFG);
1311
1312         switch (tmp & CLKCFG_FSB_MASK) {
1313         case CLKCFG_FSB_533:
1314                 dev_priv->fsb_freq = 533; /* 133*4 */
1315                 break;
1316         case CLKCFG_FSB_800:
1317                 dev_priv->fsb_freq = 800; /* 200*4 */
1318                 break;
1319         case CLKCFG_FSB_667:
1320                 dev_priv->fsb_freq =  667; /* 167*4 */
1321                 break;
1322         case CLKCFG_FSB_400:
1323                 dev_priv->fsb_freq = 400; /* 100*4 */
1324                 break;
1325         }
1326
1327         switch (tmp & CLKCFG_MEM_MASK) {
1328         case CLKCFG_MEM_533:
1329                 dev_priv->mem_freq = 533;
1330                 break;
1331         case CLKCFG_MEM_667:
1332                 dev_priv->mem_freq = 667;
1333                 break;
1334         case CLKCFG_MEM_800:
1335                 dev_priv->mem_freq = 800;
1336                 break;
1337         }
1338 }
1339
1340 /**
1341  * i915_driver_load - setup chip and create an initial config
1342  * @dev: DRM device
1343  * @flags: startup flags
1344  *
1345  * The driver load routine has to do several things:
1346  *   - drive output discovery via intel_modeset_init()
1347  *   - initialize the memory manager
1348  *   - allocate initial config memory
1349  *   - setup the DRM framebuffer with the allocated memory
1350  */
1351 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1352 {
1353         struct drm_i915_private *dev_priv = dev->dev_private;
1354         resource_size_t base, size;
1355         int ret = 0, mmio_bar;
1356         uint32_t agp_size, prealloc_size, prealloc_start;
1357
1358         /* i915 has 4 more counters */
1359         dev->counters += 4;
1360         dev->types[6] = _DRM_STAT_IRQ;
1361         dev->types[7] = _DRM_STAT_PRIMARY;
1362         dev->types[8] = _DRM_STAT_SECONDARY;
1363         dev->types[9] = _DRM_STAT_DMA;
1364
1365         dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1366         if (dev_priv == NULL)
1367                 return -ENOMEM;
1368
1369         dev->dev_private = (void *)dev_priv;
1370         dev_priv->dev = dev;
1371         dev_priv->info = (struct intel_device_info *) flags;
1372
1373         /* Add register map (needed for suspend/resume) */
1374         mmio_bar = IS_I9XX(dev) ? 0 : 1;
1375         base = drm_get_resource_start(dev, mmio_bar);
1376         size = drm_get_resource_len(dev, mmio_bar);
1377
1378         if (i915_get_bridge_dev(dev)) {
1379                 ret = -EIO;
1380                 goto free_priv;
1381         }
1382
1383         dev_priv->regs = ioremap(base, size);
1384         if (!dev_priv->regs) {
1385                 DRM_ERROR("failed to map registers\n");
1386                 ret = -EIO;
1387                 goto put_bridge;
1388         }
1389
1390         dev_priv->mm.gtt_mapping =
1391                 io_mapping_create_wc(dev->agp->base,
1392                                      dev->agp->agp_info.aper_size * 1024*1024);
1393         if (dev_priv->mm.gtt_mapping == NULL) {
1394                 ret = -EIO;
1395                 goto out_rmmap;
1396         }
1397
1398         /* Set up a WC MTRR for non-PAT systems.  This is more common than
1399          * one would think, because the kernel disables PAT on first
1400          * generation Core chips because WC PAT gets overridden by a UC
1401          * MTRR if present.  Even if a UC MTRR isn't present.
1402          */
1403         dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
1404                                          dev->agp->agp_info.aper_size *
1405                                          1024 * 1024,
1406                                          MTRR_TYPE_WRCOMB, 1);
1407         if (dev_priv->mm.gtt_mtrr < 0) {
1408                 DRM_INFO("MTRR allocation failed.  Graphics "
1409                          "performance may suffer.\n");
1410         }
1411
1412         ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start);
1413         if (ret)
1414                 goto out_iomapfree;
1415
1416         dev_priv->wq = create_singlethread_workqueue("i915");
1417         if (dev_priv->wq == NULL) {
1418                 DRM_ERROR("Failed to create our workqueue.\n");
1419                 ret = -ENOMEM;
1420                 goto out_iomapfree;
1421         }
1422
1423         /* enable GEM by default */
1424         dev_priv->has_gem = 1;
1425
1426         if (prealloc_size > agp_size * 3 / 4) {
1427                 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
1428                           "memory stolen.\n",
1429                           prealloc_size / 1024, agp_size / 1024);
1430                 DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
1431                           "updating the BIOS to fix).\n");
1432                 dev_priv->has_gem = 0;
1433         }
1434
1435         dev->driver->get_vblank_counter = i915_get_vblank_counter;
1436         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1437         if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
1438                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
1439                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
1440         }
1441
1442         i915_gem_load(dev);
1443
1444         /* Init HWS */
1445         if (!I915_NEED_GFX_HWS(dev)) {
1446                 ret = i915_init_phys_hws(dev);
1447                 if (ret != 0)
1448                         goto out_workqueue_free;
1449         }
1450
1451         i915_get_mem_freq(dev);
1452
1453         /* On the 945G/GM, the chipset reports the MSI capability on the
1454          * integrated graphics even though the support isn't actually there
1455          * according to the published specs.  It doesn't appear to function
1456          * correctly in testing on 945G.
1457          * This may be a side effect of MSI having been made available for PEG
1458          * and the registers being closely associated.
1459          *
1460          * According to chipset errata, on the 965GM, MSI interrupts may
1461          * be lost or delayed, but we use them anyways to avoid
1462          * stuck interrupts on some machines.
1463          */
1464         if (!IS_I945G(dev) && !IS_I945GM(dev))
1465                 pci_enable_msi(dev->pdev);
1466
1467         spin_lock_init(&dev_priv->user_irq_lock);
1468         spin_lock_init(&dev_priv->error_lock);
1469         dev_priv->user_irq_refcount = 0;
1470         dev_priv->trace_irq_seqno = 0;
1471
1472         ret = drm_vblank_init(dev, I915_NUM_PIPE);
1473
1474         if (ret) {
1475                 (void) i915_driver_unload(dev);
1476                 return ret;
1477         }
1478
1479         /* Start out suspended */
1480         dev_priv->mm.suspended = 1;
1481
1482         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1483                 ret = i915_load_modeset_init(dev, prealloc_start,
1484                                              prealloc_size, agp_size);
1485                 if (ret < 0) {
1486                         DRM_ERROR("failed to init modeset\n");
1487                         goto out_workqueue_free;
1488                 }
1489         }
1490
1491         /* Must be done after probing outputs */
1492         intel_opregion_init(dev, 0);
1493
1494         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1495                     (unsigned long) dev);
1496         return 0;
1497
1498 out_workqueue_free:
1499         destroy_workqueue(dev_priv->wq);
1500 out_iomapfree:
1501         io_mapping_free(dev_priv->mm.gtt_mapping);
1502 out_rmmap:
1503         iounmap(dev_priv->regs);
1504 put_bridge:
1505         pci_dev_put(dev_priv->bridge_dev);
1506 free_priv:
1507         kfree(dev_priv);
1508         return ret;
1509 }
1510
1511 int i915_driver_unload(struct drm_device *dev)
1512 {
1513         struct drm_i915_private *dev_priv = dev->dev_private;
1514
1515         destroy_workqueue(dev_priv->wq);
1516         del_timer_sync(&dev_priv->hangcheck_timer);
1517
1518         io_mapping_free(dev_priv->mm.gtt_mapping);
1519         if (dev_priv->mm.gtt_mtrr >= 0) {
1520                 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
1521                          dev->agp->agp_info.aper_size * 1024 * 1024);
1522                 dev_priv->mm.gtt_mtrr = -1;
1523         }
1524
1525         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1526                 /*
1527                  * free the memory space allocated for the child device
1528                  * config parsed from VBT
1529                  */
1530                 if (dev_priv->child_dev && dev_priv->child_dev_num) {
1531                         kfree(dev_priv->child_dev);
1532                         dev_priv->child_dev = NULL;
1533                         dev_priv->child_dev_num = 0;
1534                 }
1535                 drm_irq_uninstall(dev);
1536                 vga_client_register(dev->pdev, NULL, NULL, NULL);
1537         }
1538
1539         if (dev->pdev->msi_enabled)
1540                 pci_disable_msi(dev->pdev);
1541
1542         if (dev_priv->regs != NULL)
1543                 iounmap(dev_priv->regs);
1544
1545         intel_opregion_free(dev, 0);
1546
1547         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1548                 intel_modeset_cleanup(dev);
1549
1550                 i915_gem_free_all_phys_object(dev);
1551
1552                 mutex_lock(&dev->struct_mutex);
1553                 i915_gem_cleanup_ringbuffer(dev);
1554                 mutex_unlock(&dev->struct_mutex);
1555                 drm_mm_takedown(&dev_priv->vram);
1556                 i915_gem_lastclose(dev);
1557
1558                 intel_cleanup_overlay(dev);
1559         }
1560
1561         pci_dev_put(dev_priv->bridge_dev);
1562         kfree(dev->dev_private);
1563
1564         return 0;
1565 }
1566
1567 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1568 {
1569         struct drm_i915_file_private *i915_file_priv;
1570
1571         DRM_DEBUG_DRIVER("\n");
1572         i915_file_priv = (struct drm_i915_file_private *)
1573             kmalloc(sizeof(*i915_file_priv), GFP_KERNEL);
1574
1575         if (!i915_file_priv)
1576                 return -ENOMEM;
1577
1578         file_priv->driver_priv = i915_file_priv;
1579
1580         INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
1581
1582         return 0;
1583 }
1584
1585 /**
1586  * i915_driver_lastclose - clean up after all DRM clients have exited
1587  * @dev: DRM device
1588  *
1589  * Take care of cleaning up after all DRM clients have exited.  In the
1590  * mode setting case, we want to restore the kernel's initial mode (just
1591  * in case the last client left us in a bad state).
1592  *
1593  * Additionally, in the non-mode setting case, we'll tear down the AGP
1594  * and DMA structures, since the kernel won't be using them, and clea
1595  * up any GEM state.
1596  */
1597 void i915_driver_lastclose(struct drm_device * dev)
1598 {
1599         drm_i915_private_t *dev_priv = dev->dev_private;
1600
1601         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1602                 drm_fb_helper_restore();
1603                 return;
1604         }
1605
1606         i915_gem_lastclose(dev);
1607
1608         if (dev_priv->agp_heap)
1609                 i915_mem_takedown(&(dev_priv->agp_heap));
1610
1611         i915_dma_cleanup(dev);
1612 }
1613
1614 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1615 {
1616         drm_i915_private_t *dev_priv = dev->dev_private;
1617         i915_gem_release(dev, file_priv);
1618         if (!drm_core_check_feature(dev, DRIVER_MODESET))
1619                 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
1620 }
1621
1622 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1623 {
1624         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1625
1626         kfree(i915_file_priv);
1627 }
1628
1629 struct drm_ioctl_desc i915_ioctls[] = {
1630         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1631         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1632         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1633         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1634         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1635         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1636         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1637         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1638         DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
1639         DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
1640         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1641         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1642         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1643         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1644         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
1645         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1646         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1647         DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1648         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
1649         DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1650         DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1651         DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
1652         DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
1653         DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1654         DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1655         DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
1656         DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0),
1657         DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0),
1658         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
1659         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, 0),
1660         DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0),
1661         DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),
1662         DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
1663         DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
1664         DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0),
1665         DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
1666         DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, 0),
1667         DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW),
1668         DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW),
1669 };
1670
1671 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1672
1673 /**
1674  * Determine if the device really is AGP or not.
1675  *
1676  * All Intel graphics chipsets are treated as AGP, even if they are really
1677  * PCI-e.
1678  *
1679  * \param dev   The device to be tested.
1680  *
1681  * \returns
1682  * A value of 1 is always retured to indictate every i9x5 is AGP.
1683  */
1684 int i915_driver_device_is_agp(struct drm_device * dev)
1685 {
1686         return 1;
1687 }