drm: Add support for platform devices to register as DRM devices
[linux-2.6.git] / drivers / gpu / drm / i915 / i915_dma.c
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2  */
3 /*
4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5  * All Rights Reserved.
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a
8  * copy of this software and associated documentation files (the
9  * "Software"), to deal in the Software without restriction, including
10  * without limitation the rights to use, copy, modify, merge, publish,
11  * distribute, sub license, and/or sell copies of the Software, and to
12  * permit persons to whom the Software is furnished to do so, subject to
13  * the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the
16  * next paragraph) shall be included in all copies or substantial portions
17  * of the Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26  *
27  */
28
29 #include "drmP.h"
30 #include "drm.h"
31 #include "drm_crtc_helper.h"
32 #include "drm_fb_helper.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "i915_trace.h"
37 #include <linux/pci.h>
38 #include <linux/vgaarb.h>
39 #include <linux/acpi.h>
40 #include <linux/pnp.h>
41 #include <linux/vga_switcheroo.h>
42 #include <linux/slab.h>
43
44 /* Really want an OS-independent resettable timer.  Would like to have
45  * this loop run for (eg) 3 sec, but have the timer reset every time
46  * the head pointer changes, so that EBUSY only happens if the ring
47  * actually stalls for (eg) 3 seconds.
48  */
49 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
50 {
51         drm_i915_private_t *dev_priv = dev->dev_private;
52         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
53         u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
54         u32 last_acthd = I915_READ(acthd_reg);
55         u32 acthd;
56         u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
57         int i;
58
59         trace_i915_ring_wait_begin (dev);
60
61         for (i = 0; i < 100000; i++) {
62                 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
63                 acthd = I915_READ(acthd_reg);
64                 ring->space = ring->head - (ring->tail + 8);
65                 if (ring->space < 0)
66                         ring->space += ring->Size;
67                 if (ring->space >= n) {
68                         trace_i915_ring_wait_end (dev);
69                         return 0;
70                 }
71
72                 if (dev->primary->master) {
73                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
74                         if (master_priv->sarea_priv)
75                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
76                 }
77
78
79                 if (ring->head != last_head)
80                         i = 0;
81                 if (acthd != last_acthd)
82                         i = 0;
83
84                 last_head = ring->head;
85                 last_acthd = acthd;
86                 msleep_interruptible(10);
87
88         }
89
90         trace_i915_ring_wait_end (dev);
91         return -EBUSY;
92 }
93
94 /* As a ringbuffer is only allowed to wrap between instructions, fill
95  * the tail with NOOPs.
96  */
97 int i915_wrap_ring(struct drm_device *dev)
98 {
99         drm_i915_private_t *dev_priv = dev->dev_private;
100         volatile unsigned int *virt;
101         int rem;
102
103         rem = dev_priv->ring.Size - dev_priv->ring.tail;
104         if (dev_priv->ring.space < rem) {
105                 int ret = i915_wait_ring(dev, rem, __func__);
106                 if (ret)
107                         return ret;
108         }
109         dev_priv->ring.space -= rem;
110
111         virt = (unsigned int *)
112                 (dev_priv->ring.virtual_start + dev_priv->ring.tail);
113         rem /= 4;
114         while (rem--)
115                 *virt++ = MI_NOOP;
116
117         dev_priv->ring.tail = 0;
118
119         return 0;
120 }
121
122 /**
123  * Sets up the hardware status page for devices that need a physical address
124  * in the register.
125  */
126 static int i915_init_phys_hws(struct drm_device *dev)
127 {
128         drm_i915_private_t *dev_priv = dev->dev_private;
129         /* Program Hardware Status Page */
130         dev_priv->status_page_dmah =
131                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
132
133         if (!dev_priv->status_page_dmah) {
134                 DRM_ERROR("Can not allocate hardware status page\n");
135                 return -ENOMEM;
136         }
137         dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
138         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
139
140         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
141
142         if (IS_I965G(dev))
143                 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
144                                              0xf0;
145
146         I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
147         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
148         return 0;
149 }
150
151 /**
152  * Frees the hardware status page, whether it's a physical address or a virtual
153  * address set up by the X Server.
154  */
155 static void i915_free_hws(struct drm_device *dev)
156 {
157         drm_i915_private_t *dev_priv = dev->dev_private;
158         if (dev_priv->status_page_dmah) {
159                 drm_pci_free(dev, dev_priv->status_page_dmah);
160                 dev_priv->status_page_dmah = NULL;
161         }
162
163         if (dev_priv->status_gfx_addr) {
164                 dev_priv->status_gfx_addr = 0;
165                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
166         }
167
168         /* Need to rewrite hardware status page */
169         I915_WRITE(HWS_PGA, 0x1ffff000);
170 }
171
172 void i915_kernel_lost_context(struct drm_device * dev)
173 {
174         drm_i915_private_t *dev_priv = dev->dev_private;
175         struct drm_i915_master_private *master_priv;
176         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
177
178         /*
179          * We should never lose context on the ring with modesetting
180          * as we don't expose it to userspace
181          */
182         if (drm_core_check_feature(dev, DRIVER_MODESET))
183                 return;
184
185         ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
186         ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
187         ring->space = ring->head - (ring->tail + 8);
188         if (ring->space < 0)
189                 ring->space += ring->Size;
190
191         if (!dev->primary->master)
192                 return;
193
194         master_priv = dev->primary->master->driver_priv;
195         if (ring->head == ring->tail && master_priv->sarea_priv)
196                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
197 }
198
199 static int i915_dma_cleanup(struct drm_device * dev)
200 {
201         drm_i915_private_t *dev_priv = dev->dev_private;
202         /* Make sure interrupts are disabled here because the uninstall ioctl
203          * may not have been called from userspace and after dev_private
204          * is freed, it's too late.
205          */
206         if (dev->irq_enabled)
207                 drm_irq_uninstall(dev);
208
209         if (dev_priv->ring.virtual_start) {
210                 drm_core_ioremapfree(&dev_priv->ring.map, dev);
211                 dev_priv->ring.virtual_start = NULL;
212                 dev_priv->ring.map.handle = NULL;
213                 dev_priv->ring.map.size = 0;
214         }
215
216         /* Clear the HWS virtual address at teardown */
217         if (I915_NEED_GFX_HWS(dev))
218                 i915_free_hws(dev);
219
220         return 0;
221 }
222
223 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
224 {
225         drm_i915_private_t *dev_priv = dev->dev_private;
226         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
227
228         master_priv->sarea = drm_getsarea(dev);
229         if (master_priv->sarea) {
230                 master_priv->sarea_priv = (drm_i915_sarea_t *)
231                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
232         } else {
233                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
234         }
235
236         if (init->ring_size != 0) {
237                 if (dev_priv->ring.ring_obj != NULL) {
238                         i915_dma_cleanup(dev);
239                         DRM_ERROR("Client tried to initialize ringbuffer in "
240                                   "GEM mode\n");
241                         return -EINVAL;
242                 }
243
244                 dev_priv->ring.Size = init->ring_size;
245
246                 dev_priv->ring.map.offset = init->ring_start;
247                 dev_priv->ring.map.size = init->ring_size;
248                 dev_priv->ring.map.type = 0;
249                 dev_priv->ring.map.flags = 0;
250                 dev_priv->ring.map.mtrr = 0;
251
252                 drm_core_ioremap_wc(&dev_priv->ring.map, dev);
253
254                 if (dev_priv->ring.map.handle == NULL) {
255                         i915_dma_cleanup(dev);
256                         DRM_ERROR("can not ioremap virtual address for"
257                                   " ring buffer\n");
258                         return -ENOMEM;
259                 }
260         }
261
262         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
263
264         dev_priv->cpp = init->cpp;
265         dev_priv->back_offset = init->back_offset;
266         dev_priv->front_offset = init->front_offset;
267         dev_priv->current_page = 0;
268         if (master_priv->sarea_priv)
269                 master_priv->sarea_priv->pf_current_page = 0;
270
271         /* Allow hardware batchbuffers unless told otherwise.
272          */
273         dev_priv->allow_batchbuffer = 1;
274
275         return 0;
276 }
277
278 static int i915_dma_resume(struct drm_device * dev)
279 {
280         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
281
282         DRM_DEBUG_DRIVER("%s\n", __func__);
283
284         if (dev_priv->ring.map.handle == NULL) {
285                 DRM_ERROR("can not ioremap virtual address for"
286                           " ring buffer\n");
287                 return -ENOMEM;
288         }
289
290         /* Program Hardware Status Page */
291         if (!dev_priv->hw_status_page) {
292                 DRM_ERROR("Can not find hardware status page\n");
293                 return -EINVAL;
294         }
295         DRM_DEBUG_DRIVER("hw status page @ %p\n",
296                                 dev_priv->hw_status_page);
297
298         if (dev_priv->status_gfx_addr != 0)
299                 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
300         else
301                 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
302         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
303
304         return 0;
305 }
306
307 static int i915_dma_init(struct drm_device *dev, void *data,
308                          struct drm_file *file_priv)
309 {
310         drm_i915_init_t *init = data;
311         int retcode = 0;
312
313         switch (init->func) {
314         case I915_INIT_DMA:
315                 retcode = i915_initialize(dev, init);
316                 break;
317         case I915_CLEANUP_DMA:
318                 retcode = i915_dma_cleanup(dev);
319                 break;
320         case I915_RESUME_DMA:
321                 retcode = i915_dma_resume(dev);
322                 break;
323         default:
324                 retcode = -EINVAL;
325                 break;
326         }
327
328         return retcode;
329 }
330
331 /* Implement basically the same security restrictions as hardware does
332  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
333  *
334  * Most of the calculations below involve calculating the size of a
335  * particular instruction.  It's important to get the size right as
336  * that tells us where the next instruction to check is.  Any illegal
337  * instruction detected will be given a size of zero, which is a
338  * signal to abort the rest of the buffer.
339  */
340 static int do_validate_cmd(int cmd)
341 {
342         switch (((cmd >> 29) & 0x7)) {
343         case 0x0:
344                 switch ((cmd >> 23) & 0x3f) {
345                 case 0x0:
346                         return 1;       /* MI_NOOP */
347                 case 0x4:
348                         return 1;       /* MI_FLUSH */
349                 default:
350                         return 0;       /* disallow everything else */
351                 }
352                 break;
353         case 0x1:
354                 return 0;       /* reserved */
355         case 0x2:
356                 return (cmd & 0xff) + 2;        /* 2d commands */
357         case 0x3:
358                 if (((cmd >> 24) & 0x1f) <= 0x18)
359                         return 1;
360
361                 switch ((cmd >> 24) & 0x1f) {
362                 case 0x1c:
363                         return 1;
364                 case 0x1d:
365                         switch ((cmd >> 16) & 0xff) {
366                         case 0x3:
367                                 return (cmd & 0x1f) + 2;
368                         case 0x4:
369                                 return (cmd & 0xf) + 2;
370                         default:
371                                 return (cmd & 0xffff) + 2;
372                         }
373                 case 0x1e:
374                         if (cmd & (1 << 23))
375                                 return (cmd & 0xffff) + 1;
376                         else
377                                 return 1;
378                 case 0x1f:
379                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
380                                 return (cmd & 0x1ffff) + 2;
381                         else if (cmd & (1 << 17))       /* indirect random */
382                                 if ((cmd & 0xffff) == 0)
383                                         return 0;       /* unknown length, too hard */
384                                 else
385                                         return (((cmd & 0xffff) + 1) / 2) + 1;
386                         else
387                                 return 2;       /* indirect sequential */
388                 default:
389                         return 0;
390                 }
391         default:
392                 return 0;
393         }
394
395         return 0;
396 }
397
398 static int validate_cmd(int cmd)
399 {
400         int ret = do_validate_cmd(cmd);
401
402 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
403
404         return ret;
405 }
406
407 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
408 {
409         drm_i915_private_t *dev_priv = dev->dev_private;
410         int i;
411         RING_LOCALS;
412
413         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
414                 return -EINVAL;
415
416         BEGIN_LP_RING((dwords+1)&~1);
417
418         for (i = 0; i < dwords;) {
419                 int cmd, sz;
420
421                 cmd = buffer[i];
422
423                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
424                         return -EINVAL;
425
426                 OUT_RING(cmd);
427
428                 while (++i, --sz) {
429                         OUT_RING(buffer[i]);
430                 }
431         }
432
433         if (dwords & 1)
434                 OUT_RING(0);
435
436         ADVANCE_LP_RING();
437
438         return 0;
439 }
440
441 int
442 i915_emit_box(struct drm_device *dev,
443               struct drm_clip_rect *boxes,
444               int i, int DR1, int DR4)
445 {
446         drm_i915_private_t *dev_priv = dev->dev_private;
447         struct drm_clip_rect box = boxes[i];
448         RING_LOCALS;
449
450         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
451                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
452                           box.x1, box.y1, box.x2, box.y2);
453                 return -EINVAL;
454         }
455
456         if (IS_I965G(dev)) {
457                 BEGIN_LP_RING(4);
458                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
459                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
460                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
461                 OUT_RING(DR4);
462                 ADVANCE_LP_RING();
463         } else {
464                 BEGIN_LP_RING(6);
465                 OUT_RING(GFX_OP_DRAWRECT_INFO);
466                 OUT_RING(DR1);
467                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
468                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
469                 OUT_RING(DR4);
470                 OUT_RING(0);
471                 ADVANCE_LP_RING();
472         }
473
474         return 0;
475 }
476
477 /* XXX: Emitting the counter should really be moved to part of the IRQ
478  * emit. For now, do it in both places:
479  */
480
481 static void i915_emit_breadcrumb(struct drm_device *dev)
482 {
483         drm_i915_private_t *dev_priv = dev->dev_private;
484         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
485         RING_LOCALS;
486
487         dev_priv->counter++;
488         if (dev_priv->counter > 0x7FFFFFFFUL)
489                 dev_priv->counter = 0;
490         if (master_priv->sarea_priv)
491                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
492
493         BEGIN_LP_RING(4);
494         OUT_RING(MI_STORE_DWORD_INDEX);
495         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
496         OUT_RING(dev_priv->counter);
497         OUT_RING(0);
498         ADVANCE_LP_RING();
499 }
500
501 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
502                                    drm_i915_cmdbuffer_t *cmd,
503                                    struct drm_clip_rect *cliprects,
504                                    void *cmdbuf)
505 {
506         int nbox = cmd->num_cliprects;
507         int i = 0, count, ret;
508
509         if (cmd->sz & 0x3) {
510                 DRM_ERROR("alignment");
511                 return -EINVAL;
512         }
513
514         i915_kernel_lost_context(dev);
515
516         count = nbox ? nbox : 1;
517
518         for (i = 0; i < count; i++) {
519                 if (i < nbox) {
520                         ret = i915_emit_box(dev, cliprects, i,
521                                             cmd->DR1, cmd->DR4);
522                         if (ret)
523                                 return ret;
524                 }
525
526                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
527                 if (ret)
528                         return ret;
529         }
530
531         i915_emit_breadcrumb(dev);
532         return 0;
533 }
534
535 static int i915_dispatch_batchbuffer(struct drm_device * dev,
536                                      drm_i915_batchbuffer_t * batch,
537                                      struct drm_clip_rect *cliprects)
538 {
539         drm_i915_private_t *dev_priv = dev->dev_private;
540         int nbox = batch->num_cliprects;
541         int i = 0, count;
542         RING_LOCALS;
543
544         if ((batch->start | batch->used) & 0x7) {
545                 DRM_ERROR("alignment");
546                 return -EINVAL;
547         }
548
549         i915_kernel_lost_context(dev);
550
551         count = nbox ? nbox : 1;
552
553         for (i = 0; i < count; i++) {
554                 if (i < nbox) {
555                         int ret = i915_emit_box(dev, cliprects, i,
556                                                 batch->DR1, batch->DR4);
557                         if (ret)
558                                 return ret;
559                 }
560
561                 if (!IS_I830(dev) && !IS_845G(dev)) {
562                         BEGIN_LP_RING(2);
563                         if (IS_I965G(dev)) {
564                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
565                                 OUT_RING(batch->start);
566                         } else {
567                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
568                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
569                         }
570                         ADVANCE_LP_RING();
571                 } else {
572                         BEGIN_LP_RING(4);
573                         OUT_RING(MI_BATCH_BUFFER);
574                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
575                         OUT_RING(batch->start + batch->used - 4);
576                         OUT_RING(0);
577                         ADVANCE_LP_RING();
578                 }
579         }
580
581         i915_emit_breadcrumb(dev);
582
583         return 0;
584 }
585
586 static int i915_dispatch_flip(struct drm_device * dev)
587 {
588         drm_i915_private_t *dev_priv = dev->dev_private;
589         struct drm_i915_master_private *master_priv =
590                 dev->primary->master->driver_priv;
591         RING_LOCALS;
592
593         if (!master_priv->sarea_priv)
594                 return -EINVAL;
595
596         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
597                           __func__,
598                          dev_priv->current_page,
599                          master_priv->sarea_priv->pf_current_page);
600
601         i915_kernel_lost_context(dev);
602
603         BEGIN_LP_RING(2);
604         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
605         OUT_RING(0);
606         ADVANCE_LP_RING();
607
608         BEGIN_LP_RING(6);
609         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
610         OUT_RING(0);
611         if (dev_priv->current_page == 0) {
612                 OUT_RING(dev_priv->back_offset);
613                 dev_priv->current_page = 1;
614         } else {
615                 OUT_RING(dev_priv->front_offset);
616                 dev_priv->current_page = 0;
617         }
618         OUT_RING(0);
619         ADVANCE_LP_RING();
620
621         BEGIN_LP_RING(2);
622         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
623         OUT_RING(0);
624         ADVANCE_LP_RING();
625
626         master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
627
628         BEGIN_LP_RING(4);
629         OUT_RING(MI_STORE_DWORD_INDEX);
630         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
631         OUT_RING(dev_priv->counter);
632         OUT_RING(0);
633         ADVANCE_LP_RING();
634
635         master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
636         return 0;
637 }
638
639 static int i915_quiescent(struct drm_device * dev)
640 {
641         drm_i915_private_t *dev_priv = dev->dev_private;
642
643         i915_kernel_lost_context(dev);
644         return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
645 }
646
647 static int i915_flush_ioctl(struct drm_device *dev, void *data,
648                             struct drm_file *file_priv)
649 {
650         int ret;
651
652         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
653
654         mutex_lock(&dev->struct_mutex);
655         ret = i915_quiescent(dev);
656         mutex_unlock(&dev->struct_mutex);
657
658         return ret;
659 }
660
661 static int i915_batchbuffer(struct drm_device *dev, void *data,
662                             struct drm_file *file_priv)
663 {
664         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
665         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
666         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
667             master_priv->sarea_priv;
668         drm_i915_batchbuffer_t *batch = data;
669         int ret;
670         struct drm_clip_rect *cliprects = NULL;
671
672         if (!dev_priv->allow_batchbuffer) {
673                 DRM_ERROR("Batchbuffer ioctl disabled\n");
674                 return -EINVAL;
675         }
676
677         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
678                         batch->start, batch->used, batch->num_cliprects);
679
680         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
681
682         if (batch->num_cliprects < 0)
683                 return -EINVAL;
684
685         if (batch->num_cliprects) {
686                 cliprects = kcalloc(batch->num_cliprects,
687                                     sizeof(struct drm_clip_rect),
688                                     GFP_KERNEL);
689                 if (cliprects == NULL)
690                         return -ENOMEM;
691
692                 ret = copy_from_user(cliprects, batch->cliprects,
693                                      batch->num_cliprects *
694                                      sizeof(struct drm_clip_rect));
695                 if (ret != 0)
696                         goto fail_free;
697         }
698
699         mutex_lock(&dev->struct_mutex);
700         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
701         mutex_unlock(&dev->struct_mutex);
702
703         if (sarea_priv)
704                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
705
706 fail_free:
707         kfree(cliprects);
708
709         return ret;
710 }
711
712 static int i915_cmdbuffer(struct drm_device *dev, void *data,
713                           struct drm_file *file_priv)
714 {
715         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
716         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
717         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
718             master_priv->sarea_priv;
719         drm_i915_cmdbuffer_t *cmdbuf = data;
720         struct drm_clip_rect *cliprects = NULL;
721         void *batch_data;
722         int ret;
723
724         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
725                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
726
727         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
728
729         if (cmdbuf->num_cliprects < 0)
730                 return -EINVAL;
731
732         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
733         if (batch_data == NULL)
734                 return -ENOMEM;
735
736         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
737         if (ret != 0)
738                 goto fail_batch_free;
739
740         if (cmdbuf->num_cliprects) {
741                 cliprects = kcalloc(cmdbuf->num_cliprects,
742                                     sizeof(struct drm_clip_rect), GFP_KERNEL);
743                 if (cliprects == NULL) {
744                         ret = -ENOMEM;
745                         goto fail_batch_free;
746                 }
747
748                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
749                                      cmdbuf->num_cliprects *
750                                      sizeof(struct drm_clip_rect));
751                 if (ret != 0)
752                         goto fail_clip_free;
753         }
754
755         mutex_lock(&dev->struct_mutex);
756         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
757         mutex_unlock(&dev->struct_mutex);
758         if (ret) {
759                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
760                 goto fail_clip_free;
761         }
762
763         if (sarea_priv)
764                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
765
766 fail_clip_free:
767         kfree(cliprects);
768 fail_batch_free:
769         kfree(batch_data);
770
771         return ret;
772 }
773
774 static int i915_flip_bufs(struct drm_device *dev, void *data,
775                           struct drm_file *file_priv)
776 {
777         int ret;
778
779         DRM_DEBUG_DRIVER("%s\n", __func__);
780
781         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
782
783         mutex_lock(&dev->struct_mutex);
784         ret = i915_dispatch_flip(dev);
785         mutex_unlock(&dev->struct_mutex);
786
787         return ret;
788 }
789
790 static int i915_getparam(struct drm_device *dev, void *data,
791                          struct drm_file *file_priv)
792 {
793         drm_i915_private_t *dev_priv = dev->dev_private;
794         drm_i915_getparam_t *param = data;
795         int value;
796
797         if (!dev_priv) {
798                 DRM_ERROR("called with no initialization\n");
799                 return -EINVAL;
800         }
801
802         switch (param->param) {
803         case I915_PARAM_IRQ_ACTIVE:
804                 value = dev->pdev->irq ? 1 : 0;
805                 break;
806         case I915_PARAM_ALLOW_BATCHBUFFER:
807                 value = dev_priv->allow_batchbuffer ? 1 : 0;
808                 break;
809         case I915_PARAM_LAST_DISPATCH:
810                 value = READ_BREADCRUMB(dev_priv);
811                 break;
812         case I915_PARAM_CHIPSET_ID:
813                 value = dev->pci_device;
814                 break;
815         case I915_PARAM_HAS_GEM:
816                 value = dev_priv->has_gem;
817                 break;
818         case I915_PARAM_NUM_FENCES_AVAIL:
819                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
820                 break;
821         case I915_PARAM_HAS_OVERLAY:
822                 value = dev_priv->overlay ? 1 : 0;
823                 break;
824         case I915_PARAM_HAS_PAGEFLIPPING:
825                 value = 1;
826                 break;
827         case I915_PARAM_HAS_EXECBUF2:
828                 /* depends on GEM */
829                 value = dev_priv->has_gem;
830                 break;
831         default:
832                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
833                                  param->param);
834                 return -EINVAL;
835         }
836
837         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
838                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
839                 return -EFAULT;
840         }
841
842         return 0;
843 }
844
845 static int i915_setparam(struct drm_device *dev, void *data,
846                          struct drm_file *file_priv)
847 {
848         drm_i915_private_t *dev_priv = dev->dev_private;
849         drm_i915_setparam_t *param = data;
850
851         if (!dev_priv) {
852                 DRM_ERROR("called with no initialization\n");
853                 return -EINVAL;
854         }
855
856         switch (param->param) {
857         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
858                 break;
859         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
860                 dev_priv->tex_lru_log_granularity = param->value;
861                 break;
862         case I915_SETPARAM_ALLOW_BATCHBUFFER:
863                 dev_priv->allow_batchbuffer = param->value;
864                 break;
865         case I915_SETPARAM_NUM_USED_FENCES:
866                 if (param->value > dev_priv->num_fence_regs ||
867                     param->value < 0)
868                         return -EINVAL;
869                 /* Userspace can use first N regs */
870                 dev_priv->fence_reg_start = param->value;
871                 break;
872         default:
873                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
874                                         param->param);
875                 return -EINVAL;
876         }
877
878         return 0;
879 }
880
881 static int i915_set_status_page(struct drm_device *dev, void *data,
882                                 struct drm_file *file_priv)
883 {
884         drm_i915_private_t *dev_priv = dev->dev_private;
885         drm_i915_hws_addr_t *hws = data;
886
887         if (!I915_NEED_GFX_HWS(dev))
888                 return -EINVAL;
889
890         if (!dev_priv) {
891                 DRM_ERROR("called with no initialization\n");
892                 return -EINVAL;
893         }
894
895         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
896                 WARN(1, "tried to set status page when mode setting active\n");
897                 return 0;
898         }
899
900         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
901
902         dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
903
904         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
905         dev_priv->hws_map.size = 4*1024;
906         dev_priv->hws_map.type = 0;
907         dev_priv->hws_map.flags = 0;
908         dev_priv->hws_map.mtrr = 0;
909
910         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
911         if (dev_priv->hws_map.handle == NULL) {
912                 i915_dma_cleanup(dev);
913                 dev_priv->status_gfx_addr = 0;
914                 DRM_ERROR("can not ioremap virtual address for"
915                                 " G33 hw status page\n");
916                 return -ENOMEM;
917         }
918         dev_priv->hw_status_page = dev_priv->hws_map.handle;
919
920         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
921         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
922         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
923                                 dev_priv->status_gfx_addr);
924         DRM_DEBUG_DRIVER("load hws at %p\n",
925                                 dev_priv->hw_status_page);
926         return 0;
927 }
928
929 static int i915_get_bridge_dev(struct drm_device *dev)
930 {
931         struct drm_i915_private *dev_priv = dev->dev_private;
932
933         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
934         if (!dev_priv->bridge_dev) {
935                 DRM_ERROR("bridge device not found\n");
936                 return -1;
937         }
938         return 0;
939 }
940
941 #define MCHBAR_I915 0x44
942 #define MCHBAR_I965 0x48
943 #define MCHBAR_SIZE (4*4096)
944
945 #define DEVEN_REG 0x54
946 #define   DEVEN_MCHBAR_EN (1 << 28)
947
948 /* Allocate space for the MCH regs if needed, return nonzero on error */
949 static int
950 intel_alloc_mchbar_resource(struct drm_device *dev)
951 {
952         drm_i915_private_t *dev_priv = dev->dev_private;
953         int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
954         u32 temp_lo, temp_hi = 0;
955         u64 mchbar_addr;
956         int ret = 0;
957
958         if (IS_I965G(dev))
959                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
960         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
961         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
962
963         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
964 #ifdef CONFIG_PNP
965         if (mchbar_addr &&
966             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) {
967                 ret = 0;
968                 goto out;
969         }
970 #endif
971
972         /* Get some space for it */
973         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res,
974                                      MCHBAR_SIZE, MCHBAR_SIZE,
975                                      PCIBIOS_MIN_MEM,
976                                      0,   pcibios_align_resource,
977                                      dev_priv->bridge_dev);
978         if (ret) {
979                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
980                 dev_priv->mch_res.start = 0;
981                 goto out;
982         }
983
984         if (IS_I965G(dev))
985                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
986                                        upper_32_bits(dev_priv->mch_res.start));
987
988         pci_write_config_dword(dev_priv->bridge_dev, reg,
989                                lower_32_bits(dev_priv->mch_res.start));
990 out:
991         return ret;
992 }
993
994 /* Setup MCHBAR if possible, return true if we should disable it again */
995 static void
996 intel_setup_mchbar(struct drm_device *dev)
997 {
998         drm_i915_private_t *dev_priv = dev->dev_private;
999         int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
1000         u32 temp;
1001         bool enabled;
1002
1003         dev_priv->mchbar_need_disable = false;
1004
1005         if (IS_I915G(dev) || IS_I915GM(dev)) {
1006                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1007                 enabled = !!(temp & DEVEN_MCHBAR_EN);
1008         } else {
1009                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1010                 enabled = temp & 1;
1011         }
1012
1013         /* If it's already enabled, don't have to do anything */
1014         if (enabled)
1015                 return;
1016
1017         if (intel_alloc_mchbar_resource(dev))
1018                 return;
1019
1020         dev_priv->mchbar_need_disable = true;
1021
1022         /* Space is allocated or reserved, so enable it. */
1023         if (IS_I915G(dev) || IS_I915GM(dev)) {
1024                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1025                                        temp | DEVEN_MCHBAR_EN);
1026         } else {
1027                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1028                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1029         }
1030 }
1031
1032 static void
1033 intel_teardown_mchbar(struct drm_device *dev)
1034 {
1035         drm_i915_private_t *dev_priv = dev->dev_private;
1036         int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
1037         u32 temp;
1038
1039         if (dev_priv->mchbar_need_disable) {
1040                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1041                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1042                         temp &= ~DEVEN_MCHBAR_EN;
1043                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1044                 } else {
1045                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1046                         temp &= ~1;
1047                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1048                 }
1049         }
1050
1051         if (dev_priv->mch_res.start)
1052                 release_resource(&dev_priv->mch_res);
1053 }
1054
1055 /**
1056  * i915_probe_agp - get AGP bootup configuration
1057  * @pdev: PCI device
1058  * @aperture_size: returns AGP aperture configured size
1059  * @preallocated_size: returns size of BIOS preallocated AGP space
1060  *
1061  * Since Intel integrated graphics are UMA, the BIOS has to set aside
1062  * some RAM for the framebuffer at early boot.  This code figures out
1063  * how much was set aside so we can use it for our own purposes.
1064  */
1065 static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
1066                           uint32_t *preallocated_size,
1067                           uint32_t *start)
1068 {
1069         struct drm_i915_private *dev_priv = dev->dev_private;
1070         u16 tmp = 0;
1071         unsigned long overhead;
1072         unsigned long stolen;
1073
1074         /* Get the fb aperture size and "stolen" memory amount. */
1075         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
1076
1077         *aperture_size = 1024 * 1024;
1078         *preallocated_size = 1024 * 1024;
1079
1080         switch (dev->pdev->device) {
1081         case PCI_DEVICE_ID_INTEL_82830_CGC:
1082         case PCI_DEVICE_ID_INTEL_82845G_IG:
1083         case PCI_DEVICE_ID_INTEL_82855GM_IG:
1084         case PCI_DEVICE_ID_INTEL_82865_IG:
1085                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
1086                         *aperture_size *= 64;
1087                 else
1088                         *aperture_size *= 128;
1089                 break;
1090         default:
1091                 /* 9xx supports large sizes, just look at the length */
1092                 *aperture_size = pci_resource_len(dev->pdev, 2);
1093                 break;
1094         }
1095
1096         /*
1097          * Some of the preallocated space is taken by the GTT
1098          * and popup.  GTT is 1K per MB of aperture size, and popup is 4K.
1099          */
1100         if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev))
1101                 overhead = 4096;
1102         else
1103                 overhead = (*aperture_size / 1024) + 4096;
1104
1105         if (IS_GEN6(dev)) {
1106                 /* SNB has memory control reg at 0x50.w */
1107                 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &tmp);
1108
1109                 switch (tmp & SNB_GMCH_GMS_STOLEN_MASK) {
1110                 case INTEL_855_GMCH_GMS_DISABLED:
1111                         DRM_ERROR("video memory is disabled\n");
1112                         return -1;
1113                 case SNB_GMCH_GMS_STOLEN_32M:
1114                         stolen = 32 * 1024 * 1024;
1115                         break;
1116                 case SNB_GMCH_GMS_STOLEN_64M:
1117                         stolen = 64 * 1024 * 1024;
1118                         break;
1119                 case SNB_GMCH_GMS_STOLEN_96M:
1120                         stolen = 96 * 1024 * 1024;
1121                         break;
1122                 case SNB_GMCH_GMS_STOLEN_128M:
1123                         stolen = 128 * 1024 * 1024;
1124                         break;
1125                 case SNB_GMCH_GMS_STOLEN_160M:
1126                         stolen = 160 * 1024 * 1024;
1127                         break;
1128                 case SNB_GMCH_GMS_STOLEN_192M:
1129                         stolen = 192 * 1024 * 1024;
1130                         break;
1131                 case SNB_GMCH_GMS_STOLEN_224M:
1132                         stolen = 224 * 1024 * 1024;
1133                         break;
1134                 case SNB_GMCH_GMS_STOLEN_256M:
1135                         stolen = 256 * 1024 * 1024;
1136                         break;
1137                 case SNB_GMCH_GMS_STOLEN_288M:
1138                         stolen = 288 * 1024 * 1024;
1139                         break;
1140                 case SNB_GMCH_GMS_STOLEN_320M:
1141                         stolen = 320 * 1024 * 1024;
1142                         break;
1143                 case SNB_GMCH_GMS_STOLEN_352M:
1144                         stolen = 352 * 1024 * 1024;
1145                         break;
1146                 case SNB_GMCH_GMS_STOLEN_384M:
1147                         stolen = 384 * 1024 * 1024;
1148                         break;
1149                 case SNB_GMCH_GMS_STOLEN_416M:
1150                         stolen = 416 * 1024 * 1024;
1151                         break;
1152                 case SNB_GMCH_GMS_STOLEN_448M:
1153                         stolen = 448 * 1024 * 1024;
1154                         break;
1155                 case SNB_GMCH_GMS_STOLEN_480M:
1156                         stolen = 480 * 1024 * 1024;
1157                         break;
1158                 case SNB_GMCH_GMS_STOLEN_512M:
1159                         stolen = 512 * 1024 * 1024;
1160                         break;
1161                 default:
1162                         DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1163                                   tmp & SNB_GMCH_GMS_STOLEN_MASK);
1164                         return -1;
1165                 }
1166         } else {
1167                 switch (tmp & INTEL_GMCH_GMS_MASK) {
1168                 case INTEL_855_GMCH_GMS_DISABLED:
1169                         DRM_ERROR("video memory is disabled\n");
1170                         return -1;
1171                 case INTEL_855_GMCH_GMS_STOLEN_1M:
1172                         stolen = 1 * 1024 * 1024;
1173                         break;
1174                 case INTEL_855_GMCH_GMS_STOLEN_4M:
1175                         stolen = 4 * 1024 * 1024;
1176                         break;
1177                 case INTEL_855_GMCH_GMS_STOLEN_8M:
1178                         stolen = 8 * 1024 * 1024;
1179                         break;
1180                 case INTEL_855_GMCH_GMS_STOLEN_16M:
1181                         stolen = 16 * 1024 * 1024;
1182                         break;
1183                 case INTEL_855_GMCH_GMS_STOLEN_32M:
1184                         stolen = 32 * 1024 * 1024;
1185                         break;
1186                 case INTEL_915G_GMCH_GMS_STOLEN_48M:
1187                         stolen = 48 * 1024 * 1024;
1188                         break;
1189                 case INTEL_915G_GMCH_GMS_STOLEN_64M:
1190                         stolen = 64 * 1024 * 1024;
1191                         break;
1192                 case INTEL_GMCH_GMS_STOLEN_128M:
1193                         stolen = 128 * 1024 * 1024;
1194                         break;
1195                 case INTEL_GMCH_GMS_STOLEN_256M:
1196                         stolen = 256 * 1024 * 1024;
1197                         break;
1198                 case INTEL_GMCH_GMS_STOLEN_96M:
1199                         stolen = 96 * 1024 * 1024;
1200                         break;
1201                 case INTEL_GMCH_GMS_STOLEN_160M:
1202                         stolen = 160 * 1024 * 1024;
1203                         break;
1204                 case INTEL_GMCH_GMS_STOLEN_224M:
1205                         stolen = 224 * 1024 * 1024;
1206                         break;
1207                 case INTEL_GMCH_GMS_STOLEN_352M:
1208                         stolen = 352 * 1024 * 1024;
1209                         break;
1210                 default:
1211                         DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1212                                   tmp & INTEL_GMCH_GMS_MASK);
1213                         return -1;
1214                 }
1215         }
1216
1217         *preallocated_size = stolen - overhead;
1218         *start = overhead;
1219
1220         return 0;
1221 }
1222
1223 #define PTE_ADDRESS_MASK                0xfffff000
1224 #define PTE_ADDRESS_MASK_HIGH           0x000000f0 /* i915+ */
1225 #define PTE_MAPPING_TYPE_UNCACHED       (0 << 1)
1226 #define PTE_MAPPING_TYPE_DCACHE         (1 << 1) /* i830 only */
1227 #define PTE_MAPPING_TYPE_CACHED         (3 << 1)
1228 #define PTE_MAPPING_TYPE_MASK           (3 << 1)
1229 #define PTE_VALID                       (1 << 0)
1230
1231 /**
1232  * i915_gtt_to_phys - take a GTT address and turn it into a physical one
1233  * @dev: drm device
1234  * @gtt_addr: address to translate
1235  *
1236  * Some chip functions require allocations from stolen space but need the
1237  * physical address of the memory in question.  We use this routine
1238  * to get a physical address suitable for register programming from a given
1239  * GTT address.
1240  */
1241 static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1242                                       unsigned long gtt_addr)
1243 {
1244         unsigned long *gtt;
1245         unsigned long entry, phys;
1246         int gtt_bar = IS_I9XX(dev) ? 0 : 1;
1247         int gtt_offset, gtt_size;
1248
1249         if (IS_I965G(dev)) {
1250                 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
1251                         gtt_offset = 2*1024*1024;
1252                         gtt_size = 2*1024*1024;
1253                 } else {
1254                         gtt_offset = 512*1024;
1255                         gtt_size = 512*1024;
1256                 }
1257         } else {
1258                 gtt_bar = 3;
1259                 gtt_offset = 0;
1260                 gtt_size = pci_resource_len(dev->pdev, gtt_bar);
1261         }
1262
1263         gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
1264                          gtt_size);
1265         if (!gtt) {
1266                 DRM_ERROR("ioremap of GTT failed\n");
1267                 return 0;
1268         }
1269
1270         entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
1271
1272         DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
1273
1274         /* Mask out these reserved bits on this hardware. */
1275         if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
1276             IS_I945G(dev) || IS_I945GM(dev)) {
1277                 entry &= ~PTE_ADDRESS_MASK_HIGH;
1278         }
1279
1280         /* If it's not a mapping type we know, then bail. */
1281         if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
1282             (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
1283                 iounmap(gtt);
1284                 return 0;
1285         }
1286
1287         if (!(entry & PTE_VALID)) {
1288                 DRM_ERROR("bad GTT entry in stolen space\n");
1289                 iounmap(gtt);
1290                 return 0;
1291         }
1292
1293         iounmap(gtt);
1294
1295         phys =(entry & PTE_ADDRESS_MASK) |
1296                 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
1297
1298         DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
1299
1300         return phys;
1301 }
1302
1303 static void i915_warn_stolen(struct drm_device *dev)
1304 {
1305         DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1306         DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1307 }
1308
1309 static void i915_setup_compression(struct drm_device *dev, int size)
1310 {
1311         struct drm_i915_private *dev_priv = dev->dev_private;
1312         struct drm_mm_node *compressed_fb, *compressed_llb;
1313         unsigned long cfb_base;
1314         unsigned long ll_base = 0;
1315
1316         /* Leave 1M for line length buffer & misc. */
1317         compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
1318         if (!compressed_fb) {
1319                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1320                 i915_warn_stolen(dev);
1321                 return;
1322         }
1323
1324         compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1325         if (!compressed_fb) {
1326                 i915_warn_stolen(dev);
1327                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1328                 return;
1329         }
1330
1331         cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
1332         if (!cfb_base) {
1333                 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1334                 drm_mm_put_block(compressed_fb);
1335         }
1336
1337         if (!IS_GM45(dev)) {
1338                 compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096,
1339                                                     4096, 0);
1340                 if (!compressed_llb) {
1341                         i915_warn_stolen(dev);
1342                         return;
1343                 }
1344
1345                 compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
1346                 if (!compressed_llb) {
1347                         i915_warn_stolen(dev);
1348                         return;
1349                 }
1350
1351                 ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
1352                 if (!ll_base) {
1353                         DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1354                         drm_mm_put_block(compressed_fb);
1355                         drm_mm_put_block(compressed_llb);
1356                 }
1357         }
1358
1359         dev_priv->cfb_size = size;
1360
1361         intel_disable_fbc(dev);
1362         dev_priv->compressed_fb = compressed_fb;
1363
1364         if (IS_GM45(dev)) {
1365                 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1366         } else {
1367                 I915_WRITE(FBC_CFB_BASE, cfb_base);
1368                 I915_WRITE(FBC_LL_BASE, ll_base);
1369                 dev_priv->compressed_llb = compressed_llb;
1370         }
1371
1372         DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
1373                   ll_base, size >> 20);
1374 }
1375
1376 static void i915_cleanup_compression(struct drm_device *dev)
1377 {
1378         struct drm_i915_private *dev_priv = dev->dev_private;
1379
1380         drm_mm_put_block(dev_priv->compressed_fb);
1381         if (!IS_GM45(dev))
1382                 drm_mm_put_block(dev_priv->compressed_llb);
1383 }
1384
1385 /* true = enable decode, false = disable decoder */
1386 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1387 {
1388         struct drm_device *dev = cookie;
1389
1390         intel_modeset_vga_set_state(dev, state);
1391         if (state)
1392                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1393                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1394         else
1395                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1396 }
1397
1398 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1399 {
1400         struct drm_device *dev = pci_get_drvdata(pdev);
1401         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1402         if (state == VGA_SWITCHEROO_ON) {
1403                 printk(KERN_INFO "i915: switched off\n");
1404                 /* i915 resume handler doesn't set to D0 */
1405                 pci_set_power_state(dev->pdev, PCI_D0);
1406                 i915_resume(dev);
1407         } else {
1408                 printk(KERN_ERR "i915: switched off\n");
1409                 i915_suspend(dev, pmm);
1410         }
1411 }
1412
1413 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1414 {
1415         struct drm_device *dev = pci_get_drvdata(pdev);
1416         bool can_switch;
1417
1418         spin_lock(&dev->count_lock);
1419         can_switch = (dev->open_count == 0);
1420         spin_unlock(&dev->count_lock);
1421         return can_switch;
1422 }
1423
1424 static int i915_load_modeset_init(struct drm_device *dev,
1425                                   unsigned long prealloc_start,
1426                                   unsigned long prealloc_size,
1427                                   unsigned long agp_size)
1428 {
1429         struct drm_i915_private *dev_priv = dev->dev_private;
1430         int fb_bar = IS_I9XX(dev) ? 2 : 0;
1431         int ret = 0;
1432
1433         dev->mode_config.fb_base = pci_resource_start(dev->pdev, fb_bar) &
1434                 0xff000000;
1435
1436         /* Basic memrange allocator for stolen space (aka vram) */
1437         drm_mm_init(&dev_priv->vram, 0, prealloc_size);
1438         DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
1439
1440         /* We're off and running w/KMS */
1441         dev_priv->mm.suspended = 0;
1442
1443         /* Let GEM Manage from end of prealloc space to end of aperture.
1444          *
1445          * However, leave one page at the end still bound to the scratch page.
1446          * There are a number of places where the hardware apparently
1447          * prefetches past the end of the object, and we've seen multiple
1448          * hangs with the GPU head pointer stuck in a batchbuffer bound
1449          * at the last page of the aperture.  One page should be enough to
1450          * keep any prefetching inside of the aperture.
1451          */
1452         i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
1453
1454         mutex_lock(&dev->struct_mutex);
1455         ret = i915_gem_init_ringbuffer(dev);
1456         mutex_unlock(&dev->struct_mutex);
1457         if (ret)
1458                 goto out;
1459
1460         /* Try to set up FBC with a reasonable compressed buffer size */
1461         if (I915_HAS_FBC(dev) && i915_powersave) {
1462                 int cfb_size;
1463
1464                 /* Try to get an 8M buffer... */
1465                 if (prealloc_size > (9*1024*1024))
1466                         cfb_size = 8*1024*1024;
1467                 else /* fall back to 7/8 of the stolen space */
1468                         cfb_size = prealloc_size * 7 / 8;
1469                 i915_setup_compression(dev, cfb_size);
1470         }
1471
1472         /* Allow hardware batchbuffers unless told otherwise.
1473          */
1474         dev_priv->allow_batchbuffer = 1;
1475
1476         ret = intel_init_bios(dev);
1477         if (ret)
1478                 DRM_INFO("failed to find VBIOS tables\n");
1479
1480         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1481         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1482         if (ret)
1483                 goto destroy_ringbuffer;
1484
1485         ret = vga_switcheroo_register_client(dev->pdev,
1486                                              i915_switcheroo_set_state,
1487                                              i915_switcheroo_can_switch);
1488         if (ret)
1489                 goto destroy_ringbuffer;
1490
1491         intel_modeset_init(dev);
1492
1493         ret = drm_irq_install(dev);
1494         if (ret)
1495                 goto destroy_ringbuffer;
1496
1497         /* Always safe in the mode setting case. */
1498         /* FIXME: do pre/post-mode set stuff in core KMS code */
1499         dev->vblank_disable_allowed = 1;
1500
1501         /*
1502          * Initialize the hardware status page IRQ location.
1503          */
1504
1505         I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
1506
1507         intel_fbdev_init(dev);
1508         drm_kms_helper_poll_init(dev);
1509         return 0;
1510
1511 destroy_ringbuffer:
1512         mutex_lock(&dev->struct_mutex);
1513         i915_gem_cleanup_ringbuffer(dev);
1514         mutex_unlock(&dev->struct_mutex);
1515 out:
1516         return ret;
1517 }
1518
1519 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1520 {
1521         struct drm_i915_master_private *master_priv;
1522
1523         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1524         if (!master_priv)
1525                 return -ENOMEM;
1526
1527         master->driver_priv = master_priv;
1528         return 0;
1529 }
1530
1531 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1532 {
1533         struct drm_i915_master_private *master_priv = master->driver_priv;
1534
1535         if (!master_priv)
1536                 return;
1537
1538         kfree(master_priv);
1539
1540         master->driver_priv = NULL;
1541 }
1542
1543 static void i915_get_mem_freq(struct drm_device *dev)
1544 {
1545         drm_i915_private_t *dev_priv = dev->dev_private;
1546         u32 tmp;
1547
1548         if (!IS_PINEVIEW(dev))
1549                 return;
1550
1551         tmp = I915_READ(CLKCFG);
1552
1553         switch (tmp & CLKCFG_FSB_MASK) {
1554         case CLKCFG_FSB_533:
1555                 dev_priv->fsb_freq = 533; /* 133*4 */
1556                 break;
1557         case CLKCFG_FSB_800:
1558                 dev_priv->fsb_freq = 800; /* 200*4 */
1559                 break;
1560         case CLKCFG_FSB_667:
1561                 dev_priv->fsb_freq =  667; /* 167*4 */
1562                 break;
1563         case CLKCFG_FSB_400:
1564                 dev_priv->fsb_freq = 400; /* 100*4 */
1565                 break;
1566         }
1567
1568         switch (tmp & CLKCFG_MEM_MASK) {
1569         case CLKCFG_MEM_533:
1570                 dev_priv->mem_freq = 533;
1571                 break;
1572         case CLKCFG_MEM_667:
1573                 dev_priv->mem_freq = 667;
1574                 break;
1575         case CLKCFG_MEM_800:
1576                 dev_priv->mem_freq = 800;
1577                 break;
1578         }
1579 }
1580
1581 /**
1582  * i915_driver_load - setup chip and create an initial config
1583  * @dev: DRM device
1584  * @flags: startup flags
1585  *
1586  * The driver load routine has to do several things:
1587  *   - drive output discovery via intel_modeset_init()
1588  *   - initialize the memory manager
1589  *   - allocate initial config memory
1590  *   - setup the DRM framebuffer with the allocated memory
1591  */
1592 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1593 {
1594         struct drm_i915_private *dev_priv;
1595         resource_size_t base, size;
1596         int ret = 0, mmio_bar;
1597         uint32_t agp_size, prealloc_size, prealloc_start;
1598
1599         /* i915 has 4 more counters */
1600         dev->counters += 4;
1601         dev->types[6] = _DRM_STAT_IRQ;
1602         dev->types[7] = _DRM_STAT_PRIMARY;
1603         dev->types[8] = _DRM_STAT_SECONDARY;
1604         dev->types[9] = _DRM_STAT_DMA;
1605
1606         dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1607         if (dev_priv == NULL)
1608                 return -ENOMEM;
1609
1610         dev->dev_private = (void *)dev_priv;
1611         dev_priv->dev = dev;
1612         dev_priv->info = (struct intel_device_info *) flags;
1613
1614         /* Add register map (needed for suspend/resume) */
1615         mmio_bar = IS_I9XX(dev) ? 0 : 1;
1616         base = pci_resource_start(dev->pdev, mmio_bar);
1617         size = pci_resource_len(dev->pdev, mmio_bar);
1618
1619         if (i915_get_bridge_dev(dev)) {
1620                 ret = -EIO;
1621                 goto free_priv;
1622         }
1623
1624         dev_priv->regs = ioremap(base, size);
1625         if (!dev_priv->regs) {
1626                 DRM_ERROR("failed to map registers\n");
1627                 ret = -EIO;
1628                 goto put_bridge;
1629         }
1630
1631         dev_priv->mm.gtt_mapping =
1632                 io_mapping_create_wc(dev->agp->base,
1633                                      dev->agp->agp_info.aper_size * 1024*1024);
1634         if (dev_priv->mm.gtt_mapping == NULL) {
1635                 ret = -EIO;
1636                 goto out_rmmap;
1637         }
1638
1639         /* Set up a WC MTRR for non-PAT systems.  This is more common than
1640          * one would think, because the kernel disables PAT on first
1641          * generation Core chips because WC PAT gets overridden by a UC
1642          * MTRR if present.  Even if a UC MTRR isn't present.
1643          */
1644         dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
1645                                          dev->agp->agp_info.aper_size *
1646                                          1024 * 1024,
1647                                          MTRR_TYPE_WRCOMB, 1);
1648         if (dev_priv->mm.gtt_mtrr < 0) {
1649                 DRM_INFO("MTRR allocation failed.  Graphics "
1650                          "performance may suffer.\n");
1651         }
1652
1653         ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start);
1654         if (ret)
1655                 goto out_iomapfree;
1656
1657         dev_priv->wq = create_singlethread_workqueue("i915");
1658         if (dev_priv->wq == NULL) {
1659                 DRM_ERROR("Failed to create our workqueue.\n");
1660                 ret = -ENOMEM;
1661                 goto out_iomapfree;
1662         }
1663
1664         /* enable GEM by default */
1665         dev_priv->has_gem = 1;
1666
1667         if (prealloc_size > agp_size * 3 / 4) {
1668                 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
1669                           "memory stolen.\n",
1670                           prealloc_size / 1024, agp_size / 1024);
1671                 DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
1672                           "updating the BIOS to fix).\n");
1673                 dev_priv->has_gem = 0;
1674         }
1675
1676         dev->driver->get_vblank_counter = i915_get_vblank_counter;
1677         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1678         if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
1679                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
1680                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
1681         }
1682
1683         /* Try to make sure MCHBAR is enabled before poking at it */
1684         intel_setup_mchbar(dev);
1685
1686         i915_gem_load(dev);
1687
1688         /* Init HWS */
1689         if (!I915_NEED_GFX_HWS(dev)) {
1690                 ret = i915_init_phys_hws(dev);
1691                 if (ret != 0)
1692                         goto out_workqueue_free;
1693         }
1694
1695         i915_get_mem_freq(dev);
1696
1697         /* On the 945G/GM, the chipset reports the MSI capability on the
1698          * integrated graphics even though the support isn't actually there
1699          * according to the published specs.  It doesn't appear to function
1700          * correctly in testing on 945G.
1701          * This may be a side effect of MSI having been made available for PEG
1702          * and the registers being closely associated.
1703          *
1704          * According to chipset errata, on the 965GM, MSI interrupts may
1705          * be lost or delayed, but we use them anyways to avoid
1706          * stuck interrupts on some machines.
1707          */
1708         if (!IS_I945G(dev) && !IS_I945GM(dev))
1709                 pci_enable_msi(dev->pdev);
1710
1711         spin_lock_init(&dev_priv->user_irq_lock);
1712         spin_lock_init(&dev_priv->error_lock);
1713         dev_priv->user_irq_refcount = 0;
1714         dev_priv->trace_irq_seqno = 0;
1715
1716         ret = drm_vblank_init(dev, I915_NUM_PIPE);
1717
1718         if (ret) {
1719                 (void) i915_driver_unload(dev);
1720                 return ret;
1721         }
1722
1723         /* Start out suspended */
1724         dev_priv->mm.suspended = 1;
1725
1726         intel_detect_pch(dev);
1727
1728         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1729                 ret = i915_load_modeset_init(dev, prealloc_start,
1730                                              prealloc_size, agp_size);
1731                 if (ret < 0) {
1732                         DRM_ERROR("failed to init modeset\n");
1733                         goto out_workqueue_free;
1734                 }
1735         }
1736
1737         /* Must be done after probing outputs */
1738         intel_opregion_init(dev, 0);
1739
1740         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1741                     (unsigned long) dev);
1742         return 0;
1743
1744 out_workqueue_free:
1745         destroy_workqueue(dev_priv->wq);
1746 out_iomapfree:
1747         io_mapping_free(dev_priv->mm.gtt_mapping);
1748 out_rmmap:
1749         iounmap(dev_priv->regs);
1750 put_bridge:
1751         pci_dev_put(dev_priv->bridge_dev);
1752 free_priv:
1753         kfree(dev_priv);
1754         return ret;
1755 }
1756
1757 int i915_driver_unload(struct drm_device *dev)
1758 {
1759         struct drm_i915_private *dev_priv = dev->dev_private;
1760
1761         i915_destroy_error_state(dev);
1762
1763         destroy_workqueue(dev_priv->wq);
1764         del_timer_sync(&dev_priv->hangcheck_timer);
1765
1766         io_mapping_free(dev_priv->mm.gtt_mapping);
1767         if (dev_priv->mm.gtt_mtrr >= 0) {
1768                 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
1769                          dev->agp->agp_info.aper_size * 1024 * 1024);
1770                 dev_priv->mm.gtt_mtrr = -1;
1771         }
1772
1773         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1774                 intel_modeset_cleanup(dev);
1775
1776                 /*
1777                  * free the memory space allocated for the child device
1778                  * config parsed from VBT
1779                  */
1780                 if (dev_priv->child_dev && dev_priv->child_dev_num) {
1781                         kfree(dev_priv->child_dev);
1782                         dev_priv->child_dev = NULL;
1783                         dev_priv->child_dev_num = 0;
1784                 }
1785                 drm_irq_uninstall(dev);
1786                 vga_switcheroo_unregister_client(dev->pdev);
1787                 vga_client_register(dev->pdev, NULL, NULL, NULL);
1788         }
1789
1790         if (dev->pdev->msi_enabled)
1791                 pci_disable_msi(dev->pdev);
1792
1793         if (dev_priv->regs != NULL)
1794                 iounmap(dev_priv->regs);
1795
1796         intel_opregion_free(dev, 0);
1797
1798         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1799                 i915_gem_free_all_phys_object(dev);
1800
1801                 mutex_lock(&dev->struct_mutex);
1802                 i915_gem_cleanup_ringbuffer(dev);
1803                 mutex_unlock(&dev->struct_mutex);
1804                 if (I915_HAS_FBC(dev) && i915_powersave)
1805                         i915_cleanup_compression(dev);
1806                 drm_mm_takedown(&dev_priv->vram);
1807                 i915_gem_lastclose(dev);
1808
1809                 intel_cleanup_overlay(dev);
1810         }
1811
1812         intel_teardown_mchbar(dev);
1813
1814         pci_dev_put(dev_priv->bridge_dev);
1815         kfree(dev->dev_private);
1816
1817         return 0;
1818 }
1819
1820 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1821 {
1822         struct drm_i915_file_private *i915_file_priv;
1823
1824         DRM_DEBUG_DRIVER("\n");
1825         i915_file_priv = (struct drm_i915_file_private *)
1826             kmalloc(sizeof(*i915_file_priv), GFP_KERNEL);
1827
1828         if (!i915_file_priv)
1829                 return -ENOMEM;
1830
1831         file_priv->driver_priv = i915_file_priv;
1832
1833         INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
1834
1835         return 0;
1836 }
1837
1838 /**
1839  * i915_driver_lastclose - clean up after all DRM clients have exited
1840  * @dev: DRM device
1841  *
1842  * Take care of cleaning up after all DRM clients have exited.  In the
1843  * mode setting case, we want to restore the kernel's initial mode (just
1844  * in case the last client left us in a bad state).
1845  *
1846  * Additionally, in the non-mode setting case, we'll tear down the AGP
1847  * and DMA structures, since the kernel won't be using them, and clea
1848  * up any GEM state.
1849  */
1850 void i915_driver_lastclose(struct drm_device * dev)
1851 {
1852         drm_i915_private_t *dev_priv = dev->dev_private;
1853
1854         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1855                 drm_fb_helper_restore();
1856                 vga_switcheroo_process_delayed_switch();
1857                 return;
1858         }
1859
1860         i915_gem_lastclose(dev);
1861
1862         if (dev_priv->agp_heap)
1863                 i915_mem_takedown(&(dev_priv->agp_heap));
1864
1865         i915_dma_cleanup(dev);
1866 }
1867
1868 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1869 {
1870         drm_i915_private_t *dev_priv = dev->dev_private;
1871         i915_gem_release(dev, file_priv);
1872         if (!drm_core_check_feature(dev, DRIVER_MODESET))
1873                 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
1874 }
1875
1876 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1877 {
1878         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1879
1880         kfree(i915_file_priv);
1881 }
1882
1883 struct drm_ioctl_desc i915_ioctls[] = {
1884         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1885         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1886         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1887         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1888         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1889         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1890         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1891         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1892         DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
1893         DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
1894         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1895         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1896         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1897         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1898         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
1899         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1900         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1901         DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1902         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1903         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
1904         DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1905         DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1906         DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1907         DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
1908         DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1909         DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1910         DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
1911         DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1912         DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1913         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
1914         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1915         DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1916         DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1917         DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
1918         DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
1919         DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1920         DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1921         DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1922         DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1923         DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1924 };
1925
1926 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1927
1928 /**
1929  * Determine if the device really is AGP or not.
1930  *
1931  * All Intel graphics chipsets are treated as AGP, even if they are really
1932  * PCI-e.
1933  *
1934  * \param dev   The device to be tested.
1935  *
1936  * \returns
1937  * A value of 1 is always retured to indictate every i9x5 is AGP.
1938  */
1939 int i915_driver_device_is_agp(struct drm_device * dev)
1940 {
1941         return 1;
1942 }