0dee776b91fbc302eef50c6e9142fe9ecec70a39
[linux-2.6.git] / drivers / gpu / drm / i915 / i915_dma.c
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2  */
3 /*
4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5  * All Rights Reserved.
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a
8  * copy of this software and associated documentation files (the
9  * "Software"), to deal in the Software without restriction, including
10  * without limitation the rights to use, copy, modify, merge, publish,
11  * distribute, sub license, and/or sell copies of the Software, and to
12  * permit persons to whom the Software is furnished to do so, subject to
13  * the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the
16  * next paragraph) shall be included in all copies or substantial portions
17  * of the Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26  *
27  */
28
29 #include "drmP.h"
30 #include "drm.h"
31 #include "drm_crtc_helper.h"
32 #include "intel_drv.h"
33 #include "i915_drm.h"
34 #include "i915_drv.h"
35
36 /* Really want an OS-independent resettable timer.  Would like to have
37  * this loop run for (eg) 3 sec, but have the timer reset every time
38  * the head pointer changes, so that EBUSY only happens if the ring
39  * actually stalls for (eg) 3 seconds.
40  */
41 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
42 {
43         drm_i915_private_t *dev_priv = dev->dev_private;
44         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
45         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
46         u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
47         u32 last_acthd = I915_READ(acthd_reg);
48         u32 acthd;
49         u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
50         int i;
51
52         for (i = 0; i < 100000; i++) {
53                 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
54                 acthd = I915_READ(acthd_reg);
55                 ring->space = ring->head - (ring->tail + 8);
56                 if (ring->space < 0)
57                         ring->space += ring->Size;
58                 if (ring->space >= n)
59                         return 0;
60
61                 if (master_priv->sarea_priv)
62                         master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
63
64                 if (ring->head != last_head)
65                         i = 0;
66                 if (acthd != last_acthd)
67                         i = 0;
68
69                 last_head = ring->head;
70                 last_acthd = acthd;
71                 msleep_interruptible(10);
72
73         }
74
75         return -EBUSY;
76 }
77
78 /**
79  * Sets up the hardware status page for devices that need a physical address
80  * in the register.
81  */
82 static int i915_init_phys_hws(struct drm_device *dev)
83 {
84         drm_i915_private_t *dev_priv = dev->dev_private;
85         /* Program Hardware Status Page */
86         dev_priv->status_page_dmah =
87                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
88
89         if (!dev_priv->status_page_dmah) {
90                 DRM_ERROR("Can not allocate hardware status page\n");
91                 return -ENOMEM;
92         }
93         dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
94         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
95
96         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
97
98         I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
99         DRM_DEBUG("Enabled hardware status page\n");
100         return 0;
101 }
102
103 /**
104  * Frees the hardware status page, whether it's a physical address or a virtual
105  * address set up by the X Server.
106  */
107 static void i915_free_hws(struct drm_device *dev)
108 {
109         drm_i915_private_t *dev_priv = dev->dev_private;
110         if (dev_priv->status_page_dmah) {
111                 drm_pci_free(dev, dev_priv->status_page_dmah);
112                 dev_priv->status_page_dmah = NULL;
113         }
114
115         if (dev_priv->status_gfx_addr) {
116                 dev_priv->status_gfx_addr = 0;
117                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
118         }
119
120         /* Need to rewrite hardware status page */
121         I915_WRITE(HWS_PGA, 0x1ffff000);
122 }
123
124 void i915_kernel_lost_context(struct drm_device * dev)
125 {
126         drm_i915_private_t *dev_priv = dev->dev_private;
127         struct drm_i915_master_private *master_priv;
128         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
129
130         /*
131          * We should never lose context on the ring with modesetting
132          * as we don't expose it to userspace
133          */
134         if (drm_core_check_feature(dev, DRIVER_MODESET))
135                 return;
136
137         ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
138         ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
139         ring->space = ring->head - (ring->tail + 8);
140         if (ring->space < 0)
141                 ring->space += ring->Size;
142
143         if (!dev->primary->master)
144                 return;
145
146         master_priv = dev->primary->master->driver_priv;
147         if (ring->head == ring->tail && master_priv->sarea_priv)
148                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
149 }
150
151 static int i915_dma_cleanup(struct drm_device * dev)
152 {
153         drm_i915_private_t *dev_priv = dev->dev_private;
154         /* Make sure interrupts are disabled here because the uninstall ioctl
155          * may not have been called from userspace and after dev_private
156          * is freed, it's too late.
157          */
158         if (dev->irq_enabled)
159                 drm_irq_uninstall(dev);
160
161         if (dev_priv->ring.virtual_start) {
162                 drm_core_ioremapfree(&dev_priv->ring.map, dev);
163                 dev_priv->ring.virtual_start = NULL;
164                 dev_priv->ring.map.handle = NULL;
165                 dev_priv->ring.map.size = 0;
166         }
167
168         /* Clear the HWS virtual address at teardown */
169         if (I915_NEED_GFX_HWS(dev))
170                 i915_free_hws(dev);
171
172         return 0;
173 }
174
175 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
176 {
177         drm_i915_private_t *dev_priv = dev->dev_private;
178         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
179
180         if (init->ring_size != 0) {
181                 if (dev_priv->ring.ring_obj != NULL) {
182                         i915_dma_cleanup(dev);
183                         DRM_ERROR("Client tried to initialize ringbuffer in "
184                                   "GEM mode\n");
185                         return -EINVAL;
186                 }
187
188                 dev_priv->ring.Size = init->ring_size;
189                 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
190
191                 dev_priv->ring.map.offset = init->ring_start;
192                 dev_priv->ring.map.size = init->ring_size;
193                 dev_priv->ring.map.type = 0;
194                 dev_priv->ring.map.flags = 0;
195                 dev_priv->ring.map.mtrr = 0;
196
197                 drm_core_ioremap(&dev_priv->ring.map, dev);
198
199                 if (dev_priv->ring.map.handle == NULL) {
200                         i915_dma_cleanup(dev);
201                         DRM_ERROR("can not ioremap virtual address for"
202                                   " ring buffer\n");
203                         return -ENOMEM;
204                 }
205         }
206
207         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
208
209         dev_priv->cpp = init->cpp;
210         dev_priv->back_offset = init->back_offset;
211         dev_priv->front_offset = init->front_offset;
212         dev_priv->current_page = 0;
213         if (master_priv->sarea_priv)
214                 master_priv->sarea_priv->pf_current_page = 0;
215
216         /* Allow hardware batchbuffers unless told otherwise.
217          */
218         dev_priv->allow_batchbuffer = 1;
219
220         return 0;
221 }
222
223 static int i915_dma_resume(struct drm_device * dev)
224 {
225         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
226
227         DRM_DEBUG("%s\n", __func__);
228
229         if (dev_priv->ring.map.handle == NULL) {
230                 DRM_ERROR("can not ioremap virtual address for"
231                           " ring buffer\n");
232                 return -ENOMEM;
233         }
234
235         /* Program Hardware Status Page */
236         if (!dev_priv->hw_status_page) {
237                 DRM_ERROR("Can not find hardware status page\n");
238                 return -EINVAL;
239         }
240         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
241
242         if (dev_priv->status_gfx_addr != 0)
243                 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
244         else
245                 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
246         DRM_DEBUG("Enabled hardware status page\n");
247
248         return 0;
249 }
250
251 static int i915_dma_init(struct drm_device *dev, void *data,
252                          struct drm_file *file_priv)
253 {
254         drm_i915_init_t *init = data;
255         int retcode = 0;
256
257         switch (init->func) {
258         case I915_INIT_DMA:
259                 retcode = i915_initialize(dev, init);
260                 break;
261         case I915_CLEANUP_DMA:
262                 retcode = i915_dma_cleanup(dev);
263                 break;
264         case I915_RESUME_DMA:
265                 retcode = i915_dma_resume(dev);
266                 break;
267         default:
268                 retcode = -EINVAL;
269                 break;
270         }
271
272         return retcode;
273 }
274
275 /* Implement basically the same security restrictions as hardware does
276  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
277  *
278  * Most of the calculations below involve calculating the size of a
279  * particular instruction.  It's important to get the size right as
280  * that tells us where the next instruction to check is.  Any illegal
281  * instruction detected will be given a size of zero, which is a
282  * signal to abort the rest of the buffer.
283  */
284 static int do_validate_cmd(int cmd)
285 {
286         switch (((cmd >> 29) & 0x7)) {
287         case 0x0:
288                 switch ((cmd >> 23) & 0x3f) {
289                 case 0x0:
290                         return 1;       /* MI_NOOP */
291                 case 0x4:
292                         return 1;       /* MI_FLUSH */
293                 default:
294                         return 0;       /* disallow everything else */
295                 }
296                 break;
297         case 0x1:
298                 return 0;       /* reserved */
299         case 0x2:
300                 return (cmd & 0xff) + 2;        /* 2d commands */
301         case 0x3:
302                 if (((cmd >> 24) & 0x1f) <= 0x18)
303                         return 1;
304
305                 switch ((cmd >> 24) & 0x1f) {
306                 case 0x1c:
307                         return 1;
308                 case 0x1d:
309                         switch ((cmd >> 16) & 0xff) {
310                         case 0x3:
311                                 return (cmd & 0x1f) + 2;
312                         case 0x4:
313                                 return (cmd & 0xf) + 2;
314                         default:
315                                 return (cmd & 0xffff) + 2;
316                         }
317                 case 0x1e:
318                         if (cmd & (1 << 23))
319                                 return (cmd & 0xffff) + 1;
320                         else
321                                 return 1;
322                 case 0x1f:
323                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
324                                 return (cmd & 0x1ffff) + 2;
325                         else if (cmd & (1 << 17))       /* indirect random */
326                                 if ((cmd & 0xffff) == 0)
327                                         return 0;       /* unknown length, too hard */
328                                 else
329                                         return (((cmd & 0xffff) + 1) / 2) + 1;
330                         else
331                                 return 2;       /* indirect sequential */
332                 default:
333                         return 0;
334                 }
335         default:
336                 return 0;
337         }
338
339         return 0;
340 }
341
342 static int validate_cmd(int cmd)
343 {
344         int ret = do_validate_cmd(cmd);
345
346 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
347
348         return ret;
349 }
350
351 static int i915_emit_cmds(struct drm_device * dev, int __user * buffer, int dwords)
352 {
353         drm_i915_private_t *dev_priv = dev->dev_private;
354         int i;
355         RING_LOCALS;
356
357         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
358                 return -EINVAL;
359
360         BEGIN_LP_RING((dwords+1)&~1);
361
362         for (i = 0; i < dwords;) {
363                 int cmd, sz;
364
365                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
366                         return -EINVAL;
367
368                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
369                         return -EINVAL;
370
371                 OUT_RING(cmd);
372
373                 while (++i, --sz) {
374                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
375                                                          sizeof(cmd))) {
376                                 return -EINVAL;
377                         }
378                         OUT_RING(cmd);
379                 }
380         }
381
382         if (dwords & 1)
383                 OUT_RING(0);
384
385         ADVANCE_LP_RING();
386
387         return 0;
388 }
389
390 int
391 i915_emit_box(struct drm_device *dev,
392               struct drm_clip_rect __user *boxes,
393               int i, int DR1, int DR4)
394 {
395         drm_i915_private_t *dev_priv = dev->dev_private;
396         struct drm_clip_rect box;
397         RING_LOCALS;
398
399         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
400                 return -EFAULT;
401         }
402
403         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
404                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
405                           box.x1, box.y1, box.x2, box.y2);
406                 return -EINVAL;
407         }
408
409         if (IS_I965G(dev)) {
410                 BEGIN_LP_RING(4);
411                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
412                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
413                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
414                 OUT_RING(DR4);
415                 ADVANCE_LP_RING();
416         } else {
417                 BEGIN_LP_RING(6);
418                 OUT_RING(GFX_OP_DRAWRECT_INFO);
419                 OUT_RING(DR1);
420                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
421                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
422                 OUT_RING(DR4);
423                 OUT_RING(0);
424                 ADVANCE_LP_RING();
425         }
426
427         return 0;
428 }
429
430 /* XXX: Emitting the counter should really be moved to part of the IRQ
431  * emit. For now, do it in both places:
432  */
433
434 static void i915_emit_breadcrumb(struct drm_device *dev)
435 {
436         drm_i915_private_t *dev_priv = dev->dev_private;
437         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
438         RING_LOCALS;
439
440         dev_priv->counter++;
441         if (dev_priv->counter > 0x7FFFFFFFUL)
442                 dev_priv->counter = 0;
443         if (master_priv->sarea_priv)
444                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
445
446         BEGIN_LP_RING(4);
447         OUT_RING(MI_STORE_DWORD_INDEX);
448         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
449         OUT_RING(dev_priv->counter);
450         OUT_RING(0);
451         ADVANCE_LP_RING();
452 }
453
454 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
455                                    drm_i915_cmdbuffer_t * cmd)
456 {
457         int nbox = cmd->num_cliprects;
458         int i = 0, count, ret;
459
460         if (cmd->sz & 0x3) {
461                 DRM_ERROR("alignment");
462                 return -EINVAL;
463         }
464
465         i915_kernel_lost_context(dev);
466
467         count = nbox ? nbox : 1;
468
469         for (i = 0; i < count; i++) {
470                 if (i < nbox) {
471                         ret = i915_emit_box(dev, cmd->cliprects, i,
472                                             cmd->DR1, cmd->DR4);
473                         if (ret)
474                                 return ret;
475                 }
476
477                 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
478                 if (ret)
479                         return ret;
480         }
481
482         i915_emit_breadcrumb(dev);
483         return 0;
484 }
485
486 static int i915_dispatch_batchbuffer(struct drm_device * dev,
487                                      drm_i915_batchbuffer_t * batch)
488 {
489         drm_i915_private_t *dev_priv = dev->dev_private;
490         struct drm_clip_rect __user *boxes = batch->cliprects;
491         int nbox = batch->num_cliprects;
492         int i = 0, count;
493         RING_LOCALS;
494
495         if ((batch->start | batch->used) & 0x7) {
496                 DRM_ERROR("alignment");
497                 return -EINVAL;
498         }
499
500         i915_kernel_lost_context(dev);
501
502         count = nbox ? nbox : 1;
503
504         for (i = 0; i < count; i++) {
505                 if (i < nbox) {
506                         int ret = i915_emit_box(dev, boxes, i,
507                                                 batch->DR1, batch->DR4);
508                         if (ret)
509                                 return ret;
510                 }
511
512                 if (!IS_I830(dev) && !IS_845G(dev)) {
513                         BEGIN_LP_RING(2);
514                         if (IS_I965G(dev)) {
515                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
516                                 OUT_RING(batch->start);
517                         } else {
518                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
519                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
520                         }
521                         ADVANCE_LP_RING();
522                 } else {
523                         BEGIN_LP_RING(4);
524                         OUT_RING(MI_BATCH_BUFFER);
525                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
526                         OUT_RING(batch->start + batch->used - 4);
527                         OUT_RING(0);
528                         ADVANCE_LP_RING();
529                 }
530         }
531
532         i915_emit_breadcrumb(dev);
533
534         return 0;
535 }
536
537 static int i915_dispatch_flip(struct drm_device * dev)
538 {
539         drm_i915_private_t *dev_priv = dev->dev_private;
540         struct drm_i915_master_private *master_priv =
541                 dev->primary->master->driver_priv;
542         RING_LOCALS;
543
544         if (!master_priv->sarea_priv)
545                 return -EINVAL;
546
547         DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
548                   __func__,
549                   dev_priv->current_page,
550                   master_priv->sarea_priv->pf_current_page);
551
552         i915_kernel_lost_context(dev);
553
554         BEGIN_LP_RING(2);
555         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
556         OUT_RING(0);
557         ADVANCE_LP_RING();
558
559         BEGIN_LP_RING(6);
560         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
561         OUT_RING(0);
562         if (dev_priv->current_page == 0) {
563                 OUT_RING(dev_priv->back_offset);
564                 dev_priv->current_page = 1;
565         } else {
566                 OUT_RING(dev_priv->front_offset);
567                 dev_priv->current_page = 0;
568         }
569         OUT_RING(0);
570         ADVANCE_LP_RING();
571
572         BEGIN_LP_RING(2);
573         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
574         OUT_RING(0);
575         ADVANCE_LP_RING();
576
577         master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
578
579         BEGIN_LP_RING(4);
580         OUT_RING(MI_STORE_DWORD_INDEX);
581         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
582         OUT_RING(dev_priv->counter);
583         OUT_RING(0);
584         ADVANCE_LP_RING();
585
586         master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
587         return 0;
588 }
589
590 static int i915_quiescent(struct drm_device * dev)
591 {
592         drm_i915_private_t *dev_priv = dev->dev_private;
593
594         i915_kernel_lost_context(dev);
595         return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
596 }
597
598 static int i915_flush_ioctl(struct drm_device *dev, void *data,
599                             struct drm_file *file_priv)
600 {
601         int ret;
602
603         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
604
605         mutex_lock(&dev->struct_mutex);
606         ret = i915_quiescent(dev);
607         mutex_unlock(&dev->struct_mutex);
608
609         return ret;
610 }
611
612 static int i915_batchbuffer(struct drm_device *dev, void *data,
613                             struct drm_file *file_priv)
614 {
615         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
616         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
617         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
618             master_priv->sarea_priv;
619         drm_i915_batchbuffer_t *batch = data;
620         int ret;
621
622         if (!dev_priv->allow_batchbuffer) {
623                 DRM_ERROR("Batchbuffer ioctl disabled\n");
624                 return -EINVAL;
625         }
626
627         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
628                   batch->start, batch->used, batch->num_cliprects);
629
630         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
631
632         if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
633                                                        batch->num_cliprects *
634                                                        sizeof(struct drm_clip_rect)))
635                 return -EFAULT;
636
637         mutex_lock(&dev->struct_mutex);
638         ret = i915_dispatch_batchbuffer(dev, batch);
639         mutex_unlock(&dev->struct_mutex);
640
641         if (sarea_priv)
642                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
643         return ret;
644 }
645
646 static int i915_cmdbuffer(struct drm_device *dev, void *data,
647                           struct drm_file *file_priv)
648 {
649         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
650         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
651         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
652             master_priv->sarea_priv;
653         drm_i915_cmdbuffer_t *cmdbuf = data;
654         int ret;
655
656         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
657                   cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
658
659         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
660
661         if (cmdbuf->num_cliprects &&
662             DRM_VERIFYAREA_READ(cmdbuf->cliprects,
663                                 cmdbuf->num_cliprects *
664                                 sizeof(struct drm_clip_rect))) {
665                 DRM_ERROR("Fault accessing cliprects\n");
666                 return -EFAULT;
667         }
668
669         mutex_lock(&dev->struct_mutex);
670         ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
671         mutex_unlock(&dev->struct_mutex);
672         if (ret) {
673                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
674                 return ret;
675         }
676
677         if (sarea_priv)
678                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
679         return 0;
680 }
681
682 static int i915_flip_bufs(struct drm_device *dev, void *data,
683                           struct drm_file *file_priv)
684 {
685         int ret;
686
687         DRM_DEBUG("%s\n", __func__);
688
689         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
690
691         mutex_lock(&dev->struct_mutex);
692         ret = i915_dispatch_flip(dev);
693         mutex_unlock(&dev->struct_mutex);
694
695         return ret;
696 }
697
698 static int i915_getparam(struct drm_device *dev, void *data,
699                          struct drm_file *file_priv)
700 {
701         drm_i915_private_t *dev_priv = dev->dev_private;
702         drm_i915_getparam_t *param = data;
703         int value;
704
705         if (!dev_priv) {
706                 DRM_ERROR("called with no initialization\n");
707                 return -EINVAL;
708         }
709
710         switch (param->param) {
711         case I915_PARAM_IRQ_ACTIVE:
712                 value = dev->pdev->irq ? 1 : 0;
713                 break;
714         case I915_PARAM_ALLOW_BATCHBUFFER:
715                 value = dev_priv->allow_batchbuffer ? 1 : 0;
716                 break;
717         case I915_PARAM_LAST_DISPATCH:
718                 value = READ_BREADCRUMB(dev_priv);
719                 break;
720         case I915_PARAM_CHIPSET_ID:
721                 value = dev->pci_device;
722                 break;
723         case I915_PARAM_HAS_GEM:
724                 value = dev_priv->has_gem;
725                 break;
726         default:
727                 DRM_ERROR("Unknown parameter %d\n", param->param);
728                 return -EINVAL;
729         }
730
731         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
732                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
733                 return -EFAULT;
734         }
735
736         return 0;
737 }
738
739 static int i915_setparam(struct drm_device *dev, void *data,
740                          struct drm_file *file_priv)
741 {
742         drm_i915_private_t *dev_priv = dev->dev_private;
743         drm_i915_setparam_t *param = data;
744
745         if (!dev_priv) {
746                 DRM_ERROR("called with no initialization\n");
747                 return -EINVAL;
748         }
749
750         switch (param->param) {
751         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
752                 break;
753         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
754                 dev_priv->tex_lru_log_granularity = param->value;
755                 break;
756         case I915_SETPARAM_ALLOW_BATCHBUFFER:
757                 dev_priv->allow_batchbuffer = param->value;
758                 break;
759         default:
760                 DRM_ERROR("unknown parameter %d\n", param->param);
761                 return -EINVAL;
762         }
763
764         return 0;
765 }
766
767 static int i915_set_status_page(struct drm_device *dev, void *data,
768                                 struct drm_file *file_priv)
769 {
770         drm_i915_private_t *dev_priv = dev->dev_private;
771         drm_i915_hws_addr_t *hws = data;
772
773         if (!I915_NEED_GFX_HWS(dev))
774                 return -EINVAL;
775
776         if (!dev_priv) {
777                 DRM_ERROR("called with no initialization\n");
778                 return -EINVAL;
779         }
780
781         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
782                 WARN(1, "tried to set status page when mode setting active\n");
783                 return 0;
784         }
785
786         printk(KERN_DEBUG "set status page addr 0x%08x\n", (u32)hws->addr);
787
788         dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
789
790         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
791         dev_priv->hws_map.size = 4*1024;
792         dev_priv->hws_map.type = 0;
793         dev_priv->hws_map.flags = 0;
794         dev_priv->hws_map.mtrr = 0;
795
796         drm_core_ioremap(&dev_priv->hws_map, dev);
797         if (dev_priv->hws_map.handle == NULL) {
798                 i915_dma_cleanup(dev);
799                 dev_priv->status_gfx_addr = 0;
800                 DRM_ERROR("can not ioremap virtual address for"
801                                 " G33 hw status page\n");
802                 return -ENOMEM;
803         }
804         dev_priv->hw_status_page = dev_priv->hws_map.handle;
805
806         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
807         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
808         DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
809                         dev_priv->status_gfx_addr);
810         DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
811         return 0;
812 }
813
814 /**
815  * i915_probe_agp - get AGP bootup configuration
816  * @pdev: PCI device
817  * @aperture_size: returns AGP aperture configured size
818  * @preallocated_size: returns size of BIOS preallocated AGP space
819  *
820  * Since Intel integrated graphics are UMA, the BIOS has to set aside
821  * some RAM for the framebuffer at early boot.  This code figures out
822  * how much was set aside so we can use it for our own purposes.
823  */
824 int i915_probe_agp(struct drm_device *dev, unsigned long *aperture_size,
825                    unsigned long *preallocated_size)
826 {
827         struct pci_dev *bridge_dev;
828         u16 tmp = 0;
829         unsigned long overhead;
830
831         bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
832         if (!bridge_dev) {
833                 DRM_ERROR("bridge device not found\n");
834                 return -1;
835         }
836
837         /* Get the fb aperture size and "stolen" memory amount. */
838         pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
839         pci_dev_put(bridge_dev);
840
841         *aperture_size = 1024 * 1024;
842         *preallocated_size = 1024 * 1024;
843
844         switch (dev->pdev->device) {
845         case PCI_DEVICE_ID_INTEL_82830_CGC:
846         case PCI_DEVICE_ID_INTEL_82845G_IG:
847         case PCI_DEVICE_ID_INTEL_82855GM_IG:
848         case PCI_DEVICE_ID_INTEL_82865_IG:
849                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
850                         *aperture_size *= 64;
851                 else
852                         *aperture_size *= 128;
853                 break;
854         default:
855                 /* 9xx supports large sizes, just look at the length */
856                 *aperture_size = pci_resource_len(dev->pdev, 2);
857                 break;
858         }
859
860         /*
861          * Some of the preallocated space is taken by the GTT
862          * and popup.  GTT is 1K per MB of aperture size, and popup is 4K.
863          */
864         if (IS_G4X(dev))
865                 overhead = 4096;
866         else
867                 overhead = (*aperture_size / 1024) + 4096;
868
869         switch (tmp & INTEL_855_GMCH_GMS_MASK) {
870         case INTEL_855_GMCH_GMS_STOLEN_1M:
871                 break; /* 1M already */
872         case INTEL_855_GMCH_GMS_STOLEN_4M:
873                 *preallocated_size *= 4;
874                 break;
875         case INTEL_855_GMCH_GMS_STOLEN_8M:
876                 *preallocated_size *= 8;
877                 break;
878         case INTEL_855_GMCH_GMS_STOLEN_16M:
879                 *preallocated_size *= 16;
880                 break;
881         case INTEL_855_GMCH_GMS_STOLEN_32M:
882                 *preallocated_size *= 32;
883                 break;
884         case INTEL_915G_GMCH_GMS_STOLEN_48M:
885                 *preallocated_size *= 48;
886                 break;
887         case INTEL_915G_GMCH_GMS_STOLEN_64M:
888                 *preallocated_size *= 64;
889                 break;
890         case INTEL_855_GMCH_GMS_DISABLED:
891                 DRM_ERROR("video memory is disabled\n");
892                 return -1;
893         default:
894                 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
895                         tmp & INTEL_855_GMCH_GMS_MASK);
896                 return -1;
897         }
898         *preallocated_size -= overhead;
899
900         return 0;
901 }
902
903 static int i915_load_modeset_init(struct drm_device *dev)
904 {
905         struct drm_i915_private *dev_priv = dev->dev_private;
906         unsigned long agp_size, prealloc_size;
907         int fb_bar = IS_I9XX(dev) ? 2 : 0;
908         int ret = 0;
909
910         dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) &
911                 0xff000000;
912
913         DRM_DEBUG("*** fb base 0x%08lx\n", dev->mode_config.fb_base);
914
915         if (IS_MOBILE(dev) || (IS_I9XX(dev) && !IS_I965G(dev) && !IS_G33(dev)))
916                 dev_priv->cursor_needs_physical = true;
917         else
918                 dev_priv->cursor_needs_physical = false;
919
920         i915_probe_agp(dev, &agp_size, &prealloc_size);
921
922         /* Basic memrange allocator for stolen space (aka vram) */
923         drm_mm_init(&dev_priv->vram, 0, prealloc_size);
924
925         /* Let GEM Manage from end of prealloc space to end of aperture */
926         i915_gem_do_init(dev, prealloc_size, agp_size);
927
928         ret = i915_gem_init_ringbuffer(dev);
929         if (ret)
930                 goto out;
931
932         dev_priv->mm.gtt_mapping =
933                 io_mapping_create_wc(dev->agp->base,
934                                      dev->agp->agp_info.aper_size * 1024*1024);
935
936         /* Allow hardware batchbuffers unless told otherwise.
937          */
938         dev_priv->allow_batchbuffer = 1;
939
940         ret = intel_init_bios(dev);
941         if (ret)
942                 DRM_INFO("failed to find VBIOS tables\n");
943
944         ret = drm_irq_install(dev);
945         if (ret)
946                 goto destroy_ringbuffer;
947
948         /* FIXME: re-add hotplug support */
949 #if 0
950         ret = drm_hotplug_init(dev);
951         if (ret)
952                 goto destroy_ringbuffer;
953 #endif
954
955         /* Always safe in the mode setting case. */
956         /* FIXME: do pre/post-mode set stuff in core KMS code */
957         dev->vblank_disable_allowed = 1;
958
959         /*
960          * Initialize the hardware status page IRQ location.
961          */
962
963         I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
964
965         intel_modeset_init(dev);
966
967         drm_helper_initial_config(dev, false);
968
969         dev->devname = kstrdup(DRIVER_NAME, GFP_KERNEL);
970         if (!dev->devname) {
971                 ret = -ENOMEM;
972                 goto modeset_cleanup;
973         }
974
975         return 0;
976
977 modeset_cleanup:
978         intel_modeset_cleanup(dev);
979 destroy_ringbuffer:
980         i915_gem_cleanup_ringbuffer(dev);
981 out:
982         return ret;
983 }
984
985 int i915_master_create(struct drm_device *dev, struct drm_master *master)
986 {
987         struct drm_i915_master_private *master_priv;
988
989         master_priv = drm_calloc(1, sizeof(*master_priv), DRM_MEM_DRIVER);
990         if (!master_priv)
991                 return -ENOMEM;
992
993         master->driver_priv = master_priv;
994         return 0;
995 }
996
997 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
998 {
999         struct drm_i915_master_private *master_priv = master->driver_priv;
1000
1001         if (!master_priv)
1002                 return;
1003
1004         drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
1005
1006         master->driver_priv = NULL;
1007 }
1008
1009
1010 int i915_driver_firstopen(struct drm_device *dev)
1011 {
1012         if (drm_core_check_feature(dev, DRIVER_MODESET))
1013                 return 0;
1014         return 0;
1015 }
1016
1017 /**
1018  * i915_driver_load - setup chip and create an initial config
1019  * @dev: DRM device
1020  * @flags: startup flags
1021  *
1022  * The driver load routine has to do several things:
1023  *   - drive output discovery via intel_modeset_init()
1024  *   - initialize the memory manager
1025  *   - allocate initial config memory
1026  *   - setup the DRM framebuffer with the allocated memory
1027  */
1028 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1029 {
1030         struct drm_i915_private *dev_priv = dev->dev_private;
1031         unsigned long base, size;
1032         int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
1033
1034         /* i915 has 4 more counters */
1035         dev->counters += 4;
1036         dev->types[6] = _DRM_STAT_IRQ;
1037         dev->types[7] = _DRM_STAT_PRIMARY;
1038         dev->types[8] = _DRM_STAT_SECONDARY;
1039         dev->types[9] = _DRM_STAT_DMA;
1040
1041         dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
1042         if (dev_priv == NULL)
1043                 return -ENOMEM;
1044
1045         memset(dev_priv, 0, sizeof(drm_i915_private_t));
1046
1047         dev->dev_private = (void *)dev_priv;
1048         dev_priv->dev = dev;
1049
1050         /* Add register map (needed for suspend/resume) */
1051         base = drm_get_resource_start(dev, mmio_bar);
1052         size = drm_get_resource_len(dev, mmio_bar);
1053
1054         dev_priv->regs = ioremap(base, size);
1055         if (!dev_priv->regs) {
1056                 DRM_ERROR("failed to map registers\n");
1057                 ret = -EIO;
1058                 goto free_priv;
1059         }
1060
1061 #ifdef CONFIG_HIGHMEM64G
1062         /* don't enable GEM on PAE - needs agp + set_memory_* interface fixes */
1063         dev_priv->has_gem = 0;
1064 #else
1065         /* enable GEM by default */
1066         dev_priv->has_gem = 1;
1067 #endif
1068
1069         i915_gem_load(dev);
1070
1071         /* Init HWS */
1072         if (!I915_NEED_GFX_HWS(dev)) {
1073                 ret = i915_init_phys_hws(dev);
1074                 if (ret != 0)
1075                         goto out_rmmap;
1076         }
1077
1078         /* On the 945G/GM, the chipset reports the MSI capability on the
1079          * integrated graphics even though the support isn't actually there
1080          * according to the published specs.  It doesn't appear to function
1081          * correctly in testing on 945G.
1082          * This may be a side effect of MSI having been made available for PEG
1083          * and the registers being closely associated.
1084          *
1085          * According to chipset errata, on the 965GM, MSI interrupts may
1086          * be lost or delayed, but we use them anyways to avoid
1087          * stuck interrupts on some machines.
1088          */
1089         if (!IS_I945G(dev) && !IS_I945GM(dev))
1090                 pci_enable_msi(dev->pdev);
1091
1092         intel_opregion_init(dev);
1093
1094         spin_lock_init(&dev_priv->user_irq_lock);
1095         dev_priv->user_irq_refcount = 0;
1096
1097         ret = drm_vblank_init(dev, I915_NUM_PIPE);
1098
1099         if (ret) {
1100                 (void) i915_driver_unload(dev);
1101                 return ret;
1102         }
1103
1104         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1105                 ret = i915_load_modeset_init(dev);
1106                 if (ret < 0) {
1107                         DRM_ERROR("failed to init modeset\n");
1108                         goto out_rmmap;
1109                 }
1110         }
1111
1112         return 0;
1113
1114 out_rmmap:
1115         iounmap(dev_priv->regs);
1116 free_priv:
1117         drm_free(dev_priv, sizeof(struct drm_i915_private), DRM_MEM_DRIVER);
1118         return ret;
1119 }
1120
1121 int i915_driver_unload(struct drm_device *dev)
1122 {
1123         struct drm_i915_private *dev_priv = dev->dev_private;
1124
1125         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1126                 io_mapping_free(dev_priv->mm.gtt_mapping);
1127                 drm_irq_uninstall(dev);
1128         }
1129
1130         if (dev->pdev->msi_enabled)
1131                 pci_disable_msi(dev->pdev);
1132
1133         if (dev_priv->regs != NULL)
1134                 iounmap(dev_priv->regs);
1135
1136         intel_opregion_free(dev);
1137
1138         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1139                 intel_modeset_cleanup(dev);
1140
1141                 mutex_lock(&dev->struct_mutex);
1142                 i915_gem_cleanup_ringbuffer(dev);
1143                 mutex_unlock(&dev->struct_mutex);
1144                 drm_mm_takedown(&dev_priv->vram);
1145                 i915_gem_lastclose(dev);
1146         }
1147
1148         drm_free(dev->dev_private, sizeof(drm_i915_private_t),
1149                  DRM_MEM_DRIVER);
1150
1151         return 0;
1152 }
1153
1154 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1155 {
1156         struct drm_i915_file_private *i915_file_priv;
1157
1158         DRM_DEBUG("\n");
1159         i915_file_priv = (struct drm_i915_file_private *)
1160             drm_alloc(sizeof(*i915_file_priv), DRM_MEM_FILES);
1161
1162         if (!i915_file_priv)
1163                 return -ENOMEM;
1164
1165         file_priv->driver_priv = i915_file_priv;
1166
1167         i915_file_priv->mm.last_gem_seqno = 0;
1168         i915_file_priv->mm.last_gem_throttle_seqno = 0;
1169
1170         return 0;
1171 }
1172
1173 /**
1174  * i915_driver_lastclose - clean up after all DRM clients have exited
1175  * @dev: DRM device
1176  *
1177  * Take care of cleaning up after all DRM clients have exited.  In the
1178  * mode setting case, we want to restore the kernel's initial mode (just
1179  * in case the last client left us in a bad state).
1180  *
1181  * Additionally, in the non-mode setting case, we'll tear down the AGP
1182  * and DMA structures, since the kernel won't be using them, and clea
1183  * up any GEM state.
1184  */
1185 void i915_driver_lastclose(struct drm_device * dev)
1186 {
1187         drm_i915_private_t *dev_priv = dev->dev_private;
1188
1189         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1190                 intelfb_restore();
1191                 return;
1192         }
1193
1194         i915_gem_lastclose(dev);
1195
1196         if (dev_priv->agp_heap)
1197                 i915_mem_takedown(&(dev_priv->agp_heap));
1198
1199         i915_dma_cleanup(dev);
1200 }
1201
1202 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1203 {
1204         drm_i915_private_t *dev_priv = dev->dev_private;
1205         if (!drm_core_check_feature(dev, DRIVER_MODESET))
1206                 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
1207 }
1208
1209 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1210 {
1211         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1212
1213         drm_free(i915_file_priv, sizeof(*i915_file_priv), DRM_MEM_FILES);
1214 }
1215
1216 struct drm_ioctl_desc i915_ioctls[] = {
1217         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1218         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1219         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1220         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1221         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1222         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1223         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1224         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1225         DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
1226         DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
1227         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1228         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1229         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1230         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1231         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
1232         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1233         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1234         DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1235         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
1236         DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1237         DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1238         DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
1239         DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
1240         DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1241         DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1242         DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
1243         DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0),
1244         DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0),
1245         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
1246         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, 0),
1247         DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0),
1248         DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),
1249         DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
1250         DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
1251         DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0),
1252 };
1253
1254 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1255
1256 /**
1257  * Determine if the device really is AGP or not.
1258  *
1259  * All Intel graphics chipsets are treated as AGP, even if they are really
1260  * PCI-e.
1261  *
1262  * \param dev   The device to be tested.
1263  *
1264  * \returns
1265  * A value of 1 is always retured to indictate every i9x5 is AGP.
1266  */
1267 int i915_driver_device_is_agp(struct drm_device * dev)
1268 {
1269         return 1;
1270 }