0743fe90f1e3f4dc9213429e941c7331ad528022
[linux-2.6.git] / drivers / gpu / drm / i810 / i810_drv.h
1 /* i810_drv.h -- Private header for the Matrox g200/g400 driver -*- linux-c -*-
2  * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
3  *
4  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6  * All rights reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the "Software"),
10  * to deal in the Software without restriction, including without limitation
11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12  * and/or sell copies of the Software, and to permit persons to whom the
13  * Software is furnished to do so, subject to the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the next
16  * paragraph) shall be included in all copies or substantial portions of the
17  * Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25  * DEALINGS IN THE SOFTWARE.
26  *
27  * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
28  *          Jeff Hartmann <jhartmann@valinux.com>
29  *
30  */
31
32 #ifndef _I810_DRV_H_
33 #define _I810_DRV_H_
34
35 /* General customization:
36  */
37
38 #define DRIVER_AUTHOR           "VA Linux Systems Inc."
39
40 #define DRIVER_NAME             "i810"
41 #define DRIVER_DESC             "Intel i810"
42 #define DRIVER_DATE             "20030605"
43
44 /* Interface history
45  *
46  * 1.1   - XFree86 4.1
47  * 1.2   - XvMC interfaces
48  *       - XFree86 4.2
49  * 1.2.1 - Disable copying code (leave stub ioctls for backwards compatibility)
50  *       - Remove requirement for interrupt (leave stubs again)
51  * 1.3   - Add page flipping.
52  * 1.4   - fix DRM interface
53  */
54 #define DRIVER_MAJOR            1
55 #define DRIVER_MINOR            4
56 #define DRIVER_PATCHLEVEL       0
57
58 typedef struct drm_i810_buf_priv {
59         u32 *in_use;
60         int my_use_idx;
61         int currently_mapped;
62         void *virtual;
63         void *kernel_virtual;
64         drm_local_map_t map;
65 } drm_i810_buf_priv_t;
66
67 typedef struct _drm_i810_ring_buffer {
68         int tail_mask;
69         unsigned long Start;
70         unsigned long End;
71         unsigned long Size;
72         u8 *virtual_start;
73         int head;
74         int tail;
75         int space;
76         drm_local_map_t map;
77 } drm_i810_ring_buffer_t;
78
79 typedef struct drm_i810_private {
80         struct drm_local_map *sarea_map;
81         struct drm_local_map *mmio_map;
82
83         drm_i810_sarea_t *sarea_priv;
84         drm_i810_ring_buffer_t ring;
85
86         void *hw_status_page;
87         unsigned long counter;
88
89         dma_addr_t dma_status_page;
90
91         struct drm_buf *mmap_buffer;
92
93         u32 front_di1, back_di1, zi1;
94
95         int back_offset;
96         int depth_offset;
97         int overlay_offset;
98         int overlay_physical;
99         int w, h;
100         int pitch;
101         int back_pitch;
102         int depth_pitch;
103
104         int do_boxes;
105         int dma_used;
106
107         int current_page;
108         int page_flipping;
109
110         wait_queue_head_t irq_queue;
111         atomic_t irq_received;
112         atomic_t irq_emitted;
113
114         int front_offset;
115 } drm_i810_private_t;
116
117                                 /* i810_dma.c */
118 extern int i810_driver_dma_quiescent(struct drm_device *dev);
119 extern void i810_driver_reclaim_buffers_locked(struct drm_device *dev,
120                                                struct drm_file *file_priv);
121 extern int i810_driver_load(struct drm_device *, unsigned long flags);
122 extern void i810_driver_lastclose(struct drm_device *dev);
123 extern void i810_driver_preclose(struct drm_device *dev,
124                                  struct drm_file *file_priv);
125 extern void i810_driver_reclaim_buffers_locked(struct drm_device *dev,
126                                                struct drm_file *file_priv);
127 extern int i810_driver_device_is_agp(struct drm_device *dev);
128
129 extern struct drm_ioctl_desc i810_ioctls[];
130 extern int i810_max_ioctl;
131
132 #define I810_BASE(reg)          ((unsigned long) \
133                                 dev_priv->mmio_map->handle)
134 #define I810_ADDR(reg)          (I810_BASE(reg) + reg)
135 #define I810_DEREF(reg)         (*(__volatile__ int *)I810_ADDR(reg))
136 #define I810_READ(reg)          I810_DEREF(reg)
137 #define I810_WRITE(reg, val)    do { I810_DEREF(reg) = val; } while (0)
138 #define I810_DEREF16(reg)       (*(__volatile__ u16 *)I810_ADDR(reg))
139 #define I810_READ16(reg)        I810_DEREF16(reg)
140 #define I810_WRITE16(reg, val)  do { I810_DEREF16(reg) = val; } while (0)
141
142 #define I810_VERBOSE 0
143 #define RING_LOCALS     unsigned int outring, ringmask; \
144                         volatile char *virt;
145
146 #define BEGIN_LP_RING(n) do {                                   \
147         if (I810_VERBOSE)                                       \
148                 DRM_DEBUG("BEGIN_LP_RING(%d)\n", n);            \
149         if (dev_priv->ring.space < n*4)                         \
150                 i810_wait_ring(dev, n*4);                       \
151         dev_priv->ring.space -= n*4;                            \
152         outring = dev_priv->ring.tail;                          \
153         ringmask = dev_priv->ring.tail_mask;                    \
154         virt = dev_priv->ring.virtual_start;                    \
155 } while (0)
156
157 #define ADVANCE_LP_RING() do {                                  \
158         if (I810_VERBOSE)                                       \
159                 DRM_DEBUG("ADVANCE_LP_RING\n");                 \
160         dev_priv->ring.tail = outring;                          \
161         I810_WRITE(LP_RING + RING_TAIL, outring);               \
162 } while (0)
163
164 #define OUT_RING(n) do {                                        \
165         if (I810_VERBOSE)                                       \
166                 DRM_DEBUG("   OUT_RING %x\n", (int)(n));        \
167         *(volatile unsigned int *)(virt + outring) = n;         \
168         outring += 4;                                           \
169         outring &= ringmask;                                    \
170 } while (0)
171
172 #define GFX_OP_USER_INTERRUPT           ((0<<29)|(2<<23))
173 #define GFX_OP_BREAKPOINT_INTERRUPT     ((0<<29)|(1<<23))
174 #define CMD_REPORT_HEAD                 (7<<23)
175 #define CMD_STORE_DWORD_IDX             ((0x21<<23) | 0x1)
176 #define CMD_OP_BATCH_BUFFER  ((0x0<<29)|(0x30<<23)|0x1)
177
178 #define INST_PARSER_CLIENT   0x00000000
179 #define INST_OP_FLUSH        0x02000000
180 #define INST_FLUSH_MAP_CACHE 0x00000001
181
182 #define BB1_START_ADDR_MASK   (~0x7)
183 #define BB1_PROTECTED         (1<<0)
184 #define BB1_UNPROTECTED       (0<<0)
185 #define BB2_END_ADDR_MASK     (~0x7)
186
187 #define I810REG_HWSTAM          0x02098
188 #define I810REG_INT_IDENTITY_R  0x020a4
189 #define I810REG_INT_MASK_R      0x020a8
190 #define I810REG_INT_ENABLE_R    0x020a0
191
192 #define LP_RING                 0x2030
193 #define HP_RING                 0x2040
194 #define RING_TAIL               0x00
195 #define TAIL_ADDR               0x000FFFF8
196 #define RING_HEAD               0x04
197 #define HEAD_WRAP_COUNT         0xFFE00000
198 #define HEAD_WRAP_ONE           0x00200000
199 #define HEAD_ADDR               0x001FFFFC
200 #define RING_START              0x08
201 #define START_ADDR              0x00FFFFF8
202 #define RING_LEN                0x0C
203 #define RING_NR_PAGES           0x000FF000
204 #define RING_REPORT_MASK        0x00000006
205 #define RING_REPORT_64K         0x00000002
206 #define RING_REPORT_128K        0x00000004
207 #define RING_NO_REPORT          0x00000000
208 #define RING_VALID_MASK         0x00000001
209 #define RING_VALID              0x00000001
210 #define RING_INVALID            0x00000000
211
212 #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
213 #define SC_UPDATE_SCISSOR       (0x1<<1)
214 #define SC_ENABLE_MASK          (0x1<<0)
215 #define SC_ENABLE               (0x1<<0)
216
217 #define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
218 #define SCI_YMIN_MASK      (0xffff<<16)
219 #define SCI_XMIN_MASK      (0xffff<<0)
220 #define SCI_YMAX_MASK      (0xffff<<16)
221 #define SCI_XMAX_MASK      (0xffff<<0)
222
223 #define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
224 #define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
225 #define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x2)
226 #define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
227 #define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
228 #define GFX_OP_PRIMITIVE         ((0x3<<29)|(0x1f<<24))
229
230 #define CMD_OP_Z_BUFFER_INFO     ((0x0<<29)|(0x16<<23))
231 #define CMD_OP_DESTBUFFER_INFO   ((0x0<<29)|(0x15<<23))
232 #define CMD_OP_FRONTBUFFER_INFO  ((0x0<<29)|(0x14<<23))
233 #define CMD_OP_WAIT_FOR_EVENT    ((0x0<<29)|(0x03<<23))
234
235 #define BR00_BITBLT_CLIENT   0x40000000
236 #define BR00_OP_COLOR_BLT    0x10000000
237 #define BR00_OP_SRC_COPY_BLT 0x10C00000
238 #define BR13_SOLID_PATTERN   0x80000000
239
240 #define WAIT_FOR_PLANE_A_SCANLINES (1<<1)
241 #define WAIT_FOR_PLANE_A_FLIP      (1<<2)
242 #define WAIT_FOR_VBLANK (1<<3)
243
244 #endif