firewire: core: do not DMA-map stack addresses
[linux-2.6.git] / drivers / firewire / ohci.c
1 /*
2  * Driver for OHCI 1394 controllers
3  *
4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software Foundation,
18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/firewire.h>
26 #include <linux/firewire-constants.h>
27 #include <linux/gfp.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/io.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
33 #include <linux/mm.h>
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/pci.h>
37 #include <linux/spinlock.h>
38 #include <linux/string.h>
39
40 #include <asm/atomic.h>
41 #include <asm/byteorder.h>
42 #include <asm/page.h>
43 #include <asm/system.h>
44
45 #ifdef CONFIG_PPC_PMAC
46 #include <asm/pmac_feature.h>
47 #endif
48
49 #include "core.h"
50 #include "ohci.h"
51
52 #define DESCRIPTOR_OUTPUT_MORE          0
53 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
54 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
55 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
56 #define DESCRIPTOR_STATUS               (1 << 11)
57 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
58 #define DESCRIPTOR_PING                 (1 << 7)
59 #define DESCRIPTOR_YY                   (1 << 6)
60 #define DESCRIPTOR_NO_IRQ               (0 << 4)
61 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
62 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
63 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
64 #define DESCRIPTOR_WAIT                 (3 << 0)
65
66 struct descriptor {
67         __le16 req_count;
68         __le16 control;
69         __le32 data_address;
70         __le32 branch_address;
71         __le16 res_count;
72         __le16 transfer_status;
73 } __attribute__((aligned(16)));
74
75 struct db_descriptor {
76         __le16 first_size;
77         __le16 control;
78         __le16 second_req_count;
79         __le16 first_req_count;
80         __le32 branch_address;
81         __le16 second_res_count;
82         __le16 first_res_count;
83         __le32 reserved0;
84         __le32 first_buffer;
85         __le32 second_buffer;
86         __le32 reserved1;
87 } __attribute__((aligned(16)));
88
89 #define CONTROL_SET(regs)       (regs)
90 #define CONTROL_CLEAR(regs)     ((regs) + 4)
91 #define COMMAND_PTR(regs)       ((regs) + 12)
92 #define CONTEXT_MATCH(regs)     ((regs) + 16)
93
94 struct ar_buffer {
95         struct descriptor descriptor;
96         struct ar_buffer *next;
97         __le32 data[0];
98 };
99
100 struct ar_context {
101         struct fw_ohci *ohci;
102         struct ar_buffer *current_buffer;
103         struct ar_buffer *last_buffer;
104         void *pointer;
105         u32 regs;
106         struct tasklet_struct tasklet;
107 };
108
109 struct context;
110
111 typedef int (*descriptor_callback_t)(struct context *ctx,
112                                      struct descriptor *d,
113                                      struct descriptor *last);
114
115 /*
116  * A buffer that contains a block of DMA-able coherent memory used for
117  * storing a portion of a DMA descriptor program.
118  */
119 struct descriptor_buffer {
120         struct list_head list;
121         dma_addr_t buffer_bus;
122         size_t buffer_size;
123         size_t used;
124         struct descriptor buffer[0];
125 };
126
127 struct context {
128         struct fw_ohci *ohci;
129         u32 regs;
130         int total_allocation;
131
132         /*
133          * List of page-sized buffers for storing DMA descriptors.
134          * Head of list contains buffers in use and tail of list contains
135          * free buffers.
136          */
137         struct list_head buffer_list;
138
139         /*
140          * Pointer to a buffer inside buffer_list that contains the tail
141          * end of the current DMA program.
142          */
143         struct descriptor_buffer *buffer_tail;
144
145         /*
146          * The descriptor containing the branch address of the first
147          * descriptor that has not yet been filled by the device.
148          */
149         struct descriptor *last;
150
151         /*
152          * The last descriptor in the DMA program.  It contains the branch
153          * address that must be updated upon appending a new descriptor.
154          */
155         struct descriptor *prev;
156
157         descriptor_callback_t callback;
158
159         struct tasklet_struct tasklet;
160 };
161
162 #define IT_HEADER_SY(v)          ((v) <<  0)
163 #define IT_HEADER_TCODE(v)       ((v) <<  4)
164 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
165 #define IT_HEADER_TAG(v)         ((v) << 14)
166 #define IT_HEADER_SPEED(v)       ((v) << 16)
167 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
168
169 struct iso_context {
170         struct fw_iso_context base;
171         struct context context;
172         int excess_bytes;
173         void *header;
174         size_t header_length;
175 };
176
177 #define CONFIG_ROM_SIZE 1024
178
179 struct fw_ohci {
180         struct fw_card card;
181
182         __iomem char *registers;
183         dma_addr_t self_id_bus;
184         __le32 *self_id_cpu;
185         struct tasklet_struct bus_reset_tasklet;
186         int node_id;
187         int generation;
188         int request_generation; /* for timestamping incoming requests */
189         atomic_t bus_seconds;
190
191         bool use_dualbuffer;
192         bool old_uninorth;
193         bool bus_reset_packet_quirk;
194
195         /*
196          * Spinlock for accessing fw_ohci data.  Never call out of
197          * this driver with this lock held.
198          */
199         spinlock_t lock;
200         u32 self_id_buffer[512];
201
202         /* Config rom buffers */
203         __be32 *config_rom;
204         dma_addr_t config_rom_bus;
205         __be32 *next_config_rom;
206         dma_addr_t next_config_rom_bus;
207         u32 next_header;
208
209         struct ar_context ar_request_ctx;
210         struct ar_context ar_response_ctx;
211         struct context at_request_ctx;
212         struct context at_response_ctx;
213
214         u32 it_context_mask;
215         struct iso_context *it_context_list;
216         u64 ir_context_channels;
217         u32 ir_context_mask;
218         struct iso_context *ir_context_list;
219 };
220
221 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
222 {
223         return container_of(card, struct fw_ohci, card);
224 }
225
226 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
227 #define IR_CONTEXT_BUFFER_FILL          0x80000000
228 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
229 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
230 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
231 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
232
233 #define CONTEXT_RUN     0x8000
234 #define CONTEXT_WAKE    0x1000
235 #define CONTEXT_DEAD    0x0800
236 #define CONTEXT_ACTIVE  0x0400
237
238 #define OHCI1394_MAX_AT_REQ_RETRIES     0xf
239 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
240 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
241
242 #define OHCI1394_REGISTER_SIZE          0x800
243 #define OHCI_LOOP_COUNT                 500
244 #define OHCI1394_PCI_HCI_Control        0x40
245 #define SELF_ID_BUF_SIZE                0x800
246 #define OHCI_TCODE_PHY_PACKET           0x0e
247 #define OHCI_VERSION_1_1                0x010010
248
249 static char ohci_driver_name[] = KBUILD_MODNAME;
250
251 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
252
253 #define OHCI_PARAM_DEBUG_AT_AR          1
254 #define OHCI_PARAM_DEBUG_SELFIDS        2
255 #define OHCI_PARAM_DEBUG_IRQS           4
256 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
257
258 static int param_debug;
259 module_param_named(debug, param_debug, int, 0644);
260 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
261         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
262         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
263         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
264         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
265         ", or a combination, or all = -1)");
266
267 static void log_irqs(u32 evt)
268 {
269         if (likely(!(param_debug &
270                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
271                 return;
272
273         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
274             !(evt & OHCI1394_busReset))
275                 return;
276
277         fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
278             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
279             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
280             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
281             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
282             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
283             evt & OHCI1394_isochRx              ? " IR"                 : "",
284             evt & OHCI1394_isochTx              ? " IT"                 : "",
285             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
286             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
287             evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
288             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
289             evt & OHCI1394_busReset             ? " busReset"           : "",
290             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
291                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
292                     OHCI1394_respTxComplete | OHCI1394_isochRx |
293                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
294                     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
295                     OHCI1394_regAccessFail | OHCI1394_busReset)
296                                                 ? " ?"                  : "");
297 }
298
299 static const char *speed[] = {
300         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
301 };
302 static const char *power[] = {
303         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
304         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
305 };
306 static const char port[] = { '.', '-', 'p', 'c', };
307
308 static char _p(u32 *s, int shift)
309 {
310         return port[*s >> shift & 3];
311 }
312
313 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
314 {
315         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
316                 return;
317
318         fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
319                   self_id_count, generation, node_id);
320
321         for (; self_id_count--; ++s)
322                 if ((*s & 1 << 23) == 0)
323                         fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
324                             "%s gc=%d %s %s%s%s\n",
325                             *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
326                             speed[*s >> 14 & 3], *s >> 16 & 63,
327                             power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
328                             *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
329                 else
330                         fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
331                             *s, *s >> 24 & 63,
332                             _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
333                             _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
334 }
335
336 static const char *evts[] = {
337         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
338         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
339         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
340         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
341         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
342         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
343         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
344         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
345         [0x10] = "-reserved-",          [0x11] = "ack_complete",
346         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
347         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
348         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
349         [0x18] = "-reserved-",          [0x19] = "-reserved-",
350         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
351         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
352         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
353         [0x20] = "pending/cancelled",
354 };
355 static const char *tcodes[] = {
356         [0x0] = "QW req",               [0x1] = "BW req",
357         [0x2] = "W resp",               [0x3] = "-reserved-",
358         [0x4] = "QR req",               [0x5] = "BR req",
359         [0x6] = "QR resp",              [0x7] = "BR resp",
360         [0x8] = "cycle start",          [0x9] = "Lk req",
361         [0xa] = "async stream packet",  [0xb] = "Lk resp",
362         [0xc] = "-reserved-",           [0xd] = "-reserved-",
363         [0xe] = "link internal",        [0xf] = "-reserved-",
364 };
365 static const char *phys[] = {
366         [0x0] = "phy config packet",    [0x1] = "link-on packet",
367         [0x2] = "self-id packet",       [0x3] = "-reserved-",
368 };
369
370 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
371 {
372         int tcode = header[0] >> 4 & 0xf;
373         char specific[12];
374
375         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
376                 return;
377
378         if (unlikely(evt >= ARRAY_SIZE(evts)))
379                         evt = 0x1f;
380
381         if (evt == OHCI1394_evt_bus_reset) {
382                 fw_notify("A%c evt_bus_reset, generation %d\n",
383                     dir, (header[2] >> 16) & 0xff);
384                 return;
385         }
386
387         if (header[0] == ~header[1]) {
388                 fw_notify("A%c %s, %s, %08x\n",
389                     dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
390                 return;
391         }
392
393         switch (tcode) {
394         case 0x0: case 0x6: case 0x8:
395                 snprintf(specific, sizeof(specific), " = %08x",
396                          be32_to_cpu((__force __be32)header[3]));
397                 break;
398         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
399                 snprintf(specific, sizeof(specific), " %x,%x",
400                          header[3] >> 16, header[3] & 0xffff);
401                 break;
402         default:
403                 specific[0] = '\0';
404         }
405
406         switch (tcode) {
407         case 0xe: case 0xa:
408                 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
409                 break;
410         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
411                 fw_notify("A%c spd %x tl %02x, "
412                     "%04x -> %04x, %s, "
413                     "%s, %04x%08x%s\n",
414                     dir, speed, header[0] >> 10 & 0x3f,
415                     header[1] >> 16, header[0] >> 16, evts[evt],
416                     tcodes[tcode], header[1] & 0xffff, header[2], specific);
417                 break;
418         default:
419                 fw_notify("A%c spd %x tl %02x, "
420                     "%04x -> %04x, %s, "
421                     "%s%s\n",
422                     dir, speed, header[0] >> 10 & 0x3f,
423                     header[1] >> 16, header[0] >> 16, evts[evt],
424                     tcodes[tcode], specific);
425         }
426 }
427
428 #else
429
430 #define log_irqs(evt)
431 #define log_selfids(node_id, generation, self_id_count, sid)
432 #define log_ar_at_event(dir, speed, header, evt)
433
434 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
435
436 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
437 {
438         writel(data, ohci->registers + offset);
439 }
440
441 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
442 {
443         return readl(ohci->registers + offset);
444 }
445
446 static inline void flush_writes(const struct fw_ohci *ohci)
447 {
448         /* Do a dummy read to flush writes. */
449         reg_read(ohci, OHCI1394_Version);
450 }
451
452 static int ohci_update_phy_reg(struct fw_card *card, int addr,
453                                int clear_bits, int set_bits)
454 {
455         struct fw_ohci *ohci = fw_ohci(card);
456         u32 val, old;
457
458         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
459         flush_writes(ohci);
460         msleep(2);
461         val = reg_read(ohci, OHCI1394_PhyControl);
462         if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
463                 fw_error("failed to set phy reg bits.\n");
464                 return -EBUSY;
465         }
466
467         old = OHCI1394_PhyControl_ReadData(val);
468         old = (old & ~clear_bits) | set_bits;
469         reg_write(ohci, OHCI1394_PhyControl,
470                   OHCI1394_PhyControl_Write(addr, old));
471
472         return 0;
473 }
474
475 static int ar_context_add_page(struct ar_context *ctx)
476 {
477         struct device *dev = ctx->ohci->card.device;
478         struct ar_buffer *ab;
479         dma_addr_t uninitialized_var(ab_bus);
480         size_t offset;
481
482         ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
483         if (ab == NULL)
484                 return -ENOMEM;
485
486         ab->next = NULL;
487         memset(&ab->descriptor, 0, sizeof(ab->descriptor));
488         ab->descriptor.control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
489                                                     DESCRIPTOR_STATUS |
490                                                     DESCRIPTOR_BRANCH_ALWAYS);
491         offset = offsetof(struct ar_buffer, data);
492         ab->descriptor.req_count      = cpu_to_le16(PAGE_SIZE - offset);
493         ab->descriptor.data_address   = cpu_to_le32(ab_bus + offset);
494         ab->descriptor.res_count      = cpu_to_le16(PAGE_SIZE - offset);
495         ab->descriptor.branch_address = 0;
496
497         ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
498         ctx->last_buffer->next = ab;
499         ctx->last_buffer = ab;
500
501         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
502         flush_writes(ctx->ohci);
503
504         return 0;
505 }
506
507 static void ar_context_release(struct ar_context *ctx)
508 {
509         struct ar_buffer *ab, *ab_next;
510         size_t offset;
511         dma_addr_t ab_bus;
512
513         for (ab = ctx->current_buffer; ab; ab = ab_next) {
514                 ab_next = ab->next;
515                 offset = offsetof(struct ar_buffer, data);
516                 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
517                 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
518                                   ab, ab_bus);
519         }
520 }
521
522 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
523 #define cond_le32_to_cpu(v) \
524         (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
525 #else
526 #define cond_le32_to_cpu(v) le32_to_cpu(v)
527 #endif
528
529 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
530 {
531         struct fw_ohci *ohci = ctx->ohci;
532         struct fw_packet p;
533         u32 status, length, tcode;
534         int evt;
535
536         p.header[0] = cond_le32_to_cpu(buffer[0]);
537         p.header[1] = cond_le32_to_cpu(buffer[1]);
538         p.header[2] = cond_le32_to_cpu(buffer[2]);
539
540         tcode = (p.header[0] >> 4) & 0x0f;
541         switch (tcode) {
542         case TCODE_WRITE_QUADLET_REQUEST:
543         case TCODE_READ_QUADLET_RESPONSE:
544                 p.header[3] = (__force __u32) buffer[3];
545                 p.header_length = 16;
546                 p.payload_length = 0;
547                 break;
548
549         case TCODE_READ_BLOCK_REQUEST :
550                 p.header[3] = cond_le32_to_cpu(buffer[3]);
551                 p.header_length = 16;
552                 p.payload_length = 0;
553                 break;
554
555         case TCODE_WRITE_BLOCK_REQUEST:
556         case TCODE_READ_BLOCK_RESPONSE:
557         case TCODE_LOCK_REQUEST:
558         case TCODE_LOCK_RESPONSE:
559                 p.header[3] = cond_le32_to_cpu(buffer[3]);
560                 p.header_length = 16;
561                 p.payload_length = p.header[3] >> 16;
562                 break;
563
564         case TCODE_WRITE_RESPONSE:
565         case TCODE_READ_QUADLET_REQUEST:
566         case OHCI_TCODE_PHY_PACKET:
567                 p.header_length = 12;
568                 p.payload_length = 0;
569                 break;
570
571         default:
572                 /* FIXME: Stop context, discard everything, and restart? */
573                 p.header_length = 0;
574                 p.payload_length = 0;
575         }
576
577         p.payload = (void *) buffer + p.header_length;
578
579         /* FIXME: What to do about evt_* errors? */
580         length = (p.header_length + p.payload_length + 3) / 4;
581         status = cond_le32_to_cpu(buffer[length]);
582         evt    = (status >> 16) & 0x1f;
583
584         p.ack        = evt - 16;
585         p.speed      = (status >> 21) & 0x7;
586         p.timestamp  = status & 0xffff;
587         p.generation = ohci->request_generation;
588
589         log_ar_at_event('R', p.speed, p.header, evt);
590
591         /*
592          * The OHCI bus reset handler synthesizes a phy packet with
593          * the new generation number when a bus reset happens (see
594          * section 8.4.2.3).  This helps us determine when a request
595          * was received and make sure we send the response in the same
596          * generation.  We only need this for requests; for responses
597          * we use the unique tlabel for finding the matching
598          * request.
599          *
600          * Alas some chips sometimes emit bus reset packets with a
601          * wrong generation.  We set the correct generation for these
602          * at a slightly incorrect time (in bus_reset_tasklet).
603          */
604         if (evt == OHCI1394_evt_bus_reset) {
605                 if (!ohci->bus_reset_packet_quirk)
606                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
607         } else if (ctx == &ohci->ar_request_ctx) {
608                 fw_core_handle_request(&ohci->card, &p);
609         } else {
610                 fw_core_handle_response(&ohci->card, &p);
611         }
612
613         return buffer + length + 1;
614 }
615
616 static void ar_context_tasklet(unsigned long data)
617 {
618         struct ar_context *ctx = (struct ar_context *)data;
619         struct fw_ohci *ohci = ctx->ohci;
620         struct ar_buffer *ab;
621         struct descriptor *d;
622         void *buffer, *end;
623
624         ab = ctx->current_buffer;
625         d = &ab->descriptor;
626
627         if (d->res_count == 0) {
628                 size_t size, rest, offset;
629                 dma_addr_t start_bus;
630                 void *start;
631
632                 /*
633                  * This descriptor is finished and we may have a
634                  * packet split across this and the next buffer. We
635                  * reuse the page for reassembling the split packet.
636                  */
637
638                 offset = offsetof(struct ar_buffer, data);
639                 start = buffer = ab;
640                 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
641
642                 ab = ab->next;
643                 d = &ab->descriptor;
644                 size = buffer + PAGE_SIZE - ctx->pointer;
645                 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
646                 memmove(buffer, ctx->pointer, size);
647                 memcpy(buffer + size, ab->data, rest);
648                 ctx->current_buffer = ab;
649                 ctx->pointer = (void *) ab->data + rest;
650                 end = buffer + size + rest;
651
652                 while (buffer < end)
653                         buffer = handle_ar_packet(ctx, buffer);
654
655                 dma_free_coherent(ohci->card.device, PAGE_SIZE,
656                                   start, start_bus);
657                 ar_context_add_page(ctx);
658         } else {
659                 buffer = ctx->pointer;
660                 ctx->pointer = end =
661                         (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
662
663                 while (buffer < end)
664                         buffer = handle_ar_packet(ctx, buffer);
665         }
666 }
667
668 static int ar_context_init(struct ar_context *ctx,
669                            struct fw_ohci *ohci, u32 regs)
670 {
671         struct ar_buffer ab;
672
673         ctx->regs        = regs;
674         ctx->ohci        = ohci;
675         ctx->last_buffer = &ab;
676         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
677
678         ar_context_add_page(ctx);
679         ar_context_add_page(ctx);
680         ctx->current_buffer = ab.next;
681         ctx->pointer = ctx->current_buffer->data;
682
683         return 0;
684 }
685
686 static void ar_context_run(struct ar_context *ctx)
687 {
688         struct ar_buffer *ab = ctx->current_buffer;
689         dma_addr_t ab_bus;
690         size_t offset;
691
692         offset = offsetof(struct ar_buffer, data);
693         ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
694
695         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
696         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
697         flush_writes(ctx->ohci);
698 }
699
700 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
701 {
702         int b, key;
703
704         b   = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
705         key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
706
707         /* figure out which descriptor the branch address goes in */
708         if (z == 2 && (b == 3 || key == 2))
709                 return d;
710         else
711                 return d + z - 1;
712 }
713
714 static void context_tasklet(unsigned long data)
715 {
716         struct context *ctx = (struct context *) data;
717         struct descriptor *d, *last;
718         u32 address;
719         int z;
720         struct descriptor_buffer *desc;
721
722         desc = list_entry(ctx->buffer_list.next,
723                         struct descriptor_buffer, list);
724         last = ctx->last;
725         while (last->branch_address != 0) {
726                 struct descriptor_buffer *old_desc = desc;
727                 address = le32_to_cpu(last->branch_address);
728                 z = address & 0xf;
729                 address &= ~0xf;
730
731                 /* If the branch address points to a buffer outside of the
732                  * current buffer, advance to the next buffer. */
733                 if (address < desc->buffer_bus ||
734                                 address >= desc->buffer_bus + desc->used)
735                         desc = list_entry(desc->list.next,
736                                         struct descriptor_buffer, list);
737                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
738                 last = find_branch_descriptor(d, z);
739
740                 if (!ctx->callback(ctx, d, last))
741                         break;
742
743                 if (old_desc != desc) {
744                         /* If we've advanced to the next buffer, move the
745                          * previous buffer to the free list. */
746                         unsigned long flags;
747                         old_desc->used = 0;
748                         spin_lock_irqsave(&ctx->ohci->lock, flags);
749                         list_move_tail(&old_desc->list, &ctx->buffer_list);
750                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
751                 }
752                 ctx->last = last;
753         }
754 }
755
756 /*
757  * Allocate a new buffer and add it to the list of free buffers for this
758  * context.  Must be called with ohci->lock held.
759  */
760 static int context_add_buffer(struct context *ctx)
761 {
762         struct descriptor_buffer *desc;
763         dma_addr_t uninitialized_var(bus_addr);
764         int offset;
765
766         /*
767          * 16MB of descriptors should be far more than enough for any DMA
768          * program.  This will catch run-away userspace or DoS attacks.
769          */
770         if (ctx->total_allocation >= 16*1024*1024)
771                 return -ENOMEM;
772
773         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
774                         &bus_addr, GFP_ATOMIC);
775         if (!desc)
776                 return -ENOMEM;
777
778         offset = (void *)&desc->buffer - (void *)desc;
779         desc->buffer_size = PAGE_SIZE - offset;
780         desc->buffer_bus = bus_addr + offset;
781         desc->used = 0;
782
783         list_add_tail(&desc->list, &ctx->buffer_list);
784         ctx->total_allocation += PAGE_SIZE;
785
786         return 0;
787 }
788
789 static int context_init(struct context *ctx, struct fw_ohci *ohci,
790                         u32 regs, descriptor_callback_t callback)
791 {
792         ctx->ohci = ohci;
793         ctx->regs = regs;
794         ctx->total_allocation = 0;
795
796         INIT_LIST_HEAD(&ctx->buffer_list);
797         if (context_add_buffer(ctx) < 0)
798                 return -ENOMEM;
799
800         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
801                         struct descriptor_buffer, list);
802
803         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
804         ctx->callback = callback;
805
806         /*
807          * We put a dummy descriptor in the buffer that has a NULL
808          * branch address and looks like it's been sent.  That way we
809          * have a descriptor to append DMA programs to.
810          */
811         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
812         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
813         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
814         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
815         ctx->last = ctx->buffer_tail->buffer;
816         ctx->prev = ctx->buffer_tail->buffer;
817
818         return 0;
819 }
820
821 static void context_release(struct context *ctx)
822 {
823         struct fw_card *card = &ctx->ohci->card;
824         struct descriptor_buffer *desc, *tmp;
825
826         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
827                 dma_free_coherent(card->device, PAGE_SIZE, desc,
828                         desc->buffer_bus -
829                         ((void *)&desc->buffer - (void *)desc));
830 }
831
832 /* Must be called with ohci->lock held */
833 static struct descriptor *context_get_descriptors(struct context *ctx,
834                                                   int z, dma_addr_t *d_bus)
835 {
836         struct descriptor *d = NULL;
837         struct descriptor_buffer *desc = ctx->buffer_tail;
838
839         if (z * sizeof(*d) > desc->buffer_size)
840                 return NULL;
841
842         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
843                 /* No room for the descriptor in this buffer, so advance to the
844                  * next one. */
845
846                 if (desc->list.next == &ctx->buffer_list) {
847                         /* If there is no free buffer next in the list,
848                          * allocate one. */
849                         if (context_add_buffer(ctx) < 0)
850                                 return NULL;
851                 }
852                 desc = list_entry(desc->list.next,
853                                 struct descriptor_buffer, list);
854                 ctx->buffer_tail = desc;
855         }
856
857         d = desc->buffer + desc->used / sizeof(*d);
858         memset(d, 0, z * sizeof(*d));
859         *d_bus = desc->buffer_bus + desc->used;
860
861         return d;
862 }
863
864 static void context_run(struct context *ctx, u32 extra)
865 {
866         struct fw_ohci *ohci = ctx->ohci;
867
868         reg_write(ohci, COMMAND_PTR(ctx->regs),
869                   le32_to_cpu(ctx->last->branch_address));
870         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
871         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
872         flush_writes(ohci);
873 }
874
875 static void context_append(struct context *ctx,
876                            struct descriptor *d, int z, int extra)
877 {
878         dma_addr_t d_bus;
879         struct descriptor_buffer *desc = ctx->buffer_tail;
880
881         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
882
883         desc->used += (z + extra) * sizeof(*d);
884         ctx->prev->branch_address = cpu_to_le32(d_bus | z);
885         ctx->prev = find_branch_descriptor(d, z);
886
887         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
888         flush_writes(ctx->ohci);
889 }
890
891 static void context_stop(struct context *ctx)
892 {
893         u32 reg;
894         int i;
895
896         reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
897         flush_writes(ctx->ohci);
898
899         for (i = 0; i < 10; i++) {
900                 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
901                 if ((reg & CONTEXT_ACTIVE) == 0)
902                         return;
903
904                 mdelay(1);
905         }
906         fw_error("Error: DMA context still active (0x%08x)\n", reg);
907 }
908
909 struct driver_data {
910         struct fw_packet *packet;
911 };
912
913 /*
914  * This function apppends a packet to the DMA queue for transmission.
915  * Must always be called with the ochi->lock held to ensure proper
916  * generation handling and locking around packet queue manipulation.
917  */
918 static int at_context_queue_packet(struct context *ctx,
919                                    struct fw_packet *packet)
920 {
921         struct fw_ohci *ohci = ctx->ohci;
922         dma_addr_t d_bus, uninitialized_var(payload_bus);
923         struct driver_data *driver_data;
924         struct descriptor *d, *last;
925         __le32 *header;
926         int z, tcode;
927         u32 reg;
928
929         d = context_get_descriptors(ctx, 4, &d_bus);
930         if (d == NULL) {
931                 packet->ack = RCODE_SEND_ERROR;
932                 return -1;
933         }
934
935         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
936         d[0].res_count = cpu_to_le16(packet->timestamp);
937
938         /*
939          * The DMA format for asyncronous link packets is different
940          * from the IEEE1394 layout, so shift the fields around
941          * accordingly.  If header_length is 8, it's a PHY packet, to
942          * which we need to prepend an extra quadlet.
943          */
944
945         header = (__le32 *) &d[1];
946         switch (packet->header_length) {
947         case 16:
948         case 12:
949                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
950                                         (packet->speed << 16));
951                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
952                                         (packet->header[0] & 0xffff0000));
953                 header[2] = cpu_to_le32(packet->header[2]);
954
955                 tcode = (packet->header[0] >> 4) & 0x0f;
956                 if (TCODE_IS_BLOCK_PACKET(tcode))
957                         header[3] = cpu_to_le32(packet->header[3]);
958                 else
959                         header[3] = (__force __le32) packet->header[3];
960
961                 d[0].req_count = cpu_to_le16(packet->header_length);
962                 break;
963
964         case 8:
965                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
966                                         (packet->speed << 16));
967                 header[1] = cpu_to_le32(packet->header[0]);
968                 header[2] = cpu_to_le32(packet->header[1]);
969                 d[0].req_count = cpu_to_le16(12);
970                 break;
971
972         case 4:
973                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
974                                         (packet->speed << 16));
975                 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
976                 d[0].req_count = cpu_to_le16(8);
977                 break;
978
979         default:
980                 /* BUG(); */
981                 packet->ack = RCODE_SEND_ERROR;
982                 return -1;
983         }
984
985         driver_data = (struct driver_data *) &d[3];
986         driver_data->packet = packet;
987         packet->driver_data = driver_data;
988
989         if (packet->payload_length > 0) {
990                 payload_bus =
991                         dma_map_single(ohci->card.device, packet->payload,
992                                        packet->payload_length, DMA_TO_DEVICE);
993                 if (dma_mapping_error(ohci->card.device, payload_bus)) {
994                         packet->ack = RCODE_SEND_ERROR;
995                         return -1;
996                 }
997                 packet->payload_bus = payload_bus;
998
999                 d[2].req_count    = cpu_to_le16(packet->payload_length);
1000                 d[2].data_address = cpu_to_le32(payload_bus);
1001                 last = &d[2];
1002                 z = 3;
1003         } else {
1004                 last = &d[0];
1005                 z = 2;
1006         }
1007
1008         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1009                                      DESCRIPTOR_IRQ_ALWAYS |
1010                                      DESCRIPTOR_BRANCH_ALWAYS);
1011
1012         /*
1013          * If the controller and packet generations don't match, we need to
1014          * bail out and try again.  If IntEvent.busReset is set, the AT context
1015          * is halted, so appending to the context and trying to run it is
1016          * futile.  Most controllers do the right thing and just flush the AT
1017          * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1018          * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1019          * up stalling out.  So we just bail out in software and try again
1020          * later, and everyone is happy.
1021          * FIXME: Document how the locking works.
1022          */
1023         if (ohci->generation != packet->generation ||
1024             reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1025                 if (packet->payload_length > 0)
1026                         dma_unmap_single(ohci->card.device, payload_bus,
1027                                          packet->payload_length, DMA_TO_DEVICE);
1028                 packet->ack = RCODE_GENERATION;
1029                 return -1;
1030         }
1031
1032         context_append(ctx, d, z, 4 - z);
1033
1034         /* If the context isn't already running, start it up. */
1035         reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1036         if ((reg & CONTEXT_RUN) == 0)
1037                 context_run(ctx, 0);
1038
1039         return 0;
1040 }
1041
1042 static int handle_at_packet(struct context *context,
1043                             struct descriptor *d,
1044                             struct descriptor *last)
1045 {
1046         struct driver_data *driver_data;
1047         struct fw_packet *packet;
1048         struct fw_ohci *ohci = context->ohci;
1049         int evt;
1050
1051         if (last->transfer_status == 0)
1052                 /* This descriptor isn't done yet, stop iteration. */
1053                 return 0;
1054
1055         driver_data = (struct driver_data *) &d[3];
1056         packet = driver_data->packet;
1057         if (packet == NULL)
1058                 /* This packet was cancelled, just continue. */
1059                 return 1;
1060
1061         if (packet->payload_bus)
1062                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1063                                  packet->payload_length, DMA_TO_DEVICE);
1064
1065         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1066         packet->timestamp = le16_to_cpu(last->res_count);
1067
1068         log_ar_at_event('T', packet->speed, packet->header, evt);
1069
1070         switch (evt) {
1071         case OHCI1394_evt_timeout:
1072                 /* Async response transmit timed out. */
1073                 packet->ack = RCODE_CANCELLED;
1074                 break;
1075
1076         case OHCI1394_evt_flushed:
1077                 /*
1078                  * The packet was flushed should give same error as
1079                  * when we try to use a stale generation count.
1080                  */
1081                 packet->ack = RCODE_GENERATION;
1082                 break;
1083
1084         case OHCI1394_evt_missing_ack:
1085                 /*
1086                  * Using a valid (current) generation count, but the
1087                  * node is not on the bus or not sending acks.
1088                  */
1089                 packet->ack = RCODE_NO_ACK;
1090                 break;
1091
1092         case ACK_COMPLETE + 0x10:
1093         case ACK_PENDING + 0x10:
1094         case ACK_BUSY_X + 0x10:
1095         case ACK_BUSY_A + 0x10:
1096         case ACK_BUSY_B + 0x10:
1097         case ACK_DATA_ERROR + 0x10:
1098         case ACK_TYPE_ERROR + 0x10:
1099                 packet->ack = evt - 0x10;
1100                 break;
1101
1102         default:
1103                 packet->ack = RCODE_SEND_ERROR;
1104                 break;
1105         }
1106
1107         packet->callback(packet, &ohci->card, packet->ack);
1108
1109         return 1;
1110 }
1111
1112 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1113 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1114 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1115 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1116 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1117
1118 static void handle_local_rom(struct fw_ohci *ohci,
1119                              struct fw_packet *packet, u32 csr)
1120 {
1121         struct fw_packet response;
1122         int tcode, length, i;
1123
1124         tcode = HEADER_GET_TCODE(packet->header[0]);
1125         if (TCODE_IS_BLOCK_PACKET(tcode))
1126                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1127         else
1128                 length = 4;
1129
1130         i = csr - CSR_CONFIG_ROM;
1131         if (i + length > CONFIG_ROM_SIZE) {
1132                 fw_fill_response(&response, packet->header,
1133                                  RCODE_ADDRESS_ERROR, NULL, 0);
1134         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1135                 fw_fill_response(&response, packet->header,
1136                                  RCODE_TYPE_ERROR, NULL, 0);
1137         } else {
1138                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1139                                  (void *) ohci->config_rom + i, length);
1140         }
1141
1142         fw_core_handle_response(&ohci->card, &response);
1143 }
1144
1145 static void handle_local_lock(struct fw_ohci *ohci,
1146                               struct fw_packet *packet, u32 csr)
1147 {
1148         struct fw_packet response;
1149         int tcode, length, ext_tcode, sel;
1150         __be32 *payload, lock_old;
1151         u32 lock_arg, lock_data;
1152
1153         tcode = HEADER_GET_TCODE(packet->header[0]);
1154         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1155         payload = packet->payload;
1156         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1157
1158         if (tcode == TCODE_LOCK_REQUEST &&
1159             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1160                 lock_arg = be32_to_cpu(payload[0]);
1161                 lock_data = be32_to_cpu(payload[1]);
1162         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1163                 lock_arg = 0;
1164                 lock_data = 0;
1165         } else {
1166                 fw_fill_response(&response, packet->header,
1167                                  RCODE_TYPE_ERROR, NULL, 0);
1168                 goto out;
1169         }
1170
1171         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1172         reg_write(ohci, OHCI1394_CSRData, lock_data);
1173         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1174         reg_write(ohci, OHCI1394_CSRControl, sel);
1175
1176         if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1177                 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1178         else
1179                 fw_notify("swap not done yet\n");
1180
1181         fw_fill_response(&response, packet->header,
1182                          RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1183  out:
1184         fw_core_handle_response(&ohci->card, &response);
1185 }
1186
1187 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1188 {
1189         u64 offset;
1190         u32 csr;
1191
1192         if (ctx == &ctx->ohci->at_request_ctx) {
1193                 packet->ack = ACK_PENDING;
1194                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1195         }
1196
1197         offset =
1198                 ((unsigned long long)
1199                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1200                 packet->header[2];
1201         csr = offset - CSR_REGISTER_BASE;
1202
1203         /* Handle config rom reads. */
1204         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1205                 handle_local_rom(ctx->ohci, packet, csr);
1206         else switch (csr) {
1207         case CSR_BUS_MANAGER_ID:
1208         case CSR_BANDWIDTH_AVAILABLE:
1209         case CSR_CHANNELS_AVAILABLE_HI:
1210         case CSR_CHANNELS_AVAILABLE_LO:
1211                 handle_local_lock(ctx->ohci, packet, csr);
1212                 break;
1213         default:
1214                 if (ctx == &ctx->ohci->at_request_ctx)
1215                         fw_core_handle_request(&ctx->ohci->card, packet);
1216                 else
1217                         fw_core_handle_response(&ctx->ohci->card, packet);
1218                 break;
1219         }
1220
1221         if (ctx == &ctx->ohci->at_response_ctx) {
1222                 packet->ack = ACK_COMPLETE;
1223                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1224         }
1225 }
1226
1227 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1228 {
1229         unsigned long flags;
1230         int ret;
1231
1232         spin_lock_irqsave(&ctx->ohci->lock, flags);
1233
1234         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1235             ctx->ohci->generation == packet->generation) {
1236                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1237                 handle_local_request(ctx, packet);
1238                 return;
1239         }
1240
1241         ret = at_context_queue_packet(ctx, packet);
1242         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1243
1244         if (ret < 0)
1245                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1246
1247 }
1248
1249 static void bus_reset_tasklet(unsigned long data)
1250 {
1251         struct fw_ohci *ohci = (struct fw_ohci *)data;
1252         int self_id_count, i, j, reg;
1253         int generation, new_generation;
1254         unsigned long flags;
1255         void *free_rom = NULL;
1256         dma_addr_t free_rom_bus = 0;
1257
1258         reg = reg_read(ohci, OHCI1394_NodeID);
1259         if (!(reg & OHCI1394_NodeID_idValid)) {
1260                 fw_notify("node ID not valid, new bus reset in progress\n");
1261                 return;
1262         }
1263         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1264                 fw_notify("malconfigured bus\n");
1265                 return;
1266         }
1267         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1268                                OHCI1394_NodeID_nodeNumber);
1269
1270         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1271         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1272                 fw_notify("inconsistent self IDs\n");
1273                 return;
1274         }
1275         /*
1276          * The count in the SelfIDCount register is the number of
1277          * bytes in the self ID receive buffer.  Since we also receive
1278          * the inverted quadlets and a header quadlet, we shift one
1279          * bit extra to get the actual number of self IDs.
1280          */
1281         self_id_count = (reg >> 3) & 0x3ff;
1282         if (self_id_count == 0) {
1283                 fw_notify("inconsistent self IDs\n");
1284                 return;
1285         }
1286         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1287         rmb();
1288
1289         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1290                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1291                         fw_notify("inconsistent self IDs\n");
1292                         return;
1293                 }
1294                 ohci->self_id_buffer[j] =
1295                                 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1296         }
1297         rmb();
1298
1299         /*
1300          * Check the consistency of the self IDs we just read.  The
1301          * problem we face is that a new bus reset can start while we
1302          * read out the self IDs from the DMA buffer. If this happens,
1303          * the DMA buffer will be overwritten with new self IDs and we
1304          * will read out inconsistent data.  The OHCI specification
1305          * (section 11.2) recommends a technique similar to
1306          * linux/seqlock.h, where we remember the generation of the
1307          * self IDs in the buffer before reading them out and compare
1308          * it to the current generation after reading them out.  If
1309          * the two generations match we know we have a consistent set
1310          * of self IDs.
1311          */
1312
1313         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1314         if (new_generation != generation) {
1315                 fw_notify("recursive bus reset detected, "
1316                           "discarding self ids\n");
1317                 return;
1318         }
1319
1320         /* FIXME: Document how the locking works. */
1321         spin_lock_irqsave(&ohci->lock, flags);
1322
1323         ohci->generation = generation;
1324         context_stop(&ohci->at_request_ctx);
1325         context_stop(&ohci->at_response_ctx);
1326         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1327
1328         if (ohci->bus_reset_packet_quirk)
1329                 ohci->request_generation = generation;
1330
1331         /*
1332          * This next bit is unrelated to the AT context stuff but we
1333          * have to do it under the spinlock also.  If a new config rom
1334          * was set up before this reset, the old one is now no longer
1335          * in use and we can free it. Update the config rom pointers
1336          * to point to the current config rom and clear the
1337          * next_config_rom pointer so a new udpate can take place.
1338          */
1339
1340         if (ohci->next_config_rom != NULL) {
1341                 if (ohci->next_config_rom != ohci->config_rom) {
1342                         free_rom      = ohci->config_rom;
1343                         free_rom_bus  = ohci->config_rom_bus;
1344                 }
1345                 ohci->config_rom      = ohci->next_config_rom;
1346                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
1347                 ohci->next_config_rom = NULL;
1348
1349                 /*
1350                  * Restore config_rom image and manually update
1351                  * config_rom registers.  Writing the header quadlet
1352                  * will indicate that the config rom is ready, so we
1353                  * do that last.
1354                  */
1355                 reg_write(ohci, OHCI1394_BusOptions,
1356                           be32_to_cpu(ohci->config_rom[2]));
1357                 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
1358                 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
1359         }
1360
1361 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1362         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1363         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1364 #endif
1365
1366         spin_unlock_irqrestore(&ohci->lock, flags);
1367
1368         if (free_rom)
1369                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1370                                   free_rom, free_rom_bus);
1371
1372         log_selfids(ohci->node_id, generation,
1373                     self_id_count, ohci->self_id_buffer);
1374
1375         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1376                                  self_id_count, ohci->self_id_buffer);
1377 }
1378
1379 static irqreturn_t irq_handler(int irq, void *data)
1380 {
1381         struct fw_ohci *ohci = data;
1382         u32 event, iso_event, cycle_time;
1383         int i;
1384
1385         event = reg_read(ohci, OHCI1394_IntEventClear);
1386
1387         if (!event || !~event)
1388                 return IRQ_NONE;
1389
1390         /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1391         reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1392         log_irqs(event);
1393
1394         if (event & OHCI1394_selfIDComplete)
1395                 tasklet_schedule(&ohci->bus_reset_tasklet);
1396
1397         if (event & OHCI1394_RQPkt)
1398                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1399
1400         if (event & OHCI1394_RSPkt)
1401                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1402
1403         if (event & OHCI1394_reqTxComplete)
1404                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1405
1406         if (event & OHCI1394_respTxComplete)
1407                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1408
1409         iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1410         reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1411
1412         while (iso_event) {
1413                 i = ffs(iso_event) - 1;
1414                 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1415                 iso_event &= ~(1 << i);
1416         }
1417
1418         iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1419         reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1420
1421         while (iso_event) {
1422                 i = ffs(iso_event) - 1;
1423                 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1424                 iso_event &= ~(1 << i);
1425         }
1426
1427         if (unlikely(event & OHCI1394_regAccessFail))
1428                 fw_error("Register access failure - "
1429                          "please notify linux1394-devel@lists.sf.net\n");
1430
1431         if (unlikely(event & OHCI1394_postedWriteErr))
1432                 fw_error("PCI posted write error\n");
1433
1434         if (unlikely(event & OHCI1394_cycleTooLong)) {
1435                 if (printk_ratelimit())
1436                         fw_notify("isochronous cycle too long\n");
1437                 reg_write(ohci, OHCI1394_LinkControlSet,
1438                           OHCI1394_LinkControl_cycleMaster);
1439         }
1440
1441         if (event & OHCI1394_cycle64Seconds) {
1442                 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1443                 if ((cycle_time & 0x80000000) == 0)
1444                         atomic_inc(&ohci->bus_seconds);
1445         }
1446
1447         return IRQ_HANDLED;
1448 }
1449
1450 static int software_reset(struct fw_ohci *ohci)
1451 {
1452         int i;
1453
1454         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1455
1456         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1457                 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1458                      OHCI1394_HCControl_softReset) == 0)
1459                         return 0;
1460                 msleep(1);
1461         }
1462
1463         return -EBUSY;
1464 }
1465
1466 static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1467 {
1468         struct fw_ohci *ohci = fw_ohci(card);
1469         struct pci_dev *dev = to_pci_dev(card->device);
1470         u32 lps;
1471         int i;
1472
1473         if (software_reset(ohci)) {
1474                 fw_error("Failed to reset ohci card.\n");
1475                 return -EBUSY;
1476         }
1477
1478         /*
1479          * Now enable LPS, which we need in order to start accessing
1480          * most of the registers.  In fact, on some cards (ALI M5251),
1481          * accessing registers in the SClk domain without LPS enabled
1482          * will lock up the machine.  Wait 50msec to make sure we have
1483          * full link enabled.  However, with some cards (well, at least
1484          * a JMicron PCIe card), we have to try again sometimes.
1485          */
1486         reg_write(ohci, OHCI1394_HCControlSet,
1487                   OHCI1394_HCControl_LPS |
1488                   OHCI1394_HCControl_postedWriteEnable);
1489         flush_writes(ohci);
1490
1491         for (lps = 0, i = 0; !lps && i < 3; i++) {
1492                 msleep(50);
1493                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1494                       OHCI1394_HCControl_LPS;
1495         }
1496
1497         if (!lps) {
1498                 fw_error("Failed to set Link Power Status\n");
1499                 return -EIO;
1500         }
1501
1502         reg_write(ohci, OHCI1394_HCControlClear,
1503                   OHCI1394_HCControl_noByteSwapData);
1504
1505         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1506         reg_write(ohci, OHCI1394_LinkControlClear,
1507                   OHCI1394_LinkControl_rcvPhyPkt);
1508         reg_write(ohci, OHCI1394_LinkControlSet,
1509                   OHCI1394_LinkControl_rcvSelfID |
1510                   OHCI1394_LinkControl_cycleTimerEnable |
1511                   OHCI1394_LinkControl_cycleMaster);
1512
1513         reg_write(ohci, OHCI1394_ATRetries,
1514                   OHCI1394_MAX_AT_REQ_RETRIES |
1515                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1516                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1517
1518         ar_context_run(&ohci->ar_request_ctx);
1519         ar_context_run(&ohci->ar_response_ctx);
1520
1521         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1522         reg_write(ohci, OHCI1394_IntEventClear, ~0);
1523         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1524         reg_write(ohci, OHCI1394_IntMaskSet,
1525                   OHCI1394_selfIDComplete |
1526                   OHCI1394_RQPkt | OHCI1394_RSPkt |
1527                   OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1528                   OHCI1394_isochRx | OHCI1394_isochTx |
1529                   OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
1530                   OHCI1394_cycle64Seconds | OHCI1394_regAccessFail |
1531                   OHCI1394_masterIntEnable);
1532         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1533                 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
1534
1535         /* Activate link_on bit and contender bit in our self ID packets.*/
1536         if (ohci_update_phy_reg(card, 4, 0,
1537                                 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1538                 return -EIO;
1539
1540         /*
1541          * When the link is not yet enabled, the atomic config rom
1542          * update mechanism described below in ohci_set_config_rom()
1543          * is not active.  We have to update ConfigRomHeader and
1544          * BusOptions manually, and the write to ConfigROMmap takes
1545          * effect immediately.  We tie this to the enabling of the
1546          * link, so we have a valid config rom before enabling - the
1547          * OHCI requires that ConfigROMhdr and BusOptions have valid
1548          * values before enabling.
1549          *
1550          * However, when the ConfigROMmap is written, some controllers
1551          * always read back quadlets 0 and 2 from the config rom to
1552          * the ConfigRomHeader and BusOptions registers on bus reset.
1553          * They shouldn't do that in this initial case where the link
1554          * isn't enabled.  This means we have to use the same
1555          * workaround here, setting the bus header to 0 and then write
1556          * the right values in the bus reset tasklet.
1557          */
1558
1559         if (config_rom) {
1560                 ohci->next_config_rom =
1561                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1562                                            &ohci->next_config_rom_bus,
1563                                            GFP_KERNEL);
1564                 if (ohci->next_config_rom == NULL)
1565                         return -ENOMEM;
1566
1567                 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1568                 fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
1569         } else {
1570                 /*
1571                  * In the suspend case, config_rom is NULL, which
1572                  * means that we just reuse the old config rom.
1573                  */
1574                 ohci->next_config_rom = ohci->config_rom;
1575                 ohci->next_config_rom_bus = ohci->config_rom_bus;
1576         }
1577
1578         ohci->next_header = be32_to_cpu(ohci->next_config_rom[0]);
1579         ohci->next_config_rom[0] = 0;
1580         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1581         reg_write(ohci, OHCI1394_BusOptions,
1582                   be32_to_cpu(ohci->next_config_rom[2]));
1583         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1584
1585         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1586
1587         if (request_irq(dev->irq, irq_handler,
1588                         IRQF_SHARED, ohci_driver_name, ohci)) {
1589                 fw_error("Failed to allocate shared interrupt %d.\n",
1590                          dev->irq);
1591                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1592                                   ohci->config_rom, ohci->config_rom_bus);
1593                 return -EIO;
1594         }
1595
1596         reg_write(ohci, OHCI1394_HCControlSet,
1597                   OHCI1394_HCControl_linkEnable |
1598                   OHCI1394_HCControl_BIBimageValid);
1599         flush_writes(ohci);
1600
1601         /*
1602          * We are ready to go, initiate bus reset to finish the
1603          * initialization.
1604          */
1605
1606         fw_core_initiate_bus_reset(&ohci->card, 1);
1607
1608         return 0;
1609 }
1610
1611 static int ohci_set_config_rom(struct fw_card *card,
1612                                u32 *config_rom, size_t length)
1613 {
1614         struct fw_ohci *ohci;
1615         unsigned long flags;
1616         int ret = -EBUSY;
1617         __be32 *next_config_rom;
1618         dma_addr_t uninitialized_var(next_config_rom_bus);
1619
1620         ohci = fw_ohci(card);
1621
1622         /*
1623          * When the OHCI controller is enabled, the config rom update
1624          * mechanism is a bit tricky, but easy enough to use.  See
1625          * section 5.5.6 in the OHCI specification.
1626          *
1627          * The OHCI controller caches the new config rom address in a
1628          * shadow register (ConfigROMmapNext) and needs a bus reset
1629          * for the changes to take place.  When the bus reset is
1630          * detected, the controller loads the new values for the
1631          * ConfigRomHeader and BusOptions registers from the specified
1632          * config rom and loads ConfigROMmap from the ConfigROMmapNext
1633          * shadow register. All automatically and atomically.
1634          *
1635          * Now, there's a twist to this story.  The automatic load of
1636          * ConfigRomHeader and BusOptions doesn't honor the
1637          * noByteSwapData bit, so with a be32 config rom, the
1638          * controller will load be32 values in to these registers
1639          * during the atomic update, even on litte endian
1640          * architectures.  The workaround we use is to put a 0 in the
1641          * header quadlet; 0 is endian agnostic and means that the
1642          * config rom isn't ready yet.  In the bus reset tasklet we
1643          * then set up the real values for the two registers.
1644          *
1645          * We use ohci->lock to avoid racing with the code that sets
1646          * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1647          */
1648
1649         next_config_rom =
1650                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1651                                    &next_config_rom_bus, GFP_KERNEL);
1652         if (next_config_rom == NULL)
1653                 return -ENOMEM;
1654
1655         spin_lock_irqsave(&ohci->lock, flags);
1656
1657         if (ohci->next_config_rom == NULL) {
1658                 ohci->next_config_rom = next_config_rom;
1659                 ohci->next_config_rom_bus = next_config_rom_bus;
1660
1661                 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1662                 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
1663                                   length * 4);
1664
1665                 ohci->next_header = config_rom[0];
1666                 ohci->next_config_rom[0] = 0;
1667
1668                 reg_write(ohci, OHCI1394_ConfigROMmap,
1669                           ohci->next_config_rom_bus);
1670                 ret = 0;
1671         }
1672
1673         spin_unlock_irqrestore(&ohci->lock, flags);
1674
1675         /*
1676          * Now initiate a bus reset to have the changes take
1677          * effect. We clean up the old config rom memory and DMA
1678          * mappings in the bus reset tasklet, since the OHCI
1679          * controller could need to access it before the bus reset
1680          * takes effect.
1681          */
1682         if (ret == 0)
1683                 fw_core_initiate_bus_reset(&ohci->card, 1);
1684         else
1685                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1686                                   next_config_rom, next_config_rom_bus);
1687
1688         return ret;
1689 }
1690
1691 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1692 {
1693         struct fw_ohci *ohci = fw_ohci(card);
1694
1695         at_context_transmit(&ohci->at_request_ctx, packet);
1696 }
1697
1698 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1699 {
1700         struct fw_ohci *ohci = fw_ohci(card);
1701
1702         at_context_transmit(&ohci->at_response_ctx, packet);
1703 }
1704
1705 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1706 {
1707         struct fw_ohci *ohci = fw_ohci(card);
1708         struct context *ctx = &ohci->at_request_ctx;
1709         struct driver_data *driver_data = packet->driver_data;
1710         int ret = -ENOENT;
1711
1712         tasklet_disable(&ctx->tasklet);
1713
1714         if (packet->ack != 0)
1715                 goto out;
1716
1717         if (packet->payload_bus)
1718                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1719                                  packet->payload_length, DMA_TO_DEVICE);
1720
1721         log_ar_at_event('T', packet->speed, packet->header, 0x20);
1722         driver_data->packet = NULL;
1723         packet->ack = RCODE_CANCELLED;
1724         packet->callback(packet, &ohci->card, packet->ack);
1725         ret = 0;
1726  out:
1727         tasklet_enable(&ctx->tasklet);
1728
1729         return ret;
1730 }
1731
1732 static int ohci_enable_phys_dma(struct fw_card *card,
1733                                 int node_id, int generation)
1734 {
1735 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1736         return 0;
1737 #else
1738         struct fw_ohci *ohci = fw_ohci(card);
1739         unsigned long flags;
1740         int n, ret = 0;
1741
1742         /*
1743          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
1744          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
1745          */
1746
1747         spin_lock_irqsave(&ohci->lock, flags);
1748
1749         if (ohci->generation != generation) {
1750                 ret = -ESTALE;
1751                 goto out;
1752         }
1753
1754         /*
1755          * Note, if the node ID contains a non-local bus ID, physical DMA is
1756          * enabled for _all_ nodes on remote buses.
1757          */
1758
1759         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1760         if (n < 32)
1761                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1762         else
1763                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1764
1765         flush_writes(ohci);
1766  out:
1767         spin_unlock_irqrestore(&ohci->lock, flags);
1768
1769         return ret;
1770 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1771 }
1772
1773 static u64 ohci_get_bus_time(struct fw_card *card)
1774 {
1775         struct fw_ohci *ohci = fw_ohci(card);
1776         u32 cycle_time;
1777         u64 bus_time;
1778
1779         cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1780         bus_time = ((u64)atomic_read(&ohci->bus_seconds) << 32) | cycle_time;
1781
1782         return bus_time;
1783 }
1784
1785 static void copy_iso_headers(struct iso_context *ctx, void *p)
1786 {
1787         int i = ctx->header_length;
1788
1789         if (i + ctx->base.header_size > PAGE_SIZE)
1790                 return;
1791
1792         /*
1793          * The iso header is byteswapped to little endian by
1794          * the controller, but the remaining header quadlets
1795          * are big endian.  We want to present all the headers
1796          * as big endian, so we have to swap the first quadlet.
1797          */
1798         if (ctx->base.header_size > 0)
1799                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1800         if (ctx->base.header_size > 4)
1801                 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
1802         if (ctx->base.header_size > 8)
1803                 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
1804         ctx->header_length += ctx->base.header_size;
1805 }
1806
1807 static int handle_ir_dualbuffer_packet(struct context *context,
1808                                        struct descriptor *d,
1809                                        struct descriptor *last)
1810 {
1811         struct iso_context *ctx =
1812                 container_of(context, struct iso_context, context);
1813         struct db_descriptor *db = (struct db_descriptor *) d;
1814         __le32 *ir_header;
1815         size_t header_length;
1816         void *p, *end;
1817
1818         if (db->first_res_count != 0 && db->second_res_count != 0) {
1819                 if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) {
1820                         /* This descriptor isn't done yet, stop iteration. */
1821                         return 0;
1822                 }
1823                 ctx->excess_bytes -= le16_to_cpu(db->second_req_count);
1824         }
1825
1826         header_length = le16_to_cpu(db->first_req_count) -
1827                 le16_to_cpu(db->first_res_count);
1828
1829         p = db + 1;
1830         end = p + header_length;
1831         while (p < end) {
1832                 copy_iso_headers(ctx, p);
1833                 ctx->excess_bytes +=
1834                         (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff;
1835                 p += max(ctx->base.header_size, (size_t)8);
1836         }
1837
1838         ctx->excess_bytes -= le16_to_cpu(db->second_req_count) -
1839                 le16_to_cpu(db->second_res_count);
1840
1841         if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
1842                 ir_header = (__le32 *) (db + 1);
1843                 ctx->base.callback(&ctx->base,
1844                                    le32_to_cpu(ir_header[0]) & 0xffff,
1845                                    ctx->header_length, ctx->header,
1846                                    ctx->base.callback_data);
1847                 ctx->header_length = 0;
1848         }
1849
1850         return 1;
1851 }
1852
1853 static int handle_ir_packet_per_buffer(struct context *context,
1854                                        struct descriptor *d,
1855                                        struct descriptor *last)
1856 {
1857         struct iso_context *ctx =
1858                 container_of(context, struct iso_context, context);
1859         struct descriptor *pd;
1860         __le32 *ir_header;
1861         void *p;
1862
1863         for (pd = d; pd <= last; pd++) {
1864                 if (pd->transfer_status)
1865                         break;
1866         }
1867         if (pd > last)
1868                 /* Descriptor(s) not done yet, stop iteration */
1869                 return 0;
1870
1871         p = last + 1;
1872         copy_iso_headers(ctx, p);
1873
1874         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1875                 ir_header = (__le32 *) p;
1876                 ctx->base.callback(&ctx->base,
1877                                    le32_to_cpu(ir_header[0]) & 0xffff,
1878                                    ctx->header_length, ctx->header,
1879                                    ctx->base.callback_data);
1880                 ctx->header_length = 0;
1881         }
1882
1883         return 1;
1884 }
1885
1886 static int handle_it_packet(struct context *context,
1887                             struct descriptor *d,
1888                             struct descriptor *last)
1889 {
1890         struct iso_context *ctx =
1891                 container_of(context, struct iso_context, context);
1892
1893         if (last->transfer_status == 0)
1894                 /* This descriptor isn't done yet, stop iteration. */
1895                 return 0;
1896
1897         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
1898                 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1899                                    0, NULL, ctx->base.callback_data);
1900
1901         return 1;
1902 }
1903
1904 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
1905                                 int type, int channel, size_t header_size)
1906 {
1907         struct fw_ohci *ohci = fw_ohci(card);
1908         struct iso_context *ctx, *list;
1909         descriptor_callback_t callback;
1910         u64 *channels, dont_care = ~0ULL;
1911         u32 *mask, regs;
1912         unsigned long flags;
1913         int index, ret = -ENOMEM;
1914
1915         if (type == FW_ISO_CONTEXT_TRANSMIT) {
1916                 channels = &dont_care;
1917                 mask = &ohci->it_context_mask;
1918                 list = ohci->it_context_list;
1919                 callback = handle_it_packet;
1920         } else {
1921                 channels = &ohci->ir_context_channels;
1922                 mask = &ohci->ir_context_mask;
1923                 list = ohci->ir_context_list;
1924                 if (ohci->use_dualbuffer)
1925                         callback = handle_ir_dualbuffer_packet;
1926                 else
1927                         callback = handle_ir_packet_per_buffer;
1928         }
1929
1930         spin_lock_irqsave(&ohci->lock, flags);
1931         index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
1932         if (index >= 0) {
1933                 *channels &= ~(1ULL << channel);
1934                 *mask &= ~(1 << index);
1935         }
1936         spin_unlock_irqrestore(&ohci->lock, flags);
1937
1938         if (index < 0)
1939                 return ERR_PTR(-EBUSY);
1940
1941         if (type == FW_ISO_CONTEXT_TRANSMIT)
1942                 regs = OHCI1394_IsoXmitContextBase(index);
1943         else
1944                 regs = OHCI1394_IsoRcvContextBase(index);
1945
1946         ctx = &list[index];
1947         memset(ctx, 0, sizeof(*ctx));
1948         ctx->header_length = 0;
1949         ctx->header = (void *) __get_free_page(GFP_KERNEL);
1950         if (ctx->header == NULL)
1951                 goto out;
1952
1953         ret = context_init(&ctx->context, ohci, regs, callback);
1954         if (ret < 0)
1955                 goto out_with_header;
1956
1957         return &ctx->base;
1958
1959  out_with_header:
1960         free_page((unsigned long)ctx->header);
1961  out:
1962         spin_lock_irqsave(&ohci->lock, flags);
1963         *mask |= 1 << index;
1964         spin_unlock_irqrestore(&ohci->lock, flags);
1965
1966         return ERR_PTR(ret);
1967 }
1968
1969 static int ohci_start_iso(struct fw_iso_context *base,
1970                           s32 cycle, u32 sync, u32 tags)
1971 {
1972         struct iso_context *ctx = container_of(base, struct iso_context, base);
1973         struct fw_ohci *ohci = ctx->context.ohci;
1974         u32 control, match;
1975         int index;
1976
1977         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1978                 index = ctx - ohci->it_context_list;
1979                 match = 0;
1980                 if (cycle >= 0)
1981                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
1982                                 (cycle & 0x7fff) << 16;
1983
1984                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
1985                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
1986                 context_run(&ctx->context, match);
1987         } else {
1988                 index = ctx - ohci->ir_context_list;
1989                 control = IR_CONTEXT_ISOCH_HEADER;
1990                 if (ohci->use_dualbuffer)
1991                         control |= IR_CONTEXT_DUAL_BUFFER_MODE;
1992                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
1993                 if (cycle >= 0) {
1994                         match |= (cycle & 0x07fff) << 12;
1995                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
1996                 }
1997
1998                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
1999                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2000                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2001                 context_run(&ctx->context, control);
2002         }
2003
2004         return 0;
2005 }
2006
2007 static int ohci_stop_iso(struct fw_iso_context *base)
2008 {
2009         struct fw_ohci *ohci = fw_ohci(base->card);
2010         struct iso_context *ctx = container_of(base, struct iso_context, base);
2011         int index;
2012
2013         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2014                 index = ctx - ohci->it_context_list;
2015                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2016         } else {
2017                 index = ctx - ohci->ir_context_list;
2018                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2019         }
2020         flush_writes(ohci);
2021         context_stop(&ctx->context);
2022
2023         return 0;
2024 }
2025
2026 static void ohci_free_iso_context(struct fw_iso_context *base)
2027 {
2028         struct fw_ohci *ohci = fw_ohci(base->card);
2029         struct iso_context *ctx = container_of(base, struct iso_context, base);
2030         unsigned long flags;
2031         int index;
2032
2033         ohci_stop_iso(base);
2034         context_release(&ctx->context);
2035         free_page((unsigned long)ctx->header);
2036
2037         spin_lock_irqsave(&ohci->lock, flags);
2038
2039         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2040                 index = ctx - ohci->it_context_list;
2041                 ohci->it_context_mask |= 1 << index;
2042         } else {
2043                 index = ctx - ohci->ir_context_list;
2044                 ohci->ir_context_mask |= 1 << index;
2045                 ohci->ir_context_channels |= 1ULL << base->channel;
2046         }
2047
2048         spin_unlock_irqrestore(&ohci->lock, flags);
2049 }
2050
2051 static int ohci_queue_iso_transmit(struct fw_iso_context *base,
2052                                    struct fw_iso_packet *packet,
2053                                    struct fw_iso_buffer *buffer,
2054                                    unsigned long payload)
2055 {
2056         struct iso_context *ctx = container_of(base, struct iso_context, base);
2057         struct descriptor *d, *last, *pd;
2058         struct fw_iso_packet *p;
2059         __le32 *header;
2060         dma_addr_t d_bus, page_bus;
2061         u32 z, header_z, payload_z, irq;
2062         u32 payload_index, payload_end_index, next_page_index;
2063         int page, end_page, i, length, offset;
2064
2065         /*
2066          * FIXME: Cycle lost behavior should be configurable: lose
2067          * packet, retransmit or terminate..
2068          */
2069
2070         p = packet;
2071         payload_index = payload;
2072
2073         if (p->skip)
2074                 z = 1;
2075         else
2076                 z = 2;
2077         if (p->header_length > 0)
2078                 z++;
2079
2080         /* Determine the first page the payload isn't contained in. */
2081         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2082         if (p->payload_length > 0)
2083                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2084         else
2085                 payload_z = 0;
2086
2087         z += payload_z;
2088
2089         /* Get header size in number of descriptors. */
2090         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2091
2092         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2093         if (d == NULL)
2094                 return -ENOMEM;
2095
2096         if (!p->skip) {
2097                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2098                 d[0].req_count = cpu_to_le16(8);
2099
2100                 header = (__le32 *) &d[1];
2101                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2102                                         IT_HEADER_TAG(p->tag) |
2103                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2104                                         IT_HEADER_CHANNEL(ctx->base.channel) |
2105                                         IT_HEADER_SPEED(ctx->base.speed));
2106                 header[1] =
2107                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2108                                                           p->payload_length));
2109         }
2110
2111         if (p->header_length > 0) {
2112                 d[2].req_count    = cpu_to_le16(p->header_length);
2113                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2114                 memcpy(&d[z], p->header, p->header_length);
2115         }
2116
2117         pd = d + z - payload_z;
2118         payload_end_index = payload_index + p->payload_length;
2119         for (i = 0; i < payload_z; i++) {
2120                 page               = payload_index >> PAGE_SHIFT;
2121                 offset             = payload_index & ~PAGE_MASK;
2122                 next_page_index    = (page + 1) << PAGE_SHIFT;
2123                 length             =
2124                         min(next_page_index, payload_end_index) - payload_index;
2125                 pd[i].req_count    = cpu_to_le16(length);
2126
2127                 page_bus = page_private(buffer->pages[page]);
2128                 pd[i].data_address = cpu_to_le32(page_bus + offset);
2129
2130                 payload_index += length;
2131         }
2132
2133         if (p->interrupt)
2134                 irq = DESCRIPTOR_IRQ_ALWAYS;
2135         else
2136                 irq = DESCRIPTOR_NO_IRQ;
2137
2138         last = z == 2 ? d : d + z - 1;
2139         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2140                                      DESCRIPTOR_STATUS |
2141                                      DESCRIPTOR_BRANCH_ALWAYS |
2142                                      irq);
2143
2144         context_append(&ctx->context, d, z, header_z);
2145
2146         return 0;
2147 }
2148
2149 static int ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
2150                                              struct fw_iso_packet *packet,
2151                                              struct fw_iso_buffer *buffer,
2152                                              unsigned long payload)
2153 {
2154         struct iso_context *ctx = container_of(base, struct iso_context, base);
2155         struct db_descriptor *db = NULL;
2156         struct descriptor *d;
2157         struct fw_iso_packet *p;
2158         dma_addr_t d_bus, page_bus;
2159         u32 z, header_z, length, rest;
2160         int page, offset, packet_count, header_size;
2161
2162         /*
2163          * FIXME: Cycle lost behavior should be configurable: lose
2164          * packet, retransmit or terminate..
2165          */
2166
2167         p = packet;
2168         z = 2;
2169
2170         /*
2171          * The OHCI controller puts the isochronous header and trailer in the
2172          * buffer, so we need at least 8 bytes.
2173          */
2174         packet_count = p->header_length / ctx->base.header_size;
2175         header_size = packet_count * max(ctx->base.header_size, (size_t)8);
2176
2177         /* Get header size in number of descriptors. */
2178         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2179         page     = payload >> PAGE_SHIFT;
2180         offset   = payload & ~PAGE_MASK;
2181         rest     = p->payload_length;
2182
2183         /* FIXME: make packet-per-buffer/dual-buffer a context option */
2184         while (rest > 0) {
2185                 d = context_get_descriptors(&ctx->context,
2186                                             z + header_z, &d_bus);
2187                 if (d == NULL)
2188                         return -ENOMEM;
2189
2190                 db = (struct db_descriptor *) d;
2191                 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
2192                                           DESCRIPTOR_BRANCH_ALWAYS);
2193                 db->first_size =
2194                     cpu_to_le16(max(ctx->base.header_size, (size_t)8));
2195                 if (p->skip && rest == p->payload_length) {
2196                         db->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2197                         db->first_req_count = db->first_size;
2198                 } else {
2199                         db->first_req_count = cpu_to_le16(header_size);
2200                 }
2201                 db->first_res_count = db->first_req_count;
2202                 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
2203
2204                 if (p->skip && rest == p->payload_length)
2205                         length = 4;
2206                 else if (offset + rest < PAGE_SIZE)
2207                         length = rest;
2208                 else
2209                         length = PAGE_SIZE - offset;
2210
2211                 db->second_req_count = cpu_to_le16(length);
2212                 db->second_res_count = db->second_req_count;
2213                 page_bus = page_private(buffer->pages[page]);
2214                 db->second_buffer = cpu_to_le32(page_bus + offset);
2215
2216                 if (p->interrupt && length == rest)
2217                         db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2218
2219                 context_append(&ctx->context, d, z, header_z);
2220                 offset = (offset + length) & ~PAGE_MASK;
2221                 rest -= length;
2222                 if (offset == 0)
2223                         page++;
2224         }
2225
2226         return 0;
2227 }
2228
2229 static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2230                                         struct fw_iso_packet *packet,
2231                                         struct fw_iso_buffer *buffer,
2232                                         unsigned long payload)
2233 {
2234         struct iso_context *ctx = container_of(base, struct iso_context, base);
2235         struct descriptor *d = NULL, *pd = NULL;
2236         struct fw_iso_packet *p = packet;
2237         dma_addr_t d_bus, page_bus;
2238         u32 z, header_z, rest;
2239         int i, j, length;
2240         int page, offset, packet_count, header_size, payload_per_buffer;
2241
2242         /*
2243          * The OHCI controller puts the isochronous header and trailer in the
2244          * buffer, so we need at least 8 bytes.
2245          */
2246         packet_count = p->header_length / ctx->base.header_size;
2247         header_size  = max(ctx->base.header_size, (size_t)8);
2248
2249         /* Get header size in number of descriptors. */
2250         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2251         page     = payload >> PAGE_SHIFT;
2252         offset   = payload & ~PAGE_MASK;
2253         payload_per_buffer = p->payload_length / packet_count;
2254
2255         for (i = 0; i < packet_count; i++) {
2256                 /* d points to the header descriptor */
2257                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2258                 d = context_get_descriptors(&ctx->context,
2259                                 z + header_z, &d_bus);
2260                 if (d == NULL)
2261                         return -ENOMEM;
2262
2263                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
2264                                               DESCRIPTOR_INPUT_MORE);
2265                 if (p->skip && i == 0)
2266                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2267                 d->req_count    = cpu_to_le16(header_size);
2268                 d->res_count    = d->req_count;
2269                 d->transfer_status = 0;
2270                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2271
2272                 rest = payload_per_buffer;
2273                 for (j = 1; j < z; j++) {
2274                         pd = d + j;
2275                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2276                                                   DESCRIPTOR_INPUT_MORE);
2277
2278                         if (offset + rest < PAGE_SIZE)
2279                                 length = rest;
2280                         else
2281                                 length = PAGE_SIZE - offset;
2282                         pd->req_count = cpu_to_le16(length);
2283                         pd->res_count = pd->req_count;
2284                         pd->transfer_status = 0;
2285
2286                         page_bus = page_private(buffer->pages[page]);
2287                         pd->data_address = cpu_to_le32(page_bus + offset);
2288
2289                         offset = (offset + length) & ~PAGE_MASK;
2290                         rest -= length;
2291                         if (offset == 0)
2292                                 page++;
2293                 }
2294                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2295                                           DESCRIPTOR_INPUT_LAST |
2296                                           DESCRIPTOR_BRANCH_ALWAYS);
2297                 if (p->interrupt && i == packet_count - 1)
2298                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2299
2300                 context_append(&ctx->context, d, z, header_z);
2301         }
2302
2303         return 0;
2304 }
2305
2306 static int ohci_queue_iso(struct fw_iso_context *base,
2307                           struct fw_iso_packet *packet,
2308                           struct fw_iso_buffer *buffer,
2309                           unsigned long payload)
2310 {
2311         struct iso_context *ctx = container_of(base, struct iso_context, base);
2312         unsigned long flags;
2313         int ret;
2314
2315         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2316         if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2317                 ret = ohci_queue_iso_transmit(base, packet, buffer, payload);
2318         else if (ctx->context.ohci->use_dualbuffer)
2319                 ret = ohci_queue_iso_receive_dualbuffer(base, packet,
2320                                                         buffer, payload);
2321         else
2322                 ret = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2323                                                         buffer, payload);
2324         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2325
2326         return ret;
2327 }
2328
2329 static const struct fw_card_driver ohci_driver = {
2330         .enable                 = ohci_enable,
2331         .update_phy_reg         = ohci_update_phy_reg,
2332         .set_config_rom         = ohci_set_config_rom,
2333         .send_request           = ohci_send_request,
2334         .send_response          = ohci_send_response,
2335         .cancel_packet          = ohci_cancel_packet,
2336         .enable_phys_dma        = ohci_enable_phys_dma,
2337         .get_bus_time           = ohci_get_bus_time,
2338
2339         .allocate_iso_context   = ohci_allocate_iso_context,
2340         .free_iso_context       = ohci_free_iso_context,
2341         .queue_iso              = ohci_queue_iso,
2342         .start_iso              = ohci_start_iso,
2343         .stop_iso               = ohci_stop_iso,
2344 };
2345
2346 #ifdef CONFIG_PPC_PMAC
2347 static void ohci_pmac_on(struct pci_dev *dev)
2348 {
2349         if (machine_is(powermac)) {
2350                 struct device_node *ofn = pci_device_to_OF_node(dev);
2351
2352                 if (ofn) {
2353                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2354                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2355                 }
2356         }
2357 }
2358
2359 static void ohci_pmac_off(struct pci_dev *dev)
2360 {
2361         if (machine_is(powermac)) {
2362                 struct device_node *ofn = pci_device_to_OF_node(dev);
2363
2364                 if (ofn) {
2365                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2366                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2367                 }
2368         }
2369 }
2370 #else
2371 #define ohci_pmac_on(dev)
2372 #define ohci_pmac_off(dev)
2373 #endif /* CONFIG_PPC_PMAC */
2374
2375 static int __devinit pci_probe(struct pci_dev *dev,
2376                                const struct pci_device_id *ent)
2377 {
2378         struct fw_ohci *ohci;
2379         u32 bus_options, max_receive, link_speed, version;
2380         u64 guid;
2381         int err;
2382         size_t size;
2383
2384         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2385         if (ohci == NULL) {
2386                 err = -ENOMEM;
2387                 goto fail;
2388         }
2389
2390         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2391
2392         ohci_pmac_on(dev);
2393
2394         err = pci_enable_device(dev);
2395         if (err) {
2396                 fw_error("Failed to enable OHCI hardware\n");
2397                 goto fail_free;
2398         }
2399
2400         pci_set_master(dev);
2401         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2402         pci_set_drvdata(dev, ohci);
2403
2404         spin_lock_init(&ohci->lock);
2405
2406         tasklet_init(&ohci->bus_reset_tasklet,
2407                      bus_reset_tasklet, (unsigned long)ohci);
2408
2409         err = pci_request_region(dev, 0, ohci_driver_name);
2410         if (err) {
2411                 fw_error("MMIO resource unavailable\n");
2412                 goto fail_disable;
2413         }
2414
2415         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2416         if (ohci->registers == NULL) {
2417                 fw_error("Failed to remap registers\n");
2418                 err = -ENXIO;
2419                 goto fail_iomem;
2420         }
2421
2422         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2423         ohci->use_dualbuffer = version >= OHCI_VERSION_1_1;
2424
2425 /* x86-32 currently doesn't use highmem for dma_alloc_coherent */
2426 #if !defined(CONFIG_X86_32)
2427         /* dual-buffer mode is broken with descriptor addresses above 2G */
2428         if (dev->vendor == PCI_VENDOR_ID_TI &&
2429             dev->device == PCI_DEVICE_ID_TI_TSB43AB22)
2430                 ohci->use_dualbuffer = false;
2431 #endif
2432
2433 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
2434         ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE &&
2435                              dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW;
2436 #endif
2437         ohci->bus_reset_packet_quirk = dev->vendor == PCI_VENDOR_ID_TI;
2438
2439         ar_context_init(&ohci->ar_request_ctx, ohci,
2440                         OHCI1394_AsReqRcvContextControlSet);
2441
2442         ar_context_init(&ohci->ar_response_ctx, ohci,
2443                         OHCI1394_AsRspRcvContextControlSet);
2444
2445         context_init(&ohci->at_request_ctx, ohci,
2446                      OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2447
2448         context_init(&ohci->at_response_ctx, ohci,
2449                      OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2450
2451         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2452         ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2453         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2454         size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
2455         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2456
2457         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2458         ohci->ir_context_channels = ~0ULL;
2459         ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2460         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2461         size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
2462         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2463
2464         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2465                 err = -ENOMEM;
2466                 goto fail_contexts;
2467         }
2468
2469         /* self-id dma buffer allocation */
2470         ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2471                                                SELF_ID_BUF_SIZE,
2472                                                &ohci->self_id_bus,
2473                                                GFP_KERNEL);
2474         if (ohci->self_id_cpu == NULL) {
2475                 err = -ENOMEM;
2476                 goto fail_contexts;
2477         }
2478
2479         bus_options = reg_read(ohci, OHCI1394_BusOptions);
2480         max_receive = (bus_options >> 12) & 0xf;
2481         link_speed = bus_options & 0x7;
2482         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2483                 reg_read(ohci, OHCI1394_GUIDLo);
2484
2485         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2486         if (err)
2487                 goto fail_self_id;
2488
2489         fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
2490                   dev_name(&dev->dev), version >> 16, version & 0xff);
2491
2492         return 0;
2493
2494  fail_self_id:
2495         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2496                           ohci->self_id_cpu, ohci->self_id_bus);
2497  fail_contexts:
2498         kfree(ohci->ir_context_list);
2499         kfree(ohci->it_context_list);
2500         context_release(&ohci->at_response_ctx);
2501         context_release(&ohci->at_request_ctx);
2502         ar_context_release(&ohci->ar_response_ctx);
2503         ar_context_release(&ohci->ar_request_ctx);
2504         pci_iounmap(dev, ohci->registers);
2505  fail_iomem:
2506         pci_release_region(dev, 0);
2507  fail_disable:
2508         pci_disable_device(dev);
2509  fail_free:
2510         kfree(&ohci->card);
2511         ohci_pmac_off(dev);
2512  fail:
2513         if (err == -ENOMEM)
2514                 fw_error("Out of memory\n");
2515
2516         return err;
2517 }
2518
2519 static void pci_remove(struct pci_dev *dev)
2520 {
2521         struct fw_ohci *ohci;
2522
2523         ohci = pci_get_drvdata(dev);
2524         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2525         flush_writes(ohci);
2526         fw_core_remove_card(&ohci->card);
2527
2528         /*
2529          * FIXME: Fail all pending packets here, now that the upper
2530          * layers can't queue any more.
2531          */
2532
2533         software_reset(ohci);
2534         free_irq(dev->irq, ohci);
2535
2536         if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
2537                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2538                                   ohci->next_config_rom, ohci->next_config_rom_bus);
2539         if (ohci->config_rom)
2540                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2541                                   ohci->config_rom, ohci->config_rom_bus);
2542         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2543                           ohci->self_id_cpu, ohci->self_id_bus);
2544         ar_context_release(&ohci->ar_request_ctx);
2545         ar_context_release(&ohci->ar_response_ctx);
2546         context_release(&ohci->at_request_ctx);
2547         context_release(&ohci->at_response_ctx);
2548         kfree(ohci->it_context_list);
2549         kfree(ohci->ir_context_list);
2550         pci_iounmap(dev, ohci->registers);
2551         pci_release_region(dev, 0);
2552         pci_disable_device(dev);
2553         kfree(&ohci->card);
2554         ohci_pmac_off(dev);
2555
2556         fw_notify("Removed fw-ohci device.\n");
2557 }
2558
2559 #ifdef CONFIG_PM
2560 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2561 {
2562         struct fw_ohci *ohci = pci_get_drvdata(dev);
2563         int err;
2564
2565         software_reset(ohci);
2566         free_irq(dev->irq, ohci);
2567         err = pci_save_state(dev);
2568         if (err) {
2569                 fw_error("pci_save_state failed\n");
2570                 return err;
2571         }
2572         err = pci_set_power_state(dev, pci_choose_state(dev, state));
2573         if (err)
2574                 fw_error("pci_set_power_state failed with %d\n", err);
2575         ohci_pmac_off(dev);
2576
2577         return 0;
2578 }
2579
2580 static int pci_resume(struct pci_dev *dev)
2581 {
2582         struct fw_ohci *ohci = pci_get_drvdata(dev);
2583         int err;
2584
2585         ohci_pmac_on(dev);
2586         pci_set_power_state(dev, PCI_D0);
2587         pci_restore_state(dev);
2588         err = pci_enable_device(dev);
2589         if (err) {
2590                 fw_error("pci_enable_device failed\n");
2591                 return err;
2592         }
2593
2594         return ohci_enable(&ohci->card, NULL, 0);
2595 }
2596 #endif
2597
2598 static struct pci_device_id pci_table[] = {
2599         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2600         { }
2601 };
2602
2603 MODULE_DEVICE_TABLE(pci, pci_table);
2604
2605 static struct pci_driver fw_ohci_pci_driver = {
2606         .name           = ohci_driver_name,
2607         .id_table       = pci_table,
2608         .probe          = pci_probe,
2609         .remove         = pci_remove,
2610 #ifdef CONFIG_PM
2611         .resume         = pci_resume,
2612         .suspend        = pci_suspend,
2613 #endif
2614 };
2615
2616 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2617 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2618 MODULE_LICENSE("GPL");
2619
2620 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2621 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2622 MODULE_ALIAS("ohci1394");
2623 #endif
2624
2625 static int __init fw_ohci_init(void)
2626 {
2627         return pci_register_driver(&fw_ohci_pci_driver);
2628 }
2629
2630 static void __exit fw_ohci_cleanup(void)
2631 {
2632         pci_unregister_driver(&fw_ohci_pci_driver);
2633 }
2634
2635 module_init(fw_ohci_init);
2636 module_exit(fw_ohci_cleanup);