firewire: allocate broadcast channel in hardware
[linux-2.6.git] / drivers / firewire / ohci.c
1 /*
2  * Driver for OHCI 1394 controllers
3  *
4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software Foundation,
18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/firewire.h>
26 #include <linux/firewire-constants.h>
27 #include <linux/gfp.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/io.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
33 #include <linux/mm.h>
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/pci.h>
37 #include <linux/pci_ids.h>
38 #include <linux/spinlock.h>
39 #include <linux/string.h>
40
41 #include <asm/byteorder.h>
42 #include <asm/page.h>
43 #include <asm/system.h>
44
45 #ifdef CONFIG_PPC_PMAC
46 #include <asm/pmac_feature.h>
47 #endif
48
49 #include "core.h"
50 #include "ohci.h"
51
52 #define DESCRIPTOR_OUTPUT_MORE          0
53 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
54 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
55 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
56 #define DESCRIPTOR_STATUS               (1 << 11)
57 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
58 #define DESCRIPTOR_PING                 (1 << 7)
59 #define DESCRIPTOR_YY                   (1 << 6)
60 #define DESCRIPTOR_NO_IRQ               (0 << 4)
61 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
62 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
63 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
64 #define DESCRIPTOR_WAIT                 (3 << 0)
65
66 struct descriptor {
67         __le16 req_count;
68         __le16 control;
69         __le32 data_address;
70         __le32 branch_address;
71         __le16 res_count;
72         __le16 transfer_status;
73 } __attribute__((aligned(16)));
74
75 #define CONTROL_SET(regs)       (regs)
76 #define CONTROL_CLEAR(regs)     ((regs) + 4)
77 #define COMMAND_PTR(regs)       ((regs) + 12)
78 #define CONTEXT_MATCH(regs)     ((regs) + 16)
79
80 struct ar_buffer {
81         struct descriptor descriptor;
82         struct ar_buffer *next;
83         __le32 data[0];
84 };
85
86 struct ar_context {
87         struct fw_ohci *ohci;
88         struct ar_buffer *current_buffer;
89         struct ar_buffer *last_buffer;
90         void *pointer;
91         u32 regs;
92         struct tasklet_struct tasklet;
93 };
94
95 struct context;
96
97 typedef int (*descriptor_callback_t)(struct context *ctx,
98                                      struct descriptor *d,
99                                      struct descriptor *last);
100
101 /*
102  * A buffer that contains a block of DMA-able coherent memory used for
103  * storing a portion of a DMA descriptor program.
104  */
105 struct descriptor_buffer {
106         struct list_head list;
107         dma_addr_t buffer_bus;
108         size_t buffer_size;
109         size_t used;
110         struct descriptor buffer[0];
111 };
112
113 struct context {
114         struct fw_ohci *ohci;
115         u32 regs;
116         int total_allocation;
117
118         /*
119          * List of page-sized buffers for storing DMA descriptors.
120          * Head of list contains buffers in use and tail of list contains
121          * free buffers.
122          */
123         struct list_head buffer_list;
124
125         /*
126          * Pointer to a buffer inside buffer_list that contains the tail
127          * end of the current DMA program.
128          */
129         struct descriptor_buffer *buffer_tail;
130
131         /*
132          * The descriptor containing the branch address of the first
133          * descriptor that has not yet been filled by the device.
134          */
135         struct descriptor *last;
136
137         /*
138          * The last descriptor in the DMA program.  It contains the branch
139          * address that must be updated upon appending a new descriptor.
140          */
141         struct descriptor *prev;
142
143         descriptor_callback_t callback;
144
145         struct tasklet_struct tasklet;
146 };
147
148 #define IT_HEADER_SY(v)          ((v) <<  0)
149 #define IT_HEADER_TCODE(v)       ((v) <<  4)
150 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
151 #define IT_HEADER_TAG(v)         ((v) << 14)
152 #define IT_HEADER_SPEED(v)       ((v) << 16)
153 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
154
155 struct iso_context {
156         struct fw_iso_context base;
157         struct context context;
158         int excess_bytes;
159         void *header;
160         size_t header_length;
161 };
162
163 #define CONFIG_ROM_SIZE 1024
164
165 struct fw_ohci {
166         struct fw_card card;
167
168         __iomem char *registers;
169         int node_id;
170         int generation;
171         int request_generation; /* for timestamping incoming requests */
172         unsigned quirks;
173         unsigned int pri_req_max;
174         unsigned int features;
175         u32 bus_time;
176         bool is_root;
177
178         /*
179          * Spinlock for accessing fw_ohci data.  Never call out of
180          * this driver with this lock held.
181          */
182         spinlock_t lock;
183
184         struct ar_context ar_request_ctx;
185         struct ar_context ar_response_ctx;
186         struct context at_request_ctx;
187         struct context at_response_ctx;
188
189         u32 it_context_mask;
190         struct iso_context *it_context_list;
191         u64 ir_context_channels;
192         u32 ir_context_mask;
193         struct iso_context *ir_context_list;
194
195         __be32    *config_rom;
196         dma_addr_t config_rom_bus;
197         __be32    *next_config_rom;
198         dma_addr_t next_config_rom_bus;
199         __be32     next_header;
200
201         __le32    *self_id_cpu;
202         dma_addr_t self_id_bus;
203         struct tasklet_struct bus_reset_tasklet;
204
205         u32 self_id_buffer[512];
206 };
207
208 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
209 {
210         return container_of(card, struct fw_ohci, card);
211 }
212
213 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
214 #define IR_CONTEXT_BUFFER_FILL          0x80000000
215 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
216 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
217 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
218 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
219
220 #define CONTEXT_RUN     0x8000
221 #define CONTEXT_WAKE    0x1000
222 #define CONTEXT_DEAD    0x0800
223 #define CONTEXT_ACTIVE  0x0400
224
225 #define OHCI1394_MAX_AT_REQ_RETRIES     0xf
226 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
227 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
228
229 #define OHCI1394_REGISTER_SIZE          0x800
230 #define OHCI_LOOP_COUNT                 500
231 #define OHCI1394_PCI_HCI_Control        0x40
232 #define SELF_ID_BUF_SIZE                0x800
233 #define OHCI_TCODE_PHY_PACKET           0x0e
234 #define OHCI_VERSION_1_1                0x010010
235
236 static char ohci_driver_name[] = KBUILD_MODNAME;
237
238 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
239 #define PCI_DEVICE_ID_TI_TSB12LV22      0x8009
240
241 #define QUIRK_CYCLE_TIMER               1
242 #define QUIRK_RESET_PACKET              2
243 #define QUIRK_BE_HEADERS                4
244 #define QUIRK_NO_1394A                  8
245 #define QUIRK_NO_MSI                    16
246
247 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
248 static const struct {
249         unsigned short vendor, device, flags;
250 } ohci_quirks[] = {
251         {PCI_VENDOR_ID_TI,      PCI_DEVICE_ID_TI_TSB12LV22, QUIRK_CYCLE_TIMER |
252                                                             QUIRK_RESET_PACKET |
253                                                             QUIRK_NO_1394A},
254         {PCI_VENDOR_ID_TI,      PCI_ANY_ID,     QUIRK_RESET_PACKET},
255         {PCI_VENDOR_ID_AL,      PCI_ANY_ID,     QUIRK_CYCLE_TIMER},
256         {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, QUIRK_NO_MSI},
257         {PCI_VENDOR_ID_NEC,     PCI_ANY_ID,     QUIRK_CYCLE_TIMER},
258         {PCI_VENDOR_ID_VIA,     PCI_ANY_ID,     QUIRK_CYCLE_TIMER},
259         {PCI_VENDOR_ID_APPLE,   PCI_DEVICE_ID_APPLE_UNI_N_FW, QUIRK_BE_HEADERS},
260 };
261
262 /* This overrides anything that was found in ohci_quirks[]. */
263 static int param_quirks;
264 module_param_named(quirks, param_quirks, int, 0644);
265 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
266         ", nonatomic cycle timer = "    __stringify(QUIRK_CYCLE_TIMER)
267         ", reset packet generation = "  __stringify(QUIRK_RESET_PACKET)
268         ", AR/selfID endianess = "      __stringify(QUIRK_BE_HEADERS)
269         ", no 1394a enhancements = "    __stringify(QUIRK_NO_1394A)
270         ", disable MSI = "              __stringify(QUIRK_NO_MSI)
271         ")");
272
273 #define OHCI_PARAM_DEBUG_AT_AR          1
274 #define OHCI_PARAM_DEBUG_SELFIDS        2
275 #define OHCI_PARAM_DEBUG_IRQS           4
276 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
277
278 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
279
280 static int param_debug;
281 module_param_named(debug, param_debug, int, 0644);
282 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
283         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
284         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
285         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
286         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
287         ", or a combination, or all = -1)");
288
289 static void log_irqs(u32 evt)
290 {
291         if (likely(!(param_debug &
292                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
293                 return;
294
295         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
296             !(evt & OHCI1394_busReset))
297                 return;
298
299         fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
300             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
301             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
302             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
303             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
304             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
305             evt & OHCI1394_isochRx              ? " IR"                 : "",
306             evt & OHCI1394_isochTx              ? " IT"                 : "",
307             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
308             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
309             evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
310             evt & OHCI1394_cycleInconsistent    ? " cycleInconsistent"  : "",
311             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
312             evt & OHCI1394_busReset             ? " busReset"           : "",
313             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
314                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
315                     OHCI1394_respTxComplete | OHCI1394_isochRx |
316                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
317                     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
318                     OHCI1394_cycleInconsistent |
319                     OHCI1394_regAccessFail | OHCI1394_busReset)
320                                                 ? " ?"                  : "");
321 }
322
323 static const char *speed[] = {
324         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
325 };
326 static const char *power[] = {
327         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
328         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
329 };
330 static const char port[] = { '.', '-', 'p', 'c', };
331
332 static char _p(u32 *s, int shift)
333 {
334         return port[*s >> shift & 3];
335 }
336
337 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
338 {
339         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
340                 return;
341
342         fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
343                   self_id_count, generation, node_id);
344
345         for (; self_id_count--; ++s)
346                 if ((*s & 1 << 23) == 0)
347                         fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
348                             "%s gc=%d %s %s%s%s\n",
349                             *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
350                             speed[*s >> 14 & 3], *s >> 16 & 63,
351                             power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
352                             *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
353                 else
354                         fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
355                             *s, *s >> 24 & 63,
356                             _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
357                             _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
358 }
359
360 static const char *evts[] = {
361         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
362         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
363         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
364         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
365         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
366         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
367         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
368         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
369         [0x10] = "-reserved-",          [0x11] = "ack_complete",
370         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
371         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
372         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
373         [0x18] = "-reserved-",          [0x19] = "-reserved-",
374         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
375         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
376         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
377         [0x20] = "pending/cancelled",
378 };
379 static const char *tcodes[] = {
380         [0x0] = "QW req",               [0x1] = "BW req",
381         [0x2] = "W resp",               [0x3] = "-reserved-",
382         [0x4] = "QR req",               [0x5] = "BR req",
383         [0x6] = "QR resp",              [0x7] = "BR resp",
384         [0x8] = "cycle start",          [0x9] = "Lk req",
385         [0xa] = "async stream packet",  [0xb] = "Lk resp",
386         [0xc] = "-reserved-",           [0xd] = "-reserved-",
387         [0xe] = "link internal",        [0xf] = "-reserved-",
388 };
389 static const char *phys[] = {
390         [0x0] = "phy config packet",    [0x1] = "link-on packet",
391         [0x2] = "self-id packet",       [0x3] = "-reserved-",
392 };
393
394 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
395 {
396         int tcode = header[0] >> 4 & 0xf;
397         char specific[12];
398
399         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
400                 return;
401
402         if (unlikely(evt >= ARRAY_SIZE(evts)))
403                         evt = 0x1f;
404
405         if (evt == OHCI1394_evt_bus_reset) {
406                 fw_notify("A%c evt_bus_reset, generation %d\n",
407                     dir, (header[2] >> 16) & 0xff);
408                 return;
409         }
410
411         if (header[0] == ~header[1]) {
412                 fw_notify("A%c %s, %s, %08x\n",
413                     dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
414                 return;
415         }
416
417         switch (tcode) {
418         case 0x0: case 0x6: case 0x8:
419                 snprintf(specific, sizeof(specific), " = %08x",
420                          be32_to_cpu((__force __be32)header[3]));
421                 break;
422         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
423                 snprintf(specific, sizeof(specific), " %x,%x",
424                          header[3] >> 16, header[3] & 0xffff);
425                 break;
426         default:
427                 specific[0] = '\0';
428         }
429
430         switch (tcode) {
431         case 0xe: case 0xa:
432                 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
433                 break;
434         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
435                 fw_notify("A%c spd %x tl %02x, "
436                     "%04x -> %04x, %s, "
437                     "%s, %04x%08x%s\n",
438                     dir, speed, header[0] >> 10 & 0x3f,
439                     header[1] >> 16, header[0] >> 16, evts[evt],
440                     tcodes[tcode], header[1] & 0xffff, header[2], specific);
441                 break;
442         default:
443                 fw_notify("A%c spd %x tl %02x, "
444                     "%04x -> %04x, %s, "
445                     "%s%s\n",
446                     dir, speed, header[0] >> 10 & 0x3f,
447                     header[1] >> 16, header[0] >> 16, evts[evt],
448                     tcodes[tcode], specific);
449         }
450 }
451
452 #else
453
454 #define param_debug 0
455 static inline void log_irqs(u32 evt) {}
456 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
457 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
458
459 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
460
461 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
462 {
463         writel(data, ohci->registers + offset);
464 }
465
466 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
467 {
468         return readl(ohci->registers + offset);
469 }
470
471 static inline void flush_writes(const struct fw_ohci *ohci)
472 {
473         /* Do a dummy read to flush writes. */
474         reg_read(ohci, OHCI1394_Version);
475 }
476
477 static int read_phy_reg(struct fw_ohci *ohci, int addr)
478 {
479         u32 val;
480         int i;
481
482         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
483         for (i = 0; i < 3 + 100; i++) {
484                 val = reg_read(ohci, OHCI1394_PhyControl);
485                 if (val & OHCI1394_PhyControl_ReadDone)
486                         return OHCI1394_PhyControl_ReadData(val);
487
488                 /*
489                  * Try a few times without waiting.  Sleeping is necessary
490                  * only when the link/PHY interface is busy.
491                  */
492                 if (i >= 3)
493                         msleep(1);
494         }
495         fw_error("failed to read phy reg\n");
496
497         return -EBUSY;
498 }
499
500 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
501 {
502         int i;
503
504         reg_write(ohci, OHCI1394_PhyControl,
505                   OHCI1394_PhyControl_Write(addr, val));
506         for (i = 0; i < 3 + 100; i++) {
507                 val = reg_read(ohci, OHCI1394_PhyControl);
508                 if (!(val & OHCI1394_PhyControl_WritePending))
509                         return 0;
510
511                 if (i >= 3)
512                         msleep(1);
513         }
514         fw_error("failed to write phy reg\n");
515
516         return -EBUSY;
517 }
518
519 static int ohci_update_phy_reg(struct fw_card *card, int addr,
520                                int clear_bits, int set_bits)
521 {
522         struct fw_ohci *ohci = fw_ohci(card);
523         int ret;
524
525         ret = read_phy_reg(ohci, addr);
526         if (ret < 0)
527                 return ret;
528
529         /*
530          * The interrupt status bits are cleared by writing a one bit.
531          * Avoid clearing them unless explicitly requested in set_bits.
532          */
533         if (addr == 5)
534                 clear_bits |= PHY_INT_STATUS_BITS;
535
536         return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
537 }
538
539 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
540 {
541         int ret;
542
543         ret = ohci_update_phy_reg(&ohci->card, 7, PHY_PAGE_SELECT, page << 5);
544         if (ret < 0)
545                 return ret;
546
547         return read_phy_reg(ohci, addr);
548 }
549
550 static int ar_context_add_page(struct ar_context *ctx)
551 {
552         struct device *dev = ctx->ohci->card.device;
553         struct ar_buffer *ab;
554         dma_addr_t uninitialized_var(ab_bus);
555         size_t offset;
556
557         ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
558         if (ab == NULL)
559                 return -ENOMEM;
560
561         ab->next = NULL;
562         memset(&ab->descriptor, 0, sizeof(ab->descriptor));
563         ab->descriptor.control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
564                                                     DESCRIPTOR_STATUS |
565                                                     DESCRIPTOR_BRANCH_ALWAYS);
566         offset = offsetof(struct ar_buffer, data);
567         ab->descriptor.req_count      = cpu_to_le16(PAGE_SIZE - offset);
568         ab->descriptor.data_address   = cpu_to_le32(ab_bus + offset);
569         ab->descriptor.res_count      = cpu_to_le16(PAGE_SIZE - offset);
570         ab->descriptor.branch_address = 0;
571
572         ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
573         ctx->last_buffer->next = ab;
574         ctx->last_buffer = ab;
575
576         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
577         flush_writes(ctx->ohci);
578
579         return 0;
580 }
581
582 static void ar_context_release(struct ar_context *ctx)
583 {
584         struct ar_buffer *ab, *ab_next;
585         size_t offset;
586         dma_addr_t ab_bus;
587
588         for (ab = ctx->current_buffer; ab; ab = ab_next) {
589                 ab_next = ab->next;
590                 offset = offsetof(struct ar_buffer, data);
591                 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
592                 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
593                                   ab, ab_bus);
594         }
595 }
596
597 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
598 #define cond_le32_to_cpu(v) \
599         (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
600 #else
601 #define cond_le32_to_cpu(v) le32_to_cpu(v)
602 #endif
603
604 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
605 {
606         struct fw_ohci *ohci = ctx->ohci;
607         struct fw_packet p;
608         u32 status, length, tcode;
609         int evt;
610
611         p.header[0] = cond_le32_to_cpu(buffer[0]);
612         p.header[1] = cond_le32_to_cpu(buffer[1]);
613         p.header[2] = cond_le32_to_cpu(buffer[2]);
614
615         tcode = (p.header[0] >> 4) & 0x0f;
616         switch (tcode) {
617         case TCODE_WRITE_QUADLET_REQUEST:
618         case TCODE_READ_QUADLET_RESPONSE:
619                 p.header[3] = (__force __u32) buffer[3];
620                 p.header_length = 16;
621                 p.payload_length = 0;
622                 break;
623
624         case TCODE_READ_BLOCK_REQUEST :
625                 p.header[3] = cond_le32_to_cpu(buffer[3]);
626                 p.header_length = 16;
627                 p.payload_length = 0;
628                 break;
629
630         case TCODE_WRITE_BLOCK_REQUEST:
631         case TCODE_READ_BLOCK_RESPONSE:
632         case TCODE_LOCK_REQUEST:
633         case TCODE_LOCK_RESPONSE:
634                 p.header[3] = cond_le32_to_cpu(buffer[3]);
635                 p.header_length = 16;
636                 p.payload_length = p.header[3] >> 16;
637                 break;
638
639         case TCODE_WRITE_RESPONSE:
640         case TCODE_READ_QUADLET_REQUEST:
641         case OHCI_TCODE_PHY_PACKET:
642                 p.header_length = 12;
643                 p.payload_length = 0;
644                 break;
645
646         default:
647                 /* FIXME: Stop context, discard everything, and restart? */
648                 p.header_length = 0;
649                 p.payload_length = 0;
650         }
651
652         p.payload = (void *) buffer + p.header_length;
653
654         /* FIXME: What to do about evt_* errors? */
655         length = (p.header_length + p.payload_length + 3) / 4;
656         status = cond_le32_to_cpu(buffer[length]);
657         evt    = (status >> 16) & 0x1f;
658
659         p.ack        = evt - 16;
660         p.speed      = (status >> 21) & 0x7;
661         p.timestamp  = status & 0xffff;
662         p.generation = ohci->request_generation;
663
664         log_ar_at_event('R', p.speed, p.header, evt);
665
666         /*
667          * The OHCI bus reset handler synthesizes a phy packet with
668          * the new generation number when a bus reset happens (see
669          * section 8.4.2.3).  This helps us determine when a request
670          * was received and make sure we send the response in the same
671          * generation.  We only need this for requests; for responses
672          * we use the unique tlabel for finding the matching
673          * request.
674          *
675          * Alas some chips sometimes emit bus reset packets with a
676          * wrong generation.  We set the correct generation for these
677          * at a slightly incorrect time (in bus_reset_tasklet).
678          */
679         if (evt == OHCI1394_evt_bus_reset) {
680                 if (!(ohci->quirks & QUIRK_RESET_PACKET))
681                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
682         } else if (ctx == &ohci->ar_request_ctx) {
683                 fw_core_handle_request(&ohci->card, &p);
684         } else {
685                 fw_core_handle_response(&ohci->card, &p);
686         }
687
688         return buffer + length + 1;
689 }
690
691 static void ar_context_tasklet(unsigned long data)
692 {
693         struct ar_context *ctx = (struct ar_context *)data;
694         struct fw_ohci *ohci = ctx->ohci;
695         struct ar_buffer *ab;
696         struct descriptor *d;
697         void *buffer, *end;
698
699         ab = ctx->current_buffer;
700         d = &ab->descriptor;
701
702         if (d->res_count == 0) {
703                 size_t size, rest, offset;
704                 dma_addr_t start_bus;
705                 void *start;
706
707                 /*
708                  * This descriptor is finished and we may have a
709                  * packet split across this and the next buffer. We
710                  * reuse the page for reassembling the split packet.
711                  */
712
713                 offset = offsetof(struct ar_buffer, data);
714                 start = buffer = ab;
715                 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
716
717                 ab = ab->next;
718                 d = &ab->descriptor;
719                 size = buffer + PAGE_SIZE - ctx->pointer;
720                 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
721                 memmove(buffer, ctx->pointer, size);
722                 memcpy(buffer + size, ab->data, rest);
723                 ctx->current_buffer = ab;
724                 ctx->pointer = (void *) ab->data + rest;
725                 end = buffer + size + rest;
726
727                 while (buffer < end)
728                         buffer = handle_ar_packet(ctx, buffer);
729
730                 dma_free_coherent(ohci->card.device, PAGE_SIZE,
731                                   start, start_bus);
732                 ar_context_add_page(ctx);
733         } else {
734                 buffer = ctx->pointer;
735                 ctx->pointer = end =
736                         (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
737
738                 while (buffer < end)
739                         buffer = handle_ar_packet(ctx, buffer);
740         }
741 }
742
743 static int ar_context_init(struct ar_context *ctx,
744                            struct fw_ohci *ohci, u32 regs)
745 {
746         struct ar_buffer ab;
747
748         ctx->regs        = regs;
749         ctx->ohci        = ohci;
750         ctx->last_buffer = &ab;
751         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
752
753         ar_context_add_page(ctx);
754         ar_context_add_page(ctx);
755         ctx->current_buffer = ab.next;
756         ctx->pointer = ctx->current_buffer->data;
757
758         return 0;
759 }
760
761 static void ar_context_run(struct ar_context *ctx)
762 {
763         struct ar_buffer *ab = ctx->current_buffer;
764         dma_addr_t ab_bus;
765         size_t offset;
766
767         offset = offsetof(struct ar_buffer, data);
768         ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
769
770         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
771         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
772         flush_writes(ctx->ohci);
773 }
774
775 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
776 {
777         int b, key;
778
779         b   = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
780         key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
781
782         /* figure out which descriptor the branch address goes in */
783         if (z == 2 && (b == 3 || key == 2))
784                 return d;
785         else
786                 return d + z - 1;
787 }
788
789 static void context_tasklet(unsigned long data)
790 {
791         struct context *ctx = (struct context *) data;
792         struct descriptor *d, *last;
793         u32 address;
794         int z;
795         struct descriptor_buffer *desc;
796
797         desc = list_entry(ctx->buffer_list.next,
798                         struct descriptor_buffer, list);
799         last = ctx->last;
800         while (last->branch_address != 0) {
801                 struct descriptor_buffer *old_desc = desc;
802                 address = le32_to_cpu(last->branch_address);
803                 z = address & 0xf;
804                 address &= ~0xf;
805
806                 /* If the branch address points to a buffer outside of the
807                  * current buffer, advance to the next buffer. */
808                 if (address < desc->buffer_bus ||
809                                 address >= desc->buffer_bus + desc->used)
810                         desc = list_entry(desc->list.next,
811                                         struct descriptor_buffer, list);
812                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
813                 last = find_branch_descriptor(d, z);
814
815                 if (!ctx->callback(ctx, d, last))
816                         break;
817
818                 if (old_desc != desc) {
819                         /* If we've advanced to the next buffer, move the
820                          * previous buffer to the free list. */
821                         unsigned long flags;
822                         old_desc->used = 0;
823                         spin_lock_irqsave(&ctx->ohci->lock, flags);
824                         list_move_tail(&old_desc->list, &ctx->buffer_list);
825                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
826                 }
827                 ctx->last = last;
828         }
829 }
830
831 /*
832  * Allocate a new buffer and add it to the list of free buffers for this
833  * context.  Must be called with ohci->lock held.
834  */
835 static int context_add_buffer(struct context *ctx)
836 {
837         struct descriptor_buffer *desc;
838         dma_addr_t uninitialized_var(bus_addr);
839         int offset;
840
841         /*
842          * 16MB of descriptors should be far more than enough for any DMA
843          * program.  This will catch run-away userspace or DoS attacks.
844          */
845         if (ctx->total_allocation >= 16*1024*1024)
846                 return -ENOMEM;
847
848         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
849                         &bus_addr, GFP_ATOMIC);
850         if (!desc)
851                 return -ENOMEM;
852
853         offset = (void *)&desc->buffer - (void *)desc;
854         desc->buffer_size = PAGE_SIZE - offset;
855         desc->buffer_bus = bus_addr + offset;
856         desc->used = 0;
857
858         list_add_tail(&desc->list, &ctx->buffer_list);
859         ctx->total_allocation += PAGE_SIZE;
860
861         return 0;
862 }
863
864 static int context_init(struct context *ctx, struct fw_ohci *ohci,
865                         u32 regs, descriptor_callback_t callback)
866 {
867         ctx->ohci = ohci;
868         ctx->regs = regs;
869         ctx->total_allocation = 0;
870
871         INIT_LIST_HEAD(&ctx->buffer_list);
872         if (context_add_buffer(ctx) < 0)
873                 return -ENOMEM;
874
875         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
876                         struct descriptor_buffer, list);
877
878         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
879         ctx->callback = callback;
880
881         /*
882          * We put a dummy descriptor in the buffer that has a NULL
883          * branch address and looks like it's been sent.  That way we
884          * have a descriptor to append DMA programs to.
885          */
886         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
887         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
888         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
889         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
890         ctx->last = ctx->buffer_tail->buffer;
891         ctx->prev = ctx->buffer_tail->buffer;
892
893         return 0;
894 }
895
896 static void context_release(struct context *ctx)
897 {
898         struct fw_card *card = &ctx->ohci->card;
899         struct descriptor_buffer *desc, *tmp;
900
901         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
902                 dma_free_coherent(card->device, PAGE_SIZE, desc,
903                         desc->buffer_bus -
904                         ((void *)&desc->buffer - (void *)desc));
905 }
906
907 /* Must be called with ohci->lock held */
908 static struct descriptor *context_get_descriptors(struct context *ctx,
909                                                   int z, dma_addr_t *d_bus)
910 {
911         struct descriptor *d = NULL;
912         struct descriptor_buffer *desc = ctx->buffer_tail;
913
914         if (z * sizeof(*d) > desc->buffer_size)
915                 return NULL;
916
917         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
918                 /* No room for the descriptor in this buffer, so advance to the
919                  * next one. */
920
921                 if (desc->list.next == &ctx->buffer_list) {
922                         /* If there is no free buffer next in the list,
923                          * allocate one. */
924                         if (context_add_buffer(ctx) < 0)
925                                 return NULL;
926                 }
927                 desc = list_entry(desc->list.next,
928                                 struct descriptor_buffer, list);
929                 ctx->buffer_tail = desc;
930         }
931
932         d = desc->buffer + desc->used / sizeof(*d);
933         memset(d, 0, z * sizeof(*d));
934         *d_bus = desc->buffer_bus + desc->used;
935
936         return d;
937 }
938
939 static void context_run(struct context *ctx, u32 extra)
940 {
941         struct fw_ohci *ohci = ctx->ohci;
942
943         reg_write(ohci, COMMAND_PTR(ctx->regs),
944                   le32_to_cpu(ctx->last->branch_address));
945         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
946         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
947         flush_writes(ohci);
948 }
949
950 static void context_append(struct context *ctx,
951                            struct descriptor *d, int z, int extra)
952 {
953         dma_addr_t d_bus;
954         struct descriptor_buffer *desc = ctx->buffer_tail;
955
956         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
957
958         desc->used += (z + extra) * sizeof(*d);
959         ctx->prev->branch_address = cpu_to_le32(d_bus | z);
960         ctx->prev = find_branch_descriptor(d, z);
961
962         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
963         flush_writes(ctx->ohci);
964 }
965
966 static void context_stop(struct context *ctx)
967 {
968         u32 reg;
969         int i;
970
971         reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
972         flush_writes(ctx->ohci);
973
974         for (i = 0; i < 10; i++) {
975                 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
976                 if ((reg & CONTEXT_ACTIVE) == 0)
977                         return;
978
979                 mdelay(1);
980         }
981         fw_error("Error: DMA context still active (0x%08x)\n", reg);
982 }
983
984 struct driver_data {
985         struct fw_packet *packet;
986 };
987
988 /*
989  * This function apppends a packet to the DMA queue for transmission.
990  * Must always be called with the ochi->lock held to ensure proper
991  * generation handling and locking around packet queue manipulation.
992  */
993 static int at_context_queue_packet(struct context *ctx,
994                                    struct fw_packet *packet)
995 {
996         struct fw_ohci *ohci = ctx->ohci;
997         dma_addr_t d_bus, uninitialized_var(payload_bus);
998         struct driver_data *driver_data;
999         struct descriptor *d, *last;
1000         __le32 *header;
1001         int z, tcode;
1002         u32 reg;
1003
1004         d = context_get_descriptors(ctx, 4, &d_bus);
1005         if (d == NULL) {
1006                 packet->ack = RCODE_SEND_ERROR;
1007                 return -1;
1008         }
1009
1010         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1011         d[0].res_count = cpu_to_le16(packet->timestamp);
1012
1013         /*
1014          * The DMA format for asyncronous link packets is different
1015          * from the IEEE1394 layout, so shift the fields around
1016          * accordingly.  If header_length is 8, it's a PHY packet, to
1017          * which we need to prepend an extra quadlet.
1018          */
1019
1020         header = (__le32 *) &d[1];
1021         switch (packet->header_length) {
1022         case 16:
1023         case 12:
1024                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1025                                         (packet->speed << 16));
1026                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1027                                         (packet->header[0] & 0xffff0000));
1028                 header[2] = cpu_to_le32(packet->header[2]);
1029
1030                 tcode = (packet->header[0] >> 4) & 0x0f;
1031                 if (TCODE_IS_BLOCK_PACKET(tcode))
1032                         header[3] = cpu_to_le32(packet->header[3]);
1033                 else
1034                         header[3] = (__force __le32) packet->header[3];
1035
1036                 d[0].req_count = cpu_to_le16(packet->header_length);
1037                 break;
1038
1039         case 8:
1040                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1041                                         (packet->speed << 16));
1042                 header[1] = cpu_to_le32(packet->header[0]);
1043                 header[2] = cpu_to_le32(packet->header[1]);
1044                 d[0].req_count = cpu_to_le16(12);
1045                 break;
1046
1047         case 4:
1048                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1049                                         (packet->speed << 16));
1050                 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1051                 d[0].req_count = cpu_to_le16(8);
1052                 break;
1053
1054         default:
1055                 /* BUG(); */
1056                 packet->ack = RCODE_SEND_ERROR;
1057                 return -1;
1058         }
1059
1060         driver_data = (struct driver_data *) &d[3];
1061         driver_data->packet = packet;
1062         packet->driver_data = driver_data;
1063
1064         if (packet->payload_length > 0) {
1065                 payload_bus =
1066                         dma_map_single(ohci->card.device, packet->payload,
1067                                        packet->payload_length, DMA_TO_DEVICE);
1068                 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1069                         packet->ack = RCODE_SEND_ERROR;
1070                         return -1;
1071                 }
1072                 packet->payload_bus     = payload_bus;
1073                 packet->payload_mapped  = true;
1074
1075                 d[2].req_count    = cpu_to_le16(packet->payload_length);
1076                 d[2].data_address = cpu_to_le32(payload_bus);
1077                 last = &d[2];
1078                 z = 3;
1079         } else {
1080                 last = &d[0];
1081                 z = 2;
1082         }
1083
1084         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1085                                      DESCRIPTOR_IRQ_ALWAYS |
1086                                      DESCRIPTOR_BRANCH_ALWAYS);
1087
1088         /*
1089          * If the controller and packet generations don't match, we need to
1090          * bail out and try again.  If IntEvent.busReset is set, the AT context
1091          * is halted, so appending to the context and trying to run it is
1092          * futile.  Most controllers do the right thing and just flush the AT
1093          * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1094          * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1095          * up stalling out.  So we just bail out in software and try again
1096          * later, and everyone is happy.
1097          * FIXME: Document how the locking works.
1098          */
1099         if (ohci->generation != packet->generation ||
1100             reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1101                 if (packet->payload_mapped)
1102                         dma_unmap_single(ohci->card.device, payload_bus,
1103                                          packet->payload_length, DMA_TO_DEVICE);
1104                 packet->ack = RCODE_GENERATION;
1105                 return -1;
1106         }
1107
1108         context_append(ctx, d, z, 4 - z);
1109
1110         /* If the context isn't already running, start it up. */
1111         reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1112         if ((reg & CONTEXT_RUN) == 0)
1113                 context_run(ctx, 0);
1114
1115         return 0;
1116 }
1117
1118 static int handle_at_packet(struct context *context,
1119                             struct descriptor *d,
1120                             struct descriptor *last)
1121 {
1122         struct driver_data *driver_data;
1123         struct fw_packet *packet;
1124         struct fw_ohci *ohci = context->ohci;
1125         int evt;
1126
1127         if (last->transfer_status == 0)
1128                 /* This descriptor isn't done yet, stop iteration. */
1129                 return 0;
1130
1131         driver_data = (struct driver_data *) &d[3];
1132         packet = driver_data->packet;
1133         if (packet == NULL)
1134                 /* This packet was cancelled, just continue. */
1135                 return 1;
1136
1137         if (packet->payload_mapped)
1138                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1139                                  packet->payload_length, DMA_TO_DEVICE);
1140
1141         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1142         packet->timestamp = le16_to_cpu(last->res_count);
1143
1144         log_ar_at_event('T', packet->speed, packet->header, evt);
1145
1146         switch (evt) {
1147         case OHCI1394_evt_timeout:
1148                 /* Async response transmit timed out. */
1149                 packet->ack = RCODE_CANCELLED;
1150                 break;
1151
1152         case OHCI1394_evt_flushed:
1153                 /*
1154                  * The packet was flushed should give same error as
1155                  * when we try to use a stale generation count.
1156                  */
1157                 packet->ack = RCODE_GENERATION;
1158                 break;
1159
1160         case OHCI1394_evt_missing_ack:
1161                 /*
1162                  * Using a valid (current) generation count, but the
1163                  * node is not on the bus or not sending acks.
1164                  */
1165                 packet->ack = RCODE_NO_ACK;
1166                 break;
1167
1168         case ACK_COMPLETE + 0x10:
1169         case ACK_PENDING + 0x10:
1170         case ACK_BUSY_X + 0x10:
1171         case ACK_BUSY_A + 0x10:
1172         case ACK_BUSY_B + 0x10:
1173         case ACK_DATA_ERROR + 0x10:
1174         case ACK_TYPE_ERROR + 0x10:
1175                 packet->ack = evt - 0x10;
1176                 break;
1177
1178         default:
1179                 packet->ack = RCODE_SEND_ERROR;
1180                 break;
1181         }
1182
1183         packet->callback(packet, &ohci->card, packet->ack);
1184
1185         return 1;
1186 }
1187
1188 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1189 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1190 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1191 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1192 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1193
1194 static void handle_local_rom(struct fw_ohci *ohci,
1195                              struct fw_packet *packet, u32 csr)
1196 {
1197         struct fw_packet response;
1198         int tcode, length, i;
1199
1200         tcode = HEADER_GET_TCODE(packet->header[0]);
1201         if (TCODE_IS_BLOCK_PACKET(tcode))
1202                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1203         else
1204                 length = 4;
1205
1206         i = csr - CSR_CONFIG_ROM;
1207         if (i + length > CONFIG_ROM_SIZE) {
1208                 fw_fill_response(&response, packet->header,
1209                                  RCODE_ADDRESS_ERROR, NULL, 0);
1210         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1211                 fw_fill_response(&response, packet->header,
1212                                  RCODE_TYPE_ERROR, NULL, 0);
1213         } else {
1214                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1215                                  (void *) ohci->config_rom + i, length);
1216         }
1217
1218         fw_core_handle_response(&ohci->card, &response);
1219 }
1220
1221 static void handle_local_lock(struct fw_ohci *ohci,
1222                               struct fw_packet *packet, u32 csr)
1223 {
1224         struct fw_packet response;
1225         int tcode, length, ext_tcode, sel;
1226         __be32 *payload, lock_old;
1227         u32 lock_arg, lock_data;
1228
1229         tcode = HEADER_GET_TCODE(packet->header[0]);
1230         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1231         payload = packet->payload;
1232         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1233
1234         if (tcode == TCODE_LOCK_REQUEST &&
1235             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1236                 lock_arg = be32_to_cpu(payload[0]);
1237                 lock_data = be32_to_cpu(payload[1]);
1238         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1239                 lock_arg = 0;
1240                 lock_data = 0;
1241         } else {
1242                 fw_fill_response(&response, packet->header,
1243                                  RCODE_TYPE_ERROR, NULL, 0);
1244                 goto out;
1245         }
1246
1247         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1248         reg_write(ohci, OHCI1394_CSRData, lock_data);
1249         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1250         reg_write(ohci, OHCI1394_CSRControl, sel);
1251
1252         if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1253                 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1254         else
1255                 fw_notify("swap not done yet\n");
1256
1257         fw_fill_response(&response, packet->header,
1258                          RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1259  out:
1260         fw_core_handle_response(&ohci->card, &response);
1261 }
1262
1263 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1264 {
1265         u64 offset;
1266         u32 csr;
1267
1268         if (ctx == &ctx->ohci->at_request_ctx) {
1269                 packet->ack = ACK_PENDING;
1270                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1271         }
1272
1273         offset =
1274                 ((unsigned long long)
1275                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1276                 packet->header[2];
1277         csr = offset - CSR_REGISTER_BASE;
1278
1279         /* Handle config rom reads. */
1280         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1281                 handle_local_rom(ctx->ohci, packet, csr);
1282         else switch (csr) {
1283         case CSR_BUS_MANAGER_ID:
1284         case CSR_BANDWIDTH_AVAILABLE:
1285         case CSR_CHANNELS_AVAILABLE_HI:
1286         case CSR_CHANNELS_AVAILABLE_LO:
1287                 handle_local_lock(ctx->ohci, packet, csr);
1288                 break;
1289         default:
1290                 if (ctx == &ctx->ohci->at_request_ctx)
1291                         fw_core_handle_request(&ctx->ohci->card, packet);
1292                 else
1293                         fw_core_handle_response(&ctx->ohci->card, packet);
1294                 break;
1295         }
1296
1297         if (ctx == &ctx->ohci->at_response_ctx) {
1298                 packet->ack = ACK_COMPLETE;
1299                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1300         }
1301 }
1302
1303 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1304 {
1305         unsigned long flags;
1306         int ret;
1307
1308         spin_lock_irqsave(&ctx->ohci->lock, flags);
1309
1310         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1311             ctx->ohci->generation == packet->generation) {
1312                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1313                 handle_local_request(ctx, packet);
1314                 return;
1315         }
1316
1317         ret = at_context_queue_packet(ctx, packet);
1318         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1319
1320         if (ret < 0)
1321                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1322
1323 }
1324
1325 static u32 cycle_timer_ticks(u32 cycle_timer)
1326 {
1327         u32 ticks;
1328
1329         ticks = cycle_timer & 0xfff;
1330         ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1331         ticks += (3072 * 8000) * (cycle_timer >> 25);
1332
1333         return ticks;
1334 }
1335
1336 /*
1337  * Some controllers exhibit one or more of the following bugs when updating the
1338  * iso cycle timer register:
1339  *  - When the lowest six bits are wrapping around to zero, a read that happens
1340  *    at the same time will return garbage in the lowest ten bits.
1341  *  - When the cycleOffset field wraps around to zero, the cycleCount field is
1342  *    not incremented for about 60 ns.
1343  *  - Occasionally, the entire register reads zero.
1344  *
1345  * To catch these, we read the register three times and ensure that the
1346  * difference between each two consecutive reads is approximately the same, i.e.
1347  * less than twice the other.  Furthermore, any negative difference indicates an
1348  * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1349  * execute, so we have enough precision to compute the ratio of the differences.)
1350  */
1351 static u32 get_cycle_time(struct fw_ohci *ohci)
1352 {
1353         u32 c0, c1, c2;
1354         u32 t0, t1, t2;
1355         s32 diff01, diff12;
1356         int i;
1357
1358         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1359
1360         if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1361                 i = 0;
1362                 c1 = c2;
1363                 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1364                 do {
1365                         c0 = c1;
1366                         c1 = c2;
1367                         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1368                         t0 = cycle_timer_ticks(c0);
1369                         t1 = cycle_timer_ticks(c1);
1370                         t2 = cycle_timer_ticks(c2);
1371                         diff01 = t1 - t0;
1372                         diff12 = t2 - t1;
1373                 } while ((diff01 <= 0 || diff12 <= 0 ||
1374                           diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1375                          && i++ < 20);
1376         }
1377
1378         return c2;
1379 }
1380
1381 /*
1382  * This function has to be called at least every 64 seconds.  The bus_time
1383  * field stores not only the upper 25 bits of the BUS_TIME register but also
1384  * the most significant bit of the cycle timer in bit 6 so that we can detect
1385  * changes in this bit.
1386  */
1387 static u32 update_bus_time(struct fw_ohci *ohci)
1388 {
1389         u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1390
1391         if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1392                 ohci->bus_time += 0x40;
1393
1394         return ohci->bus_time | cycle_time_seconds;
1395 }
1396
1397 static void bus_reset_tasklet(unsigned long data)
1398 {
1399         struct fw_ohci *ohci = (struct fw_ohci *)data;
1400         int self_id_count, i, j, reg;
1401         int generation, new_generation;
1402         unsigned long flags;
1403         void *free_rom = NULL;
1404         dma_addr_t free_rom_bus = 0;
1405         bool is_new_root;
1406
1407         reg = reg_read(ohci, OHCI1394_NodeID);
1408         if (!(reg & OHCI1394_NodeID_idValid)) {
1409                 fw_notify("node ID not valid, new bus reset in progress\n");
1410                 return;
1411         }
1412         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1413                 fw_notify("malconfigured bus\n");
1414                 return;
1415         }
1416         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1417                                OHCI1394_NodeID_nodeNumber);
1418
1419         is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1420         if (!(ohci->is_root && is_new_root))
1421                 reg_write(ohci, OHCI1394_LinkControlSet,
1422                           OHCI1394_LinkControl_cycleMaster);
1423         ohci->is_root = is_new_root;
1424
1425         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1426         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1427                 fw_notify("inconsistent self IDs\n");
1428                 return;
1429         }
1430         /*
1431          * The count in the SelfIDCount register is the number of
1432          * bytes in the self ID receive buffer.  Since we also receive
1433          * the inverted quadlets and a header quadlet, we shift one
1434          * bit extra to get the actual number of self IDs.
1435          */
1436         self_id_count = (reg >> 3) & 0xff;
1437         if (self_id_count == 0 || self_id_count > 252) {
1438                 fw_notify("inconsistent self IDs\n");
1439                 return;
1440         }
1441         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1442         rmb();
1443
1444         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1445                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1446                         fw_notify("inconsistent self IDs\n");
1447                         return;
1448                 }
1449                 ohci->self_id_buffer[j] =
1450                                 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1451         }
1452         rmb();
1453
1454         /*
1455          * Check the consistency of the self IDs we just read.  The
1456          * problem we face is that a new bus reset can start while we
1457          * read out the self IDs from the DMA buffer. If this happens,
1458          * the DMA buffer will be overwritten with new self IDs and we
1459          * will read out inconsistent data.  The OHCI specification
1460          * (section 11.2) recommends a technique similar to
1461          * linux/seqlock.h, where we remember the generation of the
1462          * self IDs in the buffer before reading them out and compare
1463          * it to the current generation after reading them out.  If
1464          * the two generations match we know we have a consistent set
1465          * of self IDs.
1466          */
1467
1468         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1469         if (new_generation != generation) {
1470                 fw_notify("recursive bus reset detected, "
1471                           "discarding self ids\n");
1472                 return;
1473         }
1474
1475         /* FIXME: Document how the locking works. */
1476         spin_lock_irqsave(&ohci->lock, flags);
1477
1478         ohci->generation = generation;
1479         context_stop(&ohci->at_request_ctx);
1480         context_stop(&ohci->at_response_ctx);
1481         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1482
1483         if (ohci->quirks & QUIRK_RESET_PACKET)
1484                 ohci->request_generation = generation;
1485
1486         /*
1487          * This next bit is unrelated to the AT context stuff but we
1488          * have to do it under the spinlock also.  If a new config rom
1489          * was set up before this reset, the old one is now no longer
1490          * in use and we can free it. Update the config rom pointers
1491          * to point to the current config rom and clear the
1492          * next_config_rom pointer so a new udpate can take place.
1493          */
1494
1495         if (ohci->next_config_rom != NULL) {
1496                 if (ohci->next_config_rom != ohci->config_rom) {
1497                         free_rom      = ohci->config_rom;
1498                         free_rom_bus  = ohci->config_rom_bus;
1499                 }
1500                 ohci->config_rom      = ohci->next_config_rom;
1501                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
1502                 ohci->next_config_rom = NULL;
1503
1504                 /*
1505                  * Restore config_rom image and manually update
1506                  * config_rom registers.  Writing the header quadlet
1507                  * will indicate that the config rom is ready, so we
1508                  * do that last.
1509                  */
1510                 reg_write(ohci, OHCI1394_BusOptions,
1511                           be32_to_cpu(ohci->config_rom[2]));
1512                 ohci->config_rom[0] = ohci->next_header;
1513                 reg_write(ohci, OHCI1394_ConfigROMhdr,
1514                           be32_to_cpu(ohci->next_header));
1515         }
1516
1517 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1518         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1519         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1520 #endif
1521
1522         spin_unlock_irqrestore(&ohci->lock, flags);
1523
1524         if (free_rom)
1525                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1526                                   free_rom, free_rom_bus);
1527
1528         log_selfids(ohci->node_id, generation,
1529                     self_id_count, ohci->self_id_buffer);
1530
1531         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1532                                  self_id_count, ohci->self_id_buffer);
1533 }
1534
1535 static irqreturn_t irq_handler(int irq, void *data)
1536 {
1537         struct fw_ohci *ohci = data;
1538         u32 event, iso_event;
1539         int i;
1540
1541         event = reg_read(ohci, OHCI1394_IntEventClear);
1542
1543         if (!event || !~event)
1544                 return IRQ_NONE;
1545
1546         /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1547         reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1548         log_irqs(event);
1549
1550         if (event & OHCI1394_selfIDComplete)
1551                 tasklet_schedule(&ohci->bus_reset_tasklet);
1552
1553         if (event & OHCI1394_RQPkt)
1554                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1555
1556         if (event & OHCI1394_RSPkt)
1557                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1558
1559         if (event & OHCI1394_reqTxComplete)
1560                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1561
1562         if (event & OHCI1394_respTxComplete)
1563                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1564
1565         iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1566         reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1567
1568         while (iso_event) {
1569                 i = ffs(iso_event) - 1;
1570                 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1571                 iso_event &= ~(1 << i);
1572         }
1573
1574         iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1575         reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1576
1577         while (iso_event) {
1578                 i = ffs(iso_event) - 1;
1579                 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1580                 iso_event &= ~(1 << i);
1581         }
1582
1583         if (unlikely(event & OHCI1394_regAccessFail))
1584                 fw_error("Register access failure - "
1585                          "please notify linux1394-devel@lists.sf.net\n");
1586
1587         if (unlikely(event & OHCI1394_postedWriteErr))
1588                 fw_error("PCI posted write error\n");
1589
1590         if (unlikely(event & OHCI1394_cycleTooLong)) {
1591                 if (printk_ratelimit())
1592                         fw_notify("isochronous cycle too long\n");
1593                 reg_write(ohci, OHCI1394_LinkControlSet,
1594                           OHCI1394_LinkControl_cycleMaster);
1595         }
1596
1597         if (unlikely(event & OHCI1394_cycleInconsistent)) {
1598                 /*
1599                  * We need to clear this event bit in order to make
1600                  * cycleMatch isochronous I/O work.  In theory we should
1601                  * stop active cycleMatch iso contexts now and restart
1602                  * them at least two cycles later.  (FIXME?)
1603                  */
1604                 if (printk_ratelimit())
1605                         fw_notify("isochronous cycle inconsistent\n");
1606         }
1607
1608         if (event & OHCI1394_cycle64Seconds) {
1609                 spin_lock(&ohci->lock);
1610                 update_bus_time(ohci);
1611                 spin_unlock(&ohci->lock);
1612         }
1613
1614         return IRQ_HANDLED;
1615 }
1616
1617 static int software_reset(struct fw_ohci *ohci)
1618 {
1619         int i;
1620
1621         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1622
1623         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1624                 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1625                      OHCI1394_HCControl_softReset) == 0)
1626                         return 0;
1627                 msleep(1);
1628         }
1629
1630         return -EBUSY;
1631 }
1632
1633 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1634 {
1635         size_t size = length * 4;
1636
1637         memcpy(dest, src, size);
1638         if (size < CONFIG_ROM_SIZE)
1639                 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1640 }
1641
1642 static int configure_1394a_enhancements(struct fw_ohci *ohci)
1643 {
1644         bool enable_1394a;
1645         int ret, clear, set, offset;
1646
1647         /* Check if the driver should configure link and PHY. */
1648         if (!(reg_read(ohci, OHCI1394_HCControlSet) &
1649               OHCI1394_HCControl_programPhyEnable))
1650                 return 0;
1651
1652         /* Paranoia: check whether the PHY supports 1394a, too. */
1653         enable_1394a = false;
1654         ret = read_phy_reg(ohci, 2);
1655         if (ret < 0)
1656                 return ret;
1657         if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
1658                 ret = read_paged_phy_reg(ohci, 1, 8);
1659                 if (ret < 0)
1660                         return ret;
1661                 if (ret >= 1)
1662                         enable_1394a = true;
1663         }
1664
1665         if (ohci->quirks & QUIRK_NO_1394A)
1666                 enable_1394a = false;
1667
1668         /* Configure PHY and link consistently. */
1669         if (enable_1394a) {
1670                 clear = 0;
1671                 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1672         } else {
1673                 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1674                 set = 0;
1675         }
1676         ret = ohci_update_phy_reg(&ohci->card, 5, clear, set);
1677         if (ret < 0)
1678                 return ret;
1679
1680         if (enable_1394a)
1681                 offset = OHCI1394_HCControlSet;
1682         else
1683                 offset = OHCI1394_HCControlClear;
1684         reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
1685
1686         /* Clean up: configuration has been taken care of. */
1687         reg_write(ohci, OHCI1394_HCControlClear,
1688                   OHCI1394_HCControl_programPhyEnable);
1689
1690         return 0;
1691 }
1692
1693 static int ohci_enable(struct fw_card *card,
1694                        const __be32 *config_rom, size_t length)
1695 {
1696         struct fw_ohci *ohci = fw_ohci(card);
1697         struct pci_dev *dev = to_pci_dev(card->device);
1698         u32 lps, seconds, version, irqs;
1699         int i, ret;
1700
1701         if (software_reset(ohci)) {
1702                 fw_error("Failed to reset ohci card.\n");
1703                 return -EBUSY;
1704         }
1705
1706         /*
1707          * Now enable LPS, which we need in order to start accessing
1708          * most of the registers.  In fact, on some cards (ALI M5251),
1709          * accessing registers in the SClk domain without LPS enabled
1710          * will lock up the machine.  Wait 50msec to make sure we have
1711          * full link enabled.  However, with some cards (well, at least
1712          * a JMicron PCIe card), we have to try again sometimes.
1713          */
1714         reg_write(ohci, OHCI1394_HCControlSet,
1715                   OHCI1394_HCControl_LPS |
1716                   OHCI1394_HCControl_postedWriteEnable);
1717         flush_writes(ohci);
1718
1719         for (lps = 0, i = 0; !lps && i < 3; i++) {
1720                 msleep(50);
1721                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1722                       OHCI1394_HCControl_LPS;
1723         }
1724
1725         if (!lps) {
1726                 fw_error("Failed to set Link Power Status\n");
1727                 return -EIO;
1728         }
1729
1730         reg_write(ohci, OHCI1394_HCControlClear,
1731                   OHCI1394_HCControl_noByteSwapData);
1732
1733         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1734         reg_write(ohci, OHCI1394_LinkControlClear,
1735                   OHCI1394_LinkControl_rcvPhyPkt);
1736         reg_write(ohci, OHCI1394_LinkControlSet,
1737                   OHCI1394_LinkControl_rcvSelfID |
1738                   OHCI1394_LinkControl_cycleTimerEnable |
1739                   OHCI1394_LinkControl_cycleMaster);
1740
1741         reg_write(ohci, OHCI1394_ATRetries,
1742                   OHCI1394_MAX_AT_REQ_RETRIES |
1743                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1744                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
1745                   (200 << 16));
1746
1747         seconds = lower_32_bits(get_seconds());
1748         reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
1749         ohci->bus_time = seconds & ~0x3f;
1750
1751         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
1752         if (version >= OHCI_VERSION_1_1) {
1753                 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
1754                           0xfffffffe);
1755                 ohci->features |= FEATURE_CHANNEL_31_ALLOCATED;
1756         }
1757
1758         /* Get implemented bits of the priority arbitration request counter. */
1759         reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
1760         ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
1761         reg_write(ohci, OHCI1394_FairnessControl, 0);
1762         if (ohci->pri_req_max != 0)
1763                 ohci->features |= FEATURE_PRIORITY_BUDGET;
1764
1765         ar_context_run(&ohci->ar_request_ctx);
1766         ar_context_run(&ohci->ar_response_ctx);
1767
1768         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1769         reg_write(ohci, OHCI1394_IntEventClear, ~0);
1770         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1771
1772         ret = configure_1394a_enhancements(ohci);
1773         if (ret < 0)
1774                 return ret;
1775
1776         /* Activate link_on bit and contender bit in our self ID packets.*/
1777         ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
1778         if (ret < 0)
1779                 return ret;
1780
1781         /*
1782          * When the link is not yet enabled, the atomic config rom
1783          * update mechanism described below in ohci_set_config_rom()
1784          * is not active.  We have to update ConfigRomHeader and
1785          * BusOptions manually, and the write to ConfigROMmap takes
1786          * effect immediately.  We tie this to the enabling of the
1787          * link, so we have a valid config rom before enabling - the
1788          * OHCI requires that ConfigROMhdr and BusOptions have valid
1789          * values before enabling.
1790          *
1791          * However, when the ConfigROMmap is written, some controllers
1792          * always read back quadlets 0 and 2 from the config rom to
1793          * the ConfigRomHeader and BusOptions registers on bus reset.
1794          * They shouldn't do that in this initial case where the link
1795          * isn't enabled.  This means we have to use the same
1796          * workaround here, setting the bus header to 0 and then write
1797          * the right values in the bus reset tasklet.
1798          */
1799
1800         if (config_rom) {
1801                 ohci->next_config_rom =
1802                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1803                                            &ohci->next_config_rom_bus,
1804                                            GFP_KERNEL);
1805                 if (ohci->next_config_rom == NULL)
1806                         return -ENOMEM;
1807
1808                 copy_config_rom(ohci->next_config_rom, config_rom, length);
1809         } else {
1810                 /*
1811                  * In the suspend case, config_rom is NULL, which
1812                  * means that we just reuse the old config rom.
1813                  */
1814                 ohci->next_config_rom = ohci->config_rom;
1815                 ohci->next_config_rom_bus = ohci->config_rom_bus;
1816         }
1817
1818         ohci->next_header = ohci->next_config_rom[0];
1819         ohci->next_config_rom[0] = 0;
1820         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1821         reg_write(ohci, OHCI1394_BusOptions,
1822                   be32_to_cpu(ohci->next_config_rom[2]));
1823         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1824
1825         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1826
1827         if (!(ohci->quirks & QUIRK_NO_MSI))
1828                 pci_enable_msi(dev);
1829         if (request_irq(dev->irq, irq_handler,
1830                         pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
1831                         ohci_driver_name, ohci)) {
1832                 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
1833                 pci_disable_msi(dev);
1834                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1835                                   ohci->config_rom, ohci->config_rom_bus);
1836                 return -EIO;
1837         }
1838
1839         irqs =  OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1840                 OHCI1394_RQPkt | OHCI1394_RSPkt |
1841                 OHCI1394_isochTx | OHCI1394_isochRx |
1842                 OHCI1394_postedWriteErr |
1843                 OHCI1394_selfIDComplete |
1844                 OHCI1394_regAccessFail |
1845                 OHCI1394_cycle64Seconds |
1846                 OHCI1394_cycleInconsistent | OHCI1394_cycleTooLong |
1847                 OHCI1394_masterIntEnable;
1848         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1849                 irqs |= OHCI1394_busReset;
1850         reg_write(ohci, OHCI1394_IntMaskSet, irqs);
1851
1852         reg_write(ohci, OHCI1394_HCControlSet,
1853                   OHCI1394_HCControl_linkEnable |
1854                   OHCI1394_HCControl_BIBimageValid);
1855         flush_writes(ohci);
1856
1857         /*
1858          * We are ready to go, initiate bus reset to finish the
1859          * initialization.
1860          */
1861
1862         fw_core_initiate_bus_reset(&ohci->card, 1);
1863
1864         return 0;
1865 }
1866
1867 static int ohci_set_config_rom(struct fw_card *card,
1868                                const __be32 *config_rom, size_t length)
1869 {
1870         struct fw_ohci *ohci;
1871         unsigned long flags;
1872         int ret = -EBUSY;
1873         __be32 *next_config_rom;
1874         dma_addr_t uninitialized_var(next_config_rom_bus);
1875
1876         ohci = fw_ohci(card);
1877
1878         /*
1879          * When the OHCI controller is enabled, the config rom update
1880          * mechanism is a bit tricky, but easy enough to use.  See
1881          * section 5.5.6 in the OHCI specification.
1882          *
1883          * The OHCI controller caches the new config rom address in a
1884          * shadow register (ConfigROMmapNext) and needs a bus reset
1885          * for the changes to take place.  When the bus reset is
1886          * detected, the controller loads the new values for the
1887          * ConfigRomHeader and BusOptions registers from the specified
1888          * config rom and loads ConfigROMmap from the ConfigROMmapNext
1889          * shadow register. All automatically and atomically.
1890          *
1891          * Now, there's a twist to this story.  The automatic load of
1892          * ConfigRomHeader and BusOptions doesn't honor the
1893          * noByteSwapData bit, so with a be32 config rom, the
1894          * controller will load be32 values in to these registers
1895          * during the atomic update, even on litte endian
1896          * architectures.  The workaround we use is to put a 0 in the
1897          * header quadlet; 0 is endian agnostic and means that the
1898          * config rom isn't ready yet.  In the bus reset tasklet we
1899          * then set up the real values for the two registers.
1900          *
1901          * We use ohci->lock to avoid racing with the code that sets
1902          * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1903          */
1904
1905         next_config_rom =
1906                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1907                                    &next_config_rom_bus, GFP_KERNEL);
1908         if (next_config_rom == NULL)
1909                 return -ENOMEM;
1910
1911         spin_lock_irqsave(&ohci->lock, flags);
1912
1913         if (ohci->next_config_rom == NULL) {
1914                 ohci->next_config_rom = next_config_rom;
1915                 ohci->next_config_rom_bus = next_config_rom_bus;
1916
1917                 copy_config_rom(ohci->next_config_rom, config_rom, length);
1918
1919                 ohci->next_header = config_rom[0];
1920                 ohci->next_config_rom[0] = 0;
1921
1922                 reg_write(ohci, OHCI1394_ConfigROMmap,
1923                           ohci->next_config_rom_bus);
1924                 ret = 0;
1925         }
1926
1927         spin_unlock_irqrestore(&ohci->lock, flags);
1928
1929         /*
1930          * Now initiate a bus reset to have the changes take
1931          * effect. We clean up the old config rom memory and DMA
1932          * mappings in the bus reset tasklet, since the OHCI
1933          * controller could need to access it before the bus reset
1934          * takes effect.
1935          */
1936         if (ret == 0)
1937                 fw_core_initiate_bus_reset(&ohci->card, 1);
1938         else
1939                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1940                                   next_config_rom, next_config_rom_bus);
1941
1942         return ret;
1943 }
1944
1945 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1946 {
1947         struct fw_ohci *ohci = fw_ohci(card);
1948
1949         at_context_transmit(&ohci->at_request_ctx, packet);
1950 }
1951
1952 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1953 {
1954         struct fw_ohci *ohci = fw_ohci(card);
1955
1956         at_context_transmit(&ohci->at_response_ctx, packet);
1957 }
1958
1959 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1960 {
1961         struct fw_ohci *ohci = fw_ohci(card);
1962         struct context *ctx = &ohci->at_request_ctx;
1963         struct driver_data *driver_data = packet->driver_data;
1964         int ret = -ENOENT;
1965
1966         tasklet_disable(&ctx->tasklet);
1967
1968         if (packet->ack != 0)
1969                 goto out;
1970
1971         if (packet->payload_mapped)
1972                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1973                                  packet->payload_length, DMA_TO_DEVICE);
1974
1975         log_ar_at_event('T', packet->speed, packet->header, 0x20);
1976         driver_data->packet = NULL;
1977         packet->ack = RCODE_CANCELLED;
1978         packet->callback(packet, &ohci->card, packet->ack);
1979         ret = 0;
1980  out:
1981         tasklet_enable(&ctx->tasklet);
1982
1983         return ret;
1984 }
1985
1986 static int ohci_enable_phys_dma(struct fw_card *card,
1987                                 int node_id, int generation)
1988 {
1989 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1990         return 0;
1991 #else
1992         struct fw_ohci *ohci = fw_ohci(card);
1993         unsigned long flags;
1994         int n, ret = 0;
1995
1996         /*
1997          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
1998          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
1999          */
2000
2001         spin_lock_irqsave(&ohci->lock, flags);
2002
2003         if (ohci->generation != generation) {
2004                 ret = -ESTALE;
2005                 goto out;
2006         }
2007
2008         /*
2009          * Note, if the node ID contains a non-local bus ID, physical DMA is
2010          * enabled for _all_ nodes on remote buses.
2011          */
2012
2013         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2014         if (n < 32)
2015                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2016         else
2017                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2018
2019         flush_writes(ohci);
2020  out:
2021         spin_unlock_irqrestore(&ohci->lock, flags);
2022
2023         return ret;
2024 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2025 }
2026
2027 static u32 ohci_read_csr_reg(struct fw_card *card, int csr_offset)
2028 {
2029         struct fw_ohci *ohci = fw_ohci(card);
2030         unsigned long flags;
2031         u32 value;
2032
2033         switch (csr_offset) {
2034         case CSR_STATE_CLEAR:
2035         case CSR_STATE_SET:
2036                 /* the controller driver handles only the cmstr bit */
2037                 if (ohci->is_root &&
2038                     (reg_read(ohci, OHCI1394_LinkControlSet) &
2039                      OHCI1394_LinkControl_cycleMaster))
2040                         return CSR_STATE_BIT_CMSTR;
2041                 else
2042                         return 0;
2043
2044         case CSR_NODE_IDS:
2045                 return reg_read(ohci, OHCI1394_NodeID) << 16;
2046
2047         case CSR_CYCLE_TIME:
2048                 return get_cycle_time(ohci);
2049
2050         case CSR_BUS_TIME:
2051                 /*
2052                  * We might be called just after the cycle timer has wrapped
2053                  * around but just before the cycle64Seconds handler, so we
2054                  * better check here, too, if the bus time needs to be updated.
2055                  */
2056                 spin_lock_irqsave(&ohci->lock, flags);
2057                 value = update_bus_time(ohci);
2058                 spin_unlock_irqrestore(&ohci->lock, flags);
2059                 return value;
2060
2061         case CSR_BUSY_TIMEOUT:
2062                 value = reg_read(ohci, OHCI1394_ATRetries);
2063                 return (value >> 4) & 0x0ffff00f;
2064
2065         case CSR_PRIORITY_BUDGET:
2066                 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2067                         (ohci->pri_req_max << 8);
2068
2069         default:
2070                 WARN_ON(1);
2071                 return 0;
2072         }
2073 }
2074
2075 static void ohci_write_csr_reg(struct fw_card *card, int csr_offset, u32 value)
2076 {
2077         struct fw_ohci *ohci = fw_ohci(card);
2078         unsigned long flags;
2079
2080         switch (csr_offset) {
2081         case CSR_STATE_CLEAR:
2082                 /* the controller driver handles only the cmstr bit */
2083                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2084                         reg_write(ohci, OHCI1394_LinkControlClear,
2085                                   OHCI1394_LinkControl_cycleMaster);
2086                         flush_writes(ohci);
2087                 }
2088                 break;
2089
2090         case CSR_STATE_SET:
2091                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2092                         reg_write(ohci, OHCI1394_LinkControlSet,
2093                                   OHCI1394_LinkControl_cycleMaster);
2094                         flush_writes(ohci);
2095                 }
2096                 break;
2097
2098         case CSR_NODE_IDS:
2099                 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2100                 flush_writes(ohci);
2101                 break;
2102
2103         case CSR_CYCLE_TIME:
2104                 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2105                 reg_write(ohci, OHCI1394_IntEventSet,
2106                           OHCI1394_cycleInconsistent);
2107                 flush_writes(ohci);
2108                 break;
2109
2110         case CSR_BUS_TIME:
2111                 spin_lock_irqsave(&ohci->lock, flags);
2112                 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2113                 spin_unlock_irqrestore(&ohci->lock, flags);
2114                 break;
2115
2116         case CSR_BUSY_TIMEOUT:
2117                 value = (value & 0xf) | ((value & 0xf) << 4) |
2118                         ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2119                 reg_write(ohci, OHCI1394_ATRetries, value);
2120                 flush_writes(ohci);
2121                 break;
2122
2123         case CSR_PRIORITY_BUDGET:
2124                 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2125                 flush_writes(ohci);
2126                 break;
2127
2128         default:
2129                 WARN_ON(1);
2130                 break;
2131         }
2132 }
2133
2134 static unsigned int ohci_get_features(struct fw_card *card)
2135 {
2136         struct fw_ohci *ohci = fw_ohci(card);
2137
2138         return ohci->features;
2139 }
2140
2141 static void copy_iso_headers(struct iso_context *ctx, void *p)
2142 {
2143         int i = ctx->header_length;
2144
2145         if (i + ctx->base.header_size > PAGE_SIZE)
2146                 return;
2147
2148         /*
2149          * The iso header is byteswapped to little endian by
2150          * the controller, but the remaining header quadlets
2151          * are big endian.  We want to present all the headers
2152          * as big endian, so we have to swap the first quadlet.
2153          */
2154         if (ctx->base.header_size > 0)
2155                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2156         if (ctx->base.header_size > 4)
2157                 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2158         if (ctx->base.header_size > 8)
2159                 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2160         ctx->header_length += ctx->base.header_size;
2161 }
2162
2163 static int handle_ir_packet_per_buffer(struct context *context,
2164                                        struct descriptor *d,
2165                                        struct descriptor *last)
2166 {
2167         struct iso_context *ctx =
2168                 container_of(context, struct iso_context, context);
2169         struct descriptor *pd;
2170         __le32 *ir_header;
2171         void *p;
2172
2173         for (pd = d; pd <= last; pd++) {
2174                 if (pd->transfer_status)
2175                         break;
2176         }
2177         if (pd > last)
2178                 /* Descriptor(s) not done yet, stop iteration */
2179                 return 0;
2180
2181         p = last + 1;
2182         copy_iso_headers(ctx, p);
2183
2184         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2185                 ir_header = (__le32 *) p;
2186                 ctx->base.callback(&ctx->base,
2187                                    le32_to_cpu(ir_header[0]) & 0xffff,
2188                                    ctx->header_length, ctx->header,
2189                                    ctx->base.callback_data);
2190                 ctx->header_length = 0;
2191         }
2192
2193         return 1;
2194 }
2195
2196 static int handle_it_packet(struct context *context,
2197                             struct descriptor *d,
2198                             struct descriptor *last)
2199 {
2200         struct iso_context *ctx =
2201                 container_of(context, struct iso_context, context);
2202         int i;
2203         struct descriptor *pd;
2204
2205         for (pd = d; pd <= last; pd++)
2206                 if (pd->transfer_status)
2207                         break;
2208         if (pd > last)
2209                 /* Descriptor(s) not done yet, stop iteration */
2210                 return 0;
2211
2212         i = ctx->header_length;
2213         if (i + 4 < PAGE_SIZE) {
2214                 /* Present this value as big-endian to match the receive code */
2215                 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2216                                 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2217                                 le16_to_cpu(pd->res_count));
2218                 ctx->header_length += 4;
2219         }
2220         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2221                 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
2222                                    ctx->header_length, ctx->header,
2223                                    ctx->base.callback_data);
2224                 ctx->header_length = 0;
2225         }
2226         return 1;
2227 }
2228
2229 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2230                                 int type, int channel, size_t header_size)
2231 {
2232         struct fw_ohci *ohci = fw_ohci(card);
2233         struct iso_context *ctx, *list;
2234         descriptor_callback_t callback;
2235         u64 *channels, dont_care = ~0ULL;
2236         u32 *mask, regs;
2237         unsigned long flags;
2238         int index, ret = -ENOMEM;
2239
2240         if (type == FW_ISO_CONTEXT_TRANSMIT) {
2241                 channels = &dont_care;
2242                 mask = &ohci->it_context_mask;
2243                 list = ohci->it_context_list;
2244                 callback = handle_it_packet;
2245         } else {
2246                 channels = &ohci->ir_context_channels;
2247                 mask = &ohci->ir_context_mask;
2248                 list = ohci->ir_context_list;
2249                 callback = handle_ir_packet_per_buffer;
2250         }
2251
2252         spin_lock_irqsave(&ohci->lock, flags);
2253         index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2254         if (index >= 0) {
2255                 *channels &= ~(1ULL << channel);
2256                 *mask &= ~(1 << index);
2257         }
2258         spin_unlock_irqrestore(&ohci->lock, flags);
2259
2260         if (index < 0)
2261                 return ERR_PTR(-EBUSY);
2262
2263         if (type == FW_ISO_CONTEXT_TRANSMIT)
2264                 regs = OHCI1394_IsoXmitContextBase(index);
2265         else
2266                 regs = OHCI1394_IsoRcvContextBase(index);
2267
2268         ctx = &list[index];
2269         memset(ctx, 0, sizeof(*ctx));
2270         ctx->header_length = 0;
2271         ctx->header = (void *) __get_free_page(GFP_KERNEL);
2272         if (ctx->header == NULL)
2273                 goto out;
2274
2275         ret = context_init(&ctx->context, ohci, regs, callback);
2276         if (ret < 0)
2277                 goto out_with_header;
2278
2279         return &ctx->base;
2280
2281  out_with_header:
2282         free_page((unsigned long)ctx->header);
2283  out:
2284         spin_lock_irqsave(&ohci->lock, flags);
2285         *mask |= 1 << index;
2286         spin_unlock_irqrestore(&ohci->lock, flags);
2287
2288         return ERR_PTR(ret);
2289 }
2290
2291 static int ohci_start_iso(struct fw_iso_context *base,
2292                           s32 cycle, u32 sync, u32 tags)
2293 {
2294         struct iso_context *ctx = container_of(base, struct iso_context, base);
2295         struct fw_ohci *ohci = ctx->context.ohci;
2296         u32 control, match;
2297         int index;
2298
2299         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2300                 index = ctx - ohci->it_context_list;
2301                 match = 0;
2302                 if (cycle >= 0)
2303                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2304                                 (cycle & 0x7fff) << 16;
2305
2306                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2307                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2308                 context_run(&ctx->context, match);
2309         } else {
2310                 index = ctx - ohci->ir_context_list;
2311                 control = IR_CONTEXT_ISOCH_HEADER;
2312                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2313                 if (cycle >= 0) {
2314                         match |= (cycle & 0x07fff) << 12;
2315                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2316                 }
2317
2318                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2319                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2320                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2321                 context_run(&ctx->context, control);
2322         }
2323
2324         return 0;
2325 }
2326
2327 static int ohci_stop_iso(struct fw_iso_context *base)
2328 {
2329         struct fw_ohci *ohci = fw_ohci(base->card);
2330         struct iso_context *ctx = container_of(base, struct iso_context, base);
2331         int index;
2332
2333         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2334                 index = ctx - ohci->it_context_list;
2335                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2336         } else {
2337                 index = ctx - ohci->ir_context_list;
2338                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2339         }
2340         flush_writes(ohci);
2341         context_stop(&ctx->context);
2342
2343         return 0;
2344 }
2345
2346 static void ohci_free_iso_context(struct fw_iso_context *base)
2347 {
2348         struct fw_ohci *ohci = fw_ohci(base->card);
2349         struct iso_context *ctx = container_of(base, struct iso_context, base);
2350         unsigned long flags;
2351         int index;
2352
2353         ohci_stop_iso(base);
2354         context_release(&ctx->context);
2355         free_page((unsigned long)ctx->header);
2356
2357         spin_lock_irqsave(&ohci->lock, flags);
2358
2359         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2360                 index = ctx - ohci->it_context_list;
2361                 ohci->it_context_mask |= 1 << index;
2362         } else {
2363                 index = ctx - ohci->ir_context_list;
2364                 ohci->ir_context_mask |= 1 << index;
2365                 ohci->ir_context_channels |= 1ULL << base->channel;
2366         }
2367
2368         spin_unlock_irqrestore(&ohci->lock, flags);
2369 }
2370
2371 static int ohci_queue_iso_transmit(struct fw_iso_context *base,
2372                                    struct fw_iso_packet *packet,
2373                                    struct fw_iso_buffer *buffer,
2374                                    unsigned long payload)
2375 {
2376         struct iso_context *ctx = container_of(base, struct iso_context, base);
2377         struct descriptor *d, *last, *pd;
2378         struct fw_iso_packet *p;
2379         __le32 *header;
2380         dma_addr_t d_bus, page_bus;
2381         u32 z, header_z, payload_z, irq;
2382         u32 payload_index, payload_end_index, next_page_index;
2383         int page, end_page, i, length, offset;
2384
2385         p = packet;
2386         payload_index = payload;
2387
2388         if (p->skip)
2389                 z = 1;
2390         else
2391                 z = 2;
2392         if (p->header_length > 0)
2393                 z++;
2394
2395         /* Determine the first page the payload isn't contained in. */
2396         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2397         if (p->payload_length > 0)
2398                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2399         else
2400                 payload_z = 0;
2401
2402         z += payload_z;
2403
2404         /* Get header size in number of descriptors. */
2405         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2406
2407         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2408         if (d == NULL)
2409                 return -ENOMEM;
2410
2411         if (!p->skip) {
2412                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2413                 d[0].req_count = cpu_to_le16(8);
2414                 /*
2415                  * Link the skip address to this descriptor itself.  This causes
2416                  * a context to skip a cycle whenever lost cycles or FIFO
2417                  * overruns occur, without dropping the data.  The application
2418                  * should then decide whether this is an error condition or not.
2419                  * FIXME:  Make the context's cycle-lost behaviour configurable?
2420                  */
2421                 d[0].branch_address = cpu_to_le32(d_bus | z);
2422
2423                 header = (__le32 *) &d[1];
2424                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2425                                         IT_HEADER_TAG(p->tag) |
2426                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2427                                         IT_HEADER_CHANNEL(ctx->base.channel) |
2428                                         IT_HEADER_SPEED(ctx->base.speed));
2429                 header[1] =
2430                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2431                                                           p->payload_length));
2432         }
2433
2434         if (p->header_length > 0) {
2435                 d[2].req_count    = cpu_to_le16(p->header_length);
2436                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2437                 memcpy(&d[z], p->header, p->header_length);
2438         }
2439
2440         pd = d + z - payload_z;
2441         payload_end_index = payload_index + p->payload_length;
2442         for (i = 0; i < payload_z; i++) {
2443                 page               = payload_index >> PAGE_SHIFT;
2444                 offset             = payload_index & ~PAGE_MASK;
2445                 next_page_index    = (page + 1) << PAGE_SHIFT;
2446                 length             =
2447                         min(next_page_index, payload_end_index) - payload_index;
2448                 pd[i].req_count    = cpu_to_le16(length);
2449
2450                 page_bus = page_private(buffer->pages[page]);
2451                 pd[i].data_address = cpu_to_le32(page_bus + offset);
2452
2453                 payload_index += length;
2454         }
2455
2456         if (p->interrupt)
2457                 irq = DESCRIPTOR_IRQ_ALWAYS;
2458         else
2459                 irq = DESCRIPTOR_NO_IRQ;
2460
2461         last = z == 2 ? d : d + z - 1;
2462         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2463                                      DESCRIPTOR_STATUS |
2464                                      DESCRIPTOR_BRANCH_ALWAYS |
2465                                      irq);
2466
2467         context_append(&ctx->context, d, z, header_z);
2468
2469         return 0;
2470 }
2471
2472 static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2473                                         struct fw_iso_packet *packet,
2474                                         struct fw_iso_buffer *buffer,
2475                                         unsigned long payload)
2476 {
2477         struct iso_context *ctx = container_of(base, struct iso_context, base);
2478         struct descriptor *d, *pd;
2479         struct fw_iso_packet *p = packet;
2480         dma_addr_t d_bus, page_bus;
2481         u32 z, header_z, rest;
2482         int i, j, length;
2483         int page, offset, packet_count, header_size, payload_per_buffer;
2484
2485         /*
2486          * The OHCI controller puts the isochronous header and trailer in the
2487          * buffer, so we need at least 8 bytes.
2488          */
2489         packet_count = p->header_length / ctx->base.header_size;
2490         header_size  = max(ctx->base.header_size, (size_t)8);
2491
2492         /* Get header size in number of descriptors. */
2493         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2494         page     = payload >> PAGE_SHIFT;
2495         offset   = payload & ~PAGE_MASK;
2496         payload_per_buffer = p->payload_length / packet_count;
2497
2498         for (i = 0; i < packet_count; i++) {
2499                 /* d points to the header descriptor */
2500                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2501                 d = context_get_descriptors(&ctx->context,
2502                                 z + header_z, &d_bus);
2503                 if (d == NULL)
2504                         return -ENOMEM;
2505
2506                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
2507                                               DESCRIPTOR_INPUT_MORE);
2508                 if (p->skip && i == 0)
2509                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2510                 d->req_count    = cpu_to_le16(header_size);
2511                 d->res_count    = d->req_count;
2512                 d->transfer_status = 0;
2513                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2514
2515                 rest = payload_per_buffer;
2516                 pd = d;
2517                 for (j = 1; j < z; j++) {
2518                         pd++;
2519                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2520                                                   DESCRIPTOR_INPUT_MORE);
2521
2522                         if (offset + rest < PAGE_SIZE)
2523                                 length = rest;
2524                         else
2525                                 length = PAGE_SIZE - offset;
2526                         pd->req_count = cpu_to_le16(length);
2527                         pd->res_count = pd->req_count;
2528                         pd->transfer_status = 0;
2529
2530                         page_bus = page_private(buffer->pages[page]);
2531                         pd->data_address = cpu_to_le32(page_bus + offset);
2532
2533                         offset = (offset + length) & ~PAGE_MASK;
2534                         rest -= length;
2535                         if (offset == 0)
2536                                 page++;
2537                 }
2538                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2539                                           DESCRIPTOR_INPUT_LAST |
2540                                           DESCRIPTOR_BRANCH_ALWAYS);
2541                 if (p->interrupt && i == packet_count - 1)
2542                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2543
2544                 context_append(&ctx->context, d, z, header_z);
2545         }
2546
2547         return 0;
2548 }
2549
2550 static int ohci_queue_iso(struct fw_iso_context *base,
2551                           struct fw_iso_packet *packet,
2552                           struct fw_iso_buffer *buffer,
2553                           unsigned long payload)
2554 {
2555         struct iso_context *ctx = container_of(base, struct iso_context, base);
2556         unsigned long flags;
2557         int ret;
2558
2559         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2560         if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2561                 ret = ohci_queue_iso_transmit(base, packet, buffer, payload);
2562         else
2563                 ret = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2564                                                         buffer, payload);
2565         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2566
2567         return ret;
2568 }
2569
2570 static const struct fw_card_driver ohci_driver = {
2571         .enable                 = ohci_enable,
2572         .update_phy_reg         = ohci_update_phy_reg,
2573         .set_config_rom         = ohci_set_config_rom,
2574         .send_request           = ohci_send_request,
2575         .send_response          = ohci_send_response,
2576         .cancel_packet          = ohci_cancel_packet,
2577         .enable_phys_dma        = ohci_enable_phys_dma,
2578         .read_csr_reg           = ohci_read_csr_reg,
2579         .write_csr_reg          = ohci_write_csr_reg,
2580         .get_features           = ohci_get_features,
2581
2582         .allocate_iso_context   = ohci_allocate_iso_context,
2583         .free_iso_context       = ohci_free_iso_context,
2584         .queue_iso              = ohci_queue_iso,
2585         .start_iso              = ohci_start_iso,
2586         .stop_iso               = ohci_stop_iso,
2587 };
2588
2589 #ifdef CONFIG_PPC_PMAC
2590 static void pmac_ohci_on(struct pci_dev *dev)
2591 {
2592         if (machine_is(powermac)) {
2593                 struct device_node *ofn = pci_device_to_OF_node(dev);
2594
2595                 if (ofn) {
2596                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2597                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2598                 }
2599         }
2600 }
2601
2602 static void pmac_ohci_off(struct pci_dev *dev)
2603 {
2604         if (machine_is(powermac)) {
2605                 struct device_node *ofn = pci_device_to_OF_node(dev);
2606
2607                 if (ofn) {
2608                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2609                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2610                 }
2611         }
2612 }
2613 #else
2614 static inline void pmac_ohci_on(struct pci_dev *dev) {}
2615 static inline void pmac_ohci_off(struct pci_dev *dev) {}
2616 #endif /* CONFIG_PPC_PMAC */
2617
2618 static int __devinit pci_probe(struct pci_dev *dev,
2619                                const struct pci_device_id *ent)
2620 {
2621         struct fw_ohci *ohci;
2622         u32 bus_options, max_receive, link_speed, version, link_enh;
2623         u64 guid;
2624         int i, err, n_ir, n_it;
2625         size_t size;
2626
2627         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2628         if (ohci == NULL) {
2629                 err = -ENOMEM;
2630                 goto fail;
2631         }
2632
2633         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2634
2635         pmac_ohci_on(dev);
2636
2637         err = pci_enable_device(dev);
2638         if (err) {
2639                 fw_error("Failed to enable OHCI hardware\n");
2640                 goto fail_free;
2641         }
2642
2643         pci_set_master(dev);
2644         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2645         pci_set_drvdata(dev, ohci);
2646
2647         spin_lock_init(&ohci->lock);
2648
2649         tasklet_init(&ohci->bus_reset_tasklet,
2650                      bus_reset_tasklet, (unsigned long)ohci);
2651
2652         err = pci_request_region(dev, 0, ohci_driver_name);
2653         if (err) {
2654                 fw_error("MMIO resource unavailable\n");
2655                 goto fail_disable;
2656         }
2657
2658         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2659         if (ohci->registers == NULL) {
2660                 fw_error("Failed to remap registers\n");
2661                 err = -ENXIO;
2662                 goto fail_iomem;
2663         }
2664
2665         for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
2666                 if (ohci_quirks[i].vendor == dev->vendor &&
2667                     (ohci_quirks[i].device == dev->device ||
2668                      ohci_quirks[i].device == (unsigned short)PCI_ANY_ID)) {
2669                         ohci->quirks = ohci_quirks[i].flags;
2670                         break;
2671                 }
2672         if (param_quirks)
2673                 ohci->quirks = param_quirks;
2674
2675         /* TI OHCI-Lynx and compatible: set recommended configuration bits. */
2676         if (dev->vendor == PCI_VENDOR_ID_TI) {
2677                 pci_read_config_dword(dev, PCI_CFG_TI_LinkEnh, &link_enh);
2678
2679                 /* adjust latency of ATx FIFO: use 1.7 KB threshold */
2680                 link_enh &= ~TI_LinkEnh_atx_thresh_mask;
2681                 link_enh |= TI_LinkEnh_atx_thresh_1_7K;
2682
2683                 /* use priority arbitration for asynchronous responses */
2684                 link_enh |= TI_LinkEnh_enab_unfair;
2685
2686                 /* required for aPhyEnhanceEnable to work */
2687                 link_enh |= TI_LinkEnh_enab_accel;
2688
2689                 pci_write_config_dword(dev, PCI_CFG_TI_LinkEnh, link_enh);
2690         }
2691
2692         ar_context_init(&ohci->ar_request_ctx, ohci,
2693                         OHCI1394_AsReqRcvContextControlSet);
2694
2695         ar_context_init(&ohci->ar_response_ctx, ohci,
2696                         OHCI1394_AsRspRcvContextControlSet);
2697
2698         context_init(&ohci->at_request_ctx, ohci,
2699                      OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2700
2701         context_init(&ohci->at_response_ctx, ohci,
2702                      OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2703
2704         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2705         ohci->ir_context_channels = ~0ULL;
2706         ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2707         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2708         n_ir = hweight32(ohci->ir_context_mask);
2709         size = sizeof(struct iso_context) * n_ir;
2710         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2711
2712         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2713         ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2714         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2715         n_it = hweight32(ohci->it_context_mask);
2716         size = sizeof(struct iso_context) * n_it;
2717         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2718
2719         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2720                 err = -ENOMEM;
2721                 goto fail_contexts;
2722         }
2723
2724         /* self-id dma buffer allocation */
2725         ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2726                                                SELF_ID_BUF_SIZE,
2727                                                &ohci->self_id_bus,
2728                                                GFP_KERNEL);
2729         if (ohci->self_id_cpu == NULL) {
2730                 err = -ENOMEM;
2731                 goto fail_contexts;
2732         }
2733
2734         bus_options = reg_read(ohci, OHCI1394_BusOptions);
2735         max_receive = (bus_options >> 12) & 0xf;
2736         link_speed = bus_options & 0x7;
2737         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2738                 reg_read(ohci, OHCI1394_GUIDLo);
2739
2740         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2741         if (err)
2742                 goto fail_self_id;
2743
2744         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2745         fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
2746                   "%d IR + %d IT contexts, quirks 0x%x\n",
2747                   dev_name(&dev->dev), version >> 16, version & 0xff,
2748                   n_ir, n_it, ohci->quirks);
2749
2750         return 0;
2751
2752  fail_self_id:
2753         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2754                           ohci->self_id_cpu, ohci->self_id_bus);
2755  fail_contexts:
2756         kfree(ohci->ir_context_list);
2757         kfree(ohci->it_context_list);
2758         context_release(&ohci->at_response_ctx);
2759         context_release(&ohci->at_request_ctx);
2760         ar_context_release(&ohci->ar_response_ctx);
2761         ar_context_release(&ohci->ar_request_ctx);
2762         pci_iounmap(dev, ohci->registers);
2763  fail_iomem:
2764         pci_release_region(dev, 0);
2765  fail_disable:
2766         pci_disable_device(dev);
2767  fail_free:
2768         kfree(&ohci->card);
2769         pmac_ohci_off(dev);
2770  fail:
2771         if (err == -ENOMEM)
2772                 fw_error("Out of memory\n");
2773
2774         return err;
2775 }
2776
2777 static void pci_remove(struct pci_dev *dev)
2778 {
2779         struct fw_ohci *ohci;
2780
2781         ohci = pci_get_drvdata(dev);
2782         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2783         flush_writes(ohci);
2784         fw_core_remove_card(&ohci->card);
2785
2786         /*
2787          * FIXME: Fail all pending packets here, now that the upper
2788          * layers can't queue any more.
2789          */
2790
2791         software_reset(ohci);
2792         free_irq(dev->irq, ohci);
2793
2794         if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
2795                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2796                                   ohci->next_config_rom, ohci->next_config_rom_bus);
2797         if (ohci->config_rom)
2798                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2799                                   ohci->config_rom, ohci->config_rom_bus);
2800         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2801                           ohci->self_id_cpu, ohci->self_id_bus);
2802         ar_context_release(&ohci->ar_request_ctx);
2803         ar_context_release(&ohci->ar_response_ctx);
2804         context_release(&ohci->at_request_ctx);
2805         context_release(&ohci->at_response_ctx);
2806         kfree(ohci->it_context_list);
2807         kfree(ohci->ir_context_list);
2808         pci_disable_msi(dev);
2809         pci_iounmap(dev, ohci->registers);
2810         pci_release_region(dev, 0);
2811         pci_disable_device(dev);
2812         kfree(&ohci->card);
2813         pmac_ohci_off(dev);
2814
2815         fw_notify("Removed fw-ohci device.\n");
2816 }
2817
2818 #ifdef CONFIG_PM
2819 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2820 {
2821         struct fw_ohci *ohci = pci_get_drvdata(dev);
2822         int err;
2823
2824         software_reset(ohci);
2825         free_irq(dev->irq, ohci);
2826         pci_disable_msi(dev);
2827         err = pci_save_state(dev);
2828         if (err) {
2829                 fw_error("pci_save_state failed\n");
2830                 return err;
2831         }
2832         err = pci_set_power_state(dev, pci_choose_state(dev, state));
2833         if (err)
2834                 fw_error("pci_set_power_state failed with %d\n", err);
2835         pmac_ohci_off(dev);
2836
2837         return 0;
2838 }
2839
2840 static int pci_resume(struct pci_dev *dev)
2841 {
2842         struct fw_ohci *ohci = pci_get_drvdata(dev);
2843         int err;
2844
2845         pmac_ohci_on(dev);
2846         pci_set_power_state(dev, PCI_D0);
2847         pci_restore_state(dev);
2848         err = pci_enable_device(dev);
2849         if (err) {
2850                 fw_error("pci_enable_device failed\n");
2851                 return err;
2852         }
2853
2854         return ohci_enable(&ohci->card, NULL, 0);
2855 }
2856 #endif
2857
2858 static const struct pci_device_id pci_table[] = {
2859         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2860         { }
2861 };
2862
2863 MODULE_DEVICE_TABLE(pci, pci_table);
2864
2865 static struct pci_driver fw_ohci_pci_driver = {
2866         .name           = ohci_driver_name,
2867         .id_table       = pci_table,
2868         .probe          = pci_probe,
2869         .remove         = pci_remove,
2870 #ifdef CONFIG_PM
2871         .resume         = pci_resume,
2872         .suspend        = pci_suspend,
2873 #endif
2874 };
2875
2876 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2877 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2878 MODULE_LICENSE("GPL");
2879
2880 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2881 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2882 MODULE_ALIAS("ohci1394");
2883 #endif
2884
2885 static int __init fw_ohci_init(void)
2886 {
2887         return pci_register_driver(&fw_ohci_pci_driver);
2888 }
2889
2890 static void __exit fw_ohci_cleanup(void)
2891 {
2892         pci_unregister_driver(&fw_ohci_pci_driver);
2893 }
2894
2895 module_init(fw_ohci_init);
2896 module_exit(fw_ohci_cleanup);