firewire: Implement proper transaction cancelation.
[linux-2.6.git] / drivers / firewire / fw-ohci.c
1 /*                                              -*- c-basic-offset: 8 -*-
2  *
3  * fw-ohci.c - Driver for OHCI 1394 boards
4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software Foundation,
18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
25 #include <linux/pci.h>
26 #include <linux/delay.h>
27 #include <linux/poll.h>
28 #include <linux/dma-mapping.h>
29
30 #include <asm/uaccess.h>
31 #include <asm/semaphore.h>
32
33 #include "fw-transaction.h"
34 #include "fw-ohci.h"
35
36 #define descriptor_output_more          0
37 #define descriptor_output_last          (1 << 12)
38 #define descriptor_input_more           (2 << 12)
39 #define descriptor_input_last           (3 << 12)
40 #define descriptor_status               (1 << 11)
41 #define descriptor_key_immediate        (2 << 8)
42 #define descriptor_ping                 (1 << 7)
43 #define descriptor_yy                   (1 << 6)
44 #define descriptor_no_irq               (0 << 4)
45 #define descriptor_irq_error            (1 << 4)
46 #define descriptor_irq_always           (3 << 4)
47 #define descriptor_branch_always        (3 << 2)
48
49 struct descriptor {
50         __le16 req_count;
51         __le16 control;
52         __le32 data_address;
53         __le32 branch_address;
54         __le16 res_count;
55         __le16 transfer_status;
56 } __attribute__((aligned(16)));
57
58 #define control_set(regs)       (regs)
59 #define control_clear(regs)     ((regs) + 4)
60 #define command_ptr(regs)       ((regs) + 12)
61 #define context_match(regs)     ((regs) + 16)
62
63 struct ar_buffer {
64         struct descriptor descriptor;
65         struct ar_buffer *next;
66         __le32 data[0];
67 };
68
69 struct ar_context {
70         struct fw_ohci *ohci;
71         struct ar_buffer *current_buffer;
72         struct ar_buffer *last_buffer;
73         void *pointer;
74         u32 regs;
75         struct tasklet_struct tasklet;
76 };
77
78 struct at_context {
79         struct fw_ohci *ohci;
80         dma_addr_t descriptor_bus;
81         dma_addr_t buffer_bus;
82         struct fw_packet *current_packet;
83
84         struct list_head list;
85
86         struct {
87                 struct descriptor more;
88                 __le32 header[4];
89                 struct descriptor last;
90         } d;
91
92         u32 regs;
93
94         struct tasklet_struct tasklet;
95 };
96
97 #define it_header_sy(v)          ((v) <<  0)
98 #define it_header_tcode(v)       ((v) <<  4)
99 #define it_header_channel(v)     ((v) <<  8)
100 #define it_header_tag(v)         ((v) << 14)
101 #define it_header_speed(v)       ((v) << 16)
102 #define it_header_data_length(v) ((v) << 16)
103
104 struct iso_context {
105         struct fw_iso_context base;
106         struct tasklet_struct tasklet;
107         u32 regs;
108
109         struct descriptor *buffer;
110         dma_addr_t buffer_bus;
111         struct descriptor *head_descriptor;
112         struct descriptor *tail_descriptor;
113         struct descriptor *tail_descriptor_last;
114         struct descriptor *prev_descriptor;
115 };
116
117 #define CONFIG_ROM_SIZE 1024
118
119 struct fw_ohci {
120         struct fw_card card;
121
122         __iomem char *registers;
123         dma_addr_t self_id_bus;
124         __le32 *self_id_cpu;
125         struct tasklet_struct bus_reset_tasklet;
126         int node_id;
127         int generation;
128         int request_generation;
129
130         /* Spinlock for accessing fw_ohci data.  Never call out of
131          * this driver with this lock held. */
132         spinlock_t lock;
133         u32 self_id_buffer[512];
134
135         /* Config rom buffers */
136         __be32 *config_rom;
137         dma_addr_t config_rom_bus;
138         __be32 *next_config_rom;
139         dma_addr_t next_config_rom_bus;
140         u32 next_header;
141
142         struct ar_context ar_request_ctx;
143         struct ar_context ar_response_ctx;
144         struct at_context at_request_ctx;
145         struct at_context at_response_ctx;
146
147         u32 it_context_mask;
148         struct iso_context *it_context_list;
149         u32 ir_context_mask;
150         struct iso_context *ir_context_list;
151 };
152
153 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
154 {
155         return container_of(card, struct fw_ohci, card);
156 }
157
158 #define CONTEXT_CYCLE_MATCH_ENABLE      0x80000000
159
160 #define CONTEXT_RUN     0x8000
161 #define CONTEXT_WAKE    0x1000
162 #define CONTEXT_DEAD    0x0800
163 #define CONTEXT_ACTIVE  0x0400
164
165 #define OHCI1394_MAX_AT_REQ_RETRIES     0x2
166 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
167 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
168
169 #define FW_OHCI_MAJOR                   240
170 #define OHCI1394_REGISTER_SIZE          0x800
171 #define OHCI_LOOP_COUNT                 500
172 #define OHCI1394_PCI_HCI_Control        0x40
173 #define SELF_ID_BUF_SIZE                0x800
174 #define OHCI_TCODE_PHY_PACKET           0x0e
175
176 static char ohci_driver_name[] = KBUILD_MODNAME;
177
178 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
179 {
180         writel(data, ohci->registers + offset);
181 }
182
183 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
184 {
185         return readl(ohci->registers + offset);
186 }
187
188 static inline void flush_writes(const struct fw_ohci *ohci)
189 {
190         /* Do a dummy read to flush writes. */
191         reg_read(ohci, OHCI1394_Version);
192 }
193
194 static int
195 ohci_update_phy_reg(struct fw_card *card, int addr,
196                     int clear_bits, int set_bits)
197 {
198         struct fw_ohci *ohci = fw_ohci(card);
199         u32 val, old;
200
201         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
202         msleep(2);
203         val = reg_read(ohci, OHCI1394_PhyControl);
204         if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
205                 fw_error("failed to set phy reg bits.\n");
206                 return -EBUSY;
207         }
208
209         old = OHCI1394_PhyControl_ReadData(val);
210         old = (old & ~clear_bits) | set_bits;
211         reg_write(ohci, OHCI1394_PhyControl,
212                   OHCI1394_PhyControl_Write(addr, old));
213
214         return 0;
215 }
216
217 static int ar_context_add_page(struct ar_context *ctx)
218 {
219         struct device *dev = ctx->ohci->card.device;
220         struct ar_buffer *ab;
221         dma_addr_t ab_bus;
222         size_t offset;
223
224         ab = (struct ar_buffer *) __get_free_page(GFP_ATOMIC);
225         if (ab == NULL)
226                 return -ENOMEM;
227
228         ab_bus = dma_map_single(dev, ab, PAGE_SIZE, DMA_BIDIRECTIONAL);
229         if (dma_mapping_error(ab_bus)) {
230                 free_page((unsigned long) ab);
231                 return -ENOMEM;
232         }
233
234         memset(&ab->descriptor, 0, sizeof ab->descriptor);
235         ab->descriptor.control        = cpu_to_le16(descriptor_input_more |
236                                                     descriptor_status |
237                                                     descriptor_branch_always);
238         offset = offsetof(struct ar_buffer, data);
239         ab->descriptor.req_count      = cpu_to_le16(PAGE_SIZE - offset);
240         ab->descriptor.data_address   = cpu_to_le32(ab_bus + offset);
241         ab->descriptor.res_count      = cpu_to_le16(PAGE_SIZE - offset);
242         ab->descriptor.branch_address = 0;
243
244         dma_sync_single_for_device(dev, ab_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
245
246         ctx->last_buffer->descriptor.branch_address = ab_bus | 1;
247         ctx->last_buffer->next = ab;
248         ctx->last_buffer = ab;
249
250         reg_write(ctx->ohci, control_set(ctx->regs), CONTEXT_WAKE);
251         flush_writes(ctx->ohci);
252
253         return 0;
254 }
255
256 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
257 {
258         struct fw_ohci *ohci = ctx->ohci;
259         struct fw_packet p;
260         u32 status, length, tcode;
261
262         p.header[0] = le32_to_cpu(buffer[0]);
263         p.header[1] = le32_to_cpu(buffer[1]);
264         p.header[2] = le32_to_cpu(buffer[2]);
265
266         tcode = (p.header[0] >> 4) & 0x0f;
267         switch (tcode) {
268         case TCODE_WRITE_QUADLET_REQUEST:
269         case TCODE_READ_QUADLET_RESPONSE:
270                 p.header[3] = (__force __u32) buffer[3];
271                 p.header_length = 16;
272                 p.payload_length = 0;
273                 break;
274
275         case TCODE_READ_BLOCK_REQUEST :
276                 p.header[3] = le32_to_cpu(buffer[3]);
277                 p.header_length = 16;
278                 p.payload_length = 0;
279                 break;
280
281         case TCODE_WRITE_BLOCK_REQUEST:
282         case TCODE_READ_BLOCK_RESPONSE:
283         case TCODE_LOCK_REQUEST:
284         case TCODE_LOCK_RESPONSE:
285                 p.header[3] = le32_to_cpu(buffer[3]);
286                 p.header_length = 16;
287                 p.payload_length = p.header[3] >> 16;
288                 break;
289
290         case TCODE_WRITE_RESPONSE:
291         case TCODE_READ_QUADLET_REQUEST:
292         case OHCI_TCODE_PHY_PACKET:
293                 p.header_length = 12;
294                 p.payload_length = 0;
295                 break;
296         }
297
298         p.payload = (void *) buffer + p.header_length;
299
300         /* FIXME: What to do about evt_* errors? */
301         length = (p.header_length + p.payload_length + 3) / 4;
302         status = le32_to_cpu(buffer[length]);
303
304         p.ack        = ((status >> 16) & 0x1f) - 16;
305         p.speed      = (status >> 21) & 0x7;
306         p.timestamp  = status & 0xffff;
307         p.generation = ohci->request_generation;
308
309         /* The OHCI bus reset handler synthesizes a phy packet with
310          * the new generation number when a bus reset happens (see
311          * section 8.4.2.3).  This helps us determine when a request
312          * was received and make sure we send the response in the same
313          * generation.  We only need this for requests; for responses
314          * we use the unique tlabel for finding the matching
315          * request. */
316
317         if (p.ack + 16 == 0x09)
318                 ohci->request_generation = (buffer[2] >> 16) & 0xff;
319         else if (ctx == &ohci->ar_request_ctx)
320                 fw_core_handle_request(&ohci->card, &p);
321         else
322                 fw_core_handle_response(&ohci->card, &p);
323
324         return buffer + length + 1;
325 }
326
327 static void ar_context_tasklet(unsigned long data)
328 {
329         struct ar_context *ctx = (struct ar_context *)data;
330         struct fw_ohci *ohci = ctx->ohci;
331         struct ar_buffer *ab;
332         struct descriptor *d;
333         void *buffer, *end;
334
335         ab = ctx->current_buffer;
336         d = &ab->descriptor;
337
338         if (d->res_count == 0) {
339                 size_t size, rest, offset;
340
341                 /* This descriptor is finished and we may have a
342                  * packet split across this and the next buffer. We
343                  * reuse the page for reassembling the split packet. */
344
345                 offset = offsetof(struct ar_buffer, data);
346                 dma_unmap_single(ohci->card.device,
347                                  ab->descriptor.data_address - offset,
348                                  PAGE_SIZE, DMA_BIDIRECTIONAL);
349
350                 buffer = ab;
351                 ab = ab->next;
352                 d = &ab->descriptor;
353                 size = buffer + PAGE_SIZE - ctx->pointer;
354                 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
355                 memmove(buffer, ctx->pointer, size);
356                 memcpy(buffer + size, ab->data, rest);
357                 ctx->current_buffer = ab;
358                 ctx->pointer = (void *) ab->data + rest;
359                 end = buffer + size + rest;
360
361                 while (buffer < end)
362                         buffer = handle_ar_packet(ctx, buffer);
363
364                 free_page((unsigned long)buffer);
365                 ar_context_add_page(ctx);
366         } else {
367                 buffer = ctx->pointer;
368                 ctx->pointer = end =
369                         (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
370
371                 while (buffer < end)
372                         buffer = handle_ar_packet(ctx, buffer);
373         }
374 }
375
376 static int
377 ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs)
378 {
379         struct ar_buffer ab;
380
381         ctx->regs        = regs;
382         ctx->ohci        = ohci;
383         ctx->last_buffer = &ab;
384         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
385
386         ar_context_add_page(ctx);
387         ar_context_add_page(ctx);
388         ctx->current_buffer = ab.next;
389         ctx->pointer = ctx->current_buffer->data;
390
391         reg_write(ctx->ohci, command_ptr(ctx->regs), ab.descriptor.branch_address);
392         reg_write(ctx->ohci, control_set(ctx->regs), CONTEXT_RUN);
393         flush_writes(ctx->ohci);
394
395         return 0;
396 }
397
398 static void
399 do_packet_callbacks(struct fw_ohci *ohci, struct list_head *list)
400 {
401         struct fw_packet *p, *next;
402
403         list_for_each_entry_safe(p, next, list, link)
404                 p->callback(p, &ohci->card, p->ack);
405 }
406
407 static void
408 complete_transmission(struct fw_packet *packet,
409                       int ack, struct list_head *list)
410 {
411         list_move_tail(&packet->link, list);
412         packet->ack = ack;
413 }
414
415 /* This function prepares the first packet in the context queue for
416  * transmission.  Must always be called with the ochi->lock held to
417  * ensure proper generation handling and locking around packet queue
418  * manipulation. */
419 static void
420 at_context_setup_packet(struct at_context *ctx, struct list_head *list)
421 {
422         struct fw_packet *packet;
423         struct fw_ohci *ohci = ctx->ohci;
424         int z, tcode;
425
426         packet = fw_packet(ctx->list.next);
427
428         memset(&ctx->d, 0, sizeof ctx->d);
429         if (packet->payload_length > 0) {
430                 packet->payload_bus = dma_map_single(ohci->card.device,
431                                                      packet->payload,
432                                                      packet->payload_length,
433                                                      DMA_TO_DEVICE);
434                 if (packet->payload_bus == 0) {
435                         complete_transmission(packet, RCODE_SEND_ERROR, list);
436                         return;
437                 }
438
439                 ctx->d.more.control      =
440                         cpu_to_le16(descriptor_output_more |
441                                     descriptor_key_immediate);
442                 ctx->d.more.req_count    = cpu_to_le16(packet->header_length);
443                 ctx->d.more.res_count    = cpu_to_le16(packet->timestamp);
444                 ctx->d.last.control      =
445                         cpu_to_le16(descriptor_output_last |
446                                     descriptor_irq_always |
447                                     descriptor_branch_always);
448                 ctx->d.last.req_count    = cpu_to_le16(packet->payload_length);
449                 ctx->d.last.data_address = cpu_to_le32(packet->payload_bus);
450                 z = 3;
451         } else {
452                 ctx->d.more.control   =
453                         cpu_to_le16(descriptor_output_last |
454                                     descriptor_key_immediate |
455                                     descriptor_irq_always |
456                                     descriptor_branch_always);
457                 ctx->d.more.req_count = cpu_to_le16(packet->header_length);
458                 ctx->d.more.res_count = cpu_to_le16(packet->timestamp);
459                 z = 2;
460         }
461
462         /* The DMA format for asyncronous link packets is different
463          * from the IEEE1394 layout, so shift the fields around
464          * accordingly.  If header_length is 8, it's a PHY packet, to
465          * which we need to prepend an extra quadlet. */
466         if (packet->header_length > 8) {
467                 ctx->d.header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
468                                                (packet->speed << 16));
469                 ctx->d.header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
470                                                (packet->header[0] & 0xffff0000));
471                 ctx->d.header[2] = cpu_to_le32(packet->header[2]);
472
473                 tcode = (packet->header[0] >> 4) & 0x0f;
474                 if (TCODE_IS_BLOCK_PACKET(tcode))
475                         ctx->d.header[3] = cpu_to_le32(packet->header[3]);
476                 else
477                         ctx->d.header[3] = packet->header[3];
478         } else {
479                 ctx->d.header[0] =
480                         cpu_to_le32((OHCI1394_phy_tcode << 4) |
481                                     (packet->speed << 16));
482                 ctx->d.header[1] = cpu_to_le32(packet->header[0]);
483                 ctx->d.header[2] = cpu_to_le32(packet->header[1]);
484                 ctx->d.more.req_count = cpu_to_le16(12);
485         }
486
487         /* FIXME: Document how the locking works. */
488         if (ohci->generation == packet->generation) {
489                 reg_write(ctx->ohci, command_ptr(ctx->regs),
490                           ctx->descriptor_bus | z);
491                 reg_write(ctx->ohci, control_set(ctx->regs),
492                           CONTEXT_RUN | CONTEXT_WAKE);
493                 ctx->current_packet = packet;
494         } else {
495                 /* We dont return error codes from this function; all
496                  * transmission errors are reported through the
497                  * callback. */
498                 complete_transmission(packet, RCODE_GENERATION, list);
499         }
500 }
501
502 static void at_context_stop(struct at_context *ctx)
503 {
504         u32 reg;
505
506         reg_write(ctx->ohci, control_clear(ctx->regs), CONTEXT_RUN);
507
508         reg = reg_read(ctx->ohci, control_set(ctx->regs));
509         if (reg & CONTEXT_ACTIVE)
510                 fw_notify("Tried to stop context, but it is still active "
511                           "(0x%08x).\n", reg);
512 }
513
514 static void at_context_tasklet(unsigned long data)
515 {
516         struct at_context *ctx = (struct at_context *)data;
517         struct fw_ohci *ohci = ctx->ohci;
518         struct fw_packet *packet;
519         LIST_HEAD(list);
520         unsigned long flags;
521         int evt;
522
523         spin_lock_irqsave(&ohci->lock, flags);
524
525         packet = fw_packet(ctx->list.next);
526
527         at_context_stop(ctx);
528
529         /* If the head of the list isn't the packet that just got
530          * transmitted, the packet got cancelled before we finished
531          * transmitting it. */
532         if (ctx->current_packet != packet)
533                 goto skip_to_next;
534
535         if (packet->payload_length > 0) {
536                 dma_unmap_single(ohci->card.device, packet->payload_bus,
537                                  packet->payload_length, DMA_TO_DEVICE);
538                 evt = le16_to_cpu(ctx->d.last.transfer_status) & 0x1f;
539                 packet->timestamp = le16_to_cpu(ctx->d.last.res_count);
540         }
541         else {
542                 evt = le16_to_cpu(ctx->d.more.transfer_status) & 0x1f;
543                 packet->timestamp = le16_to_cpu(ctx->d.more.res_count);
544         }
545
546         if (evt < 16) {
547                 switch (evt) {
548                 case OHCI1394_evt_timeout:
549                         /* Async response transmit timed out. */
550                         complete_transmission(packet, RCODE_CANCELLED, &list);
551                         break;
552
553                 case OHCI1394_evt_flushed:
554                         /* The packet was flushed should give same
555                          * error as when we try to use a stale
556                          * generation count. */
557                         complete_transmission(packet,
558                                               RCODE_GENERATION, &list);
559                         break;
560
561                 case OHCI1394_evt_missing_ack:
562                         /* Using a valid (current) generation count,
563                          * but the node is not on the bus or not
564                          * sending acks. */
565                         complete_transmission(packet, RCODE_NO_ACK, &list);
566                         break;
567
568                 default:
569                         complete_transmission(packet, RCODE_SEND_ERROR, &list);
570                         break;
571                 }
572         } else
573                 complete_transmission(packet, evt - 16, &list);
574
575  skip_to_next:
576         /* If more packets are queued, set up the next one. */
577         if (!list_empty(&ctx->list))
578                 at_context_setup_packet(ctx, &list);
579
580         spin_unlock_irqrestore(&ohci->lock, flags);
581
582         do_packet_callbacks(ohci, &list);
583 }
584
585 static int
586 at_context_init(struct at_context *ctx, struct fw_ohci *ohci, u32 regs)
587 {
588         INIT_LIST_HEAD(&ctx->list);
589
590         ctx->descriptor_bus =
591                 dma_map_single(ohci->card.device, &ctx->d,
592                                sizeof ctx->d, DMA_TO_DEVICE);
593         if (ctx->descriptor_bus == 0)
594                 return -ENOMEM;
595
596         ctx->regs = regs;
597         ctx->ohci = ohci;
598
599         tasklet_init(&ctx->tasklet, at_context_tasklet, (unsigned long)ctx);
600
601         return 0;
602 }
603
604 #define header_get_destination(q)       (((q) >> 16) & 0xffff)
605 #define header_get_tcode(q)             (((q) >> 4) & 0x0f)
606 #define header_get_offset_high(q)       (((q) >> 0) & 0xffff)
607 #define header_get_data_length(q)       (((q) >> 16) & 0xffff)
608 #define header_get_extended_tcode(q)    (((q) >> 0) & 0xffff)
609
610 static void
611 handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
612 {
613         struct fw_packet response;
614         int tcode, length, i;
615
616         tcode = header_get_tcode(packet->header[0]);
617         if (TCODE_IS_BLOCK_PACKET(tcode))
618                 length = header_get_data_length(packet->header[3]);
619         else
620                 length = 4;
621
622         i = csr - CSR_CONFIG_ROM;
623         if (i + length > CONFIG_ROM_SIZE) {
624                 fw_fill_response(&response, packet->header,
625                                  RCODE_ADDRESS_ERROR, NULL, 0);
626         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
627                 fw_fill_response(&response, packet->header,
628                                  RCODE_TYPE_ERROR, NULL, 0);
629         } else {
630                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
631                                  (void *) ohci->config_rom + i, length);
632         }
633
634         fw_core_handle_response(&ohci->card, &response);
635 }
636
637 static void
638 handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
639 {
640         struct fw_packet response;
641         int tcode, length, ext_tcode, sel;
642         __be32 *payload, lock_old;
643         u32 lock_arg, lock_data;
644
645         tcode = header_get_tcode(packet->header[0]);
646         length = header_get_data_length(packet->header[3]);
647         payload = packet->payload;
648         ext_tcode = header_get_extended_tcode(packet->header[3]);
649
650         if (tcode == TCODE_LOCK_REQUEST &&
651             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
652                 lock_arg = be32_to_cpu(payload[0]);
653                 lock_data = be32_to_cpu(payload[1]);
654         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
655                 lock_arg = 0;
656                 lock_data = 0;
657         } else {
658                 fw_fill_response(&response, packet->header,
659                                  RCODE_TYPE_ERROR, NULL, 0);
660                 goto out;
661         }
662
663         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
664         reg_write(ohci, OHCI1394_CSRData, lock_data);
665         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
666         reg_write(ohci, OHCI1394_CSRControl, sel);
667
668         if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
669                 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
670         else
671                 fw_notify("swap not done yet\n");
672
673         fw_fill_response(&response, packet->header,
674                          RCODE_COMPLETE, &lock_old, sizeof lock_old);
675  out:
676         fw_core_handle_response(&ohci->card, &response);
677 }
678
679 static void
680 handle_local_request(struct at_context *ctx, struct fw_packet *packet)
681 {
682         u64 offset;
683         u32 csr;
684
685         packet->ack = ACK_PENDING;
686         packet->callback(packet, &ctx->ohci->card, packet->ack);
687
688         offset =
689                 ((unsigned long long)
690                  header_get_offset_high(packet->header[1]) << 32) |
691                 packet->header[2];
692         csr = offset - CSR_REGISTER_BASE;
693
694         /* Handle config rom reads. */
695         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
696                 handle_local_rom(ctx->ohci, packet, csr);
697         else switch (csr) {
698         case CSR_BUS_MANAGER_ID:
699         case CSR_BANDWIDTH_AVAILABLE:
700         case CSR_CHANNELS_AVAILABLE_HI:
701         case CSR_CHANNELS_AVAILABLE_LO:
702                 handle_local_lock(ctx->ohci, packet, csr);
703                 break;
704         default:
705                 if (ctx == &ctx->ohci->at_request_ctx)
706                         fw_core_handle_request(&ctx->ohci->card, packet);
707                 else
708                         fw_core_handle_response(&ctx->ohci->card, packet);
709                 break;
710         }
711 }
712
713 static void
714 at_context_transmit(struct at_context *ctx, struct fw_packet *packet)
715 {
716         LIST_HEAD(list);
717         unsigned long flags;
718
719         spin_lock_irqsave(&ctx->ohci->lock, flags);
720
721         if (header_get_destination(packet->header[0]) == ctx->ohci->node_id &&
722             ctx->ohci->generation == packet->generation) {
723                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
724                 handle_local_request(ctx, packet);
725                 return;
726         }
727
728         list_add_tail(&packet->link, &ctx->list);
729         if (ctx->list.next == &packet->link)
730                 at_context_setup_packet(ctx, &list);
731
732         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
733
734         do_packet_callbacks(ctx->ohci, &list);
735 }
736
737 static void bus_reset_tasklet(unsigned long data)
738 {
739         struct fw_ohci *ohci = (struct fw_ohci *)data;
740         int self_id_count, i, j, reg;
741         int generation, new_generation;
742         unsigned long flags;
743
744         reg = reg_read(ohci, OHCI1394_NodeID);
745         if (!(reg & OHCI1394_NodeID_idValid)) {
746                 fw_error("node ID not valid, new bus reset in progress\n");
747                 return;
748         }
749         ohci->node_id = reg & 0xffff;
750
751         /* The count in the SelfIDCount register is the number of
752          * bytes in the self ID receive buffer.  Since we also receive
753          * the inverted quadlets and a header quadlet, we shift one
754          * bit extra to get the actual number of self IDs. */
755
756         self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff;
757         generation = (le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
758
759         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
760                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1])
761                         fw_error("inconsistent self IDs\n");
762                 ohci->self_id_buffer[j] = le32_to_cpu(ohci->self_id_cpu[i]);
763         }
764
765         /* Check the consistency of the self IDs we just read.  The
766          * problem we face is that a new bus reset can start while we
767          * read out the self IDs from the DMA buffer. If this happens,
768          * the DMA buffer will be overwritten with new self IDs and we
769          * will read out inconsistent data.  The OHCI specification
770          * (section 11.2) recommends a technique similar to
771          * linux/seqlock.h, where we remember the generation of the
772          * self IDs in the buffer before reading them out and compare
773          * it to the current generation after reading them out.  If
774          * the two generations match we know we have a consistent set
775          * of self IDs. */
776
777         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
778         if (new_generation != generation) {
779                 fw_notify("recursive bus reset detected, "
780                           "discarding self ids\n");
781                 return;
782         }
783
784         /* FIXME: Document how the locking works. */
785         spin_lock_irqsave(&ohci->lock, flags);
786
787         ohci->generation = generation;
788         at_context_stop(&ohci->at_request_ctx);
789         at_context_stop(&ohci->at_response_ctx);
790         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
791
792         /* This next bit is unrelated to the AT context stuff but we
793          * have to do it under the spinlock also.  If a new config rom
794          * was set up before this reset, the old one is now no longer
795          * in use and we can free it. Update the config rom pointers
796          * to point to the current config rom and clear the
797          * next_config_rom pointer so a new udpate can take place. */
798
799         if (ohci->next_config_rom != NULL) {
800                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
801                                   ohci->config_rom, ohci->config_rom_bus);
802                 ohci->config_rom      = ohci->next_config_rom;
803                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
804                 ohci->next_config_rom = NULL;
805
806                 /* Restore config_rom image and manually update
807                  * config_rom registers.  Writing the header quadlet
808                  * will indicate that the config rom is ready, so we
809                  * do that last. */
810                 reg_write(ohci, OHCI1394_BusOptions,
811                           be32_to_cpu(ohci->config_rom[2]));
812                 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
813                 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
814         }
815
816         spin_unlock_irqrestore(&ohci->lock, flags);
817
818         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
819                                  self_id_count, ohci->self_id_buffer);
820 }
821
822 static irqreturn_t irq_handler(int irq, void *data)
823 {
824         struct fw_ohci *ohci = data;
825         u32 event, iso_event;
826         int i;
827
828         event = reg_read(ohci, OHCI1394_IntEventClear);
829
830         if (!event)
831                 return IRQ_NONE;
832
833         reg_write(ohci, OHCI1394_IntEventClear, event);
834
835         if (event & OHCI1394_selfIDComplete)
836                 tasklet_schedule(&ohci->bus_reset_tasklet);
837
838         if (event & OHCI1394_RQPkt)
839                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
840
841         if (event & OHCI1394_RSPkt)
842                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
843
844         if (event & OHCI1394_reqTxComplete)
845                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
846
847         if (event & OHCI1394_respTxComplete)
848                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
849
850         iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventSet);
851         reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
852
853         while (iso_event) {
854                 i = ffs(iso_event) - 1;
855                 tasklet_schedule(&ohci->ir_context_list[i].tasklet);
856                 iso_event &= ~(1 << i);
857         }
858
859         iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventSet);
860         reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
861
862         while (iso_event) {
863                 i = ffs(iso_event) - 1;
864                 tasklet_schedule(&ohci->it_context_list[i].tasklet);
865                 iso_event &= ~(1 << i);
866         }
867
868         return IRQ_HANDLED;
869 }
870
871 static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
872 {
873         struct fw_ohci *ohci = fw_ohci(card);
874         struct pci_dev *dev = to_pci_dev(card->device);
875
876         /* When the link is not yet enabled, the atomic config rom
877          * update mechanism described below in ohci_set_config_rom()
878          * is not active.  We have to update ConfigRomHeader and
879          * BusOptions manually, and the write to ConfigROMmap takes
880          * effect immediately.  We tie this to the enabling of the
881          * link, so we have a valid config rom before enabling - the
882          * OHCI requires that ConfigROMhdr and BusOptions have valid
883          * values before enabling.
884          *
885          * However, when the ConfigROMmap is written, some controllers
886          * always read back quadlets 0 and 2 from the config rom to
887          * the ConfigRomHeader and BusOptions registers on bus reset.
888          * They shouldn't do that in this initial case where the link
889          * isn't enabled.  This means we have to use the same
890          * workaround here, setting the bus header to 0 and then write
891          * the right values in the bus reset tasklet.
892          */
893
894         ohci->next_config_rom =
895                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
896                                    &ohci->next_config_rom_bus, GFP_KERNEL);
897         if (ohci->next_config_rom == NULL)
898                 return -ENOMEM;
899
900         memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
901         fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
902
903         ohci->next_header = config_rom[0];
904         ohci->next_config_rom[0] = 0;
905         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
906         reg_write(ohci, OHCI1394_BusOptions, config_rom[2]);
907         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
908
909         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
910
911         if (request_irq(dev->irq, irq_handler,
912                         SA_SHIRQ, ohci_driver_name, ohci)) {
913                 fw_error("Failed to allocate shared interrupt %d.\n",
914                          dev->irq);
915                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
916                                   ohci->config_rom, ohci->config_rom_bus);
917                 return -EIO;
918         }
919
920         reg_write(ohci, OHCI1394_HCControlSet,
921                   OHCI1394_HCControl_linkEnable |
922                   OHCI1394_HCControl_BIBimageValid);
923         flush_writes(ohci);
924
925         /* We are ready to go, initiate bus reset to finish the
926          * initialization. */
927
928         fw_core_initiate_bus_reset(&ohci->card, 1);
929
930         return 0;
931 }
932
933 static int
934 ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
935 {
936         struct fw_ohci *ohci;
937         unsigned long flags;
938         int retval = 0;
939         __be32 *next_config_rom;
940         dma_addr_t next_config_rom_bus;
941
942         ohci = fw_ohci(card);
943
944         /* When the OHCI controller is enabled, the config rom update
945          * mechanism is a bit tricky, but easy enough to use.  See
946          * section 5.5.6 in the OHCI specification.
947          *
948          * The OHCI controller caches the new config rom address in a
949          * shadow register (ConfigROMmapNext) and needs a bus reset
950          * for the changes to take place.  When the bus reset is
951          * detected, the controller loads the new values for the
952          * ConfigRomHeader and BusOptions registers from the specified
953          * config rom and loads ConfigROMmap from the ConfigROMmapNext
954          * shadow register. All automatically and atomically.
955          *
956          * Now, there's a twist to this story.  The automatic load of
957          * ConfigRomHeader and BusOptions doesn't honor the
958          * noByteSwapData bit, so with a be32 config rom, the
959          * controller will load be32 values in to these registers
960          * during the atomic update, even on litte endian
961          * architectures.  The workaround we use is to put a 0 in the
962          * header quadlet; 0 is endian agnostic and means that the
963          * config rom isn't ready yet.  In the bus reset tasklet we
964          * then set up the real values for the two registers.
965          *
966          * We use ohci->lock to avoid racing with the code that sets
967          * ohci->next_config_rom to NULL (see bus_reset_tasklet).
968          */
969
970         next_config_rom =
971                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
972                                    &next_config_rom_bus, GFP_KERNEL);
973         if (next_config_rom == NULL)
974                 return -ENOMEM;
975
976         spin_lock_irqsave(&ohci->lock, flags);
977
978         if (ohci->next_config_rom == NULL) {
979                 ohci->next_config_rom = next_config_rom;
980                 ohci->next_config_rom_bus = next_config_rom_bus;
981
982                 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
983                 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
984                                   length * 4);
985
986                 ohci->next_header = config_rom[0];
987                 ohci->next_config_rom[0] = 0;
988
989                 reg_write(ohci, OHCI1394_ConfigROMmap,
990                           ohci->next_config_rom_bus);
991         } else {
992                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
993                                   next_config_rom, next_config_rom_bus);
994                 retval = -EBUSY;
995         }
996
997         spin_unlock_irqrestore(&ohci->lock, flags);
998
999         /* Now initiate a bus reset to have the changes take
1000          * effect. We clean up the old config rom memory and DMA
1001          * mappings in the bus reset tasklet, since the OHCI
1002          * controller could need to access it before the bus reset
1003          * takes effect. */
1004         if (retval == 0)
1005                 fw_core_initiate_bus_reset(&ohci->card, 1);
1006
1007         return retval;
1008 }
1009
1010 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1011 {
1012         struct fw_ohci *ohci = fw_ohci(card);
1013
1014         at_context_transmit(&ohci->at_request_ctx, packet);
1015 }
1016
1017 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1018 {
1019         struct fw_ohci *ohci = fw_ohci(card);
1020
1021         at_context_transmit(&ohci->at_response_ctx, packet);
1022 }
1023
1024 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1025 {
1026         struct fw_ohci *ohci = fw_ohci(card);
1027         LIST_HEAD(list);
1028         unsigned long flags;
1029
1030         spin_lock_irqsave(&ohci->lock, flags);
1031
1032         if (packet->ack == 0) {
1033                 fw_notify("cancelling packet %p (header[0]=%08x)\n",
1034                           packet, packet->header[0]);
1035
1036                 complete_transmission(packet, RCODE_CANCELLED, &list);
1037         }
1038
1039         spin_unlock_irqrestore(&ohci->lock, flags);
1040
1041         do_packet_callbacks(ohci, &list);
1042
1043         /* Return success if we actually cancelled something. */
1044         return list_empty(&list) ? -ENOENT : 0;
1045 }
1046
1047 static int
1048 ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
1049 {
1050         struct fw_ohci *ohci = fw_ohci(card);
1051         unsigned long flags;
1052         int n, retval = 0;
1053
1054         /* FIXME:  Make sure this bitmask is cleared when we clear the busReset
1055          * interrupt bit.  Clear physReqResourceAllBuses on bus reset. */
1056
1057         spin_lock_irqsave(&ohci->lock, flags);
1058
1059         if (ohci->generation != generation) {
1060                 retval = -ESTALE;
1061                 goto out;
1062         }
1063
1064         /* NOTE, if the node ID contains a non-local bus ID, physical DMA is
1065          * enabled for _all_ nodes on remote buses. */
1066
1067         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1068         if (n < 32)
1069                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1070         else
1071                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1072
1073         flush_writes(ohci);
1074  out:
1075         spin_unlock_irqrestore(&ohci->lock, flags);
1076         return retval;
1077 }
1078
1079 static void ir_context_tasklet(unsigned long data)
1080 {
1081         struct iso_context *ctx = (struct iso_context *)data;
1082
1083         (void)ctx;
1084 }
1085
1086 #define ISO_BUFFER_SIZE (64 * 1024)
1087
1088 static void flush_iso_context(struct iso_context *ctx)
1089 {
1090         struct fw_ohci *ohci = fw_ohci(ctx->base.card);
1091         struct descriptor *d, *last;
1092         u32 address;
1093         int z;
1094
1095         dma_sync_single_for_cpu(ohci->card.device, ctx->buffer_bus,
1096                                 ISO_BUFFER_SIZE, DMA_TO_DEVICE);
1097
1098         d    = ctx->tail_descriptor;
1099         last = ctx->tail_descriptor_last;
1100
1101         while (last->branch_address != 0 && last->transfer_status != 0) {
1102                 address = le32_to_cpu(last->branch_address);
1103                 z = address & 0xf;
1104                 d = ctx->buffer + (address - ctx->buffer_bus) / sizeof *d;
1105
1106                 if (z == 2)
1107                         last = d;
1108                 else
1109                         last = d + z - 1;
1110
1111                 if (le16_to_cpu(last->control) & descriptor_irq_always)
1112                         ctx->base.callback(&ctx->base,
1113                                            0, le16_to_cpu(last->res_count),
1114                                            ctx->base.callback_data);
1115         }
1116
1117         ctx->tail_descriptor      = d;
1118         ctx->tail_descriptor_last = last;
1119 }
1120
1121 static void it_context_tasklet(unsigned long data)
1122 {
1123         struct iso_context *ctx = (struct iso_context *)data;
1124
1125         flush_iso_context(ctx);
1126 }
1127
1128 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
1129                                                         int type)
1130 {
1131         struct fw_ohci *ohci = fw_ohci(card);
1132         struct iso_context *ctx, *list;
1133         void (*tasklet) (unsigned long data);
1134         u32 *mask;
1135         unsigned long flags;
1136         int index;
1137
1138         if (type == FW_ISO_CONTEXT_TRANSMIT) {
1139                 mask = &ohci->it_context_mask;
1140                 list = ohci->it_context_list;
1141                 tasklet = it_context_tasklet;
1142         } else {
1143                 mask = &ohci->ir_context_mask;
1144                 list = ohci->ir_context_list;
1145                 tasklet = ir_context_tasklet;
1146         }
1147
1148         spin_lock_irqsave(&ohci->lock, flags);
1149         index = ffs(*mask) - 1;
1150         if (index >= 0)
1151                 *mask &= ~(1 << index);
1152         spin_unlock_irqrestore(&ohci->lock, flags);
1153
1154         if (index < 0)
1155                 return ERR_PTR(-EBUSY);
1156
1157         ctx = &list[index];
1158         memset(ctx, 0, sizeof *ctx);
1159         tasklet_init(&ctx->tasklet, tasklet, (unsigned long)ctx);
1160
1161         ctx->buffer = kmalloc(ISO_BUFFER_SIZE, GFP_KERNEL);
1162         if (ctx->buffer == NULL) {
1163                 spin_lock_irqsave(&ohci->lock, flags);
1164                 *mask |= 1 << index;
1165                 spin_unlock_irqrestore(&ohci->lock, flags);
1166                 return ERR_PTR(-ENOMEM);
1167         }
1168
1169         ctx->buffer_bus =
1170             dma_map_single(card->device, ctx->buffer,
1171                            ISO_BUFFER_SIZE, DMA_TO_DEVICE);
1172
1173         ctx->head_descriptor      = ctx->buffer;
1174         ctx->prev_descriptor      = ctx->buffer;
1175         ctx->tail_descriptor      = ctx->buffer;
1176         ctx->tail_descriptor_last = ctx->buffer;
1177
1178         /* We put a dummy descriptor in the buffer that has a NULL
1179          * branch address and looks like it's been sent.  That way we
1180          * have a descriptor to append DMA programs to.  Also, the
1181          * ring buffer invariant is that it always has at least one
1182          * element so that head == tail means buffer full. */
1183
1184         memset(ctx->head_descriptor, 0, sizeof *ctx->head_descriptor);
1185         ctx->head_descriptor->control = cpu_to_le16(descriptor_output_last);
1186         ctx->head_descriptor->transfer_status = cpu_to_le16(0x8011);
1187         ctx->head_descriptor++;
1188
1189         return &ctx->base;
1190 }
1191
1192 static int ohci_send_iso(struct fw_iso_context *base, s32 cycle)
1193 {
1194         struct iso_context *ctx = (struct iso_context *)base;
1195         struct fw_ohci *ohci = fw_ohci(ctx->base.card);
1196         u32 cycle_match = 0;
1197         int index;
1198
1199         index = ctx - ohci->it_context_list;
1200         if (cycle > 0)
1201                 cycle_match = CONTEXT_CYCLE_MATCH_ENABLE |
1202                         (cycle & 0x7fff) << 16;
1203
1204         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
1205         reg_write(ohci, OHCI1394_IsoXmitCommandPtr(index),
1206                   le32_to_cpu(ctx->tail_descriptor_last->branch_address));
1207         reg_write(ohci, OHCI1394_IsoXmitContextControlClear(index), ~0);
1208         reg_write(ohci, OHCI1394_IsoXmitContextControlSet(index),
1209                   CONTEXT_RUN | cycle_match);
1210         flush_writes(ohci);
1211
1212         return 0;
1213 }
1214
1215 static void ohci_free_iso_context(struct fw_iso_context *base)
1216 {
1217         struct fw_ohci *ohci = fw_ohci(base->card);
1218         struct iso_context *ctx = (struct iso_context *)base;
1219         unsigned long flags;
1220         int index;
1221
1222         flush_iso_context(ctx);
1223
1224         spin_lock_irqsave(&ohci->lock, flags);
1225
1226         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1227                 index = ctx - ohci->it_context_list;
1228                 reg_write(ohci, OHCI1394_IsoXmitContextControlClear(index), ~0);
1229                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
1230                 ohci->it_context_mask |= 1 << index;
1231         } else {
1232                 index = ctx - ohci->ir_context_list;
1233                 reg_write(ohci, OHCI1394_IsoRcvContextControlClear(index), ~0);
1234                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
1235                 ohci->ir_context_mask |= 1 << index;
1236         }
1237         flush_writes(ohci);
1238
1239         dma_unmap_single(ohci->card.device, ctx->buffer_bus,
1240                          ISO_BUFFER_SIZE, DMA_TO_DEVICE);
1241
1242         spin_unlock_irqrestore(&ohci->lock, flags);
1243 }
1244
1245 static int
1246 ohci_queue_iso(struct fw_iso_context *base,
1247                struct fw_iso_packet *packet, void *payload)
1248 {
1249         struct iso_context *ctx = (struct iso_context *)base;
1250         struct fw_ohci *ohci = fw_ohci(ctx->base.card);
1251         struct descriptor *d, *end, *last, *tail, *pd;
1252         struct fw_iso_packet *p;
1253         __le32 *header;
1254         dma_addr_t d_bus;
1255         u32 z, header_z, payload_z, irq;
1256         u32 payload_index, payload_end_index, next_page_index;
1257         int index, page, end_page, i, length, offset;
1258
1259         /* FIXME: Cycle lost behavior should be configurable: lose
1260          * packet, retransmit or terminate.. */
1261
1262         p = packet;
1263         payload_index = payload - ctx->base.buffer;
1264         d = ctx->head_descriptor;
1265         tail = ctx->tail_descriptor;
1266         end = ctx->buffer + ISO_BUFFER_SIZE / sizeof(struct descriptor);
1267
1268         if (p->skip)
1269                 z = 1;
1270         else
1271                 z = 2;
1272         if (p->header_length > 0)
1273                 z++;
1274
1275         /* Determine the first page the payload isn't contained in. */
1276         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
1277         if (p->payload_length > 0)
1278                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
1279         else
1280                 payload_z = 0;
1281
1282         z += payload_z;
1283
1284         /* Get header size in number of descriptors. */
1285         header_z = DIV_ROUND_UP(p->header_length, sizeof *d);
1286
1287         if (d + z + header_z <= tail) {
1288                 goto has_space;
1289         } else if (d > tail && d + z + header_z <= end) {
1290                 goto has_space;
1291         } else if (d > tail && ctx->buffer + z + header_z <= tail) {
1292                 d = ctx->buffer;
1293                 goto has_space;
1294         }
1295
1296         /* No space in buffer */
1297         return -1;
1298
1299  has_space:
1300         memset(d, 0, (z + header_z) * sizeof *d);
1301         d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof *d;
1302
1303         if (!p->skip) {
1304                 d[0].control   = cpu_to_le16(descriptor_key_immediate);
1305                 d[0].req_count = cpu_to_le16(8);
1306
1307                 header = (__le32 *) &d[1];
1308                 header[0] = cpu_to_le32(it_header_sy(p->sy) |
1309                                         it_header_tag(p->tag) |
1310                                         it_header_tcode(TCODE_STREAM_DATA) |
1311                                         it_header_channel(ctx->base.channel) |
1312                                         it_header_speed(ctx->base.speed));
1313                 header[1] =
1314                         cpu_to_le32(it_header_data_length(p->header_length +
1315                                                           p->payload_length));
1316         }
1317
1318         if (p->header_length > 0) {
1319                 d[2].req_count    = cpu_to_le16(p->header_length);
1320                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof *d);
1321                 memcpy(&d[z], p->header, p->header_length);
1322         }
1323
1324         pd = d + z - payload_z;
1325         payload_end_index = payload_index + p->payload_length;
1326         for (i = 0; i < payload_z; i++) {
1327                 page               = payload_index >> PAGE_SHIFT;
1328                 offset             = payload_index & ~PAGE_MASK;
1329                 next_page_index    = (page + 1) << PAGE_SHIFT;
1330                 length             =
1331                         min(next_page_index, payload_end_index) - payload_index;
1332                 pd[i].req_count    = cpu_to_le16(length);
1333                 pd[i].data_address = cpu_to_le32(ctx->base.pages[page] + offset);
1334
1335                 payload_index += length;
1336         }
1337
1338         if (z == 2)
1339                 last = d;
1340         else
1341                 last = d + z - 1;
1342
1343         if (p->interrupt)
1344                 irq = descriptor_irq_always;
1345         else
1346                 irq = descriptor_no_irq;
1347
1348         last->control = cpu_to_le16(descriptor_output_last |
1349                                     descriptor_status |
1350                                     descriptor_branch_always |
1351                                     irq);
1352
1353         dma_sync_single_for_device(ohci->card.device, ctx->buffer_bus,
1354                                    ISO_BUFFER_SIZE, DMA_TO_DEVICE);
1355
1356         ctx->head_descriptor = d + z + header_z;
1357         ctx->prev_descriptor->branch_address = cpu_to_le32(d_bus | z);
1358         ctx->prev_descriptor = last;
1359
1360         index = ctx - ohci->it_context_list;
1361         reg_write(ohci, OHCI1394_IsoXmitContextControlSet(index), CONTEXT_WAKE);
1362         flush_writes(ohci);
1363
1364         return 0;
1365 }
1366
1367 static const struct fw_card_driver ohci_driver = {
1368         .name                   = ohci_driver_name,
1369         .enable                 = ohci_enable,
1370         .update_phy_reg         = ohci_update_phy_reg,
1371         .set_config_rom         = ohci_set_config_rom,
1372         .send_request           = ohci_send_request,
1373         .send_response          = ohci_send_response,
1374         .cancel_packet          = ohci_cancel_packet,
1375         .enable_phys_dma        = ohci_enable_phys_dma,
1376
1377         .allocate_iso_context   = ohci_allocate_iso_context,
1378         .free_iso_context       = ohci_free_iso_context,
1379         .queue_iso              = ohci_queue_iso,
1380         .send_iso               = ohci_send_iso,
1381 };
1382
1383 static int software_reset(struct fw_ohci *ohci)
1384 {
1385         int i;
1386
1387         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1388
1389         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1390                 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1391                      OHCI1394_HCControl_softReset) == 0)
1392                         return 0;
1393                 msleep(1);
1394         }
1395
1396         return -EBUSY;
1397 }
1398
1399 /* ---------- pci subsystem interface ---------- */
1400
1401 enum {
1402         CLEANUP_SELF_ID,
1403         CLEANUP_REGISTERS,
1404         CLEANUP_IOMEM,
1405         CLEANUP_DISABLE,
1406         CLEANUP_PUT_CARD,
1407 };
1408
1409 static int cleanup(struct fw_ohci *ohci, int stage, int code)
1410 {
1411         struct pci_dev *dev = to_pci_dev(ohci->card.device);
1412
1413         switch (stage) {
1414         case CLEANUP_SELF_ID:
1415                 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
1416                                   ohci->self_id_cpu, ohci->self_id_bus);
1417         case CLEANUP_REGISTERS:
1418                 kfree(ohci->it_context_list);
1419                 kfree(ohci->ir_context_list);
1420                 pci_iounmap(dev, ohci->registers);
1421         case CLEANUP_IOMEM:
1422                 pci_release_region(dev, 0);
1423         case CLEANUP_DISABLE:
1424                 pci_disable_device(dev);
1425         case CLEANUP_PUT_CARD:
1426                 fw_card_put(&ohci->card);
1427         }
1428
1429         return code;
1430 }
1431
1432 static int __devinit
1433 pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
1434 {
1435         struct fw_ohci *ohci;
1436         u32 bus_options, max_receive, link_speed;
1437         u64 guid;
1438         int error_code;
1439         size_t size;
1440
1441         ohci = kzalloc(sizeof *ohci, GFP_KERNEL);
1442         if (ohci == NULL) {
1443                 fw_error("Could not malloc fw_ohci data.\n");
1444                 return -ENOMEM;
1445         }
1446
1447         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
1448
1449         if (pci_enable_device(dev)) {
1450                 fw_error("Failed to enable OHCI hardware.\n");
1451                 return cleanup(ohci, CLEANUP_PUT_CARD, -ENODEV);
1452         }
1453
1454         pci_set_master(dev);
1455         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
1456         pci_set_drvdata(dev, ohci);
1457
1458         spin_lock_init(&ohci->lock);
1459
1460         tasklet_init(&ohci->bus_reset_tasklet,
1461                      bus_reset_tasklet, (unsigned long)ohci);
1462
1463         if (pci_request_region(dev, 0, ohci_driver_name)) {
1464                 fw_error("MMIO resource unavailable\n");
1465                 return cleanup(ohci, CLEANUP_DISABLE, -EBUSY);
1466         }
1467
1468         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
1469         if (ohci->registers == NULL) {
1470                 fw_error("Failed to remap registers\n");
1471                 return cleanup(ohci, CLEANUP_IOMEM, -ENXIO);
1472         }
1473
1474         if (software_reset(ohci)) {
1475                 fw_error("Failed to reset ohci card.\n");
1476                 return cleanup(ohci, CLEANUP_REGISTERS, -EBUSY);
1477         }
1478
1479         /* Now enable LPS, which we need in order to start accessing
1480          * most of the registers.  In fact, on some cards (ALI M5251),
1481          * accessing registers in the SClk domain without LPS enabled
1482          * will lock up the machine.  Wait 50msec to make sure we have
1483          * full link enabled.  */
1484         reg_write(ohci, OHCI1394_HCControlSet,
1485                   OHCI1394_HCControl_LPS |
1486                   OHCI1394_HCControl_postedWriteEnable);
1487         flush_writes(ohci);
1488         msleep(50);
1489
1490         reg_write(ohci, OHCI1394_HCControlClear,
1491                   OHCI1394_HCControl_noByteSwapData);
1492
1493         reg_write(ohci, OHCI1394_LinkControlSet,
1494                   OHCI1394_LinkControl_rcvSelfID |
1495                   OHCI1394_LinkControl_cycleTimerEnable |
1496                   OHCI1394_LinkControl_cycleMaster);
1497
1498         ar_context_init(&ohci->ar_request_ctx, ohci,
1499                         OHCI1394_AsReqRcvContextControlSet);
1500
1501         ar_context_init(&ohci->ar_response_ctx, ohci,
1502                         OHCI1394_AsRspRcvContextControlSet);
1503
1504         at_context_init(&ohci->at_request_ctx, ohci,
1505                         OHCI1394_AsReqTrContextControlSet);
1506
1507         at_context_init(&ohci->at_response_ctx, ohci,
1508                         OHCI1394_AsRspTrContextControlSet);
1509
1510         reg_write(ohci, OHCI1394_ATRetries,
1511                   OHCI1394_MAX_AT_REQ_RETRIES |
1512                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1513                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1514
1515         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
1516         ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
1517         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
1518         size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
1519         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
1520
1521         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
1522         ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
1523         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
1524         size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
1525         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
1526
1527         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
1528                 fw_error("Out of memory for it/ir contexts.\n");
1529                 return cleanup(ohci, CLEANUP_REGISTERS, -ENOMEM);
1530         }
1531
1532         /* self-id dma buffer allocation */
1533         ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
1534                                                SELF_ID_BUF_SIZE,
1535                                                &ohci->self_id_bus,
1536                                                GFP_KERNEL);
1537         if (ohci->self_id_cpu == NULL) {
1538                 fw_error("Out of memory for self ID buffer.\n");
1539                 return cleanup(ohci, CLEANUP_REGISTERS, -ENOMEM);
1540         }
1541
1542         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1543         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1544         reg_write(ohci, OHCI1394_IntEventClear, ~0);
1545         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1546         reg_write(ohci, OHCI1394_IntMaskSet,
1547                   OHCI1394_selfIDComplete |
1548                   OHCI1394_RQPkt | OHCI1394_RSPkt |
1549                   OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1550                   OHCI1394_isochRx | OHCI1394_isochTx |
1551                   OHCI1394_masterIntEnable);
1552
1553         bus_options = reg_read(ohci, OHCI1394_BusOptions);
1554         max_receive = (bus_options >> 12) & 0xf;
1555         link_speed = bus_options & 0x7;
1556         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
1557                 reg_read(ohci, OHCI1394_GUIDLo);
1558
1559         error_code = fw_card_add(&ohci->card, max_receive, link_speed, guid);
1560         if (error_code < 0)
1561                 return cleanup(ohci, CLEANUP_SELF_ID, error_code);
1562
1563         fw_notify("Added fw-ohci device %s.\n", dev->dev.bus_id);
1564
1565         return 0;
1566 }
1567
1568 static void pci_remove(struct pci_dev *dev)
1569 {
1570         struct fw_ohci *ohci;
1571
1572         ohci = pci_get_drvdata(dev);
1573         reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_masterIntEnable);
1574         fw_core_remove_card(&ohci->card);
1575
1576         /* FIXME: Fail all pending packets here, now that the upper
1577          * layers can't queue any more. */
1578
1579         software_reset(ohci);
1580         free_irq(dev->irq, ohci);
1581         cleanup(ohci, CLEANUP_SELF_ID, 0);
1582
1583         fw_notify("Removed fw-ohci device.\n");
1584 }
1585
1586 static struct pci_device_id pci_table[] = {
1587         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
1588         { }
1589 };
1590
1591 MODULE_DEVICE_TABLE(pci, pci_table);
1592
1593 static struct pci_driver fw_ohci_pci_driver = {
1594         .name           = ohci_driver_name,
1595         .id_table       = pci_table,
1596         .probe          = pci_probe,
1597         .remove         = pci_remove,
1598 };
1599
1600 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
1601 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
1602 MODULE_LICENSE("GPL");
1603
1604 static int __init fw_ohci_init(void)
1605 {
1606         return pci_register_driver(&fw_ohci_pci_driver);
1607 }
1608
1609 static void __exit fw_ohci_cleanup(void)
1610 {
1611         pci_unregister_driver(&fw_ohci_pci_driver);
1612 }
1613
1614 module_init(fw_ohci_init);
1615 module_exit(fw_ohci_cleanup);