i2c: tegra: Add delay before resetting the controller after NACK
[linux-2.6.git] / drivers / edac / i82975x_edac.c
1 /*
2  * Intel 82975X Memory Controller kernel module
3  * (C) 2007 aCarLab (India) Pvt. Ltd. (http://acarlab.com)
4  * (C) 2007 jetzbroadband (http://jetzbroadband.com)
5  * This file may be distributed under the terms of the
6  * GNU General Public License.
7  *
8  * Written by Arvind R.
9  *   Copied from i82875p_edac.c source:
10  */
11
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/pci_ids.h>
16 #include <linux/edac.h>
17 #include "edac_core.h"
18
19 #define I82975X_REVISION        " Ver: 1.0.0"
20 #define EDAC_MOD_STR            "i82975x_edac"
21
22 #define i82975x_printk(level, fmt, arg...) \
23         edac_printk(level, "i82975x", fmt, ##arg)
24
25 #define i82975x_mc_printk(mci, level, fmt, arg...) \
26         edac_mc_chipset_printk(mci, level, "i82975x", fmt, ##arg)
27
28 #ifndef PCI_DEVICE_ID_INTEL_82975_0
29 #define PCI_DEVICE_ID_INTEL_82975_0     0x277c
30 #endif                          /* PCI_DEVICE_ID_INTEL_82975_0 */
31
32 #define I82975X_NR_CSROWS(nr_chans)             (8/(nr_chans))
33
34 /* Intel 82975X register addresses - device 0 function 0 - DRAM Controller */
35 #define I82975X_EAP             0x58    /* Dram Error Address Pointer (32b)
36                                          *
37                                          * 31:7  128 byte cache-line address
38                                          * 6:1   reserved
39                                          * 0     0: CH0; 1: CH1
40                                          */
41
42 #define I82975X_DERRSYN         0x5c    /* Dram Error SYNdrome (8b)
43                                          *
44                                          *  7:0  DRAM ECC Syndrome
45                                          */
46
47 #define I82975X_DES             0x5d    /* Dram ERRor DeSTination (8b)
48                                          * 0h:    Processor Memory Reads
49                                          * 1h:7h  reserved
50                                          * More - See Page 65 of Intel DocSheet.
51                                          */
52
53 #define I82975X_ERRSTS          0xc8    /* Error Status Register (16b)
54                                          *
55                                          * 15:12 reserved
56                                          * 11    Thermal Sensor Event
57                                          * 10    reserved
58                                          *  9    non-DRAM lock error (ndlock)
59                                          *  8    Refresh Timeout
60                                          *  7:2  reserved
61                                          *  1    ECC UE (multibit DRAM error)
62                                          *  0    ECC CE (singlebit DRAM error)
63                                          */
64
65 /* Error Reporting is supported by 3 mechanisms:
66   1. DMI SERR generation  ( ERRCMD )
67   2. SMI DMI  generation  ( SMICMD )
68   3. SCI DMI  generation  ( SCICMD )
69 NOTE: Only ONE of the three must be enabled
70 */
71 #define I82975X_ERRCMD          0xca    /* Error Command (16b)
72                                          *
73                                          * 15:12 reserved
74                                          * 11    Thermal Sensor Event
75                                          * 10    reserved
76                                          *  9    non-DRAM lock error (ndlock)
77                                          *  8    Refresh Timeout
78                                          *  7:2  reserved
79                                          *  1    ECC UE (multibit DRAM error)
80                                          *  0    ECC CE (singlebit DRAM error)
81                                          */
82
83 #define I82975X_SMICMD          0xcc    /* Error Command (16b)
84                                          *
85                                          * 15:2  reserved
86                                          *  1    ECC UE (multibit DRAM error)
87                                          *  0    ECC CE (singlebit DRAM error)
88                                          */
89
90 #define I82975X_SCICMD          0xce    /* Error Command (16b)
91                                          *
92                                          * 15:2  reserved
93                                          *  1    ECC UE (multibit DRAM error)
94                                          *  0    ECC CE (singlebit DRAM error)
95                                          */
96
97 #define I82975X_XEAP    0xfc    /* Extended Dram Error Address Pointer (8b)
98                                          *
99                                          * 7:1   reserved
100                                          * 0     Bit32 of the Dram Error Address
101                                          */
102
103 #define I82975X_MCHBAR          0x44    /*
104                                          *
105                                          * 31:14 Base Addr of 16K memory-mapped
106                                          *      configuration space
107                                          * 13:1  reserverd
108                                          *  0    mem-mapped config space enable
109                                          */
110
111 /* NOTE: Following addresses have to indexed using MCHBAR offset (44h, 32b) */
112 /* Intel 82975x memory mapped register space */
113
114 #define I82975X_DRB_SHIFT 25    /* fixed 32MiB grain */
115
116 #define I82975X_DRB             0x100   /* DRAM Row Boundary (8b x 8)
117                                          *
118                                          * 7   set to 1 in highest DRB of
119                                          *      channel if 4GB in ch.
120                                          * 6:2 upper boundary of rank in
121                                          *      32MB grains
122                                          * 1:0 set to 0
123                                          */
124 #define I82975X_DRB_CH0R0               0x100
125 #define I82975X_DRB_CH0R1               0x101
126 #define I82975X_DRB_CH0R2               0x102
127 #define I82975X_DRB_CH0R3               0x103
128 #define I82975X_DRB_CH1R0               0x180
129 #define I82975X_DRB_CH1R1               0x181
130 #define I82975X_DRB_CH1R2               0x182
131 #define I82975X_DRB_CH1R3               0x183
132
133
134 #define I82975X_DRA             0x108   /* DRAM Row Attribute (4b x 8)
135                                          *  defines the PAGE SIZE to be used
136                                          *      for the rank
137                                          *  7    reserved
138                                          *  6:4  row attr of odd rank, i.e. 1
139                                          *  3    reserved
140                                          *  2:0  row attr of even rank, i.e. 0
141                                          *
142                                          * 000 = unpopulated
143                                          * 001 = reserved
144                                          * 010 = 4KiB
145                                          * 011 = 8KiB
146                                          * 100 = 16KiB
147                                          * others = reserved
148                                          */
149 #define I82975X_DRA_CH0R01              0x108
150 #define I82975X_DRA_CH0R23              0x109
151 #define I82975X_DRA_CH1R01              0x188
152 #define I82975X_DRA_CH1R23              0x189
153
154
155 #define I82975X_BNKARC  0x10e /* Type of device in each rank - Bank Arch (16b)
156                                          *
157                                          * 15:8  reserved
158                                          * 7:6  Rank 3 architecture
159                                          * 5:4  Rank 2 architecture
160                                          * 3:2  Rank 1 architecture
161                                          * 1:0  Rank 0 architecture
162                                          *
163                                          * 00 => 4 banks
164                                          * 01 => 8 banks
165                                          */
166 #define I82975X_C0BNKARC        0x10e
167 #define I82975X_C1BNKARC        0x18e
168
169
170
171 #define I82975X_DRC             0x120 /* DRAM Controller Mode0 (32b)
172                                          *
173                                          * 31:30 reserved
174                                          * 29    init complete
175                                          * 28:11 reserved, according to Intel
176                                          *    22:21 number of channels
177                                          *              00=1 01=2 in 82875
178                                          *              seems to be ECC mode
179                                          *              bits in 82975 in Asus
180                                          *              P5W
181                                          *       19:18 Data Integ Mode
182                                          *              00=none 01=ECC in 82875
183                                          * 10:8  refresh mode
184                                          *  7    reserved
185                                          *  6:4  mode select
186                                          *  3:2  reserved
187                                          *  1:0  DRAM type 10=Second Revision
188                                          *              DDR2 SDRAM
189                                          *         00, 01, 11 reserved
190                                          */
191 #define I82975X_DRC_CH0M0               0x120
192 #define I82975X_DRC_CH1M0               0x1A0
193
194
195 #define I82975X_DRC_M1  0x124 /* DRAM Controller Mode1 (32b)
196                                          * 31   0=Standard Address Map
197                                          *      1=Enhanced Address Map
198                                          * 30:0 reserved
199                                          */
200
201 #define I82975X_DRC_CH0M1               0x124
202 #define I82975X_DRC_CH1M1               0x1A4
203
204 enum i82975x_chips {
205         I82975X = 0,
206 };
207
208 struct i82975x_pvt {
209         void __iomem *mch_window;
210 };
211
212 struct i82975x_dev_info {
213         const char *ctl_name;
214 };
215
216 struct i82975x_error_info {
217         u16 errsts;
218         u32 eap;
219         u8 des;
220         u8 derrsyn;
221         u16 errsts2;
222         u8 chan;                /* the channel is bit 0 of EAP */
223         u8 xeap;                /* extended eap bit */
224 };
225
226 static const struct i82975x_dev_info i82975x_devs[] = {
227         [I82975X] = {
228                 .ctl_name = "i82975x"
229         },
230 };
231
232 static struct pci_dev *mci_pdev;        /* init dev: in case that AGP code has
233                                          * already registered driver
234                                          */
235
236 static int i82975x_registered = 1;
237
238 static void i82975x_get_error_info(struct mem_ctl_info *mci,
239                 struct i82975x_error_info *info)
240 {
241         struct pci_dev *pdev;
242
243         pdev = to_pci_dev(mci->dev);
244
245         /*
246          * This is a mess because there is no atomic way to read all the
247          * registers at once and the registers can transition from CE being
248          * overwritten by UE.
249          */
250         pci_read_config_word(pdev, I82975X_ERRSTS, &info->errsts);
251         pci_read_config_dword(pdev, I82975X_EAP, &info->eap);
252         pci_read_config_byte(pdev, I82975X_XEAP, &info->xeap);
253         pci_read_config_byte(pdev, I82975X_DES, &info->des);
254         pci_read_config_byte(pdev, I82975X_DERRSYN, &info->derrsyn);
255         pci_read_config_word(pdev, I82975X_ERRSTS, &info->errsts2);
256
257         pci_write_bits16(pdev, I82975X_ERRSTS, 0x0003, 0x0003);
258
259         /*
260          * If the error is the same then we can for both reads then
261          * the first set of reads is valid.  If there is a change then
262          * there is a CE no info and the second set of reads is valid
263          * and should be UE info.
264          */
265         if (!(info->errsts2 & 0x0003))
266                 return;
267
268         if ((info->errsts ^ info->errsts2) & 0x0003) {
269                 pci_read_config_dword(pdev, I82975X_EAP, &info->eap);
270                 pci_read_config_byte(pdev, I82975X_XEAP, &info->xeap);
271                 pci_read_config_byte(pdev, I82975X_DES, &info->des);
272                 pci_read_config_byte(pdev, I82975X_DERRSYN,
273                                 &info->derrsyn);
274         }
275 }
276
277 static int i82975x_process_error_info(struct mem_ctl_info *mci,
278                 struct i82975x_error_info *info, int handle_errors)
279 {
280         int row, multi_chan, chan;
281         unsigned long offst, page;
282
283         multi_chan = mci->csrows[0].nr_channels - 1;
284
285         if (!(info->errsts2 & 0x0003))
286                 return 0;
287
288         if (!handle_errors)
289                 return 1;
290
291         if ((info->errsts ^ info->errsts2) & 0x0003) {
292                 edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
293                 info->errsts = info->errsts2;
294         }
295
296         page = (unsigned long) info->eap;
297         if (info->xeap & 1)
298                 page |= 0x100000000ul;
299         chan = page & 1;
300         page >>= 1;
301         offst = page & ((1 << PAGE_SHIFT) - 1);
302         page >>= PAGE_SHIFT;
303         row = edac_mc_find_csrow_by_page(mci, page);
304
305         if (info->errsts & 0x0002)
306                 edac_mc_handle_ue(mci, page, offst , row, "i82975x UE");
307         else
308                 edac_mc_handle_ce(mci, page, offst, info->derrsyn, row,
309                                 multi_chan ? chan : 0,
310                                 "i82975x CE");
311
312         return 1;
313 }
314
315 static void i82975x_check(struct mem_ctl_info *mci)
316 {
317         struct i82975x_error_info info;
318
319         debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
320         i82975x_get_error_info(mci, &info);
321         i82975x_process_error_info(mci, &info, 1);
322 }
323
324 /* Return 1 if dual channel mode is active.  Else return 0. */
325 static int dual_channel_active(void __iomem *mch_window)
326 {
327         /*
328          * We treat interleaved-symmetric configuration as dual-channel - EAP's
329          * bit-0 giving the channel of the error location.
330          *
331          * All other configurations are treated as single channel - the EAP's
332          * bit-0 will resolve ok in symmetric area of mixed
333          * (symmetric/asymmetric) configurations
334          */
335         u8      drb[4][2];
336         int     row;
337         int    dualch;
338
339         for (dualch = 1, row = 0; dualch && (row < 4); row++) {
340                 drb[row][0] = readb(mch_window + I82975X_DRB + row);
341                 drb[row][1] = readb(mch_window + I82975X_DRB + row + 0x80);
342                 dualch = dualch && (drb[row][0] == drb[row][1]);
343         }
344         return dualch;
345 }
346
347 static enum dev_type i82975x_dram_type(void __iomem *mch_window, int rank)
348 {
349         /*
350          * ECC is possible on i92975x ONLY with DEV_X8
351          */
352         return DEV_X8;
353 }
354
355 static void i82975x_init_csrows(struct mem_ctl_info *mci,
356                 struct pci_dev *pdev, void __iomem *mch_window)
357 {
358         static const char *labels[4] = {
359                                                         "DIMM A1", "DIMM A2",
360                                                         "DIMM B1", "DIMM B2"
361                                                 };
362         struct csrow_info *csrow;
363         unsigned long last_cumul_size;
364         u8 value;
365         u32 cumul_size;
366         int index, chan;
367
368         last_cumul_size = 0;
369
370         /*
371          * 82875 comment:
372          * The dram row boundary (DRB) reg values are boundary address
373          * for each DRAM row with a granularity of 32 or 64MB (single/dual
374          * channel operation).  DRB regs are cumulative; therefore DRB7 will
375          * contain the total memory contained in all rows.
376          *
377          */
378
379         for (index = 0; index < mci->nr_csrows; index++) {
380                 csrow = &mci->csrows[index];
381
382                 value = readb(mch_window + I82975X_DRB + index +
383                                         ((index >= 4) ? 0x80 : 0));
384                 cumul_size = value;
385                 cumul_size <<= (I82975X_DRB_SHIFT - PAGE_SHIFT);
386                 /*
387                  * Adjust cumul_size w.r.t number of channels
388                  *
389                  */
390                 if (csrow->nr_channels > 1)
391                         cumul_size <<= 1;
392                 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
393                         cumul_size);
394
395                 /*
396                  * Initialise dram labels
397                  * index values:
398                  *   [0-7] for single-channel; i.e. csrow->nr_channels = 1
399                  *   [0-3] for dual-channel; i.e. csrow->nr_channels = 2
400                  */
401                 for (chan = 0; chan < csrow->nr_channels; chan++)
402                         strncpy(csrow->channels[chan].label,
403                                         labels[(index >> 1) + (chan * 2)],
404                                         EDAC_MC_LABEL_LEN);
405
406                 if (cumul_size == last_cumul_size)
407                         continue;       /* not populated */
408
409                 csrow->first_page = last_cumul_size;
410                 csrow->last_page = cumul_size - 1;
411                 csrow->nr_pages = cumul_size - last_cumul_size;
412                 last_cumul_size = cumul_size;
413                 csrow->grain = 1 << 6;  /* I82975X_EAP has 64B resolution */
414                 csrow->mtype = MEM_DDR2; /* I82975x supports only DDR2 */
415                 csrow->dtype = i82975x_dram_type(mch_window, index);
416                 csrow->edac_mode = EDAC_SECDED; /* only supported */
417         }
418 }
419
420 /* #define  i82975x_DEBUG_IOMEM */
421
422 #ifdef i82975x_DEBUG_IOMEM
423 static void i82975x_print_dram_timings(void __iomem *mch_window)
424 {
425         /*
426          * The register meanings are from Intel specs;
427          * (shows 13-5-5-5 for 800-DDR2)
428          * Asus P5W Bios reports 15-5-4-4
429          * What's your religion?
430          */
431         static const int caslats[4] = { 5, 4, 3, 6 };
432         u32     dtreg[2];
433
434         dtreg[0] = readl(mch_window + 0x114);
435         dtreg[1] = readl(mch_window + 0x194);
436         i82975x_printk(KERN_INFO, "DRAM Timings :     Ch0    Ch1\n"
437                 "                RAS Active Min = %d     %d\n"
438                 "                CAS latency    =  %d      %d\n"
439                 "                RAS to CAS     =  %d      %d\n"
440                 "                RAS precharge  =  %d      %d\n",
441                 (dtreg[0] >> 19 ) & 0x0f,
442                         (dtreg[1] >> 19) & 0x0f,
443                 caslats[(dtreg[0] >> 8) & 0x03],
444                         caslats[(dtreg[1] >> 8) & 0x03],
445                 ((dtreg[0] >> 4) & 0x07) + 2,
446                         ((dtreg[1] >> 4) & 0x07) + 2,
447                 (dtreg[0] & 0x07) + 2,
448                         (dtreg[1] & 0x07) + 2
449         );
450
451 }
452 #endif
453
454 static int i82975x_probe1(struct pci_dev *pdev, int dev_idx)
455 {
456         int rc = -ENODEV;
457         struct mem_ctl_info *mci;
458         struct i82975x_pvt *pvt;
459         void __iomem *mch_window;
460         u32 mchbar;
461         u32 drc[2];
462         struct i82975x_error_info discard;
463         int     chans;
464 #ifdef i82975x_DEBUG_IOMEM
465         u8 c0drb[4];
466         u8 c1drb[4];
467 #endif
468
469         debugf0("%s()\n", __func__);
470
471         pci_read_config_dword(pdev, I82975X_MCHBAR, &mchbar);
472         if (!(mchbar & 1)) {
473                 debugf3("%s(): failed, MCHBAR disabled!\n", __func__);
474                 goto fail0;
475         }
476         mchbar &= 0xffffc000;   /* bits 31:14 used for 16K window */
477         mch_window = ioremap_nocache(mchbar, 0x1000);
478
479 #ifdef i82975x_DEBUG_IOMEM
480         i82975x_printk(KERN_INFO, "MCHBAR real = %0x, remapped = %p\n",
481                                         mchbar, mch_window);
482
483         c0drb[0] = readb(mch_window + I82975X_DRB_CH0R0);
484         c0drb[1] = readb(mch_window + I82975X_DRB_CH0R1);
485         c0drb[2] = readb(mch_window + I82975X_DRB_CH0R2);
486         c0drb[3] = readb(mch_window + I82975X_DRB_CH0R3);
487         c1drb[0] = readb(mch_window + I82975X_DRB_CH1R0);
488         c1drb[1] = readb(mch_window + I82975X_DRB_CH1R1);
489         c1drb[2] = readb(mch_window + I82975X_DRB_CH1R2);
490         c1drb[3] = readb(mch_window + I82975X_DRB_CH1R3);
491         i82975x_printk(KERN_INFO, "DRBCH0R0 = 0x%02x\n", c0drb[0]);
492         i82975x_printk(KERN_INFO, "DRBCH0R1 = 0x%02x\n", c0drb[1]);
493         i82975x_printk(KERN_INFO, "DRBCH0R2 = 0x%02x\n", c0drb[2]);
494         i82975x_printk(KERN_INFO, "DRBCH0R3 = 0x%02x\n", c0drb[3]);
495         i82975x_printk(KERN_INFO, "DRBCH1R0 = 0x%02x\n", c1drb[0]);
496         i82975x_printk(KERN_INFO, "DRBCH1R1 = 0x%02x\n", c1drb[1]);
497         i82975x_printk(KERN_INFO, "DRBCH1R2 = 0x%02x\n", c1drb[2]);
498         i82975x_printk(KERN_INFO, "DRBCH1R3 = 0x%02x\n", c1drb[3]);
499 #endif
500
501         drc[0] = readl(mch_window + I82975X_DRC_CH0M0);
502         drc[1] = readl(mch_window + I82975X_DRC_CH1M0);
503 #ifdef i82975x_DEBUG_IOMEM
504         i82975x_printk(KERN_INFO, "DRC_CH0 = %0x, %s\n", drc[0],
505                         ((drc[0] >> 21) & 3) == 1 ?
506                                 "ECC enabled" : "ECC disabled");
507         i82975x_printk(KERN_INFO, "DRC_CH1 = %0x, %s\n", drc[1],
508                         ((drc[1] >> 21) & 3) == 1 ?
509                                 "ECC enabled" : "ECC disabled");
510
511         i82975x_printk(KERN_INFO, "C0 BNKARC = %0x\n",
512                 readw(mch_window + I82975X_C0BNKARC));
513         i82975x_printk(KERN_INFO, "C1 BNKARC = %0x\n",
514                 readw(mch_window + I82975X_C1BNKARC));
515         i82975x_print_dram_timings(mch_window);
516         goto fail1;
517 #endif
518         if (!(((drc[0] >> 21) & 3) == 1 || ((drc[1] >> 21) & 3) == 1)) {
519                 i82975x_printk(KERN_INFO, "ECC disabled on both channels.\n");
520                 goto fail1;
521         }
522
523         chans = dual_channel_active(mch_window) + 1;
524
525         /* assuming only one controller, index thus is 0 */
526         mci = edac_mc_alloc(sizeof(*pvt), I82975X_NR_CSROWS(chans),
527                                         chans, 0);
528         if (!mci) {
529                 rc = -ENOMEM;
530                 goto fail1;
531         }
532
533         debugf3("%s(): init mci\n", __func__);
534         mci->dev = &pdev->dev;
535         mci->mtype_cap = MEM_FLAG_DDR2;
536         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
537         mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
538         mci->mod_name = EDAC_MOD_STR;
539         mci->mod_ver = I82975X_REVISION;
540         mci->ctl_name = i82975x_devs[dev_idx].ctl_name;
541         mci->dev_name = pci_name(pdev);
542         mci->edac_check = i82975x_check;
543         mci->ctl_page_to_phys = NULL;
544         debugf3("%s(): init pvt\n", __func__);
545         pvt = (struct i82975x_pvt *) mci->pvt_info;
546         pvt->mch_window = mch_window;
547         i82975x_init_csrows(mci, pdev, mch_window);
548         mci->scrub_mode = SCRUB_HW_SRC;
549         i82975x_get_error_info(mci, &discard);  /* clear counters */
550
551         /* finalize this instance of memory controller with edac core */
552         if (edac_mc_add_mc(mci)) {
553                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
554                 goto fail2;
555         }
556
557         /* get this far and it's successful */
558         debugf3("%s(): success\n", __func__);
559         return 0;
560
561 fail2:
562         edac_mc_free(mci);
563
564 fail1:
565         iounmap(mch_window);
566 fail0:
567         return rc;
568 }
569
570 /* returns count (>= 0), or negative on error */
571 static int __devinit i82975x_init_one(struct pci_dev *pdev,
572                 const struct pci_device_id *ent)
573 {
574         int rc;
575
576         debugf0("%s()\n", __func__);
577
578         if (pci_enable_device(pdev) < 0)
579                 return -EIO;
580
581         rc = i82975x_probe1(pdev, ent->driver_data);
582
583         if (mci_pdev == NULL)
584                 mci_pdev = pci_dev_get(pdev);
585
586         return rc;
587 }
588
589 static void __devexit i82975x_remove_one(struct pci_dev *pdev)
590 {
591         struct mem_ctl_info *mci;
592         struct i82975x_pvt *pvt;
593
594         debugf0("%s()\n", __func__);
595
596         mci = edac_mc_del_mc(&pdev->dev);
597         if (mci  == NULL)
598                 return;
599
600         pvt = mci->pvt_info;
601         if (pvt->mch_window)
602                 iounmap( pvt->mch_window );
603
604         edac_mc_free(mci);
605 }
606
607 static const struct pci_device_id i82975x_pci_tbl[] __devinitdata = {
608         {
609                 PCI_VEND_DEV(INTEL, 82975_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
610                 I82975X
611         },
612         {
613                 0,
614         }       /* 0 terminated list. */
615 };
616
617 MODULE_DEVICE_TABLE(pci, i82975x_pci_tbl);
618
619 static struct pci_driver i82975x_driver = {
620         .name = EDAC_MOD_STR,
621         .probe = i82975x_init_one,
622         .remove = __devexit_p(i82975x_remove_one),
623         .id_table = i82975x_pci_tbl,
624 };
625
626 static int __init i82975x_init(void)
627 {
628         int pci_rc;
629
630         debugf3("%s()\n", __func__);
631
632        /* Ensure that the OPSTATE is set correctly for POLL or NMI */
633        opstate_init();
634
635         pci_rc = pci_register_driver(&i82975x_driver);
636         if (pci_rc < 0)
637                 goto fail0;
638
639         if (mci_pdev == NULL) {
640                 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
641                                 PCI_DEVICE_ID_INTEL_82975_0, NULL);
642
643                 if (!mci_pdev) {
644                         debugf0("i82975x pci_get_device fail\n");
645                         pci_rc = -ENODEV;
646                         goto fail1;
647                 }
648
649                 pci_rc = i82975x_init_one(mci_pdev, i82975x_pci_tbl);
650
651                 if (pci_rc < 0) {
652                         debugf0("i82975x init fail\n");
653                         pci_rc = -ENODEV;
654                         goto fail1;
655                 }
656         }
657
658         return 0;
659
660 fail1:
661         pci_unregister_driver(&i82975x_driver);
662
663 fail0:
664         if (mci_pdev != NULL)
665                 pci_dev_put(mci_pdev);
666
667         return pci_rc;
668 }
669
670 static void __exit i82975x_exit(void)
671 {
672         debugf3("%s()\n", __func__);
673
674         pci_unregister_driver(&i82975x_driver);
675
676         if (!i82975x_registered) {
677                 i82975x_remove_one(mci_pdev);
678                 pci_dev_put(mci_pdev);
679         }
680 }
681
682 module_init(i82975x_init);
683 module_exit(i82975x_exit);
684
685 MODULE_LICENSE("GPL");
686 MODULE_AUTHOR("Arvind R. <arvino55@gmail.com>");
687 MODULE_DESCRIPTION("MC support for Intel 82975 memory hub controllers");
688
689 module_param(edac_op_state, int, 0444);
690 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");