Merge branch 'master' into for-next
[linux-2.6.git] / drivers / edac / i82975x_edac.c
1 /*
2  * Intel 82975X Memory Controller kernel module
3  * (C) 2007 aCarLab (India) Pvt. Ltd. (http://acarlab.com)
4  * (C) 2007 jetzbroadband (http://jetzbroadband.com)
5  * This file may be distributed under the terms of the
6  * GNU General Public License.
7  *
8  * Written by Arvind R.
9  *   Copied from i82875p_edac.c source:
10  */
11
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/pci_ids.h>
16 #include <linux/edac.h>
17 #include "edac_core.h"
18
19 #define I82975X_REVISION        " Ver: 1.0.0 " __DATE__
20 #define EDAC_MOD_STR            "i82975x_edac"
21
22 #define i82975x_printk(level, fmt, arg...) \
23         edac_printk(level, "i82975x", fmt, ##arg)
24
25 #define i82975x_mc_printk(mci, level, fmt, arg...) \
26         edac_mc_chipset_printk(mci, level, "i82975x", fmt, ##arg)
27
28 #ifndef PCI_DEVICE_ID_INTEL_82975_0
29 #define PCI_DEVICE_ID_INTEL_82975_0     0x277c
30 #endif                          /* PCI_DEVICE_ID_INTEL_82975_0 */
31
32 #define I82975X_NR_CSROWS(nr_chans)             (8/(nr_chans))
33
34 /* Intel 82975X register addresses - device 0 function 0 - DRAM Controller */
35 #define I82975X_EAP             0x58    /* Dram Error Address Pointer (32b)
36                                          *
37                                          * 31:7  128 byte cache-line address
38                                          * 6:1   reserved
39                                          * 0     0: CH0; 1: CH1
40                                          */
41
42 #define I82975X_DERRSYN         0x5c    /* Dram Error SYNdrome (8b)
43                                          *
44                                          *  7:0  DRAM ECC Syndrome
45                                          */
46
47 #define I82975X_DES             0x5d    /* Dram ERRor DeSTination (8b)
48                                          * 0h:    Processor Memory Reads
49                                          * 1h:7h  reserved
50                                          * More - See Page 65 of Intel DocSheet.
51                                          */
52
53 #define I82975X_ERRSTS          0xc8    /* Error Status Register (16b)
54                                          *
55                                          * 15:12 reserved
56                                          * 11    Thermal Sensor Event
57                                          * 10    reserved
58                                          *  9    non-DRAM lock error (ndlock)
59                                          *  8    Refresh Timeout
60                                          *  7:2  reserved
61                                          *  1    ECC UE (multibit DRAM error)
62                                          *  0    ECC CE (singlebit DRAM error)
63                                          */
64
65 /* Error Reporting is supported by 3 mechanisms:
66   1. DMI SERR generation  ( ERRCMD )
67   2. SMI DMI  generation  ( SMICMD )
68   3. SCI DMI  generation  ( SCICMD )
69 NOTE: Only ONE of the three must be enabled
70 */
71 #define I82975X_ERRCMD          0xca    /* Error Command (16b)
72                                          *
73                                          * 15:12 reserved
74                                          * 11    Thermal Sensor Event
75                                          * 10    reserved
76                                          *  9    non-DRAM lock error (ndlock)
77                                          *  8    Refresh Timeout
78                                          *  7:2  reserved
79                                          *  1    ECC UE (multibit DRAM error)
80                                          *  0    ECC CE (singlebit DRAM error)
81                                          */
82
83 #define I82975X_SMICMD          0xcc    /* Error Command (16b)
84                                          *
85                                          * 15:2  reserved
86                                          *  1    ECC UE (multibit DRAM error)
87                                          *  0    ECC CE (singlebit DRAM error)
88                                          */
89
90 #define I82975X_SCICMD          0xce    /* Error Command (16b)
91                                          *
92                                          * 15:2  reserved
93                                          *  1    ECC UE (multibit DRAM error)
94                                          *  0    ECC CE (singlebit DRAM error)
95                                          */
96
97 #define I82975X_XEAP    0xfc    /* Extended Dram Error Address Pointer (8b)
98                                          *
99                                          * 7:1   reserved
100                                          * 0     Bit32 of the Dram Error Address
101                                          */
102
103 #define I82975X_MCHBAR          0x44    /*
104                                          *
105                                          * 31:14 Base Addr of 16K memory-mapped
106                                          *      configuration space
107                                          * 13:1  reserverd
108                                          *  0    mem-mapped config space enable
109                                          */
110
111 /* NOTE: Following addresses have to indexed using MCHBAR offset (44h, 32b) */
112 /* Intel 82975x memory mapped register space */
113
114 #define I82975X_DRB_SHIFT 25    /* fixed 32MiB grain */
115
116 #define I82975X_DRB             0x100   /* DRAM Row Boundary (8b x 8)
117                                          *
118                                          * 7   set to 1 in highest DRB of
119                                          *      channel if 4GB in ch.
120                                          * 6:2 upper boundary of rank in
121                                          *      32MB grains
122                                          * 1:0 set to 0
123                                          */
124 #define I82975X_DRB_CH0R0               0x100
125 #define I82975X_DRB_CH0R1               0x101
126 #define I82975X_DRB_CH0R2               0x102
127 #define I82975X_DRB_CH0R3               0x103
128 #define I82975X_DRB_CH1R0               0x180
129 #define I82975X_DRB_CH1R1               0x181
130 #define I82975X_DRB_CH1R2               0x182
131 #define I82975X_DRB_CH1R3               0x183
132
133
134 #define I82975X_DRA             0x108   /* DRAM Row Attribute (4b x 8)
135                                          *  defines the PAGE SIZE to be used
136                                          *      for the rank
137                                          *  7    reserved
138                                          *  6:4  row attr of odd rank, i.e. 1
139                                          *  3    reserved
140                                          *  2:0  row attr of even rank, i.e. 0
141                                          *
142                                          * 000 = unpopulated
143                                          * 001 = reserved
144                                          * 010 = 4KiB
145                                          * 011 = 8KiB
146                                          * 100 = 16KiB
147                                          * others = reserved
148                                          */
149 #define I82975X_DRA_CH0R01              0x108
150 #define I82975X_DRA_CH0R23              0x109
151 #define I82975X_DRA_CH1R01              0x188
152 #define I82975X_DRA_CH1R23              0x189
153
154
155 #define I82975X_BNKARC  0x10e /* Type of device in each rank - Bank Arch (16b)
156                                          *
157                                          * 15:8  reserved
158                                          * 7:6  Rank 3 architecture
159                                          * 5:4  Rank 2 architecture
160                                          * 3:2  Rank 1 architecture
161                                          * 1:0  Rank 0 architecture
162                                          *
163                                          * 00 => x16 devices; i.e 4 banks
164                                          * 01 => x8  devices; i.e 8 banks
165                                          */
166 #define I82975X_C0BNKARC        0x10e
167 #define I82975X_C1BNKARC        0x18e
168
169
170
171 #define I82975X_DRC             0x120 /* DRAM Controller Mode0 (32b)
172                                          *
173                                          * 31:30 reserved
174                                          * 29    init complete
175                                          * 28:11 reserved, according to Intel
176                                          *    22:21 number of channels
177                                          *              00=1 01=2 in 82875
178                                          *              seems to be ECC mode
179                                          *              bits in 82975 in Asus
180                                          *              P5W
181                                          *       19:18 Data Integ Mode
182                                          *              00=none 01=ECC in 82875
183                                          * 10:8  refresh mode
184                                          *  7    reserved
185                                          *  6:4  mode select
186                                          *  3:2  reserved
187                                          *  1:0  DRAM type 10=Second Revision
188                                          *              DDR2 SDRAM
189                                          *         00, 01, 11 reserved
190                                          */
191 #define I82975X_DRC_CH0M0               0x120
192 #define I82975X_DRC_CH1M0               0x1A0
193
194
195 #define I82975X_DRC_M1  0x124 /* DRAM Controller Mode1 (32b)
196                                          * 31   0=Standard Address Map
197                                          *      1=Enhanced Address Map
198                                          * 30:0 reserved
199                                          */
200
201 #define I82975X_DRC_CH0M1               0x124
202 #define I82975X_DRC_CH1M1               0x1A4
203
204 enum i82975x_chips {
205         I82975X = 0,
206 };
207
208 struct i82975x_pvt {
209         void __iomem *mch_window;
210 };
211
212 struct i82975x_dev_info {
213         const char *ctl_name;
214 };
215
216 struct i82975x_error_info {
217         u16 errsts;
218         u32 eap;
219         u8 des;
220         u8 derrsyn;
221         u16 errsts2;
222         u8 chan;                /* the channel is bit 0 of EAP */
223         u8 xeap;                /* extended eap bit */
224 };
225
226 static const struct i82975x_dev_info i82975x_devs[] = {
227         [I82975X] = {
228                 .ctl_name = "i82975x"
229         },
230 };
231
232 static struct pci_dev *mci_pdev;        /* init dev: in case that AGP code has
233                                          * already registered driver
234                                          */
235
236 static int i82975x_registered = 1;
237
238 static void i82975x_get_error_info(struct mem_ctl_info *mci,
239                 struct i82975x_error_info *info)
240 {
241         struct pci_dev *pdev;
242
243         pdev = to_pci_dev(mci->dev);
244
245         /*
246          * This is a mess because there is no atomic way to read all the
247          * registers at once and the registers can transition from CE being
248          * overwritten by UE.
249          */
250         pci_read_config_word(pdev, I82975X_ERRSTS, &info->errsts);
251         pci_read_config_dword(pdev, I82975X_EAP, &info->eap);
252         pci_read_config_byte(pdev, I82975X_XEAP, &info->xeap);
253         pci_read_config_byte(pdev, I82975X_DES, &info->des);
254         pci_read_config_byte(pdev, I82975X_DERRSYN, &info->derrsyn);
255         pci_read_config_word(pdev, I82975X_ERRSTS, &info->errsts2);
256
257         pci_write_bits16(pdev, I82975X_ERRSTS, 0x0003, 0x0003);
258
259         /*
260          * If the error is the same then we can for both reads then
261          * the first set of reads is valid.  If there is a change then
262          * there is a CE no info and the second set of reads is valid
263          * and should be UE info.
264          */
265         if (!(info->errsts2 & 0x0003))
266                 return;
267
268         if ((info->errsts ^ info->errsts2) & 0x0003) {
269                 pci_read_config_dword(pdev, I82975X_EAP, &info->eap);
270                 pci_read_config_byte(pdev, I82975X_XEAP, &info->xeap);
271                 pci_read_config_byte(pdev, I82975X_DES, &info->des);
272                 pci_read_config_byte(pdev, I82975X_DERRSYN,
273                                 &info->derrsyn);
274         }
275 }
276
277 static int i82975x_process_error_info(struct mem_ctl_info *mci,
278                 struct i82975x_error_info *info, int handle_errors)
279 {
280         int row, multi_chan, chan;
281
282         multi_chan = mci->csrows[0].nr_channels - 1;
283
284         if (!(info->errsts2 & 0x0003))
285                 return 0;
286
287         if (!handle_errors)
288                 return 1;
289
290         if ((info->errsts ^ info->errsts2) & 0x0003) {
291                 edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
292                 info->errsts = info->errsts2;
293         }
294
295         chan = info->eap & 1;
296         info->eap >>= 1;
297         if (info->xeap )
298                 info->eap |= 0x80000000;
299         info->eap >>= PAGE_SHIFT;
300         row = edac_mc_find_csrow_by_page(mci, info->eap);
301
302         if (info->errsts & 0x0002)
303                 edac_mc_handle_ue(mci, info->eap, 0, row, "i82975x UE");
304         else
305                 edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row,
306                                 multi_chan ? chan : 0,
307                                 "i82975x CE");
308
309         return 1;
310 }
311
312 static void i82975x_check(struct mem_ctl_info *mci)
313 {
314         struct i82975x_error_info info;
315
316         debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
317         i82975x_get_error_info(mci, &info);
318         i82975x_process_error_info(mci, &info, 1);
319 }
320
321 /* Return 1 if dual channel mode is active.  Else return 0. */
322 static int dual_channel_active(void __iomem *mch_window)
323 {
324         /*
325          * We treat interleaved-symmetric configuration as dual-channel - EAP's
326          * bit-0 giving the channel of the error location.
327          *
328          * All other configurations are treated as single channel - the EAP's
329          * bit-0 will resolve ok in symmetric area of mixed
330          * (symmetric/asymmetric) configurations
331          */
332         u8      drb[4][2];
333         int     row;
334         int    dualch;
335
336         for (dualch = 1, row = 0; dualch && (row < 4); row++) {
337                 drb[row][0] = readb(mch_window + I82975X_DRB + row);
338                 drb[row][1] = readb(mch_window + I82975X_DRB + row + 0x80);
339                 dualch = dualch && (drb[row][0] == drb[row][1]);
340         }
341         return dualch;
342 }
343
344 static enum dev_type i82975x_dram_type(void __iomem *mch_window, int rank)
345 {
346         /*
347          * ASUS P5W DH either does not program this register or programs
348          * it wrong!
349          * ECC is possible on i92975x ONLY with DEV_X8 which should mean 'val'
350          * for each rank should be 01b - the LSB of the word should be 0x55;
351          * but it reads 0!
352          */
353         return DEV_X8;
354 }
355
356 static void i82975x_init_csrows(struct mem_ctl_info *mci,
357                 struct pci_dev *pdev, void __iomem *mch_window)
358 {
359         struct csrow_info *csrow;
360         unsigned long last_cumul_size;
361         u8 value;
362         u32 cumul_size;
363         int index;
364
365         last_cumul_size = 0;
366
367         /*
368          * 82875 comment:
369          * The dram row boundary (DRB) reg values are boundary address
370          * for each DRAM row with a granularity of 32 or 64MB (single/dual
371          * channel operation).  DRB regs are cumulative; therefore DRB7 will
372          * contain the total memory contained in all eight rows.
373          *
374          * FIXME:
375          *  EDAC currently works for Dual-channel Interleaved configuration.
376          *  Other configurations, which the chip supports, need fixing/testing.
377          *
378          */
379
380         for (index = 0; index < mci->nr_csrows; index++) {
381                 csrow = &mci->csrows[index];
382
383                 value = readb(mch_window + I82975X_DRB + index +
384                                         ((index >= 4) ? 0x80 : 0));
385                 cumul_size = value;
386                 cumul_size <<= (I82975X_DRB_SHIFT - PAGE_SHIFT);
387                 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
388                         cumul_size);
389                 if (cumul_size == last_cumul_size)
390                         continue;       /* not populated */
391
392                 csrow->first_page = last_cumul_size;
393                 csrow->last_page = cumul_size - 1;
394                 csrow->nr_pages = cumul_size - last_cumul_size;
395                 last_cumul_size = cumul_size;
396                 csrow->grain = 1 << 7;  /* I82975X_EAP has 128B resolution */
397                 csrow->mtype = MEM_DDR; /* i82975x supports only DDR2 */
398                 csrow->dtype = i82975x_dram_type(mch_window, index);
399                 csrow->edac_mode = EDAC_SECDED; /* only supported */
400         }
401 }
402
403 /* #define  i82975x_DEBUG_IOMEM */
404
405 #ifdef i82975x_DEBUG_IOMEM
406 static void i82975x_print_dram_timings(void __iomem *mch_window)
407 {
408         /*
409          * The register meanings are from Intel specs;
410          * (shows 13-5-5-5 for 800-DDR2)
411          * Asus P5W Bios reports 15-5-4-4
412          * What's your religion?
413          */
414         static const int caslats[4] = { 5, 4, 3, 6 };
415         u32     dtreg[2];
416
417         dtreg[0] = readl(mch_window + 0x114);
418         dtreg[1] = readl(mch_window + 0x194);
419         i82975x_printk(KERN_INFO, "DRAM Timings :     Ch0    Ch1\n"
420                 "                RAS Active Min = %d     %d\n"
421                 "                CAS latency    =  %d      %d\n"
422                 "                RAS to CAS     =  %d      %d\n"
423                 "                RAS precharge  =  %d      %d\n",
424                 (dtreg[0] >> 19 ) & 0x0f,
425                         (dtreg[1] >> 19) & 0x0f,
426                 caslats[(dtreg[0] >> 8) & 0x03],
427                         caslats[(dtreg[1] >> 8) & 0x03],
428                 ((dtreg[0] >> 4) & 0x07) + 2,
429                         ((dtreg[1] >> 4) & 0x07) + 2,
430                 (dtreg[0] & 0x07) + 2,
431                         (dtreg[1] & 0x07) + 2
432         );
433
434 }
435 #endif
436
437 static int i82975x_probe1(struct pci_dev *pdev, int dev_idx)
438 {
439         int rc = -ENODEV;
440         struct mem_ctl_info *mci;
441         struct i82975x_pvt *pvt;
442         void __iomem *mch_window;
443         u32 mchbar;
444         u32 drc[2];
445         struct i82975x_error_info discard;
446         int     chans;
447 #ifdef i82975x_DEBUG_IOMEM
448         u8 c0drb[4];
449         u8 c1drb[4];
450 #endif
451
452         debugf0("%s()\n", __func__);
453
454         pci_read_config_dword(pdev, I82975X_MCHBAR, &mchbar);
455         if (!(mchbar & 1)) {
456                 debugf3("%s(): failed, MCHBAR disabled!\n", __func__);
457                 goto fail0;
458         }
459         mchbar &= 0xffffc000;   /* bits 31:14 used for 16K window */
460         mch_window = ioremap_nocache(mchbar, 0x1000);
461
462 #ifdef i82975x_DEBUG_IOMEM
463         i82975x_printk(KERN_INFO, "MCHBAR real = %0x, remapped = %p\n",
464                                         mchbar, mch_window);
465
466         c0drb[0] = readb(mch_window + I82975X_DRB_CH0R0);
467         c0drb[1] = readb(mch_window + I82975X_DRB_CH0R1);
468         c0drb[2] = readb(mch_window + I82975X_DRB_CH0R2);
469         c0drb[3] = readb(mch_window + I82975X_DRB_CH0R3);
470         c1drb[0] = readb(mch_window + I82975X_DRB_CH1R0);
471         c1drb[1] = readb(mch_window + I82975X_DRB_CH1R1);
472         c1drb[2] = readb(mch_window + I82975X_DRB_CH1R2);
473         c1drb[3] = readb(mch_window + I82975X_DRB_CH1R3);
474         i82975x_printk(KERN_INFO, "DRBCH0R0 = 0x%02x\n", c0drb[0]);
475         i82975x_printk(KERN_INFO, "DRBCH0R1 = 0x%02x\n", c0drb[1]);
476         i82975x_printk(KERN_INFO, "DRBCH0R2 = 0x%02x\n", c0drb[2]);
477         i82975x_printk(KERN_INFO, "DRBCH0R3 = 0x%02x\n", c0drb[3]);
478         i82975x_printk(KERN_INFO, "DRBCH1R0 = 0x%02x\n", c1drb[0]);
479         i82975x_printk(KERN_INFO, "DRBCH1R1 = 0x%02x\n", c1drb[1]);
480         i82975x_printk(KERN_INFO, "DRBCH1R2 = 0x%02x\n", c1drb[2]);
481         i82975x_printk(KERN_INFO, "DRBCH1R3 = 0x%02x\n", c1drb[3]);
482 #endif
483
484         drc[0] = readl(mch_window + I82975X_DRC_CH0M0);
485         drc[1] = readl(mch_window + I82975X_DRC_CH1M0);
486 #ifdef i82975x_DEBUG_IOMEM
487         i82975x_printk(KERN_INFO, "DRC_CH0 = %0x, %s\n", drc[0],
488                         ((drc[0] >> 21) & 3) == 1 ?
489                                 "ECC enabled" : "ECC disabled");
490         i82975x_printk(KERN_INFO, "DRC_CH1 = %0x, %s\n", drc[1],
491                         ((drc[1] >> 21) & 3) == 1 ?
492                                 "ECC enabled" : "ECC disabled");
493
494         i82975x_printk(KERN_INFO, "C0 BNKARC = %0x\n",
495                 readw(mch_window + I82975X_C0BNKARC));
496         i82975x_printk(KERN_INFO, "C1 BNKARC = %0x\n",
497                 readw(mch_window + I82975X_C1BNKARC));
498         i82975x_print_dram_timings(mch_window);
499         goto fail1;
500 #endif
501         if (!(((drc[0] >> 21) & 3) == 1 || ((drc[1] >> 21) & 3) == 1)) {
502                 i82975x_printk(KERN_INFO, "ECC disabled on both channels.\n");
503                 goto fail1;
504         }
505
506         chans = dual_channel_active(mch_window) + 1;
507
508         /* assuming only one controller, index thus is 0 */
509         mci = edac_mc_alloc(sizeof(*pvt), I82975X_NR_CSROWS(chans),
510                                         chans, 0);
511         if (!mci) {
512                 rc = -ENOMEM;
513                 goto fail1;
514         }
515
516         debugf3("%s(): init mci\n", __func__);
517         mci->dev = &pdev->dev;
518         mci->mtype_cap = MEM_FLAG_DDR;
519         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
520         mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
521         mci->mod_name = EDAC_MOD_STR;
522         mci->mod_ver = I82975X_REVISION;
523         mci->ctl_name = i82975x_devs[dev_idx].ctl_name;
524         mci->edac_check = i82975x_check;
525         mci->ctl_page_to_phys = NULL;
526         debugf3("%s(): init pvt\n", __func__);
527         pvt = (struct i82975x_pvt *) mci->pvt_info;
528         pvt->mch_window = mch_window;
529         i82975x_init_csrows(mci, pdev, mch_window);
530         i82975x_get_error_info(mci, &discard);  /* clear counters */
531
532         /* finalize this instance of memory controller with edac core */
533         if (edac_mc_add_mc(mci)) {
534                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
535                 goto fail2;
536         }
537
538         /* get this far and it's successful */
539         debugf3("%s(): success\n", __func__);
540         return 0;
541
542 fail2:
543         edac_mc_free(mci);
544
545 fail1:
546         iounmap(mch_window);
547 fail0:
548         return rc;
549 }
550
551 /* returns count (>= 0), or negative on error */
552 static int __devinit i82975x_init_one(struct pci_dev *pdev,
553                 const struct pci_device_id *ent)
554 {
555         int rc;
556
557         debugf0("%s()\n", __func__);
558
559         if (pci_enable_device(pdev) < 0)
560                 return -EIO;
561
562         rc = i82975x_probe1(pdev, ent->driver_data);
563
564         if (mci_pdev == NULL)
565                 mci_pdev = pci_dev_get(pdev);
566
567         return rc;
568 }
569
570 static void __devexit i82975x_remove_one(struct pci_dev *pdev)
571 {
572         struct mem_ctl_info *mci;
573         struct i82975x_pvt *pvt;
574
575         debugf0("%s()\n", __func__);
576
577         mci = edac_mc_del_mc(&pdev->dev);
578         if (mci  == NULL)
579                 return;
580
581         pvt = mci->pvt_info;
582         if (pvt->mch_window)
583                 iounmap( pvt->mch_window );
584
585         edac_mc_free(mci);
586 }
587
588 static const struct pci_device_id i82975x_pci_tbl[] __devinitdata = {
589         {
590                 PCI_VEND_DEV(INTEL, 82975_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
591                 I82975X
592         },
593         {
594                 0,
595         }       /* 0 terminated list. */
596 };
597
598 MODULE_DEVICE_TABLE(pci, i82975x_pci_tbl);
599
600 static struct pci_driver i82975x_driver = {
601         .name = EDAC_MOD_STR,
602         .probe = i82975x_init_one,
603         .remove = __devexit_p(i82975x_remove_one),
604         .id_table = i82975x_pci_tbl,
605 };
606
607 static int __init i82975x_init(void)
608 {
609         int pci_rc;
610
611         debugf3("%s()\n", __func__);
612
613        /* Ensure that the OPSTATE is set correctly for POLL or NMI */
614        opstate_init();
615
616         pci_rc = pci_register_driver(&i82975x_driver);
617         if (pci_rc < 0)
618                 goto fail0;
619
620         if (mci_pdev == NULL) {
621                 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
622                                 PCI_DEVICE_ID_INTEL_82975_0, NULL);
623
624                 if (!mci_pdev) {
625                         debugf0("i82975x pci_get_device fail\n");
626                         pci_rc = -ENODEV;
627                         goto fail1;
628                 }
629
630                 pci_rc = i82975x_init_one(mci_pdev, i82975x_pci_tbl);
631
632                 if (pci_rc < 0) {
633                         debugf0("i82975x init fail\n");
634                         pci_rc = -ENODEV;
635                         goto fail1;
636                 }
637         }
638
639         return 0;
640
641 fail1:
642         pci_unregister_driver(&i82975x_driver);
643
644 fail0:
645         if (mci_pdev != NULL)
646                 pci_dev_put(mci_pdev);
647
648         return pci_rc;
649 }
650
651 static void __exit i82975x_exit(void)
652 {
653         debugf3("%s()\n", __func__);
654
655         pci_unregister_driver(&i82975x_driver);
656
657         if (!i82975x_registered) {
658                 i82975x_remove_one(mci_pdev);
659                 pci_dev_put(mci_pdev);
660         }
661 }
662
663 module_init(i82975x_init);
664 module_exit(i82975x_exit);
665
666 MODULE_LICENSE("GPL");
667 MODULE_AUTHOR("Arvind R. <arvino55@gmail.com>");
668 MODULE_DESCRIPTION("MC support for Intel 82975 memory hub controllers");
669
670 module_param(edac_op_state, int, 0444);
671 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");