ebb037b78758f5f86f06abba1613121f8195d858
[linux-2.6.git] / drivers / edac / i82875p_edac.c
1 /*
2  * Intel D82875P Memory Controller kernel module
3  * (C) 2003 Linux Networx (http://lnxi.com)
4  * This file may be distributed under the terms of the
5  * GNU General Public License.
6  *
7  * Written by Thayne Harbaugh
8  * Contributors:
9  *      Wang Zhenyu at intel.com
10  *
11  * $Id: edac_i82875p.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
12  *
13  * Note: E7210 appears same as D82875P - zhenyu.z.wang at intel.com
14  */
15
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/pci_ids.h>
20 #include <linux/slab.h>
21 #include <linux/edac.h>
22 #include "edac_core.h"
23
24 #define I82875P_REVISION        " Ver: 2.0.2 " __DATE__
25 #define EDAC_MOD_STR            "i82875p_edac"
26
27 #define i82875p_printk(level, fmt, arg...) \
28         edac_printk(level, "i82875p", fmt, ##arg)
29
30 #define i82875p_mc_printk(mci, level, fmt, arg...) \
31         edac_mc_chipset_printk(mci, level, "i82875p", fmt, ##arg)
32
33 #ifndef PCI_DEVICE_ID_INTEL_82875_0
34 #define PCI_DEVICE_ID_INTEL_82875_0     0x2578
35 #endif                          /* PCI_DEVICE_ID_INTEL_82875_0 */
36
37 #ifndef PCI_DEVICE_ID_INTEL_82875_6
38 #define PCI_DEVICE_ID_INTEL_82875_6     0x257e
39 #endif                          /* PCI_DEVICE_ID_INTEL_82875_6 */
40
41 /* four csrows in dual channel, eight in single channel */
42 #define I82875P_NR_CSROWS(nr_chans) (8/(nr_chans))
43
44 /* Intel 82875p register addresses - device 0 function 0 - DRAM Controller */
45 #define I82875P_EAP             0x58    /* Error Address Pointer (32b)
46                                          *
47                                          * 31:12 block address
48                                          * 11:0  reserved
49                                          */
50
51 #define I82875P_DERRSYN         0x5c    /* DRAM Error Syndrome (8b)
52                                          *
53                                          *  7:0  DRAM ECC Syndrome
54                                          */
55
56 #define I82875P_DES             0x5d    /* DRAM Error Status (8b)
57                                          *
58                                          *  7:1  reserved
59                                          *  0    Error channel 0/1
60                                          */
61
62 #define I82875P_ERRSTS          0xc8    /* Error Status Register (16b)
63                                          *
64                                          * 15:10 reserved
65                                          *  9    non-DRAM lock error (ndlock)
66                                          *  8    Sftwr Generated SMI
67                                          *  7    ECC UE
68                                          *  6    reserved
69                                          *  5    MCH detects unimplemented cycle
70                                          *  4    AGP access outside GA
71                                          *  3    Invalid AGP access
72                                          *  2    Invalid GA translation table
73                                          *  1    Unsupported AGP command
74                                          *  0    ECC CE
75                                          */
76
77 #define I82875P_ERRCMD          0xca    /* Error Command (16b)
78                                          *
79                                          * 15:10 reserved
80                                          *  9    SERR on non-DRAM lock
81                                          *  8    SERR on ECC UE
82                                          *  7    SERR on ECC CE
83                                          *  6    target abort on high exception
84                                          *  5    detect unimplemented cyc
85                                          *  4    AGP access outside of GA
86                                          *  3    SERR on invalid AGP access
87                                          *  2    invalid translation table
88                                          *  1    SERR on unsupported AGP command
89                                          *  0    reserved
90                                          */
91
92 /* Intel 82875p register addresses - device 6 function 0 - DRAM Controller */
93 #define I82875P_PCICMD6         0x04    /* PCI Command Register (16b)
94                                          *
95                                          * 15:10 reserved
96                                          *  9    fast back-to-back - ro 0
97                                          *  8    SERR enable - ro 0
98                                          *  7    addr/data stepping - ro 0
99                                          *  6    parity err enable - ro 0
100                                          *  5    VGA palette snoop - ro 0
101                                          *  4    mem wr & invalidate - ro 0
102                                          *  3    special cycle - ro 0
103                                          *  2    bus master - ro 0
104                                          *  1    mem access dev6 - 0(dis),1(en)
105                                          *  0    IO access dev3 - 0(dis),1(en)
106                                          */
107
108 #define I82875P_BAR6            0x10    /* Mem Delays Base ADDR Reg (32b)
109                                          *
110                                          * 31:12 mem base addr [31:12]
111                                          * 11:4  address mask - ro 0
112                                          *  3    prefetchable - ro 0(non),1(pre)
113                                          *  2:1  mem type - ro 0
114                                          *  0    mem space - ro 0
115                                          */
116
117 /* Intel 82875p MMIO register space - device 0 function 0 - MMR space */
118
119 #define I82875P_DRB_SHIFT 26    /* 64MiB grain */
120 #define I82875P_DRB             0x00    /* DRAM Row Boundary (8b x 8)
121                                          *
122                                          *  7    reserved
123                                          *  6:0  64MiB row boundary addr
124                                          */
125
126 #define I82875P_DRA             0x10    /* DRAM Row Attribute (4b x 8)
127                                          *
128                                          *  7    reserved
129                                          *  6:4  row attr row 1
130                                          *  3    reserved
131                                          *  2:0  row attr row 0
132                                          *
133                                          * 000 =  4KiB
134                                          * 001 =  8KiB
135                                          * 010 = 16KiB
136                                          * 011 = 32KiB
137                                          */
138
139 #define I82875P_DRC             0x68    /* DRAM Controller Mode (32b)
140                                          *
141                                          * 31:30 reserved
142                                          * 29    init complete
143                                          * 28:23 reserved
144                                          * 22:21 nr chan 00=1,01=2
145                                          * 20    reserved
146                                          * 19:18 Data Integ Mode 00=none,01=ecc
147                                          * 17:11 reserved
148                                          * 10:8  refresh mode
149                                          *  7    reserved
150                                          *  6:4  mode select
151                                          *  3:2  reserved
152                                          *  1:0  DRAM type 01=DDR
153                                          */
154
155 enum i82875p_chips {
156         I82875P = 0,
157 };
158
159 struct i82875p_pvt {
160         struct pci_dev *ovrfl_pdev;
161         void __iomem *ovrfl_window;
162 };
163
164 struct i82875p_dev_info {
165         const char *ctl_name;
166 };
167
168 struct i82875p_error_info {
169         u16 errsts;
170         u32 eap;
171         u8 des;
172         u8 derrsyn;
173         u16 errsts2;
174 };
175
176 static const struct i82875p_dev_info i82875p_devs[] = {
177         [I82875P] = {
178                 .ctl_name = "i82875p"},
179 };
180
181 static struct pci_dev *mci_pdev;        /* init dev: in case that AGP code has
182                                          * already registered driver
183                                          */
184
185 static struct edac_pci_ctl_info *i82875p_pci;
186
187 static void i82875p_get_error_info(struct mem_ctl_info *mci,
188                                 struct i82875p_error_info *info)
189 {
190         struct pci_dev *pdev;
191
192         pdev = to_pci_dev(mci->dev);
193
194         /*
195          * This is a mess because there is no atomic way to read all the
196          * registers at once and the registers can transition from CE being
197          * overwritten by UE.
198          */
199         pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts);
200
201         if (!(info->errsts & 0x0081))
202                 return;
203
204         pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
205         pci_read_config_byte(pdev, I82875P_DES, &info->des);
206         pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
207         pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts2);
208
209         /*
210          * If the error is the same then we can for both reads then
211          * the first set of reads is valid.  If there is a change then
212          * there is a CE no info and the second set of reads is valid
213          * and should be UE info.
214          */
215         if ((info->errsts ^ info->errsts2) & 0x0081) {
216                 pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
217                 pci_read_config_byte(pdev, I82875P_DES, &info->des);
218                 pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
219         }
220
221         pci_write_bits16(pdev, I82875P_ERRSTS, 0x0081, 0x0081);
222 }
223
224 static int i82875p_process_error_info(struct mem_ctl_info *mci,
225                                 struct i82875p_error_info *info,
226                                 int handle_errors)
227 {
228         int row, multi_chan;
229
230         multi_chan = mci->csrows[0].nr_channels - 1;
231
232         if (!(info->errsts & 0x0081))
233                 return 0;
234
235         if (!handle_errors)
236                 return 1;
237
238         if ((info->errsts ^ info->errsts2) & 0x0081) {
239                 edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
240                 info->errsts = info->errsts2;
241         }
242
243         info->eap >>= PAGE_SHIFT;
244         row = edac_mc_find_csrow_by_page(mci, info->eap);
245
246         if (info->errsts & 0x0080)
247                 edac_mc_handle_ue(mci, info->eap, 0, row, "i82875p UE");
248         else
249                 edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row,
250                                 multi_chan ? (info->des & 0x1) : 0,
251                                 "i82875p CE");
252
253         return 1;
254 }
255
256 static void i82875p_check(struct mem_ctl_info *mci)
257 {
258         struct i82875p_error_info info;
259
260         debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
261         i82875p_get_error_info(mci, &info);
262         i82875p_process_error_info(mci, &info, 1);
263 }
264
265 /* Return 0 on success or 1 on failure. */
266 static int i82875p_setup_overfl_dev(struct pci_dev *pdev,
267                                 struct pci_dev **ovrfl_pdev,
268                                 void __iomem **ovrfl_window)
269 {
270         struct pci_dev *dev;
271         void __iomem *window;
272         int err;
273
274         *ovrfl_pdev = NULL;
275         *ovrfl_window = NULL;
276         dev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
277
278         if (dev == NULL) {
279                 /* Intel tells BIOS developers to hide device 6 which
280                  * configures the overflow device access containing
281                  * the DRBs - this is where we expose device 6.
282                  * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
283                  */
284                 pci_write_bits8(pdev, 0xf4, 0x2, 0x2);
285                 dev = pci_scan_single_device(pdev->bus, PCI_DEVFN(6, 0));
286
287                 if (dev == NULL)
288                         return 1;
289
290                 err = pci_bus_add_device(dev);
291                 if (err) {
292                         i82875p_printk(KERN_ERR,
293                                 "%s(): pci_bus_add_device() Failed\n",
294                                 __func__);
295                 }
296                 pci_bus_assign_resources(dev->bus);
297         }
298
299         *ovrfl_pdev = dev;
300
301         if (pci_enable_device(dev)) {
302                 i82875p_printk(KERN_ERR, "%s(): Failed to enable overflow "
303                         "device\n", __func__);
304                 return 1;
305         }
306
307         if (pci_request_regions(dev, pci_name(dev))) {
308 #ifdef CORRECT_BIOS
309                 goto fail0;
310 #endif
311         }
312
313         /* cache is irrelevant for PCI bus reads/writes */
314         window = ioremap_nocache(pci_resource_start(dev, 0),
315                                  pci_resource_len(dev, 0));
316
317         if (window == NULL) {
318                 i82875p_printk(KERN_ERR, "%s(): Failed to ioremap bar6\n",
319                         __func__);
320                 goto fail1;
321         }
322
323         *ovrfl_window = window;
324         return 0;
325
326 fail1:
327         pci_release_regions(dev);
328
329 #ifdef CORRECT_BIOS
330 fail0:
331         pci_disable_device(dev);
332 #endif
333         /* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
334         return 1;
335 }
336
337 /* Return 1 if dual channel mode is active.  Else return 0. */
338 static inline int dual_channel_active(u32 drc)
339 {
340         return (drc >> 21) & 0x1;
341 }
342
343 static void i82875p_init_csrows(struct mem_ctl_info *mci,
344                                 struct pci_dev *pdev,
345                                 void __iomem * ovrfl_window, u32 drc)
346 {
347         struct csrow_info *csrow;
348         unsigned long last_cumul_size;
349         u8 value;
350         u32 drc_ddim;           /* DRAM Data Integrity Mode 0=none,2=edac */
351         u32 cumul_size;
352         int index;
353
354         drc_ddim = (drc >> 18) & 0x1;
355         last_cumul_size = 0;
356
357         /* The dram row boundary (DRB) reg values are boundary address
358          * for each DRAM row with a granularity of 32 or 64MB (single/dual
359          * channel operation).  DRB regs are cumulative; therefore DRB7 will
360          * contain the total memory contained in all eight rows.
361          */
362
363         for (index = 0; index < mci->nr_csrows; index++) {
364                 csrow = &mci->csrows[index];
365
366                 value = readb(ovrfl_window + I82875P_DRB + index);
367                 cumul_size = value << (I82875P_DRB_SHIFT - PAGE_SHIFT);
368                 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
369                         cumul_size);
370                 if (cumul_size == last_cumul_size)
371                         continue;       /* not populated */
372
373                 csrow->first_page = last_cumul_size;
374                 csrow->last_page = cumul_size - 1;
375                 csrow->nr_pages = cumul_size - last_cumul_size;
376                 last_cumul_size = cumul_size;
377                 csrow->grain = 1 << 12; /* I82875P_EAP has 4KiB reolution */
378                 csrow->mtype = MEM_DDR;
379                 csrow->dtype = DEV_UNKNOWN;
380                 csrow->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE;
381         }
382 }
383
384 static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
385 {
386         int rc = -ENODEV;
387         struct mem_ctl_info *mci;
388         struct i82875p_pvt *pvt;
389         struct pci_dev *ovrfl_pdev;
390         void __iomem *ovrfl_window;
391         u32 drc;
392         u32 nr_chans;
393         struct i82875p_error_info discard;
394
395         debugf0("%s()\n", __func__);
396
397         ovrfl_pdev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
398
399         if (i82875p_setup_overfl_dev(pdev, &ovrfl_pdev, &ovrfl_window))
400                 return -ENODEV;
401         drc = readl(ovrfl_window + I82875P_DRC);
402         nr_chans = dual_channel_active(drc) + 1;
403         mci = edac_mc_alloc(sizeof(*pvt), I82875P_NR_CSROWS(nr_chans),
404                         nr_chans, 0);
405
406         if (!mci) {
407                 rc = -ENOMEM;
408                 goto fail0;
409         }
410
411         /* Keeps mci available after edac_mc_del_mc() till edac_mc_free() */
412         kobject_get(&mci->edac_mci_kobj);
413
414         debugf3("%s(): init mci\n", __func__);
415         mci->dev = &pdev->dev;
416         mci->mtype_cap = MEM_FLAG_DDR;
417         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
418         mci->edac_cap = EDAC_FLAG_UNKNOWN;
419         mci->mod_name = EDAC_MOD_STR;
420         mci->mod_ver = I82875P_REVISION;
421         mci->ctl_name = i82875p_devs[dev_idx].ctl_name;
422         mci->dev_name = pci_name(pdev);
423         mci->edac_check = i82875p_check;
424         mci->ctl_page_to_phys = NULL;
425         debugf3("%s(): init pvt\n", __func__);
426         pvt = (struct i82875p_pvt *)mci->pvt_info;
427         pvt->ovrfl_pdev = ovrfl_pdev;
428         pvt->ovrfl_window = ovrfl_window;
429         i82875p_init_csrows(mci, pdev, ovrfl_window, drc);
430         i82875p_get_error_info(mci, &discard);  /* clear counters */
431
432         /* Here we assume that we will never see multiple instances of this
433          * type of memory controller.  The ID is therefore hardcoded to 0.
434          */
435         if (edac_mc_add_mc(mci)) {
436                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
437                 goto fail1;
438         }
439
440         /* allocating generic PCI control info */
441         i82875p_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
442         if (!i82875p_pci) {
443                 printk(KERN_WARNING
444                         "%s(): Unable to create PCI control\n",
445                         __func__);
446                 printk(KERN_WARNING
447                         "%s(): PCI error report via EDAC not setup\n",
448                         __func__);
449         }
450
451         /* get this far and it's successful */
452         debugf3("%s(): success\n", __func__);
453         return 0;
454
455 fail1:
456         kobject_put(&mci->edac_mci_kobj);
457         edac_mc_free(mci);
458
459 fail0:
460         iounmap(ovrfl_window);
461         pci_release_regions(ovrfl_pdev);
462
463         pci_disable_device(ovrfl_pdev);
464         /* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
465         return rc;
466 }
467
468 /* returns count (>= 0), or negative on error */
469 static int __devinit i82875p_init_one(struct pci_dev *pdev,
470                                 const struct pci_device_id *ent)
471 {
472         int rc;
473
474         debugf0("%s()\n", __func__);
475         i82875p_printk(KERN_INFO, "i82875p init one\n");
476
477         if (pci_enable_device(pdev) < 0)
478                 return -EIO;
479
480         rc = i82875p_probe1(pdev, ent->driver_data);
481
482         if (mci_pdev == NULL)
483                 mci_pdev = pci_dev_get(pdev);
484
485         return rc;
486 }
487
488 static void __devexit i82875p_remove_one(struct pci_dev *pdev)
489 {
490         struct mem_ctl_info *mci;
491         struct i82875p_pvt *pvt = NULL;
492
493         debugf0("%s()\n", __func__);
494
495         if (i82875p_pci)
496                 edac_pci_release_generic_ctl(i82875p_pci);
497
498         if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
499                 return;
500
501         pvt = (struct i82875p_pvt *)mci->pvt_info;
502
503         if (pvt->ovrfl_window)
504                 iounmap(pvt->ovrfl_window);
505
506         if (pvt->ovrfl_pdev) {
507 #ifdef CORRECT_BIOS
508                 pci_release_regions(pvt->ovrfl_pdev);
509 #endif                          /*CORRECT_BIOS */
510                 pci_disable_device(pvt->ovrfl_pdev);
511                 pci_dev_put(pvt->ovrfl_pdev);
512         }
513
514         edac_mc_free(mci);
515 }
516
517 static const struct pci_device_id i82875p_pci_tbl[] __devinitdata = {
518         {
519          PCI_VEND_DEV(INTEL, 82875_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
520          I82875P},
521         {
522          0,
523          }                      /* 0 terminated list. */
524 };
525
526 MODULE_DEVICE_TABLE(pci, i82875p_pci_tbl);
527
528 static struct pci_driver i82875p_driver = {
529         .name = EDAC_MOD_STR,
530         .probe = i82875p_init_one,
531         .remove = __devexit_p(i82875p_remove_one),
532         .id_table = i82875p_pci_tbl,
533 };
534
535 static int __init i82875p_init(void)
536 {
537         int pci_rc;
538
539         debugf3("%s()\n", __func__);
540
541        /* Ensure that the OPSTATE is set correctly for POLL or NMI */
542        opstate_init();
543
544         pci_rc = pci_register_driver(&i82875p_driver);
545
546         if (pci_rc < 0)
547                 goto fail0;
548
549         if (mci_pdev == NULL) {
550                 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
551                                         PCI_DEVICE_ID_INTEL_82875_0, NULL);
552
553                 if (!mci_pdev) {
554                         debugf0("875p pci_get_device fail\n");
555                         pci_rc = -ENODEV;
556                         goto fail1;
557                 }
558
559                 pci_rc = i82875p_init_one(mci_pdev, i82875p_pci_tbl);
560
561                 if (pci_rc < 0) {
562                         debugf0("875p init fail\n");
563                         pci_rc = -ENODEV;
564                         goto fail1;
565                 }
566         }
567
568         return 0;
569
570 fail1:
571         pci_unregister_driver(&i82875p_driver);
572
573 fail0:
574         if (mci_pdev != NULL)
575                 pci_dev_put(mci_pdev);
576
577         return pci_rc;
578 }
579
580 static void __exit i82875p_exit(void)
581 {
582         debugf3("%s()\n", __func__);
583
584         i82875p_remove_one(mci_pdev);
585         pci_dev_put(mci_pdev);
586
587         pci_unregister_driver(&i82875p_driver);
588
589 }
590
591 module_init(i82875p_init);
592 module_exit(i82875p_exit);
593
594 MODULE_LICENSE("GPL");
595 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
596 MODULE_DESCRIPTION("MC support for Intel 82875 memory hub controllers");
597
598 module_param(edac_op_state, int, 0444);
599 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");