Fix 82875 PCI setup
[linux-2.6.git] / drivers / edac / i82875p_edac.c
1 /*
2  * Intel D82875P Memory Controller kernel module
3  * (C) 2003 Linux Networx (http://lnxi.com)
4  * This file may be distributed under the terms of the
5  * GNU General Public License.
6  *
7  * Written by Thayne Harbaugh
8  * Contributors:
9  *      Wang Zhenyu at intel.com
10  *
11  * $Id: edac_i82875p.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
12  *
13  * Note: E7210 appears same as D82875P - zhenyu.z.wang at intel.com
14  */
15
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/pci_ids.h>
20 #include <linux/slab.h>
21 #include "edac_mc.h"
22
23 #define I82875P_REVISION        " Ver: 2.0.1 " __DATE__
24 #define EDAC_MOD_STR            "i82875p_edac"
25
26 #define i82875p_printk(level, fmt, arg...) \
27         edac_printk(level, "i82875p", fmt, ##arg)
28
29 #define i82875p_mc_printk(mci, level, fmt, arg...) \
30         edac_mc_chipset_printk(mci, level, "i82875p", fmt, ##arg)
31
32 #ifndef PCI_DEVICE_ID_INTEL_82875_0
33 #define PCI_DEVICE_ID_INTEL_82875_0     0x2578
34 #endif                          /* PCI_DEVICE_ID_INTEL_82875_0 */
35
36 #ifndef PCI_DEVICE_ID_INTEL_82875_6
37 #define PCI_DEVICE_ID_INTEL_82875_6     0x257e
38 #endif                          /* PCI_DEVICE_ID_INTEL_82875_6 */
39
40 /* four csrows in dual channel, eight in single channel */
41 #define I82875P_NR_CSROWS(nr_chans) (8/(nr_chans))
42
43 /* Intel 82875p register addresses - device 0 function 0 - DRAM Controller */
44 #define I82875P_EAP             0x58    /* Error Address Pointer (32b)
45                                          *
46                                          * 31:12 block address
47                                          * 11:0  reserved
48                                          */
49
50 #define I82875P_DERRSYN         0x5c    /* DRAM Error Syndrome (8b)
51                                          *
52                                          *  7:0  DRAM ECC Syndrome
53                                          */
54
55 #define I82875P_DES             0x5d    /* DRAM Error Status (8b)
56                                          *
57                                          *  7:1  reserved
58                                          *  0    Error channel 0/1
59                                          */
60
61 #define I82875P_ERRSTS          0xc8    /* Error Status Register (16b)
62                                          *
63                                          * 15:10 reserved
64                                          *  9    non-DRAM lock error (ndlock)
65                                          *  8    Sftwr Generated SMI
66                                          *  7    ECC UE
67                                          *  6    reserved
68                                          *  5    MCH detects unimplemented cycle
69                                          *  4    AGP access outside GA
70                                          *  3    Invalid AGP access
71                                          *  2    Invalid GA translation table
72                                          *  1    Unsupported AGP command
73                                          *  0    ECC CE
74                                          */
75
76 #define I82875P_ERRCMD          0xca    /* Error Command (16b)
77                                          *
78                                          * 15:10 reserved
79                                          *  9    SERR on non-DRAM lock
80                                          *  8    SERR on ECC UE
81                                          *  7    SERR on ECC CE
82                                          *  6    target abort on high exception
83                                          *  5    detect unimplemented cyc
84                                          *  4    AGP access outside of GA
85                                          *  3    SERR on invalid AGP access
86                                          *  2    invalid translation table
87                                          *  1    SERR on unsupported AGP command
88                                          *  0    reserved
89                                          */
90
91 /* Intel 82875p register addresses - device 6 function 0 - DRAM Controller */
92 #define I82875P_PCICMD6         0x04    /* PCI Command Register (16b)
93                                          *
94                                          * 15:10 reserved
95                                          *  9    fast back-to-back - ro 0
96                                          *  8    SERR enable - ro 0
97                                          *  7    addr/data stepping - ro 0
98                                          *  6    parity err enable - ro 0
99                                          *  5    VGA palette snoop - ro 0
100                                          *  4    mem wr & invalidate - ro 0
101                                          *  3    special cycle - ro 0
102                                          *  2    bus master - ro 0
103                                          *  1    mem access dev6 - 0(dis),1(en)
104                                          *  0    IO access dev3 - 0(dis),1(en)
105                                          */
106
107 #define I82875P_BAR6            0x10    /* Mem Delays Base ADDR Reg (32b)
108                                          *
109                                          * 31:12 mem base addr [31:12]
110                                          * 11:4  address mask - ro 0
111                                          *  3    prefetchable - ro 0(non),1(pre)
112                                          *  2:1  mem type - ro 0
113                                          *  0    mem space - ro 0
114                                          */
115
116 /* Intel 82875p MMIO register space - device 0 function 0 - MMR space */
117
118 #define I82875P_DRB_SHIFT 26    /* 64MiB grain */
119 #define I82875P_DRB             0x00    /* DRAM Row Boundary (8b x 8)
120                                          *
121                                          *  7    reserved
122                                          *  6:0  64MiB row boundary addr
123                                          */
124
125 #define I82875P_DRA             0x10    /* DRAM Row Attribute (4b x 8)
126                                          *
127                                          *  7    reserved
128                                          *  6:4  row attr row 1
129                                          *  3    reserved
130                                          *  2:0  row attr row 0
131                                          *
132                                          * 000 =  4KiB
133                                          * 001 =  8KiB
134                                          * 010 = 16KiB
135                                          * 011 = 32KiB
136                                          */
137
138 #define I82875P_DRC             0x68    /* DRAM Controller Mode (32b)
139                                          *
140                                          * 31:30 reserved
141                                          * 29    init complete
142                                          * 28:23 reserved
143                                          * 22:21 nr chan 00=1,01=2
144                                          * 20    reserved
145                                          * 19:18 Data Integ Mode 00=none,01=ecc
146                                          * 17:11 reserved
147                                          * 10:8  refresh mode
148                                          *  7    reserved
149                                          *  6:4  mode select
150                                          *  3:2  reserved
151                                          *  1:0  DRAM type 01=DDR
152                                          */
153
154 enum i82875p_chips {
155         I82875P = 0,
156 };
157
158 struct i82875p_pvt {
159         struct pci_dev *ovrfl_pdev;
160         void __iomem *ovrfl_window;
161 };
162
163 struct i82875p_dev_info {
164         const char *ctl_name;
165 };
166
167 struct i82875p_error_info {
168         u16 errsts;
169         u32 eap;
170         u8 des;
171         u8 derrsyn;
172         u16 errsts2;
173 };
174
175 static const struct i82875p_dev_info i82875p_devs[] = {
176         [I82875P] = {
177                 .ctl_name = "i82875p"
178         },
179 };
180
181 static struct pci_dev *mci_pdev = NULL; /* init dev: in case that AGP code has
182                                          * already registered driver
183                                          */
184
185 static int i82875p_registered = 1;
186
187 static void i82875p_get_error_info(struct mem_ctl_info *mci,
188                 struct i82875p_error_info *info)
189 {
190         struct pci_dev *pdev;
191
192         pdev = to_pci_dev(mci->dev);
193
194         /*
195          * This is a mess because there is no atomic way to read all the
196          * registers at once and the registers can transition from CE being
197          * overwritten by UE.
198          */
199         pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts);
200         pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
201         pci_read_config_byte(pdev, I82875P_DES, &info->des);
202         pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
203         pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts2);
204
205         pci_write_bits16(pdev, I82875P_ERRSTS, 0x0081, 0x0081);
206
207         /*
208          * If the error is the same then we can for both reads then
209          * the first set of reads is valid.  If there is a change then
210          * there is a CE no info and the second set of reads is valid
211          * and should be UE info.
212          */
213         if (!(info->errsts2 & 0x0081))
214                 return;
215
216         if ((info->errsts ^ info->errsts2) & 0x0081) {
217                 pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
218                 pci_read_config_byte(pdev, I82875P_DES, &info->des);
219                 pci_read_config_byte(pdev, I82875P_DERRSYN,
220                                 &info->derrsyn);
221         }
222 }
223
224 static int i82875p_process_error_info(struct mem_ctl_info *mci,
225                 struct i82875p_error_info *info, int handle_errors)
226 {
227         int row, multi_chan;
228
229         multi_chan = mci->csrows[0].nr_channels - 1;
230
231         if (!(info->errsts2 & 0x0081))
232                 return 0;
233
234         if (!handle_errors)
235                 return 1;
236
237         if ((info->errsts ^ info->errsts2) & 0x0081) {
238                 edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
239                 info->errsts = info->errsts2;
240         }
241
242         info->eap >>= PAGE_SHIFT;
243         row = edac_mc_find_csrow_by_page(mci, info->eap);
244
245         if (info->errsts & 0x0080)
246                 edac_mc_handle_ue(mci, info->eap, 0, row, "i82875p UE");
247         else
248                 edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row,
249                                 multi_chan ? (info->des & 0x1) : 0,
250                                 "i82875p CE");
251
252         return 1;
253 }
254
255 static void i82875p_check(struct mem_ctl_info *mci)
256 {
257         struct i82875p_error_info info;
258
259         debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
260         i82875p_get_error_info(mci, &info);
261         i82875p_process_error_info(mci, &info, 1);
262 }
263
264 /* Return 0 on success or 1 on failure. */
265 static int i82875p_setup_overfl_dev(struct pci_dev *pdev,
266                 struct pci_dev **ovrfl_pdev, void __iomem **ovrfl_window)
267 {
268         struct pci_dev *dev;
269         void __iomem *window;
270
271         *ovrfl_pdev = NULL;
272         *ovrfl_window = NULL;
273         dev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
274
275         if (dev == NULL) {
276                 /* Intel tells BIOS developers to hide device 6 which
277                  * configures the overflow device access containing
278                  * the DRBs - this is where we expose device 6.
279                  * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
280                  */
281                 pci_write_bits8(pdev, 0xf4, 0x2, 0x2);
282                 dev = pci_scan_single_device(pdev->bus, PCI_DEVFN(6, 0));
283
284                 if (dev == NULL)
285                         return 1;
286
287                 pci_bus_add_device(dev);
288         }
289
290         *ovrfl_pdev = dev;
291
292         if (pci_enable_device(dev)) {
293                 i82875p_printk(KERN_ERR, "%s(): Failed to enable overflow "
294                                "device\n", __func__);
295                 return 1;
296         }
297
298         if (pci_request_regions(dev, pci_name(dev))) {
299 #ifdef CORRECT_BIOS
300                 goto fail0;
301 #endif
302         }
303
304         /* cache is irrelevant for PCI bus reads/writes */
305         window = ioremap_nocache(pci_resource_start(dev, 0),
306                                  pci_resource_len(dev, 0));
307
308         if (window == NULL) {
309                 i82875p_printk(KERN_ERR, "%s(): Failed to ioremap bar6\n",
310                                __func__);
311                 goto fail1;
312         }
313
314         *ovrfl_window = window;
315         return 0;
316
317 fail1:
318         pci_release_regions(dev);
319
320 #ifdef CORRECT_BIOS
321 fail0:
322         pci_disable_device(dev);
323 #endif
324         /* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
325         return 1;
326 }
327
328
329 /* Return 1 if dual channel mode is active.  Else return 0. */
330 static inline int dual_channel_active(u32 drc)
331 {
332         return (drc >> 21) & 0x1;
333 }
334
335
336 static void i82875p_init_csrows(struct mem_ctl_info *mci,
337                 struct pci_dev *pdev, void __iomem *ovrfl_window, u32 drc)
338 {
339         struct csrow_info *csrow;
340         unsigned long last_cumul_size;
341         u8 value;
342         u32 drc_ddim;  /* DRAM Data Integrity Mode 0=none,2=edac */
343         u32 cumul_size;
344         int index;
345
346         drc_ddim = (drc >> 18) & 0x1;
347         last_cumul_size = 0;
348
349         /* The dram row boundary (DRB) reg values are boundary address
350          * for each DRAM row with a granularity of 32 or 64MB (single/dual
351          * channel operation).  DRB regs are cumulative; therefore DRB7 will
352          * contain the total memory contained in all eight rows.
353          */
354
355         for (index = 0; index < mci->nr_csrows; index++) {
356                 csrow = &mci->csrows[index];
357
358                 value = readb(ovrfl_window + I82875P_DRB + index);
359                 cumul_size = value << (I82875P_DRB_SHIFT - PAGE_SHIFT);
360                 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
361                         cumul_size);
362                 if (cumul_size == last_cumul_size)
363                         continue;       /* not populated */
364
365                 csrow->first_page = last_cumul_size;
366                 csrow->last_page = cumul_size - 1;
367                 csrow->nr_pages = cumul_size - last_cumul_size;
368                 last_cumul_size = cumul_size;
369                 csrow->grain = 1 << 12; /* I82875P_EAP has 4KiB reolution */
370                 csrow->mtype = MEM_DDR;
371                 csrow->dtype = DEV_UNKNOWN;
372                 csrow->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE;
373         }
374 }
375
376 static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
377 {
378         int rc = -ENODEV;
379         struct mem_ctl_info *mci;
380         struct i82875p_pvt *pvt;
381         struct pci_dev *ovrfl_pdev;
382         void __iomem *ovrfl_window;
383         u32 drc;
384         u32 nr_chans;
385         struct i82875p_error_info discard;
386
387         debugf0("%s()\n", __func__);
388         ovrfl_pdev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
389
390         if (i82875p_setup_overfl_dev(pdev, &ovrfl_pdev, &ovrfl_window))
391                 return -ENODEV;
392         drc = readl(ovrfl_window + I82875P_DRC);
393         nr_chans = dual_channel_active(drc) + 1;
394         mci = edac_mc_alloc(sizeof(*pvt), I82875P_NR_CSROWS(nr_chans),
395                                 nr_chans);
396
397         if (!mci) {
398                 rc = -ENOMEM;
399                 goto fail0;
400         }
401
402         debugf3("%s(): init mci\n", __func__);
403         mci->dev = &pdev->dev;
404         mci->mtype_cap = MEM_FLAG_DDR;
405         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
406         mci->edac_cap = EDAC_FLAG_UNKNOWN;
407         mci->mod_name = EDAC_MOD_STR;
408         mci->mod_ver = I82875P_REVISION;
409         mci->ctl_name = i82875p_devs[dev_idx].ctl_name;
410         mci->edac_check = i82875p_check;
411         mci->ctl_page_to_phys = NULL;
412         debugf3("%s(): init pvt\n", __func__);
413         pvt = (struct i82875p_pvt *) mci->pvt_info;
414         pvt->ovrfl_pdev = ovrfl_pdev;
415         pvt->ovrfl_window = ovrfl_window;
416         i82875p_init_csrows(mci, pdev, ovrfl_window, drc);
417         i82875p_get_error_info(mci, &discard);  /* clear counters */
418
419         /* Here we assume that we will never see multiple instances of this
420          * type of memory controller.  The ID is therefore hardcoded to 0.
421          */
422         if (edac_mc_add_mc(mci,0)) {
423                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
424                 goto fail1;
425         }
426
427         /* get this far and it's successful */
428         debugf3("%s(): success\n", __func__);
429         return 0;
430
431 fail1:
432         edac_mc_free(mci);
433
434 fail0:
435         iounmap(ovrfl_window);
436         pci_release_regions(ovrfl_pdev);
437
438         pci_disable_device(ovrfl_pdev);
439         /* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
440         return rc;
441 }
442
443 /* returns count (>= 0), or negative on error */
444 static int __devinit i82875p_init_one(struct pci_dev *pdev,
445                 const struct pci_device_id *ent)
446 {
447         int rc;
448
449         debugf0("%s()\n", __func__);
450         i82875p_printk(KERN_INFO, "i82875p init one\n");
451
452         if (pci_enable_device(pdev) < 0)
453                 return -EIO;
454
455         rc = i82875p_probe1(pdev, ent->driver_data);
456
457         if (mci_pdev == NULL)
458                 mci_pdev = pci_dev_get(pdev);
459
460         return rc;
461 }
462
463 static void __devexit i82875p_remove_one(struct pci_dev *pdev)
464 {
465         struct mem_ctl_info *mci;
466         struct i82875p_pvt *pvt = NULL;
467
468         debugf0("%s()\n", __func__);
469
470         if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
471                 return;
472
473         pvt = (struct i82875p_pvt *) mci->pvt_info;
474
475         if (pvt->ovrfl_window)
476                 iounmap(pvt->ovrfl_window);
477
478         if (pvt->ovrfl_pdev) {
479 #ifdef CORRECT_BIOS
480                 pci_release_regions(pvt->ovrfl_pdev);
481 #endif                          /*CORRECT_BIOS */
482                 pci_disable_device(pvt->ovrfl_pdev);
483                 pci_dev_put(pvt->ovrfl_pdev);
484         }
485
486         edac_mc_free(mci);
487 }
488
489 static const struct pci_device_id i82875p_pci_tbl[] __devinitdata = {
490         {
491                 PCI_VEND_DEV(INTEL, 82875_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
492                 I82875P
493         },
494         {
495                 0,
496         }       /* 0 terminated list. */
497 };
498
499 MODULE_DEVICE_TABLE(pci, i82875p_pci_tbl);
500
501 static struct pci_driver i82875p_driver = {
502         .name = EDAC_MOD_STR,
503         .probe = i82875p_init_one,
504         .remove = __devexit_p(i82875p_remove_one),
505         .id_table = i82875p_pci_tbl,
506 };
507
508 static int __init i82875p_init(void)
509 {
510         int pci_rc;
511
512         debugf3("%s()\n", __func__);
513         pci_rc = pci_register_driver(&i82875p_driver);
514
515         if (pci_rc < 0)
516                 goto fail0;
517
518         if (mci_pdev == NULL) {
519                 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
520                                 PCI_DEVICE_ID_INTEL_82875_0, NULL);
521
522                 if (!mci_pdev) {
523                         debugf0("875p pci_get_device fail\n");
524                         pci_rc = -ENODEV;
525                         goto fail1;
526                 }
527
528                 pci_rc = i82875p_init_one(mci_pdev, i82875p_pci_tbl);
529
530                 if (pci_rc < 0) {
531                         debugf0("875p init fail\n");
532                         pci_rc = -ENODEV;
533                         goto fail1;
534                 }
535         }
536
537         return 0;
538
539 fail1:
540         pci_unregister_driver(&i82875p_driver);
541
542 fail0:
543         if (mci_pdev != NULL)
544                 pci_dev_put(mci_pdev);
545
546         return pci_rc;
547 }
548
549 static void __exit i82875p_exit(void)
550 {
551         debugf3("%s()\n", __func__);
552
553         pci_unregister_driver(&i82875p_driver);
554
555         if (!i82875p_registered) {
556                 i82875p_remove_one(mci_pdev);
557                 pci_dev_put(mci_pdev);
558         }
559 }
560
561 module_init(i82875p_init);
562 module_exit(i82875p_exit);
563
564 MODULE_LICENSE("GPL");
565 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
566 MODULE_DESCRIPTION("MC support for Intel 82875 memory hub controllers");