drivers/edac: cleanup spaces-gotos after Lindent messup
[linux-2.6.git] / drivers / edac / i5000_edac.c
1 /*
2  * Intel 5000(P/V/X) class Memory Controllers kernel module
3  *
4  * This file may be distributed under the terms of the
5  * GNU General Public License.
6  *
7  * Written by Douglas Thompson Linux Networx (http://lnxi.com)
8  *      norsk5@xmission.com
9  *
10  * This module is based on the following document:
11  *
12  * Intel 5000X Chipset Memory Controller Hub (MCH) - Datasheet
13  *      http://developer.intel.com/design/chipsets/datashts/313070.htm
14  *
15  */
16
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/pci.h>
20 #include <linux/pci_ids.h>
21 #include <linux/slab.h>
22 #include <linux/edac.h>
23 #include <asm/mmzone.h>
24
25 #include "edac_core.h"
26
27 /*
28  * Alter this version for the I5000 module when modifications are made
29  */
30 #define I5000_REVISION    " Ver: 2.0.12 " __DATE__
31 #define EDAC_MOD_STR      "i5000_edac"
32
33 #define i5000_printk(level, fmt, arg...) \
34         edac_printk(level, "i5000", fmt, ##arg)
35
36 #define i5000_mc_printk(mci, level, fmt, arg...) \
37         edac_mc_chipset_printk(mci, level, "i5000", fmt, ##arg)
38
39 #ifndef PCI_DEVICE_ID_INTEL_FBD_0
40 #define PCI_DEVICE_ID_INTEL_FBD_0       0x25F5
41 #endif
42 #ifndef PCI_DEVICE_ID_INTEL_FBD_1
43 #define PCI_DEVICE_ID_INTEL_FBD_1       0x25F6
44 #endif
45
46 /* Device 16,
47  * Function 0: System Address
48  * Function 1: Memory Branch Map, Control, Errors Register
49  * Function 2: FSB Error Registers
50  *
51  * All 3 functions of Device 16 (0,1,2) share the SAME DID
52  */
53 #define PCI_DEVICE_ID_INTEL_I5000_DEV16 0x25F0
54
55 /* OFFSETS for Function 0 */
56
57 /* OFFSETS for Function 1 */
58 #define         AMBASE                  0x48
59 #define         MAXCH                   0x56
60 #define         MAXDIMMPERCH            0x57
61 #define         TOLM                    0x6C
62 #define         REDMEMB                 0x7C
63 #define                 RED_ECC_LOCATOR(x)      ((x) & 0x3FFFF)
64 #define                 REC_ECC_LOCATOR_EVEN(x) ((x) & 0x001FF)
65 #define                 REC_ECC_LOCATOR_ODD(x)  ((x) & 0x3FE00)
66 #define         MIR0                    0x80
67 #define         MIR1                    0x84
68 #define         MIR2                    0x88
69 #define         AMIR0                   0x8C
70 #define         AMIR1                   0x90
71 #define         AMIR2                   0x94
72
73 #define         FERR_FAT_FBD            0x98
74 #define         NERR_FAT_FBD            0x9C
75 #define                 EXTRACT_FBDCHAN_INDX(x) (((x)>>28) & 0x3)
76 #define                 FERR_FAT_FBDCHAN 0x30000000
77 #define                 FERR_FAT_M3ERR  0x00000004
78 #define                 FERR_FAT_M2ERR  0x00000002
79 #define                 FERR_FAT_M1ERR  0x00000001
80 #define                 FERR_FAT_MASK   (FERR_FAT_M1ERR | \
81                                                 FERR_FAT_M2ERR | \
82                                                 FERR_FAT_M3ERR)
83
84 #define         FERR_NF_FBD             0xA0
85
86 /* Thermal and SPD or BFD errors */
87 #define                 FERR_NF_M28ERR  0x01000000
88 #define                 FERR_NF_M27ERR  0x00800000
89 #define                 FERR_NF_M26ERR  0x00400000
90 #define                 FERR_NF_M25ERR  0x00200000
91 #define                 FERR_NF_M24ERR  0x00100000
92 #define                 FERR_NF_M23ERR  0x00080000
93 #define                 FERR_NF_M22ERR  0x00040000
94 #define                 FERR_NF_M21ERR  0x00020000
95
96 /* Correctable errors */
97 #define                 FERR_NF_M20ERR  0x00010000
98 #define                 FERR_NF_M19ERR  0x00008000
99 #define                 FERR_NF_M18ERR  0x00004000
100 #define                 FERR_NF_M17ERR  0x00002000
101
102 /* Non-Retry or redundant Retry errors */
103 #define                 FERR_NF_M16ERR  0x00001000
104 #define                 FERR_NF_M15ERR  0x00000800
105 #define                 FERR_NF_M14ERR  0x00000400
106 #define                 FERR_NF_M13ERR  0x00000200
107
108 /* Uncorrectable errors */
109 #define                 FERR_NF_M12ERR  0x00000100
110 #define                 FERR_NF_M11ERR  0x00000080
111 #define                 FERR_NF_M10ERR  0x00000040
112 #define                 FERR_NF_M9ERR   0x00000020
113 #define                 FERR_NF_M8ERR   0x00000010
114 #define                 FERR_NF_M7ERR   0x00000008
115 #define                 FERR_NF_M6ERR   0x00000004
116 #define                 FERR_NF_M5ERR   0x00000002
117 #define                 FERR_NF_M4ERR   0x00000001
118
119 #define                 FERR_NF_UNCORRECTABLE   (FERR_NF_M12ERR | \
120                                                         FERR_NF_M11ERR | \
121                                                         FERR_NF_M10ERR | \
122                                                         FERR_NF_M8ERR | \
123                                                         FERR_NF_M7ERR | \
124                                                         FERR_NF_M6ERR | \
125                                                         FERR_NF_M5ERR | \
126                                                         FERR_NF_M4ERR)
127 #define                 FERR_NF_CORRECTABLE     (FERR_NF_M20ERR | \
128                                                         FERR_NF_M19ERR | \
129                                                         FERR_NF_M18ERR | \
130                                                         FERR_NF_M17ERR)
131 #define                 FERR_NF_DIMM_SPARE      (FERR_NF_M27ERR | \
132                                                         FERR_NF_M28ERR)
133 #define                 FERR_NF_THERMAL         (FERR_NF_M26ERR | \
134                                                         FERR_NF_M25ERR | \
135                                                         FERR_NF_M24ERR | \
136                                                         FERR_NF_M23ERR)
137 #define                 FERR_NF_SPD_PROTOCOL    (FERR_NF_M22ERR)
138 #define                 FERR_NF_NORTH_CRC       (FERR_NF_M21ERR)
139 #define                 FERR_NF_NON_RETRY       (FERR_NF_M13ERR | \
140                                                         FERR_NF_M14ERR | \
141                                                         FERR_NF_M15ERR)
142
143 #define         NERR_NF_FBD             0xA4
144 #define                 FERR_NF_MASK            (FERR_NF_UNCORRECTABLE | \
145                                                         FERR_NF_CORRECTABLE | \
146                                                         FERR_NF_DIMM_SPARE | \
147                                                         FERR_NF_THERMAL | \
148                                                         FERR_NF_SPD_PROTOCOL | \
149                                                         FERR_NF_NORTH_CRC | \
150                                                         FERR_NF_NON_RETRY)
151
152 #define         EMASK_FBD               0xA8
153 #define                 EMASK_FBD_M28ERR        0x08000000
154 #define                 EMASK_FBD_M27ERR        0x04000000
155 #define                 EMASK_FBD_M26ERR        0x02000000
156 #define                 EMASK_FBD_M25ERR        0x01000000
157 #define                 EMASK_FBD_M24ERR        0x00800000
158 #define                 EMASK_FBD_M23ERR        0x00400000
159 #define                 EMASK_FBD_M22ERR        0x00200000
160 #define                 EMASK_FBD_M21ERR        0x00100000
161 #define                 EMASK_FBD_M20ERR        0x00080000
162 #define                 EMASK_FBD_M19ERR        0x00040000
163 #define                 EMASK_FBD_M18ERR        0x00020000
164 #define                 EMASK_FBD_M17ERR        0x00010000
165
166 #define                 EMASK_FBD_M15ERR        0x00004000
167 #define                 EMASK_FBD_M14ERR        0x00002000
168 #define                 EMASK_FBD_M13ERR        0x00001000
169 #define                 EMASK_FBD_M12ERR        0x00000800
170 #define                 EMASK_FBD_M11ERR        0x00000400
171 #define                 EMASK_FBD_M10ERR        0x00000200
172 #define                 EMASK_FBD_M9ERR         0x00000100
173 #define                 EMASK_FBD_M8ERR         0x00000080
174 #define                 EMASK_FBD_M7ERR         0x00000040
175 #define                 EMASK_FBD_M6ERR         0x00000020
176 #define                 EMASK_FBD_M5ERR         0x00000010
177 #define                 EMASK_FBD_M4ERR         0x00000008
178 #define                 EMASK_FBD_M3ERR         0x00000004
179 #define                 EMASK_FBD_M2ERR         0x00000002
180 #define                 EMASK_FBD_M1ERR         0x00000001
181
182 #define                 ENABLE_EMASK_FBD_FATAL_ERRORS   (EMASK_FBD_M1ERR | \
183                                                         EMASK_FBD_M2ERR | \
184                                                         EMASK_FBD_M3ERR)
185
186 #define                 ENABLE_EMASK_FBD_UNCORRECTABLE  (EMASK_FBD_M4ERR | \
187                                                         EMASK_FBD_M5ERR | \
188                                                         EMASK_FBD_M6ERR | \
189                                                         EMASK_FBD_M7ERR | \
190                                                         EMASK_FBD_M8ERR | \
191                                                         EMASK_FBD_M9ERR | \
192                                                         EMASK_FBD_M10ERR | \
193                                                         EMASK_FBD_M11ERR | \
194                                                         EMASK_FBD_M12ERR)
195 #define                 ENABLE_EMASK_FBD_CORRECTABLE    (EMASK_FBD_M17ERR | \
196                                                         EMASK_FBD_M18ERR | \
197                                                         EMASK_FBD_M19ERR | \
198                                                         EMASK_FBD_M20ERR)
199 #define                 ENABLE_EMASK_FBD_DIMM_SPARE     (EMASK_FBD_M27ERR | \
200                                                         EMASK_FBD_M28ERR)
201 #define                 ENABLE_EMASK_FBD_THERMALS       (EMASK_FBD_M26ERR | \
202                                                         EMASK_FBD_M25ERR | \
203                                                         EMASK_FBD_M24ERR | \
204                                                         EMASK_FBD_M23ERR)
205 #define                 ENABLE_EMASK_FBD_SPD_PROTOCOL   (EMASK_FBD_M22ERR)
206 #define                 ENABLE_EMASK_FBD_NORTH_CRC      (EMASK_FBD_M21ERR)
207 #define                 ENABLE_EMASK_FBD_NON_RETRY      (EMASK_FBD_M15ERR | \
208                                                         EMASK_FBD_M14ERR | \
209                                                         EMASK_FBD_M13ERR)
210
211 #define         ENABLE_EMASK_ALL        (ENABLE_EMASK_FBD_NON_RETRY | \
212                                         ENABLE_EMASK_FBD_NORTH_CRC | \
213                                         ENABLE_EMASK_FBD_SPD_PROTOCOL | \
214                                         ENABLE_EMASK_FBD_THERMALS | \
215                                         ENABLE_EMASK_FBD_DIMM_SPARE | \
216                                         ENABLE_EMASK_FBD_FATAL_ERRORS | \
217                                         ENABLE_EMASK_FBD_CORRECTABLE | \
218                                         ENABLE_EMASK_FBD_UNCORRECTABLE)
219
220 #define         ERR0_FBD                0xAC
221 #define         ERR1_FBD                0xB0
222 #define         ERR2_FBD                0xB4
223 #define         MCERR_FBD               0xB8
224 #define         NRECMEMA                0xBE
225 #define                 NREC_BANK(x)            (((x)>>12) & 0x7)
226 #define                 NREC_RDWR(x)            (((x)>>11) & 1)
227 #define                 NREC_RANK(x)            (((x)>>8) & 0x7)
228 #define         NRECMEMB                0xC0
229 #define                 NREC_CAS(x)             (((x)>>16) & 0xFFFFFF)
230 #define                 NREC_RAS(x)             ((x) & 0x7FFF)
231 #define         NRECFGLOG               0xC4
232 #define         NREEECFBDA              0xC8
233 #define         NREEECFBDB              0xCC
234 #define         NREEECFBDC              0xD0
235 #define         NREEECFBDD              0xD4
236 #define         NREEECFBDE              0xD8
237 #define         REDMEMA                 0xDC
238 #define         RECMEMA                 0xE2
239 #define                 REC_BANK(x)             (((x)>>12) & 0x7)
240 #define                 REC_RDWR(x)             (((x)>>11) & 1)
241 #define                 REC_RANK(x)             (((x)>>8) & 0x7)
242 #define         RECMEMB                 0xE4
243 #define                 REC_CAS(x)              (((x)>>16) & 0xFFFFFF)
244 #define                 REC_RAS(x)              ((x) & 0x7FFF)
245 #define         RECFGLOG                0xE8
246 #define         RECFBDA                 0xEC
247 #define         RECFBDB                 0xF0
248 #define         RECFBDC                 0xF4
249 #define         RECFBDD                 0xF8
250 #define         RECFBDE                 0xFC
251
252 /* OFFSETS for Function 2 */
253
254 /*
255  * Device 21,
256  * Function 0: Memory Map Branch 0
257  *
258  * Device 22,
259  * Function 0: Memory Map Branch 1
260  */
261 #define PCI_DEVICE_ID_I5000_BRANCH_0    0x25F5
262 #define PCI_DEVICE_ID_I5000_BRANCH_1    0x25F6
263
264 #define AMB_PRESENT_0   0x64
265 #define AMB_PRESENT_1   0x66
266 #define MTR0            0x80
267 #define MTR1            0x84
268 #define MTR2            0x88
269 #define MTR3            0x8C
270
271 #define NUM_MTRS                4
272 #define CHANNELS_PER_BRANCH     (2)
273
274 /* Defines to extract the vaious fields from the
275  *      MTRx - Memory Technology Registers
276  */
277 #define MTR_DIMMS_PRESENT(mtr)          ((mtr) & (0x1 << 8))
278 #define MTR_DRAM_WIDTH(mtr)             ((((mtr) >> 6) & 0x1) ? 8 : 4)
279 #define MTR_DRAM_BANKS(mtr)             ((((mtr) >> 5) & 0x1) ? 8 : 4)
280 #define MTR_DRAM_BANKS_ADDR_BITS(mtr)   ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2)
281 #define MTR_DIMM_RANK(mtr)              (((mtr) >> 4) & 0x1)
282 #define MTR_DIMM_RANK_ADDR_BITS(mtr)    (MTR_DIM_RANKS(mtr) ? 2 : 1)
283 #define MTR_DIMM_ROWS(mtr)              (((mtr) >> 2) & 0x3)
284 #define MTR_DIMM_ROWS_ADDR_BITS(mtr)    (MTR_DIMM_ROWS(mtr) + 13)
285 #define MTR_DIMM_COLS(mtr)              ((mtr) & 0x3)
286 #define MTR_DIMM_COLS_ADDR_BITS(mtr)    (MTR_DIMM_COLS(mtr) + 10)
287
288 #ifdef CONFIG_EDAC_DEBUG
289 static char *numrow_toString[] = {
290         "8,192 - 13 rows",
291         "16,384 - 14 rows",
292         "32,768 - 15 rows",
293         "reserved"
294 };
295
296 static char *numcol_toString[] = {
297         "1,024 - 10 columns",
298         "2,048 - 11 columns",
299         "4,096 - 12 columns",
300         "reserved"
301 };
302 #endif
303
304 /* Enumeration of supported devices */
305 enum i5000_chips {
306         I5000P = 0,
307         I5000V = 1,             /* future */
308         I5000X = 2              /* future */
309 };
310
311 /* Device name and register DID (Device ID) */
312 struct i5000_dev_info {
313         const char *ctl_name;   /* name for this device */
314         u16 fsb_mapping_errors; /* DID for the branchmap,control */
315 };
316
317 /* Table of devices attributes supported by this driver */
318 static const struct i5000_dev_info i5000_devs[] = {
319         [I5000P] = {
320                 .ctl_name = "I5000",
321                 .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I5000_DEV16,
322         },
323 };
324
325 struct i5000_dimm_info {
326         int megabytes;          /* size, 0 means not present  */
327         int dual_rank;
328 };
329
330 #define MAX_CHANNELS    6       /* max possible channels */
331 #define MAX_CSROWS      (8*2)   /* max possible csrows per channel */
332
333 /* driver private data structure */
334 struct i5000_pvt {
335         struct pci_dev *system_address; /* 16.0 */
336         struct pci_dev *branchmap_werrors;      /* 16.1 */
337         struct pci_dev *fsb_error_regs; /* 16.2 */
338         struct pci_dev *branch_0;       /* 21.0 */
339         struct pci_dev *branch_1;       /* 22.0 */
340
341         int node_id;            /* ID of this node */
342
343         u16 tolm;               /* top of low memory */
344         u64 ambase;             /* AMB BAR */
345
346         u16 mir0, mir1, mir2;
347
348         u16 b0_mtr[NUM_MTRS];   /* Memory Technlogy Reg */
349         u16 b0_ambpresent0;     /* Branch 0, Channel 0 */
350         u16 b0_ambpresent1;     /* Brnach 0, Channel 1 */
351
352         u16 b1_mtr[NUM_MTRS];   /* Memory Technlogy Reg */
353         u16 b1_ambpresent0;     /* Branch 1, Channel 8 */
354         u16 b1_ambpresent1;     /* Branch 1, Channel 1 */
355
356         /* DIMM infomation matrix, allocating architecture maximums */
357         struct i5000_dimm_info dimm_info[MAX_CSROWS][MAX_CHANNELS];
358
359         /* Actual values for this controller */
360         int maxch;              /* Max channels */
361         int maxdimmperch;       /* Max DIMMs per channel */
362 };
363
364 /* I5000 MCH error information retrieved from Hardware */
365 struct i5000_error_info {
366
367         /* These registers are always read from the MC */
368         u32 ferr_fat_fbd;       /* First Errors Fatal */
369         u32 nerr_fat_fbd;       /* Next Errors Fatal */
370         u32 ferr_nf_fbd;        /* First Errors Non-Fatal */
371         u32 nerr_nf_fbd;        /* Next Errors Non-Fatal */
372
373         /* These registers are input ONLY if there was a Recoverable  Error */
374         u32 redmemb;            /* Recoverable Mem Data Error log B */
375         u16 recmema;            /* Recoverable Mem Error log A */
376         u32 recmemb;            /* Recoverable Mem Error log B */
377
378         /* These registers are input ONLY if there was a
379          * Non-Recoverable Error */
380         u16 nrecmema;           /* Non-Recoverable Mem log A */
381         u16 nrecmemb;           /* Non-Recoverable Mem log B */
382
383 };
384
385 static struct edac_pci_ctl_info *i5000_pci;
386
387 /******************************************************************************
388  *      i5000_get_error_info    Retrieve the hardware error information from
389  *                              the hardware and cache it in the 'info'
390  *                              structure
391  */
392 static void i5000_get_error_info(struct mem_ctl_info *mci,
393                                  struct i5000_error_info * info)
394 {
395         struct i5000_pvt *pvt;
396         u32 value;
397
398         pvt = (struct i5000_pvt *)mci->pvt_info;
399
400         /* read in the 1st FATAL error register */
401         pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value);
402
403         /* Mask only the bits that the doc says are valid
404          */
405         value &= (FERR_FAT_FBDCHAN | FERR_FAT_MASK);
406
407         /* If there is an error, then read in the */
408         /* NEXT FATAL error register and the Memory Error Log Register A */
409         if (value & FERR_FAT_MASK) {
410                 info->ferr_fat_fbd = value;
411
412                 /* harvest the various error data we need */
413                 pci_read_config_dword(pvt->branchmap_werrors,
414                                 NERR_FAT_FBD, &info->nerr_fat_fbd);
415                 pci_read_config_word(pvt->branchmap_werrors,
416                                 NRECMEMA, &info->nrecmema);
417                 pci_read_config_word(pvt->branchmap_werrors,
418                                 NRECMEMB, &info->nrecmemb);
419
420                 /* Clear the error bits, by writing them back */
421                 pci_write_config_dword(pvt->branchmap_werrors,
422                                 FERR_FAT_FBD, value);
423         } else {
424                 info->ferr_fat_fbd = 0;
425                 info->nerr_fat_fbd = 0;
426                 info->nrecmema = 0;
427                 info->nrecmemb = 0;
428         }
429
430         /* read in the 1st NON-FATAL error register */
431         pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value);
432
433         /* If there is an error, then read in the 1st NON-FATAL error
434          * register as well */
435         if (value & FERR_NF_MASK) {
436                 info->ferr_nf_fbd = value;
437
438                 /* harvest the various error data we need */
439                 pci_read_config_dword(pvt->branchmap_werrors,
440                                 NERR_NF_FBD, &info->nerr_nf_fbd);
441                 pci_read_config_word(pvt->branchmap_werrors,
442                                 RECMEMA, &info->recmema);
443                 pci_read_config_dword(pvt->branchmap_werrors,
444                                 RECMEMB, &info->recmemb);
445                 pci_read_config_dword(pvt->branchmap_werrors,
446                                 REDMEMB, &info->redmemb);
447
448                 /* Clear the error bits, by writing them back */
449                 pci_write_config_dword(pvt->branchmap_werrors,
450                                 FERR_NF_FBD, value);
451         } else {
452                 info->ferr_nf_fbd = 0;
453                 info->nerr_nf_fbd = 0;
454                 info->recmema = 0;
455                 info->recmemb = 0;
456                 info->redmemb = 0;
457         }
458 }
459
460 /******************************************************************************
461  * i5000_process_fatal_error_info(struct mem_ctl_info *mci,
462  *                                      struct i5000_error_info *info,
463  *                                      int handle_errors);
464  *
465  *      handle the Intel FATAL errors, if any
466  */
467 static void i5000_process_fatal_error_info(struct mem_ctl_info *mci,
468                                         struct i5000_error_info * info,
469                                         int handle_errors)
470 {
471         char msg[EDAC_MC_LABEL_LEN + 1 + 90];
472         u32 allErrors;
473         int branch;
474         int channel;
475         int bank;
476         int rank;
477         int rdwr;
478         int ras, cas;
479
480         /* mask off the Error bits that are possible */
481         allErrors = (info->ferr_fat_fbd & FERR_FAT_MASK);
482         if (!allErrors)
483                 return;         /* if no error, return now */
484
485         /* ONLY ONE of the possible error bits will be set, as per the docs */
486         i5000_mc_printk(mci, KERN_ERR,
487                         "FATAL ERRORS Found!!! 1st FATAL Err Reg= 0x%x\n",
488                         allErrors);
489
490         branch = EXTRACT_FBDCHAN_INDX(info->ferr_fat_fbd);
491         channel = branch;
492
493         /* Use the NON-Recoverable macros to extract data */
494         bank = NREC_BANK(info->nrecmema);
495         rank = NREC_RANK(info->nrecmema);
496         rdwr = NREC_RDWR(info->nrecmema);
497         ras = NREC_RAS(info->nrecmemb);
498         cas = NREC_CAS(info->nrecmemb);
499
500         debugf0("\t\tCSROW= %d  Channels= %d,%d  (Branch= %d "
501                 "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
502                 rank, channel, channel + 1, branch >> 1, bank,
503                 rdwr ? "Write" : "Read", ras, cas);
504
505         /* Only 1 bit will be on */
506         if (allErrors & FERR_FAT_M1ERR) {
507                 i5000_mc_printk(mci, KERN_ERR,
508                                 "Alert on non-redundant retry or fast "
509                                 "reset timeout\n");
510
511         } else if (allErrors & FERR_FAT_M2ERR) {
512                 i5000_mc_printk(mci, KERN_ERR,
513                                 "Northbound CRC error on non-redundant "
514                                 "retry\n");
515
516         } else if (allErrors & FERR_FAT_M3ERR) {
517                 i5000_mc_printk(mci, KERN_ERR,
518                                 ">Tmid Thermal event with intelligent "
519                                 "throttling disabled\n");
520         }
521
522         /* Form out message */
523         snprintf(msg, sizeof(msg),
524                  "(Branch=%d DRAM-Bank=%d RDWR=%s RAS=%d CAS=%d "
525                  "FATAL Err=0x%x)",
526                  branch >> 1, bank, rdwr ? "Write" : "Read", ras, cas,
527                  allErrors);
528
529         /* Call the helper to output message */
530         edac_mc_handle_fbd_ue(mci, rank, channel, channel + 1, msg);
531 }
532
533 /******************************************************************************
534  * i5000_process_fatal_error_info(struct mem_ctl_info *mci,
535  *                              struct i5000_error_info *info,
536  *                              int handle_errors);
537  *
538  *      handle the Intel NON-FATAL errors, if any
539  */
540 static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci,
541                                         struct i5000_error_info * info,
542                                         int handle_errors)
543 {
544         char msg[EDAC_MC_LABEL_LEN + 1 + 90];
545         u32 allErrors;
546         u32 ue_errors;
547         u32 ce_errors;
548         u32 misc_errors;
549         int branch;
550         int channel;
551         int bank;
552         int rank;
553         int rdwr;
554         int ras, cas;
555
556         /* mask off the Error bits that are possible */
557         allErrors = (info->ferr_nf_fbd & FERR_NF_MASK);
558         if (!allErrors)
559                 return;         /* if no error, return now */
560
561         /* ONLY ONE of the possible error bits will be set, as per the docs */
562         i5000_mc_printk(mci, KERN_WARNING,
563                         "NON-FATAL ERRORS Found!!! 1st NON-FATAL Err "
564                         "Reg= 0x%x\n", allErrors);
565
566         ue_errors = allErrors & FERR_NF_UNCORRECTABLE;
567         if (ue_errors) {
568                 debugf0("\tUncorrected bits= 0x%x\n", ue_errors);
569
570                 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
571                 channel = branch;
572                 bank = NREC_BANK(info->nrecmema);
573                 rank = NREC_RANK(info->nrecmema);
574                 rdwr = NREC_RDWR(info->nrecmema);
575                 ras = NREC_RAS(info->nrecmemb);
576                 cas = NREC_CAS(info->nrecmemb);
577
578                 debugf0
579                         ("\t\tCSROW= %d  Channels= %d,%d  (Branch= %d "
580                         "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
581                         rank, channel, channel + 1, branch >> 1, bank,
582                         rdwr ? "Write" : "Read", ras, cas);
583
584                 /* Form out message */
585                 snprintf(msg, sizeof(msg),
586                          "(Branch=%d DRAM-Bank=%d RDWR=%s RAS=%d "
587                          "CAS=%d, UE Err=0x%x)",
588                          branch >> 1, bank, rdwr ? "Write" : "Read", ras, cas,
589                          ue_errors);
590
591                 /* Call the helper to output message */
592                 edac_mc_handle_fbd_ue(mci, rank, channel, channel + 1, msg);
593         }
594
595         /* Check correctable errors */
596         ce_errors = allErrors & FERR_NF_CORRECTABLE;
597         if (ce_errors) {
598                 debugf0("\tCorrected bits= 0x%x\n", ce_errors);
599
600                 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
601
602                 channel = 0;
603                 if (REC_ECC_LOCATOR_ODD(info->redmemb))
604                         channel = 1;
605
606                 /* Convert channel to be based from zero, instead of
607                  * from branch base of 0 */
608                 channel += branch;
609
610                 bank = REC_BANK(info->recmema);
611                 rank = REC_RANK(info->recmema);
612                 rdwr = REC_RDWR(info->recmema);
613                 ras = REC_RAS(info->recmemb);
614                 cas = REC_CAS(info->recmemb);
615
616                 debugf0("\t\tCSROW= %d Channel= %d  (Branch %d "
617                         "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
618                         rank, channel, branch >> 1, bank,
619                         rdwr ? "Write" : "Read", ras, cas);
620
621                 /* Form out message */
622                 snprintf(msg, sizeof(msg),
623                          "(Branch=%d DRAM-Bank=%d RDWR=%s RAS=%d "
624                          "CAS=%d, CE Err=0x%x)", branch >> 1, bank,
625                          rdwr ? "Write" : "Read", ras, cas, ce_errors);
626
627                 /* Call the helper to output message */
628                 edac_mc_handle_fbd_ce(mci, rank, channel, msg);
629         }
630
631         /* See if any of the thermal errors have fired */
632         misc_errors = allErrors & FERR_NF_THERMAL;
633         if (misc_errors) {
634                 i5000_printk(KERN_WARNING, "\tTHERMAL Error, bits= 0x%x\n",
635                         misc_errors);
636         }
637
638         /* See if any of the thermal errors have fired */
639         misc_errors = allErrors & FERR_NF_NON_RETRY;
640         if (misc_errors) {
641                 i5000_printk(KERN_WARNING, "\tNON-Retry  Errors, bits= 0x%x\n",
642                         misc_errors);
643         }
644
645         /* See if any of the thermal errors have fired */
646         misc_errors = allErrors & FERR_NF_NORTH_CRC;
647         if (misc_errors) {
648                 i5000_printk(KERN_WARNING,
649                         "\tNORTHBOUND CRC  Error, bits= 0x%x\n",
650                         misc_errors);
651         }
652
653         /* See if any of the thermal errors have fired */
654         misc_errors = allErrors & FERR_NF_SPD_PROTOCOL;
655         if (misc_errors) {
656                 i5000_printk(KERN_WARNING,
657                         "\tSPD Protocol  Error, bits= 0x%x\n",
658                         misc_errors);
659         }
660
661         /* See if any of the thermal errors have fired */
662         misc_errors = allErrors & FERR_NF_DIMM_SPARE;
663         if (misc_errors) {
664                 i5000_printk(KERN_WARNING, "\tDIMM-Spare  Error, bits= 0x%x\n",
665                         misc_errors);
666         }
667 }
668
669 /******************************************************************************
670  *      i5000_process_error_info        Process the error info that is
671  *      in the 'info' structure, previously retrieved from hardware
672  */
673 static void i5000_process_error_info(struct mem_ctl_info *mci,
674                                 struct i5000_error_info * info,
675                                 int handle_errors)
676 {
677         /* First handle any fatal errors that occurred */
678         i5000_process_fatal_error_info(mci, info, handle_errors);
679
680         /* now handle any non-fatal errors that occurred */
681         i5000_process_nonfatal_error_info(mci, info, handle_errors);
682 }
683
684 /******************************************************************************
685  *      i5000_clear_error       Retrieve any error from the hardware
686  *                              but do NOT process that error.
687  *                              Used for 'clearing' out of previous errors
688  *                              Called by the Core module.
689  */
690 static void i5000_clear_error(struct mem_ctl_info *mci)
691 {
692         struct i5000_error_info info;
693
694         i5000_get_error_info(mci, &info);
695 }
696
697 /******************************************************************************
698  *      i5000_check_error       Retrieve and process errors reported by the
699  *                              hardware. Called by the Core module.
700  */
701 static void i5000_check_error(struct mem_ctl_info *mci)
702 {
703         struct i5000_error_info info;
704         debugf4("MC%d: " __FILE__ ": %s()\n", mci->mc_idx, __func__);
705         i5000_get_error_info(mci, &info);
706         i5000_process_error_info(mci, &info, 1);
707 }
708
709 /******************************************************************************
710  *      i5000_get_devices       Find and perform 'get' operation on the MCH's
711  *                      device/functions we want to reference for this driver
712  *
713  *                      Need to 'get' device 16 func 1 and func 2
714  */
715 static int i5000_get_devices(struct mem_ctl_info *mci, int dev_idx)
716 {
717         //const struct i5000_dev_info *i5000_dev = &i5000_devs[dev_idx];
718         struct i5000_pvt *pvt;
719         struct pci_dev *pdev;
720
721         pvt = (struct i5000_pvt *)mci->pvt_info;
722
723         /* Attempt to 'get' the MCH register we want */
724         pdev = NULL;
725         while (1) {
726                 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
727                                 PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev);
728
729                 /* End of list, leave */
730                 if (pdev == NULL) {
731                         i5000_printk(KERN_ERR,
732                                 "'system address,Process Bus' "
733                                 "device not found:"
734                                 "vendor 0x%x device 0x%x FUNC 1 "
735                                 "(broken BIOS?)\n",
736                                 PCI_VENDOR_ID_INTEL,
737                                 PCI_DEVICE_ID_INTEL_I5000_DEV16);
738
739                         return 1;
740                 }
741
742                 /* Scan for device 16 func 1 */
743                 if (PCI_FUNC(pdev->devfn) == 1)
744                         break;
745         }
746
747         pvt->branchmap_werrors = pdev;
748
749         /* Attempt to 'get' the MCH register we want */
750         pdev = NULL;
751         while (1) {
752                 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
753                                 PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev);
754
755                 if (pdev == NULL) {
756                         i5000_printk(KERN_ERR,
757                                 "MC: 'branchmap,control,errors' "
758                                 "device not found:"
759                                 "vendor 0x%x device 0x%x Func 2 "
760                                 "(broken BIOS?)\n",
761                                 PCI_VENDOR_ID_INTEL,
762                                 PCI_DEVICE_ID_INTEL_I5000_DEV16);
763
764                         pci_dev_put(pvt->branchmap_werrors);
765                         return 1;
766                 }
767
768                 /* Scan for device 16 func 1 */
769                 if (PCI_FUNC(pdev->devfn) == 2)
770                         break;
771         }
772
773         pvt->fsb_error_regs = pdev;
774
775         debugf1("System Address, processor bus- PCI Bus ID: %s  %x:%x\n",
776                 pci_name(pvt->system_address),
777                 pvt->system_address->vendor, pvt->system_address->device);
778         debugf1("Branchmap, control and errors - PCI Bus ID: %s  %x:%x\n",
779                 pci_name(pvt->branchmap_werrors),
780                 pvt->branchmap_werrors->vendor, pvt->branchmap_werrors->device);
781         debugf1("FSB Error Regs - PCI Bus ID: %s  %x:%x\n",
782                 pci_name(pvt->fsb_error_regs),
783                 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
784
785         pdev = NULL;
786         pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
787                         PCI_DEVICE_ID_I5000_BRANCH_0, pdev);
788
789         if (pdev == NULL) {
790                 i5000_printk(KERN_ERR,
791                         "MC: 'BRANCH 0' device not found:"
792                         "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
793                         PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_I5000_BRANCH_0);
794
795                 pci_dev_put(pvt->branchmap_werrors);
796                 pci_dev_put(pvt->fsb_error_regs);
797                 return 1;
798         }
799
800         pvt->branch_0 = pdev;
801
802         /* If this device claims to have more than 2 channels then
803          * fetch Branch 1's information
804          */
805         if (pvt->maxch >= CHANNELS_PER_BRANCH) {
806                 pdev = NULL;
807                 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
808                                 PCI_DEVICE_ID_I5000_BRANCH_1, pdev);
809
810                 if (pdev == NULL) {
811                         i5000_printk(KERN_ERR,
812                                 "MC: 'BRANCH 1' device not found:"
813                                 "vendor 0x%x device 0x%x Func 0 "
814                                 "(broken BIOS?)\n",
815                                 PCI_VENDOR_ID_INTEL,
816                                 PCI_DEVICE_ID_I5000_BRANCH_1);
817
818                         pci_dev_put(pvt->branchmap_werrors);
819                         pci_dev_put(pvt->fsb_error_regs);
820                         pci_dev_put(pvt->branch_0);
821                         return 1;
822                 }
823
824                 pvt->branch_1 = pdev;
825         }
826
827         return 0;
828 }
829
830 /******************************************************************************
831  *      i5000_put_devices       'put' all the devices that we have
832  *                              reserved via 'get'
833  */
834 static void i5000_put_devices(struct mem_ctl_info *mci)
835 {
836         struct i5000_pvt *pvt;
837
838         pvt = (struct i5000_pvt *)mci->pvt_info;
839
840         pci_dev_put(pvt->branchmap_werrors);    /* FUNC 1 */
841         pci_dev_put(pvt->fsb_error_regs);       /* FUNC 2 */
842         pci_dev_put(pvt->branch_0);     /* DEV 21 */
843
844         /* Only if more than 2 channels do we release the second branch */
845         if (pvt->maxch >= CHANNELS_PER_BRANCH) {
846                 pci_dev_put(pvt->branch_1);     /* DEV 22 */
847         }
848 }
849
850 /******************************************************************************
851  *      determine_amb_resent
852  *
853  *              the information is contained in NUM_MTRS different registers
854  *              determineing which of the NUM_MTRS requires knowing
855  *              which channel is in question
856  *
857  *      2 branches, each with 2 channels
858  *              b0_ambpresent0 for channel '0'
859  *              b0_ambpresent1 for channel '1'
860  *              b1_ambpresent0 for channel '2'
861  *              b1_ambpresent1 for channel '3'
862  */
863 static int determine_amb_present_reg(struct i5000_pvt *pvt, int channel)
864 {
865         int amb_present;
866
867         if (channel < CHANNELS_PER_BRANCH) {
868                 if (channel & 0x1)
869                         amb_present = pvt->b0_ambpresent1;
870                 else
871                         amb_present = pvt->b0_ambpresent0;
872         } else {
873                 if (channel & 0x1)
874                         amb_present = pvt->b1_ambpresent1;
875                 else
876                         amb_present = pvt->b1_ambpresent0;
877         }
878
879         return amb_present;
880 }
881
882 /******************************************************************************
883  * determine_mtr(pvt, csrow, channel)
884  *
885  *      return the proper MTR register as determine by the csrow and channel desired
886  */
887 static int determine_mtr(struct i5000_pvt *pvt, int csrow, int channel)
888 {
889         int mtr;
890
891         if (channel < CHANNELS_PER_BRANCH)
892                 mtr = pvt->b0_mtr[csrow >> 1];
893         else
894                 mtr = pvt->b1_mtr[csrow >> 1];
895
896         return mtr;
897 }
898
899 /******************************************************************************
900  */
901 static void decode_mtr(int slot_row, u16 mtr)
902 {
903         int ans;
904
905         ans = MTR_DIMMS_PRESENT(mtr);
906
907         debugf2("\tMTR%d=0x%x:  DIMMs are %s\n", slot_row, mtr,
908                 ans ? "Present" : "NOT Present");
909         if (!ans)
910                 return;
911
912         debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
913         debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
914         debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANK(mtr) ? "double" : "single");
915         debugf2("\t\tNUMROW: %s\n", numrow_toString[MTR_DIMM_ROWS(mtr)]);
916         debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]);
917 }
918
919 static void handle_channel(struct i5000_pvt *pvt, int csrow, int channel,
920                         struct i5000_dimm_info *dinfo)
921 {
922         int mtr;
923         int amb_present_reg;
924         int addrBits;
925
926         mtr = determine_mtr(pvt, csrow, channel);
927         if (MTR_DIMMS_PRESENT(mtr)) {
928                 amb_present_reg = determine_amb_present_reg(pvt, channel);
929
930                 /* Determine if there is  a  DIMM present in this DIMM slot */
931                 if (amb_present_reg & (1 << (csrow >> 1))) {
932                         dinfo->dual_rank = MTR_DIMM_RANK(mtr);
933
934                         if (!((dinfo->dual_rank == 0) &&
935                                 ((csrow & 0x1) == 0x1))) {
936                                 /* Start with the number of bits for a Bank
937                                  * on the DRAM */
938                                 addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr);
939                                 /* Add thenumber of ROW bits */
940                                 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
941                                 /* add the number of COLUMN bits */
942                                 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
943
944                                 addrBits += 6;  /* add 64 bits per DIMM */
945                                 addrBits -= 20; /* divide by 2^^20 */
946                                 addrBits -= 3;  /* 8 bits per bytes */
947
948                                 dinfo->megabytes = 1 << addrBits;
949                         }
950                 }
951         }
952 }
953
954 /******************************************************************************
955  *      calculate_dimm_size
956  *
957  *      also will output a DIMM matrix map, if debug is enabled, for viewing
958  *      how the DIMMs are populated
959  */
960 static void calculate_dimm_size(struct i5000_pvt *pvt)
961 {
962         struct i5000_dimm_info *dinfo;
963         int csrow, max_csrows;
964         char *p, *mem_buffer;
965         int space, n;
966         int channel;
967
968         /* ================= Generate some debug output ================= */
969         space = PAGE_SIZE;
970         mem_buffer = p = kmalloc(space, GFP_KERNEL);
971         if (p == NULL) {
972                 i5000_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n",
973                         __FILE__, __func__);
974                 return;
975         }
976
977         n = snprintf(p, space, "\n");
978         p += n;
979         space -= n;
980
981         /* Scan all the actual CSROWS (which is # of DIMMS * 2)
982          * and calculate the information for each DIMM
983          * Start with the highest csrow first, to display it first
984          * and work toward the 0th csrow
985          */
986         max_csrows = pvt->maxdimmperch * 2;
987         for (csrow = max_csrows - 1; csrow >= 0; csrow--) {
988
989                 /* on an odd csrow, first output a 'boundary' marker,
990                  * then reset the message buffer  */
991                 if (csrow & 0x1) {
992                         n = snprintf(p, space, "---------------------------"
993                                 "--------------------------------");
994                         p += n;
995                         space -= n;
996                         debugf2("%s\n", mem_buffer);
997                         p = mem_buffer;
998                         space = PAGE_SIZE;
999                 }
1000                 n = snprintf(p, space, "csrow %2d    ", csrow);
1001                 p += n;
1002                 space -= n;
1003
1004                 for (channel = 0; channel < pvt->maxch; channel++) {
1005                         dinfo = &pvt->dimm_info[csrow][channel];
1006                         handle_channel(pvt, csrow, channel, dinfo);
1007                         n = snprintf(p, space, "%4d MB   | ", dinfo->megabytes);
1008                         p += n;
1009                         space -= n;
1010                 }
1011                 n = snprintf(p, space, "\n");
1012                 p += n;
1013                 space -= n;
1014         }
1015
1016         /* Output the last bottom 'boundary' marker */
1017         n = snprintf(p, space, "---------------------------"
1018                 "--------------------------------\n");
1019         p += n;
1020         space -= n;
1021
1022         /* now output the 'channel' labels */
1023         n = snprintf(p, space, "            ");
1024         p += n;
1025         space -= n;
1026         for (channel = 0; channel < pvt->maxch; channel++) {
1027                 n = snprintf(p, space, "channel %d | ", channel);
1028                 p += n;
1029                 space -= n;
1030         }
1031         n = snprintf(p, space, "\n");
1032         p += n;
1033         space -= n;
1034
1035         /* output the last message and free buffer */
1036         debugf2("%s\n", mem_buffer);
1037         kfree(mem_buffer);
1038 }
1039
1040 /******************************************************************************
1041  *      i5000_get_mc_regs       read in the necessary registers and
1042  *                              cache locally
1043  *
1044  *                      Fills in the private data members
1045  */
1046 static void i5000_get_mc_regs(struct mem_ctl_info *mci)
1047 {
1048         struct i5000_pvt *pvt;
1049         u32 actual_tolm;
1050         u16 limit;
1051         int slot_row;
1052         int maxch;
1053         int maxdimmperch;
1054         int way0, way1;
1055
1056         pvt = (struct i5000_pvt *)mci->pvt_info;
1057
1058         pci_read_config_dword(pvt->system_address, AMBASE,
1059                         (u32 *) & pvt->ambase);
1060         pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32),
1061                         ((u32 *) & pvt->ambase) + sizeof(u32));
1062
1063         maxdimmperch = pvt->maxdimmperch;
1064         maxch = pvt->maxch;
1065
1066         debugf2("AMBASE= 0x%lx  MAXCH= %d  MAX-DIMM-Per-CH= %d\n",
1067                 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);
1068
1069         /* Get the Branch Map regs */
1070         pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);
1071         pvt->tolm >>= 12;
1072         debugf2("\nTOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm,
1073                 pvt->tolm);
1074
1075         actual_tolm = pvt->tolm << 28;
1076         debugf2("Actual TOLM byte addr=%u (0x%x)\n", actual_tolm, actual_tolm);
1077
1078         pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0);
1079         pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1);
1080         pci_read_config_word(pvt->branchmap_werrors, MIR2, &pvt->mir2);
1081
1082         /* Get the MIR[0-2] regs */
1083         limit = (pvt->mir0 >> 4) & 0x0FFF;
1084         way0 = pvt->mir0 & 0x1;
1085         way1 = pvt->mir0 & 0x2;
1086         debugf2("MIR0: limit= 0x%x  WAY1= %u  WAY0= %x\n", limit, way1, way0);
1087         limit = (pvt->mir1 >> 4) & 0x0FFF;
1088         way0 = pvt->mir1 & 0x1;
1089         way1 = pvt->mir1 & 0x2;
1090         debugf2("MIR1: limit= 0x%x  WAY1= %u  WAY0= %x\n", limit, way1, way0);
1091         limit = (pvt->mir2 >> 4) & 0x0FFF;
1092         way0 = pvt->mir2 & 0x1;
1093         way1 = pvt->mir2 & 0x2;
1094         debugf2("MIR2: limit= 0x%x  WAY1= %u  WAY0= %x\n", limit, way1, way0);
1095
1096         /* Get the MTR[0-3] regs */
1097         for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1098                 int where = MTR0 + (slot_row * sizeof(u32));
1099
1100                 pci_read_config_word(pvt->branch_0, where,
1101                                 &pvt->b0_mtr[slot_row]);
1102
1103                 debugf2("MTR%d where=0x%x B0 value=0x%x\n", slot_row, where,
1104                         pvt->b0_mtr[slot_row]);
1105
1106                 if (pvt->maxch >= CHANNELS_PER_BRANCH) {
1107                         pci_read_config_word(pvt->branch_1, where,
1108                                         &pvt->b1_mtr[slot_row]);
1109                         debugf2("MTR%d where=0x%x B1 value=0x%x\n", slot_row,
1110                                 where, pvt->b0_mtr[slot_row]);
1111                 } else {
1112                         pvt->b1_mtr[slot_row] = 0;
1113                 }
1114         }
1115
1116         /* Read and dump branch 0's MTRs */
1117         debugf2("\nMemory Technology Registers:\n");
1118         debugf2("   Branch 0:\n");
1119         for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1120                 decode_mtr(slot_row, pvt->b0_mtr[slot_row]);
1121         }
1122         pci_read_config_word(pvt->branch_0, AMB_PRESENT_0,
1123                         &pvt->b0_ambpresent0);
1124         debugf2("\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);
1125         pci_read_config_word(pvt->branch_0, AMB_PRESENT_1,
1126                         &pvt->b0_ambpresent1);
1127         debugf2("\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
1128
1129         /* Only if we have 2 branchs (4 channels) */
1130         if (pvt->maxch < CHANNELS_PER_BRANCH) {
1131                 pvt->b1_ambpresent0 = 0;
1132                 pvt->b1_ambpresent1 = 0;
1133         } else {
1134                 /* Read and dump  branch 1's MTRs */
1135                 debugf2("   Branch 1:\n");
1136                 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1137                         decode_mtr(slot_row, pvt->b1_mtr[slot_row]);
1138                 }
1139                 pci_read_config_word(pvt->branch_1, AMB_PRESENT_0,
1140                                 &pvt->b1_ambpresent0);
1141                 debugf2("\t\tAMB-Branch 1-present0 0x%x:\n",
1142                         pvt->b1_ambpresent0);
1143                 pci_read_config_word(pvt->branch_1, AMB_PRESENT_1,
1144                                 &pvt->b1_ambpresent1);
1145                 debugf2("\t\tAMB-Branch 1-present1 0x%x:\n",
1146                         pvt->b1_ambpresent1);
1147         }
1148
1149         /* Go and determine the size of each DIMM and place in an
1150          * orderly matrix */
1151         calculate_dimm_size(pvt);
1152 }
1153
1154 /******************************************************************************
1155  *      i5000_init_csrows       Initialize the 'csrows' table within
1156  *                              the mci control structure with the
1157  *                              addressing of memory.
1158  *
1159  *      return:
1160  *              0       success
1161  *              1       no actual memory found on this MC
1162  */
1163 static int i5000_init_csrows(struct mem_ctl_info *mci)
1164 {
1165         struct i5000_pvt *pvt;
1166         struct csrow_info *p_csrow;
1167         int empty, channel_count;
1168         int max_csrows;
1169         int mtr;
1170         int csrow_megs;
1171         int channel;
1172         int csrow;
1173
1174         pvt = (struct i5000_pvt *)mci->pvt_info;
1175
1176         channel_count = pvt->maxch;
1177         max_csrows = pvt->maxdimmperch * 2;
1178
1179         empty = 1;              /* Assume NO memory */
1180
1181         for (csrow = 0; csrow < max_csrows; csrow++) {
1182                 p_csrow = &mci->csrows[csrow];
1183
1184                 p_csrow->csrow_idx = csrow;
1185
1186                 /* use branch 0 for the basis */
1187                 mtr = pvt->b0_mtr[csrow >> 1];
1188
1189                 /* if no DIMMS on this row, continue */
1190                 if (!MTR_DIMMS_PRESENT(mtr))
1191                         continue;
1192
1193                 /* FAKE OUT VALUES, FIXME */
1194                 p_csrow->first_page = 0 + csrow * 20;
1195                 p_csrow->last_page = 9 + csrow * 20;
1196                 p_csrow->page_mask = 0xFFF;
1197
1198                 p_csrow->grain = 8;
1199
1200                 csrow_megs = 0;
1201                 for (channel = 0; channel < pvt->maxch; channel++) {
1202                         csrow_megs += pvt->dimm_info[csrow][channel].megabytes;
1203                 }
1204
1205                 p_csrow->nr_pages = csrow_megs << 8;
1206
1207                 /* Assume DDR2 for now */
1208                 p_csrow->mtype = MEM_FB_DDR2;
1209
1210                 /* ask what device type on this row */
1211                 if (MTR_DRAM_WIDTH(mtr))
1212                         p_csrow->dtype = DEV_X8;
1213                 else
1214                         p_csrow->dtype = DEV_X4;
1215
1216                 p_csrow->edac_mode = EDAC_S8ECD8ED;
1217
1218                 empty = 0;
1219         }
1220
1221         return empty;
1222 }
1223
1224 /******************************************************************************
1225  *      i5000_enable_error_reporting
1226  *                      Turn on the memory reporting features of the hardware
1227  */
1228 static void i5000_enable_error_reporting(struct mem_ctl_info *mci)
1229 {
1230         struct i5000_pvt *pvt;
1231         u32 fbd_error_mask;
1232
1233         pvt = (struct i5000_pvt *)mci->pvt_info;
1234
1235         /* Read the FBD Error Mask Register */
1236         pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD,
1237                         &fbd_error_mask);
1238
1239         /* Enable with a '0' */
1240         fbd_error_mask &= ~(ENABLE_EMASK_ALL);
1241
1242         pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD,
1243                         fbd_error_mask);
1244 }
1245
1246 /******************************************************************************
1247  * i5000_get_dimm_and_channel_counts(pdev, &num_csrows, &num_channels)
1248  *
1249  *      ask the device how many channels are present and how many CSROWS
1250  *       as well
1251  */
1252 static void i5000_get_dimm_and_channel_counts(struct pci_dev *pdev,
1253                                         int *num_dimms_per_channel,
1254                                         int *num_channels)
1255 {
1256         u8 value;
1257
1258         /* Need to retrieve just how many channels and dimms per channel are
1259          * supported on this memory controller
1260          */
1261         pci_read_config_byte(pdev, MAXDIMMPERCH, &value);
1262         *num_dimms_per_channel = (int)value *2;
1263
1264         pci_read_config_byte(pdev, MAXCH, &value);
1265         *num_channels = (int)value;
1266 }
1267
1268 /******************************************************************************
1269  *      i5000_probe1    Probe for ONE instance of device to see if it is
1270  *                      present.
1271  *      return:
1272  *              0 for FOUND a device
1273  *              < 0 for error code
1274  */
1275 static int i5000_probe1(struct pci_dev *pdev, int dev_idx)
1276 {
1277         struct mem_ctl_info *mci;
1278         struct i5000_pvt *pvt;
1279         int num_channels;
1280         int num_dimms_per_channel;
1281         int num_csrows;
1282
1283         debugf0("MC: " __FILE__ ": %s(), pdev bus %u dev=0x%x fn=0x%x\n",
1284                 __func__,
1285                 pdev->bus->number,
1286                 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1287
1288         /* We only are looking for func 0 of the set */
1289         if (PCI_FUNC(pdev->devfn) != 0)
1290                 return -ENODEV;
1291
1292         /* make sure error reporting method is sane */
1293         switch (edac_op_state) {
1294         case EDAC_OPSTATE_POLL:
1295         case EDAC_OPSTATE_NMI:
1296                 break;
1297         default:
1298                 edac_op_state = EDAC_OPSTATE_POLL;
1299                 break;
1300         }
1301
1302         /* Ask the devices for the number of CSROWS and CHANNELS so
1303          * that we can calculate the memory resources, etc
1304          *
1305          * The Chipset will report what it can handle which will be greater
1306          * or equal to what the motherboard manufacturer will implement.
1307          *
1308          * As we don't have a motherboard identification routine to determine
1309          * actual number of slots/dimms per channel, we thus utilize the
1310          * resource as specified by the chipset. Thus, we might have
1311          * have more DIMMs per channel than actually on the mobo, but this
1312          * allows the driver to support upto the chipset max, without
1313          * some fancy mobo determination.
1314          */
1315         i5000_get_dimm_and_channel_counts(pdev, &num_dimms_per_channel,
1316                                         &num_channels);
1317         num_csrows = num_dimms_per_channel * 2;
1318
1319         debugf0("MC: %s(): Number of - Channels= %d  DIMMS= %d  CSROWS= %d\n",
1320                 __func__, num_channels, num_dimms_per_channel, num_csrows);
1321
1322         /* allocate a new MC control structure */
1323         mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels);
1324
1325         if (mci == NULL)
1326                 return -ENOMEM;
1327
1328         debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
1329
1330         mci->dev = &pdev->dev;  /* record ptr  to the generic device */
1331
1332         pvt = (struct i5000_pvt *)mci->pvt_info;
1333         pvt->system_address = pdev;     /* Record this device in our private */
1334         pvt->maxch = num_channels;
1335         pvt->maxdimmperch = num_dimms_per_channel;
1336
1337         /* 'get' the pci devices we want to reserve for our use */
1338         if (i5000_get_devices(mci, dev_idx))
1339                 goto fail0;
1340
1341         /* Time to get serious */
1342         i5000_get_mc_regs(mci); /* retrieve the hardware registers */
1343
1344         mci->mc_idx = 0;
1345         mci->mtype_cap = MEM_FLAG_FB_DDR2;
1346         mci->edac_ctl_cap = EDAC_FLAG_NONE;
1347         mci->edac_cap = EDAC_FLAG_NONE;
1348         mci->mod_name = "i5000_edac.c";
1349         mci->mod_ver = I5000_REVISION;
1350         mci->ctl_name = i5000_devs[dev_idx].ctl_name;
1351         mci->dev_name = pci_name(pdev);
1352         mci->ctl_page_to_phys = NULL;
1353
1354         /* Set the function pointer to an actual operation function */
1355         mci->edac_check = i5000_check_error;
1356
1357         /* initialize the MC control structure 'csrows' table
1358          * with the mapping and control information */
1359         if (i5000_init_csrows(mci)) {
1360                 debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n"
1361                         "    because i5000_init_csrows() returned nonzero "
1362                         "value\n");
1363                 mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */
1364         } else {
1365                 debugf1("MC: Enable error reporting now\n");
1366                 i5000_enable_error_reporting(mci);
1367         }
1368
1369         /* add this new MC control structure to EDAC's list of MCs */
1370         if (edac_mc_add_mc(mci, pvt->node_id)) {
1371                 debugf0("MC: " __FILE__
1372                         ": %s(): failed edac_mc_add_mc()\n", __func__);
1373                 /* FIXME: perhaps some code should go here that disables error
1374                  * reporting if we just enabled it
1375                  */
1376                 goto fail1;
1377         }
1378
1379         i5000_clear_error(mci);
1380
1381         /* allocating generic PCI control info */
1382         i5000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
1383         if (!i5000_pci) {
1384                 printk(KERN_WARNING
1385                         "%s(): Unable to create PCI control\n",
1386                         __func__);
1387                 printk(KERN_WARNING
1388                         "%s(): PCI error report via EDAC not setup\n",
1389                         __func__);
1390         }
1391
1392         return 0;
1393
1394         /* Error exit unwinding stack */
1395 fail1:
1396
1397         i5000_put_devices(mci);
1398
1399 fail0:
1400         edac_mc_free(mci);
1401         return -ENODEV;
1402 }
1403
1404 /******************************************************************************
1405  *      i5000_init_one  constructor for one instance of device
1406  *
1407  *      returns:
1408  *              negative on error
1409  *              count (>= 0)
1410  */
1411 static int __devinit i5000_init_one(struct pci_dev *pdev,
1412                                 const struct pci_device_id *id)
1413 {
1414         int rc;
1415
1416         debugf0("MC: " __FILE__ ": %s()\n", __func__);
1417
1418         /* wake up device */
1419         rc = pci_enable_device(pdev);
1420         if (rc == -EIO)
1421                 return rc;
1422
1423         /* now probe and enable the device */
1424         return i5000_probe1(pdev, id->driver_data);
1425 }
1426
1427 /**************************************************************************
1428  *      i5000_remove_one        destructor for one instance of device
1429  *
1430  */
1431 static void __devexit i5000_remove_one(struct pci_dev *pdev)
1432 {
1433         struct mem_ctl_info *mci;
1434
1435         debugf0(__FILE__ ": %s()\n", __func__);
1436
1437         if (i5000_pci)
1438                 edac_pci_release_generic_ctl(i5000_pci);
1439
1440         if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
1441                 return;
1442
1443         /* retrieve references to resources, and free those resources */
1444         i5000_put_devices(mci);
1445
1446         edac_mc_free(mci);
1447 }
1448
1449 /**************************************************************************
1450  *      pci_device_id   table for which devices we are looking for
1451  *
1452  *      The "E500P" device is the first device supported.
1453  */
1454 static const struct pci_device_id i5000_pci_tbl[] __devinitdata = {
1455         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000_DEV16),
1456          .driver_data = I5000P},
1457
1458         {0,}                    /* 0 terminated list. */
1459 };
1460
1461 MODULE_DEVICE_TABLE(pci, i5000_pci_tbl);
1462
1463 /**************************************************************************
1464  *      i5000_driver    pci_driver structure for this module
1465  *
1466  */
1467 static struct pci_driver i5000_driver = {
1468         .name = __stringify(KBUILD_BASENAME),
1469         .probe = i5000_init_one,
1470         .remove = __devexit_p(i5000_remove_one),
1471         .id_table = i5000_pci_tbl,
1472 };
1473
1474 /**************************************************************************
1475  *      i5000_init              Module entry function
1476  *                      Try to initialize this module for its devices
1477  */
1478 static int __init i5000_init(void)
1479 {
1480         int pci_rc;
1481
1482         debugf2("MC: " __FILE__ ": %s()\n", __func__);
1483
1484         pci_rc = pci_register_driver(&i5000_driver);
1485
1486         return (pci_rc < 0) ? pci_rc : 0;
1487 }
1488
1489 /**************************************************************************
1490  *      i5000_exit()    Module exit function
1491  *                      Unregister the driver
1492  */
1493 static void __exit i5000_exit(void)
1494 {
1495         debugf2("MC: " __FILE__ ": %s()\n", __func__);
1496         pci_unregister_driver(&i5000_driver);
1497 }
1498
1499 module_init(i5000_init);
1500 module_exit(i5000_exit);
1501
1502 MODULE_LICENSE("GPL");
1503 MODULE_AUTHOR
1504     ("Linux Networx (http://lnxi.com) Doug Thompson <norsk5@xmission.com>");
1505 MODULE_DESCRIPTION("MC Driver for Intel I5000 memory controllers - "
1506                 I5000_REVISION);
1507 module_param(edac_op_state, int, 0444);
1508 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");