drivers/edac/i5000_edac.c

   1 /*
   2  * Intel 5000(P/V/X) class Memory Controllers kernel module
   3  *
   4  * This file may be distributed under the terms of the
   5  * GNU General Public License.
   6  *
   7  * Written by Douglas Thompson Linux Networx (http://lnxi.com)
   8  *      norsk5@xmission.com
   9  *
  10  * This module is based on the following document:
  11  *
  12  * Intel 5000X Chipset Memory Controller Hub (MCH) - Datasheet
  13  *      http://developer.intel.com/design/chipsets/datashts/313070.htm
  14  *
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/init.h>
  19 #include <linux/pci.h>
  20 #include <linux/pci_ids.h>
  21 #include <linux/slab.h>
  22 #include <linux/edac.h>
  23 #include <asm/mmzone.h>
  24
  25 #include "edac_core.h"
  26
  27 /*
  28  * Alter this version for the I5000 module when modifications are made
  29  */
  30 #define I5000_REVISION    " Ver: 2.0.12 " __DATE__
  31 #define EDAC_MOD_STR      "i5000_edac"
  32
  33 #define i5000_printk(level, fmt, arg...) \
  34         edac_printk(level, "i5000", fmt, ##arg)
  35
  36 #define i5000_mc_printk(mci, level, fmt, arg...) \
  37         edac_mc_chipset_printk(mci, level, "i5000", fmt, ##arg)
  38
  39 #ifndef PCI_DEVICE_ID_INTEL_FBD_0
  40 #define PCI_DEVICE_ID_INTEL_FBD_0       0x25F5
  41 #endif
  42 #ifndef PCI_DEVICE_ID_INTEL_FBD_1
  43 #define PCI_DEVICE_ID_INTEL_FBD_1       0x25F6
  44 #endif
  45
  46 /* Device 16,
  47  * Function 0: System Address
  48  * Function 1: Memory Branch Map, Control, Errors Register
  49  * Function 2: FSB Error Registers
  50  *
  51  * All 3 functions of Device 16 (0,1,2) share the SAME DID
  52  */
  53 #define PCI_DEVICE_ID_INTEL_I5000_DEV16 0x25F0
  54
  55 /* OFFSETS for Function 0 */
  56
  57 /* OFFSETS for Function 1 */
  58 #define         AMBASE                  0x48
  59 #define         MAXCH                   0x56
  60 #define         MAXDIMMPERCH            0x57
  61 #define         TOLM                    0x6C
  62 #define         REDMEMB                 0x7C
  63 #define                 RED_ECC_LOCATOR(x)      ((x) & 0x3FFFF)
  64 #define                 REC_ECC_LOCATOR_EVEN(x) ((x) & 0x001FF)
  65 #define                 REC_ECC_LOCATOR_ODD(x)  ((x) & 0x3FE00)
  66 #define         MIR0                    0x80
  67 #define         MIR1                    0x84
  68 #define         MIR2                    0x88
  69 #define         AMIR0                   0x8C
  70 #define         AMIR1                   0x90
  71 #define         AMIR2                   0x94
  72
  73 #define         FERR_FAT_FBD            0x98
  74 #define         NERR_FAT_FBD            0x9C
  75 #define                 EXTRACT_FBDCHAN_INDX(x) (((x)>>28) & 0x3)
  76 #define                 FERR_FAT_FBDCHAN 0x30000000
  77 #define                 FERR_FAT_M3ERR  0x00000004
  78 #define                 FERR_FAT_M2ERR  0x00000002
  79 #define                 FERR_FAT_M1ERR  0x00000001
  80 #define                 FERR_FAT_MASK   (FERR_FAT_M1ERR | \
  81                                                 FERR_FAT_M2ERR | \
  82                                                 FERR_FAT_M3ERR)
  83
  84 #define         FERR_NF_FBD             0xA0
  85
  86 /* Thermal and SPD or BFD errors */
  87 #define                 FERR_NF_M28ERR  0x01000000
  88 #define                 FERR_NF_M27ERR  0x00800000
  89 #define                 FERR_NF_M26ERR  0x00400000
  90 #define                 FERR_NF_M25ERR  0x00200000
  91 #define                 FERR_NF_M24ERR  0x00100000
  92 #define                 FERR_NF_M23ERR  0x00080000
  93 #define                 FERR_NF_M22ERR  0x00040000
  94 #define                 FERR_NF_M21ERR  0x00020000
  95
  96 /* Correctable errors */
  97 #define                 FERR_NF_M20ERR  0x00010000
  98 #define                 FERR_NF_M19ERR  0x00008000
  99 #define                 FERR_NF_M18ERR  0x00004000
 100 #define                 FERR_NF_M17ERR  0x00002000
 101
 102 /* Non-Retry or redundant Retry errors */
 103 #define                 FERR_NF_M16ERR  0x00001000
 104 #define                 FERR_NF_M15ERR  0x00000800
 105 #define                 FERR_NF_M14ERR  0x00000400
 106 #define                 FERR_NF_M13ERR  0x00000200
 107
 108 /* Uncorrectable errors */
 109 #define                 FERR_NF_M12ERR  0x00000100
 110 #define                 FERR_NF_M11ERR  0x00000080
 111 #define                 FERR_NF_M10ERR  0x00000040
 112 #define                 FERR_NF_M9ERR   0x00000020
 113 #define                 FERR_NF_M8ERR   0x00000010
 114 #define                 FERR_NF_M7ERR   0x00000008
 115 #define                 FERR_NF_M6ERR   0x00000004
 116 #define                 FERR_NF_M5ERR   0x00000002
 117 #define                 FERR_NF_M4ERR   0x00000001
 118
 119 #define                 FERR_NF_UNCORRECTABLE   (FERR_NF_M12ERR | \
 120                                                         FERR_NF_M11ERR | \
 121                                                         FERR_NF_M10ERR | \
 122                                                         FERR_NF_M9ERR | \
 123                                                         FERR_NF_M8ERR | \
 124                                                         FERR_NF_M7ERR | \
 125                                                         FERR_NF_M6ERR | \
 126                                                         FERR_NF_M5ERR | \
 127                                                         FERR_NF_M4ERR)
 128 #define                 FERR_NF_CORRECTABLE     (FERR_NF_M20ERR | \
 129                                                         FERR_NF_M19ERR | \
 130                                                         FERR_NF_M18ERR | \
 131                                                         FERR_NF_M17ERR)
 132 #define                 FERR_NF_DIMM_SPARE      (FERR_NF_M27ERR | \
 133                                                         FERR_NF_M28ERR)
 134 #define                 FERR_NF_THERMAL         (FERR_NF_M26ERR | \
 135                                                         FERR_NF_M25ERR | \
 136                                                         FERR_NF_M24ERR | \
 137                                                         FERR_NF_M23ERR)
 138 #define                 FERR_NF_SPD_PROTOCOL    (FERR_NF_M22ERR)
 139 #define                 FERR_NF_NORTH_CRC       (FERR_NF_M21ERR)
 140 #define                 FERR_NF_NON_RETRY       (FERR_NF_M13ERR | \
 141                                                         FERR_NF_M14ERR | \
 142                                                         FERR_NF_M15ERR)
 143
 144 #define         NERR_NF_FBD             0xA4
 145 #define                 FERR_NF_MASK            (FERR_NF_UNCORRECTABLE | \
 146                                                         FERR_NF_CORRECTABLE | \
 147                                                         FERR_NF_DIMM_SPARE | \
 148                                                         FERR_NF_THERMAL | \
 149                                                         FERR_NF_SPD_PROTOCOL | \
 150                                                         FERR_NF_NORTH_CRC | \
 151                                                         FERR_NF_NON_RETRY)
 152
 153 #define         EMASK_FBD               0xA8
 154 #define                 EMASK_FBD_M28ERR        0x08000000
 155 #define                 EMASK_FBD_M27ERR        0x04000000
 156 #define                 EMASK_FBD_M26ERR        0x02000000
 157 #define                 EMASK_FBD_M25ERR        0x01000000
 158 #define                 EMASK_FBD_M24ERR        0x00800000
 159 #define                 EMASK_FBD_M23ERR        0x00400000
 160 #define                 EMASK_FBD_M22ERR        0x00200000
 161 #define                 EMASK_FBD_M21ERR        0x00100000
 162 #define                 EMASK_FBD_M20ERR        0x00080000
 163 #define                 EMASK_FBD_M19ERR        0x00040000
 164 #define                 EMASK_FBD_M18ERR        0x00020000
 165 #define                 EMASK_FBD_M17ERR        0x00010000
 166
 167 #define                 EMASK_FBD_M15ERR        0x00004000
 168 #define                 EMASK_FBD_M14ERR        0x00002000
 169 #define                 EMASK_FBD_M13ERR        0x00001000
 170 #define                 EMASK_FBD_M12ERR        0x00000800
 171 #define                 EMASK_FBD_M11ERR        0x00000400
 172 #define                 EMASK_FBD_M10ERR        0x00000200
 173 #define                 EMASK_FBD_M9ERR         0x00000100
 174 #define                 EMASK_FBD_M8ERR         0x00000080
 175 #define                 EMASK_FBD_M7ERR         0x00000040
 176 #define                 EMASK_FBD_M6ERR         0x00000020
 177 #define                 EMASK_FBD_M5ERR         0x00000010
 178 #define                 EMASK_FBD_M4ERR         0x00000008
 179 #define                 EMASK_FBD_M3ERR         0x00000004
 180 #define                 EMASK_FBD_M2ERR         0x00000002
 181 #define                 EMASK_FBD_M1ERR         0x00000001
 182
 183 #define                 ENABLE_EMASK_FBD_FATAL_ERRORS   (EMASK_FBD_M1ERR | \
 184                                                         EMASK_FBD_M2ERR | \
 185                                                         EMASK_FBD_M3ERR)
 186
 187 #define                 ENABLE_EMASK_FBD_UNCORRECTABLE  (EMASK_FBD_M4ERR | \
 188                                                         EMASK_FBD_M5ERR | \
 189                                                         EMASK_FBD_M6ERR | \
 190                                                         EMASK_FBD_M7ERR | \
 191                                                         EMASK_FBD_M8ERR | \
 192                                                         EMASK_FBD_M9ERR | \
 193                                                         EMASK_FBD_M10ERR | \
 194                                                         EMASK_FBD_M11ERR | \
 195                                                         EMASK_FBD_M12ERR)
 196 #define                 ENABLE_EMASK_FBD_CORRECTABLE    (EMASK_FBD_M17ERR | \
 197                                                         EMASK_FBD_M18ERR | \
 198                                                         EMASK_FBD_M19ERR | \
 199                                                         EMASK_FBD_M20ERR)
 200 #define                 ENABLE_EMASK_FBD_DIMM_SPARE     (EMASK_FBD_M27ERR | \
 201                                                         EMASK_FBD_M28ERR)
 202 #define                 ENABLE_EMASK_FBD_THERMALS       (EMASK_FBD_M26ERR | \
 203                                                         EMASK_FBD_M25ERR | \
 204                                                         EMASK_FBD_M24ERR | \
 205                                                         EMASK_FBD_M23ERR)
 206 #define                 ENABLE_EMASK_FBD_SPD_PROTOCOL   (EMASK_FBD_M22ERR)
 207 #define                 ENABLE_EMASK_FBD_NORTH_CRC      (EMASK_FBD_M21ERR)
 208 #define                 ENABLE_EMASK_FBD_NON_RETRY      (EMASK_FBD_M15ERR | \
 209                                                         EMASK_FBD_M14ERR | \
 210                                                         EMASK_FBD_M13ERR)
 211
 212 #define         ENABLE_EMASK_ALL        (ENABLE_EMASK_FBD_NON_RETRY | \
 213                                         ENABLE_EMASK_FBD_NORTH_CRC | \
 214                                         ENABLE_EMASK_FBD_SPD_PROTOCOL | \
 215                                         ENABLE_EMASK_FBD_THERMALS | \
 216                                         ENABLE_EMASK_FBD_DIMM_SPARE | \
 217                                         ENABLE_EMASK_FBD_FATAL_ERRORS | \
 218                                         ENABLE_EMASK_FBD_CORRECTABLE | \
 219                                         ENABLE_EMASK_FBD_UNCORRECTABLE)
 220
 221 #define         ERR0_FBD                0xAC
 222 #define         ERR1_FBD                0xB0
 223 #define         ERR2_FBD                0xB4
 224 #define         MCERR_FBD               0xB8
 225 #define         NRECMEMA                0xBE
 226 #define                 NREC_BANK(x)            (((x)>>12) & 0x7)
 227 #define                 NREC_RDWR(x)            (((x)>>11) & 1)
 228 #define                 NREC_RANK(x)            (((x)>>8) & 0x7)
 229 #define         NRECMEMB                0xC0
 230 #define                 NREC_CAS(x)             (((x)>>16) & 0xFFFFFF)
 231 #define                 NREC_RAS(x)             ((x) & 0x7FFF)
 232 #define         NRECFGLOG               0xC4
 233 #define         NREEECFBDA              0xC8
 234 #define         NREEECFBDB              0xCC
 235 #define         NREEECFBDC              0xD0
 236 #define         NREEECFBDD              0xD4
 237 #define         NREEECFBDE              0xD8
 238 #define         REDMEMA                 0xDC
 239 #define         RECMEMA                 0xE2
 240 #define                 REC_BANK(x)             (((x)>>12) & 0x7)
 241 #define                 REC_RDWR(x)             (((x)>>11) & 1)
 242 #define                 REC_RANK(x)             (((x)>>8) & 0x7)
 243 #define         RECMEMB                 0xE4
 244 #define                 REC_CAS(x)              (((x)>>16) & 0xFFFFFF)
 245 #define                 REC_RAS(x)              ((x) & 0x7FFF)
 246 #define         RECFGLOG                0xE8
 247 #define         RECFBDA                 0xEC
 248 #define         RECFBDB                 0xF0
 249 #define         RECFBDC                 0xF4
 250 #define         RECFBDD                 0xF8
 251 #define         RECFBDE                 0xFC
 252
 253 /* OFFSETS for Function 2 */
 254
 255 /*
 256  * Device 21,
 257  * Function 0: Memory Map Branch 0
 258  *
 259  * Device 22,
 260  * Function 0: Memory Map Branch 1
 261  */
 262 #define PCI_DEVICE_ID_I5000_BRANCH_0    0x25F5
 263 #define PCI_DEVICE_ID_I5000_BRANCH_1    0x25F6
 264
 265 #define AMB_PRESENT_0   0x64
 266 #define AMB_PRESENT_1   0x66
 267 #define MTR0            0x80
 268 #define MTR1            0x84
 269 #define MTR2            0x88
 270 #define MTR3            0x8C
 271
 272 #define NUM_MTRS                4
 273 #define CHANNELS_PER_BRANCH     (2)
 274
 275 /* Defines to extract the vaious fields from the
 276  *      MTRx - Memory Technology Registers
 277  */
 278 #define MTR_DIMMS_PRESENT(mtr)          ((mtr) & (0x1 << 8))
 279 #define MTR_DRAM_WIDTH(mtr)             ((((mtr) >> 6) & 0x1) ? 8 : 4)
 280 #define MTR_DRAM_BANKS(mtr)             ((((mtr) >> 5) & 0x1) ? 8 : 4)
 281 #define MTR_DRAM_BANKS_ADDR_BITS(mtr)   ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2)
 282 #define MTR_DIMM_RANK(mtr)              (((mtr) >> 4) & 0x1)
 283 #define MTR_DIMM_RANK_ADDR_BITS(mtr)    (MTR_DIMM_RANK(mtr) ? 2 : 1)
 284 #define MTR_DIMM_ROWS(mtr)              (((mtr) >> 2) & 0x3)
 285 #define MTR_DIMM_ROWS_ADDR_BITS(mtr)    (MTR_DIMM_ROWS(mtr) + 13)
 286 #define MTR_DIMM_COLS(mtr)              ((mtr) & 0x3)
 287 #define MTR_DIMM_COLS_ADDR_BITS(mtr)    (MTR_DIMM_COLS(mtr) + 10)
 288
 289 #ifdef CONFIG_EDAC_DEBUG
 290 static char *numrow_toString[] = {
 291         "8,192 - 13 rows",
 292         "16,384 - 14 rows",
 293         "32,768 - 15 rows",
 294         "reserved"
 295 };
 296
 297 static char *numcol_toString[] = {
 298         "1,024 - 10 columns",
 299         "2,048 - 11 columns",
 300         "4,096 - 12 columns",
 301         "reserved"
 302 };
 303 #endif
 304
 305 /* enables the report of miscellaneous messages as CE errors - default off */
 306 static int misc_messages;
 307
 308 /* Enumeration of supported devices */
 309 enum i5000_chips {
 310         I5000P = 0,
 311         I5000V = 1,             /* future */
 312         I5000X = 2              /* future */
 313 };
 314
 315 /* Device name and register DID (Device ID) */
 316 struct i5000_dev_info {
 317         const char *ctl_name;   /* name for this device */
 318         u16 fsb_mapping_errors; /* DID for the branchmap,control */
 319 };
 320
 321 /* Table of devices attributes supported by this driver */
 322 static const struct i5000_dev_info i5000_devs[] = {
 323         [I5000P] = {
 324                 .ctl_name = "I5000",
 325                 .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I5000_DEV16,
 326         },
 327 };
 328
 329 struct i5000_dimm_info {
 330         int megabytes;          /* size, 0 means not present  */
 331         int dual_rank;
 332 };
 333
 334 #define MAX_CHANNELS    6       /* max possible channels */
 335 #define MAX_CSROWS      (8*2)   /* max possible csrows per channel */
 336
 337 /* driver private data structure */
 338 struct i5000_pvt {
 339         struct pci_dev *system_address; /* 16.0 */
 340         struct pci_dev *branchmap_werrors;      /* 16.1 */
 341         struct pci_dev *fsb_error_regs; /* 16.2 */
 342         struct pci_dev *branch_0;       /* 21.0 */
 343         struct pci_dev *branch_1;       /* 22.0 */
 344
 345         u16 tolm;               /* top of low memory */
 346         u64 ambase;             /* AMB BAR */
 347
 348         u16 mir0, mir1, mir2;
 349
 350         u16 b0_mtr[NUM_MTRS];   /* Memory Technlogy Reg */
 351         u16 b0_ambpresent0;     /* Branch 0, Channel 0 */
 352         u16 b0_ambpresent1;     /* Brnach 0, Channel 1 */
 353
 354         u16 b1_mtr[NUM_MTRS];   /* Memory Technlogy Reg */
 355         u16 b1_ambpresent0;     /* Branch 1, Channel 8 */
 356         u16 b1_ambpresent1;     /* Branch 1, Channel 1 */
 357
 358         /* DIMM information matrix, allocating architecture maximums */
 359         struct i5000_dimm_info dimm_info[MAX_CSROWS][MAX_CHANNELS];
 360
 361         /* Actual values for this controller */
 362         int maxch;              /* Max channels */
 363         int maxdimmperch;       /* Max DIMMs per channel */
 364 };
 365
 366 /* I5000 MCH error information retrieved from Hardware */
 367 struct i5000_error_info {
 368
 369         /* These registers are always read from the MC */
 370         u32 ferr_fat_fbd;       /* First Errors Fatal */
 371         u32 nerr_fat_fbd;       /* Next Errors Fatal */
 372         u32 ferr_nf_fbd;        /* First Errors Non-Fatal */
 373         u32 nerr_nf_fbd;        /* Next Errors Non-Fatal */
 374
 375         /* These registers are input ONLY if there was a Recoverable  Error */
 376         u32 redmemb;            /* Recoverable Mem Data Error log B */
 377         u16 recmema;            /* Recoverable Mem Error log A */
 378         u32 recmemb;            /* Recoverable Mem Error log B */
 379
 380         /* These registers are input ONLY if there was a
 381          * Non-Recoverable Error */
 382         u16 nrecmema;           /* Non-Recoverable Mem log A */
 383         u16 nrecmemb;           /* Non-Recoverable Mem log B */
 384
 385 };
 386
 387 static struct edac_pci_ctl_info *i5000_pci;
 388
 389 /*
 390  *      i5000_get_error_info    Retrieve the hardware error information from
 391  *                              the hardware and cache it in the 'info'
 392  *                              structure
 393  */
 394 static void i5000_get_error_info(struct mem_ctl_info *mci,
 395                                  struct i5000_error_info *info)
 396 {
 397         struct i5000_pvt *pvt;
 398         u32 value;
 399
 400         pvt = mci->pvt_info;
 401
 402         /* read in the 1st FATAL error register */
 403         pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value);
 404
 405         /* Mask only the bits that the doc says are valid
 406          */
 407         value &= (FERR_FAT_FBDCHAN | FERR_FAT_MASK);
 408
 409         /* If there is an error, then read in the */
 410         /* NEXT FATAL error register and the Memory Error Log Register A */
 411         if (value & FERR_FAT_MASK) {
 412                 info->ferr_fat_fbd = value;
 413
 414                 /* harvest the various error data we need */
 415                 pci_read_config_dword(pvt->branchmap_werrors,
 416                                 NERR_FAT_FBD, &info->nerr_fat_fbd);
 417                 pci_read_config_word(pvt->branchmap_werrors,
 418                                 NRECMEMA, &info->nrecmema);
 419                 pci_read_config_word(pvt->branchmap_werrors,
 420                                 NRECMEMB, &info->nrecmemb);
 421
 422                 /* Clear the error bits, by writing them back */
 423                 pci_write_config_dword(pvt->branchmap_werrors,
 424                                 FERR_FAT_FBD, value);
 425         } else {
 426                 info->ferr_fat_fbd = 0;
 427                 info->nerr_fat_fbd = 0;
 428                 info->nrecmema = 0;
 429                 info->nrecmemb = 0;
 430         }
 431
 432         /* read in the 1st NON-FATAL error register */
 433         pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value);
 434
 435         /* If there is an error, then read in the 1st NON-FATAL error
 436          * register as well */
 437         if (value & FERR_NF_MASK) {
 438                 info->ferr_nf_fbd = value;
 439
 440                 /* harvest the various error data we need */
 441                 pci_read_config_dword(pvt->branchmap_werrors,
 442                                 NERR_NF_FBD, &info->nerr_nf_fbd);
 443                 pci_read_config_word(pvt->branchmap_werrors,
 444                                 RECMEMA, &info->recmema);
 445                 pci_read_config_dword(pvt->branchmap_werrors,
 446                                 RECMEMB, &info->recmemb);
 447                 pci_read_config_dword(pvt->branchmap_werrors,
 448                                 REDMEMB, &info->redmemb);
 449
 450                 /* Clear the error bits, by writing them back */
 451                 pci_write_config_dword(pvt->branchmap_werrors,
 452                                 FERR_NF_FBD, value);
 453         } else {
 454                 info->ferr_nf_fbd = 0;
 455                 info->nerr_nf_fbd = 0;
 456                 info->recmema = 0;
 457                 info->recmemb = 0;
 458                 info->redmemb = 0;
 459         }
 460 }
 461
 462 /*
 463  * i5000_process_fatal_error_info(struct mem_ctl_info *mci,
 464  *                                      struct i5000_error_info *info,
 465  *                                      int handle_errors);
 466  *
 467  *      handle the Intel FATAL errors, if any
 468  */
 469 static void i5000_process_fatal_error_info(struct mem_ctl_info *mci,
 470                                         struct i5000_error_info *info,
 471                                         int handle_errors)
 472 {
 473         char msg[EDAC_MC_LABEL_LEN + 1 + 160];
 474         char *specific = NULL;
 475         u32 allErrors;
 476         int branch;
 477         int channel;
 478         int bank;
 479         int rank;
 480         int rdwr;
 481         int ras, cas;
 482
 483         /* mask off the Error bits that are possible */
 484         allErrors = (info->ferr_fat_fbd & FERR_FAT_MASK);
 485         if (!allErrors)
 486                 return;         /* if no error, return now */
 487
 488         branch = EXTRACT_FBDCHAN_INDX(info->ferr_fat_fbd);
 489         channel = branch;
 490
 491         /* Use the NON-Recoverable macros to extract data */
 492         bank = NREC_BANK(info->nrecmema);
 493         rank = NREC_RANK(info->nrecmema);
 494         rdwr = NREC_RDWR(info->nrecmema);
 495         ras = NREC_RAS(info->nrecmemb);
 496         cas = NREC_CAS(info->nrecmemb);
 497
 498         debugf0("\t\tCSROW= %d  Channels= %d,%d  (Branch= %d "
 499                 "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
 500                 rank, channel, channel + 1, branch >> 1, bank,
 501                 rdwr ? "Write" : "Read", ras, cas);
 502
 503         /* Only 1 bit will be on */
 504         switch (allErrors) {
 505         case FERR_FAT_M1ERR:
 506                 specific = "Alert on non-redundant retry or fast "
 507                                 "reset timeout";
 508                 break;
 509         case FERR_FAT_M2ERR:
 510                 specific = "Northbound CRC error on non-redundant "
 511                                 "retry";
 512                 break;
 513         case FERR_FAT_M3ERR:
 514                 {
 515                 static int done;
 516
 517                 /*
 518                  * This error is generated to inform that the intelligent
 519                  * throttling is disabled and the temperature passed the
 520                  * specified middle point. Since this is something the BIOS
 521                  * should take care of, we'll warn only once to avoid
 522                  * worthlessly flooding the log.
 523                  */
 524                 if (done)
 525                         return;
 526                 done++;
 527
 528                 specific = ">Tmid Thermal event with intelligent "
 529                            "throttling disabled";
 530                 }
 531                 break;
 532         }
 533
 534         /* Form out message */
 535         snprintf(msg, sizeof(msg),
 536                  "(Branch=%d DRAM-Bank=%d RDWR=%s RAS=%d CAS=%d "
 537                  "FATAL Err=0x%x (%s))",
 538                  branch >> 1, bank, rdwr ? "Write" : "Read", ras, cas,
 539                  allErrors, specific);
 540
 541         /* Call the helper to output message */
 542         edac_mc_handle_fbd_ue(mci, rank, channel, channel + 1, msg);
 543 }
 544
 545 /*
 546  * i5000_process_fatal_error_info(struct mem_ctl_info *mci,
 547  *                              struct i5000_error_info *info,
 548  *                              int handle_errors);
 549  *
 550  *      handle the Intel NON-FATAL errors, if any
 551  */
 552 static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci,
 553                                         struct i5000_error_info *info,
 554                                         int handle_errors)
 555 {
 556         char msg[EDAC_MC_LABEL_LEN + 1 + 170];
 557         char *specific = NULL;
 558         u32 allErrors;
 559         u32 ue_errors;
 560         u32 ce_errors;
 561         u32 misc_errors;
 562         int branch;
 563         int channel;
 564         int bank;
 565         int rank;
 566         int rdwr;
 567         int ras, cas;
 568
 569         /* mask off the Error bits that are possible */
 570         allErrors = (info->ferr_nf_fbd & FERR_NF_MASK);
 571         if (!allErrors)
 572                 return;         /* if no error, return now */
 573
 574         /* ONLY ONE of the possible error bits will be set, as per the docs */
 575         ue_errors = allErrors & FERR_NF_UNCORRECTABLE;
 576         if (ue_errors) {
 577                 debugf0("\tUncorrected bits= 0x%x\n", ue_errors);
 578
 579                 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
 580
 581                 /*
 582                  * According with i5000 datasheet, bit 28 has no significance
 583                  * for errors M4Err-M12Err and M17Err-M21Err, on FERR_NF_FBD
 584                  */
 585                 channel = branch & 2;
 586
 587                 bank = NREC_BANK(info->nrecmema);
 588                 rank = NREC_RANK(info->nrecmema);
 589                 rdwr = NREC_RDWR(info->nrecmema);
 590                 ras = NREC_RAS(info->nrecmemb);
 591                 cas = NREC_CAS(info->nrecmemb);
 592
 593                 debugf0
 594                         ("\t\tCSROW= %d  Channels= %d,%d  (Branch= %d "
 595                         "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
 596                         rank, channel, channel + 1, branch >> 1, bank,
 597                         rdwr ? "Write" : "Read", ras, cas);
 598
 599                 switch (ue_errors) {
 600                 case FERR_NF_M12ERR:
 601                         specific = "Non-Aliased Uncorrectable Patrol Data ECC";
 602                         break;
 603                 case FERR_NF_M11ERR:
 604                         specific = "Non-Aliased Uncorrectable Spare-Copy "
 605                                         "Data ECC";
 606                         break;
 607                 case FERR_NF_M10ERR:
 608                         specific = "Non-Aliased Uncorrectable Mirrored Demand "
 609                                         "Data ECC";
 610                         break;
 611                 case FERR_NF_M9ERR:
 612                         specific = "Non-Aliased Uncorrectable Non-Mirrored "
 613                                         "Demand Data ECC";
 614                         break;
 615                 case FERR_NF_M8ERR:
 616                         specific = "Aliased Uncorrectable Patrol Data ECC";
 617                         break;
 618                 case FERR_NF_M7ERR:
 619                         specific = "Aliased Uncorrectable Spare-Copy Data ECC";
 620                         break;
 621                 case FERR_NF_M6ERR:
 622                         specific = "Aliased Uncorrectable Mirrored Demand "
 623                                         "Data ECC";
 624                         break;
 625                 case FERR_NF_M5ERR:
 626                         specific = "Aliased Uncorrectable Non-Mirrored Demand "
 627                                         "Data ECC";
 628                         break;
 629                 case FERR_NF_M4ERR:
 630                         specific = "Uncorrectable Data ECC on Replay";
 631                         break;
 632                 }
 633
 634                 /* Form out message */
 635                 snprintf(msg, sizeof(msg),
 636                          "(Branch=%d DRAM-Bank=%d RDWR=%s RAS=%d "
 637                          "CAS=%d, UE Err=0x%x (%s))",
 638                          branch >> 1, bank, rdwr ? "Write" : "Read", ras, cas,
 639                          ue_errors, specific);
 640
 641                 /* Call the helper to output message */
 642                 edac_mc_handle_fbd_ue(mci, rank, channel, channel + 1, msg);
 643         }
 644
 645         /* Check correctable errors */
 646         ce_errors = allErrors & FERR_NF_CORRECTABLE;
 647         if (ce_errors) {
 648                 debugf0("\tCorrected bits= 0x%x\n", ce_errors);
 649
 650                 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
 651
 652                 channel = 0;
 653                 if (REC_ECC_LOCATOR_ODD(info->redmemb))
 654                         channel = 1;
 655
 656                 /* Convert channel to be based from zero, instead of
 657                  * from branch base of 0 */
 658                 channel += branch;
 659
 660                 bank = REC_BANK(info->recmema);
 661                 rank = REC_RANK(info->recmema);
 662                 rdwr = REC_RDWR(info->recmema);
 663                 ras = REC_RAS(info->recmemb);
 664                 cas = REC_CAS(info->recmemb);
 665
 666                 debugf0("\t\tCSROW= %d Channel= %d  (Branch %d "
 667                         "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
 668                         rank, channel, branch >> 1, bank,
 669                         rdwr ? "Write" : "Read", ras, cas);
 670
 671                 switch (ce_errors) {
 672                 case FERR_NF_M17ERR:
 673                         specific = "Correctable Non-Mirrored Demand Data ECC";
 674                         break;
 675                 case FERR_NF_M18ERR:
 676                         specific = "Correctable Mirrored Demand Data ECC";
 677                         break;
 678                 case FERR_NF_M19ERR:
 679                         specific = "Correctable Spare-Copy Data ECC";
 680                         break;
 681                 case FERR_NF_M20ERR:
 682                         specific = "Correctable Patrol Data ECC";
 683                         break;
 684                 }
 685
 686                 /* Form out message */
 687                 snprintf(msg, sizeof(msg),
 688                          "(Branch=%d DRAM-Bank=%d RDWR=%s RAS=%d "
 689                          "CAS=%d, CE Err=0x%x (%s))", branch >> 1, bank,
 690                          rdwr ? "Write" : "Read", ras, cas, ce_errors,
 691                          specific);
 692
 693                 /* Call the helper to output message */
 694                 edac_mc_handle_fbd_ce(mci, rank, channel, msg);
 695         }
 696
 697         if (!misc_messages)
 698                 return;
 699
 700         misc_errors = allErrors & (FERR_NF_NON_RETRY | FERR_NF_NORTH_CRC |
 701                                    FERR_NF_SPD_PROTOCOL | FERR_NF_DIMM_SPARE);
 702         if (misc_errors) {
 703                 switch (misc_errors) {
 704                 case FERR_NF_M13ERR:
 705                         specific = "Non-Retry or Redundant Retry FBD Memory "
 706                                         "Alert or Redundant Fast Reset Timeout";
 707                         break;
 708                 case FERR_NF_M14ERR:
 709                         specific = "Non-Retry or Redundant Retry FBD "
 710                                         "Configuration Alert";
 711                         break;
 712                 case FERR_NF_M15ERR:
 713                         specific = "Non-Retry or Redundant Retry FBD "
 714                                         "Northbound CRC error on read data";
 715                         break;
 716                 case FERR_NF_M21ERR:
 717                         specific = "FBD Northbound CRC error on "
 718                                         "FBD Sync Status";
 719                         break;
 720                 case FERR_NF_M22ERR:
 721                         specific = "SPD protocol error";
 722                         break;
 723                 case FERR_NF_M27ERR:
 724                         specific = "DIMM-spare copy started";
 725                         break;
 726                 case FERR_NF_M28ERR:
 727                         specific = "DIMM-spare copy completed";
 728                         break;
 729                 }
 730                 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
 731
 732                 /* Form out message */
 733                 snprintf(msg, sizeof(msg),
 734                          "(Branch=%d Err=%#x (%s))", branch >> 1,
 735                          misc_errors, specific);
 736
 737                 /* Call the helper to output message */
 738                 edac_mc_handle_fbd_ce(mci, 0, 0, msg);
 739         }
 740 }
 741
 742 /*
 743  *      i5000_process_error_info        Process the error info that is
 744  *      in the 'info' structure, previously retrieved from hardware
 745  */
 746 static void i5000_process_error_info(struct mem_ctl_info *mci,
 747                                 struct i5000_error_info *info,
 748                                 int handle_errors)
 749 {
 750         /* First handle any fatal errors that occurred */
 751         i5000_process_fatal_error_info(mci, info, handle_errors);
 752
 753         /* now handle any non-fatal errors that occurred */
 754         i5000_process_nonfatal_error_info(mci, info, handle_errors);
 755 }
 756
 757 /*
 758  *      i5000_clear_error       Retrieve any error from the hardware
 759  *                              but do NOT process that error.
 760  *                              Used for 'clearing' out of previous errors
 761  *                              Called by the Core module.
 762  */
 763 static void i5000_clear_error(struct mem_ctl_info *mci)
 764 {
 765         struct i5000_error_info info;
 766
 767         i5000_get_error_info(mci, &info);
 768 }
 769
 770 /*
 771  *      i5000_check_error       Retrieve and process errors reported by the
 772  *                              hardware. Called by the Core module.
 773  */
 774 static void i5000_check_error(struct mem_ctl_info *mci)
 775 {
 776         struct i5000_error_info info;
 777         debugf4("MC%d: " __FILE__ ": %s()\n", mci->mc_idx, __func__);
 778         i5000_get_error_info(mci, &info);
 779         i5000_process_error_info(mci, &info, 1);
 780 }
 781
 782 /*
 783  *      i5000_get_devices       Find and perform 'get' operation on the MCH's
 784  *                      device/functions we want to reference for this driver
 785  *
 786  *                      Need to 'get' device 16 func 1 and func 2
 787  */
 788 static int i5000_get_devices(struct mem_ctl_info *mci, int dev_idx)
 789 {
 790         //const struct i5000_dev_info *i5000_dev = &i5000_devs[dev_idx];
 791         struct i5000_pvt *pvt;
 792         struct pci_dev *pdev;
 793
 794         pvt = mci->pvt_info;
 795
 796         /* Attempt to 'get' the MCH register we want */
 797         pdev = NULL;
 798         while (1) {
 799                 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
 800                                 PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev);
 801
 802                 /* End of list, leave */
 803                 if (pdev == NULL) {
 804                         i5000_printk(KERN_ERR,
 805                                 "'system address,Process Bus' "
 806                                 "device not found:"
 807                                 "vendor 0x%x device 0x%x FUNC 1 "
 808                                 "(broken BIOS?)\n",
 809                                 PCI_VENDOR_ID_INTEL,
 810                                 PCI_DEVICE_ID_INTEL_I5000_DEV16);
 811
 812                         return 1;
 813                 }
 814
 815                 /* Scan for device 16 func 1 */
 816                 if (PCI_FUNC(pdev->devfn) == 1)
 817                         break;
 818         }
 819
 820         pvt->branchmap_werrors = pdev;
 821
 822         /* Attempt to 'get' the MCH register we want */
 823         pdev = NULL;
 824         while (1) {
 825                 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
 826                                 PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev);
 827
 828                 if (pdev == NULL) {
 829                         i5000_printk(KERN_ERR,
 830                                 "MC: 'branchmap,control,errors' "
 831                                 "device not found:"
 832                                 "vendor 0x%x device 0x%x Func 2 "
 833                                 "(broken BIOS?)\n",
 834                                 PCI_VENDOR_ID_INTEL,
 835                                 PCI_DEVICE_ID_INTEL_I5000_DEV16);
 836
 837                         pci_dev_put(pvt->branchmap_werrors);
 838                         return 1;
 839                 }
 840
 841                 /* Scan for device 16 func 1 */
 842                 if (PCI_FUNC(pdev->devfn) == 2)
 843                         break;
 844         }
 845
 846         pvt->fsb_error_regs = pdev;
 847
 848         debugf1("System Address, processor bus- PCI Bus ID: %s  %x:%x\n",
 849                 pci_name(pvt->system_address),
 850                 pvt->system_address->vendor, pvt->system_address->device);
 851         debugf1("Branchmap, control and errors - PCI Bus ID: %s  %x:%x\n",
 852                 pci_name(pvt->branchmap_werrors),
 853                 pvt->branchmap_werrors->vendor, pvt->branchmap_werrors->device);
 854         debugf1("FSB Error Regs - PCI Bus ID: %s  %x:%x\n",
 855                 pci_name(pvt->fsb_error_regs),
 856                 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
 857
 858         pdev = NULL;
 859         pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
 860                         PCI_DEVICE_ID_I5000_BRANCH_0, pdev);
 861
 862         if (pdev == NULL) {
 863                 i5000_printk(KERN_ERR,
 864                         "MC: 'BRANCH 0' device not found:"
 865                         "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
 866                         PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_I5000_BRANCH_0);
 867
 868                 pci_dev_put(pvt->branchmap_werrors);
 869                 pci_dev_put(pvt->fsb_error_regs);
 870                 return 1;
 871         }
 872
 873         pvt->branch_0 = pdev;
 874
 875         /* If this device claims to have more than 2 channels then
 876          * fetch Branch 1's information
 877          */
 878         if (pvt->maxch >= CHANNELS_PER_BRANCH) {
 879                 pdev = NULL;
 880                 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
 881                                 PCI_DEVICE_ID_I5000_BRANCH_1, pdev);
 882
 883                 if (pdev == NULL) {
 884                         i5000_printk(KERN_ERR,
 885                                 "MC: 'BRANCH 1' device not found:"
 886                                 "vendor 0x%x device 0x%x Func 0 "
 887                                 "(broken BIOS?)\n",
 888                                 PCI_VENDOR_ID_INTEL,
 889                                 PCI_DEVICE_ID_I5000_BRANCH_1);
 890
 891                         pci_dev_put(pvt->branchmap_werrors);
 892                         pci_dev_put(pvt->fsb_error_regs);
 893                         pci_dev_put(pvt->branch_0);
 894                         return 1;
 895                 }
 896
 897                 pvt->branch_1 = pdev;
 898         }
 899
 900         return 0;
 901 }
 902
 903 /*
 904  *      i5000_put_devices       'put' all the devices that we have
 905  *                              reserved via 'get'
 906  */
 907 static void i5000_put_devices(struct mem_ctl_info *mci)
 908 {
 909         struct i5000_pvt *pvt;
 910
 911         pvt = mci->pvt_info;
 912
 913         pci_dev_put(pvt->branchmap_werrors);    /* FUNC 1 */
 914         pci_dev_put(pvt->fsb_error_regs);       /* FUNC 2 */
 915         pci_dev_put(pvt->branch_0);     /* DEV 21 */
 916
 917         /* Only if more than 2 channels do we release the second branch */
 918         if (pvt->maxch >= CHANNELS_PER_BRANCH)
 919                 pci_dev_put(pvt->branch_1);     /* DEV 22 */
 920 }
 921
 922 /*
 923  *      determine_amb_resent
 924  *
 925  *              the information is contained in NUM_MTRS different registers
 926  *              determineing which of the NUM_MTRS requires knowing
 927  *              which channel is in question
 928  *
 929  *      2 branches, each with 2 channels
 930  *              b0_ambpresent0 for channel '0'
 931  *              b0_ambpresent1 for channel '1'
 932  *              b1_ambpresent0 for channel '2'
 933  *              b1_ambpresent1 for channel '3'
 934  */
 935 static int determine_amb_present_reg(struct i5000_pvt *pvt, int channel)
 936 {
 937         int amb_present;
 938
 939         if (channel < CHANNELS_PER_BRANCH) {
 940                 if (channel & 0x1)
 941                         amb_present = pvt->b0_ambpresent1;
 942                 else
 943                         amb_present = pvt->b0_ambpresent0;
 944         } else {
 945                 if (channel & 0x1)
 946                         amb_present = pvt->b1_ambpresent1;
 947                 else
 948                         amb_present = pvt->b1_ambpresent0;
 949         }
 950
 951         return amb_present;
 952 }
 953
 954 /*
 955  * determine_mtr(pvt, csrow, channel)
 956  *
 957  *      return the proper MTR register as determine by the csrow and channel desired
 958  */
 959 static int determine_mtr(struct i5000_pvt *pvt, int csrow, int channel)
 960 {
 961         int mtr;
 962
 963         if (channel < CHANNELS_PER_BRANCH)
 964                 mtr = pvt->b0_mtr[csrow >> 1];
 965         else
 966                 mtr = pvt->b1_mtr[csrow >> 1];
 967
 968         return mtr;
 969 }
 970
 971 /*
 972  */
 973 static void decode_mtr(int slot_row, u16 mtr)
 974 {
 975         int ans;
 976
 977         ans = MTR_DIMMS_PRESENT(mtr);
 978
 979         debugf2("\tMTR%d=0x%x:  DIMMs are %s\n", slot_row, mtr,
 980                 ans ? "Present" : "NOT Present");
 981         if (!ans)
 982                 return;
 983
 984         debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
 985         debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
 986         debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANK(mtr) ? "double" : "single");
 987         debugf2("\t\tNUMROW: %s\n", numrow_toString[MTR_DIMM_ROWS(mtr)]);
 988         debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]);
 989 }
 990
 991 static void handle_channel(struct i5000_pvt *pvt, int csrow, int channel,
 992                         struct i5000_dimm_info *dinfo)
 993 {
 994         int mtr;
 995         int amb_present_reg;
 996         int addrBits;
 997
 998         mtr = determine_mtr(pvt, csrow, channel);
 999         if (MTR_DIMMS_PRESENT(mtr)) {
1000                 amb_present_reg = determine_amb_present_reg(pvt, channel);
1001
1002                 /* Determine if there is  a  DIMM present in this DIMM slot */
1003                 if (amb_present_reg & (1 << (csrow >> 1))) {
1004                         dinfo->dual_rank = MTR_DIMM_RANK(mtr);
1005
1006                         if (!((dinfo->dual_rank == 0) &&
1007                                 ((csrow & 0x1) == 0x1))) {
1008                                 /* Start with the number of bits for a Bank
1009                                  * on the DRAM */
1010                                 addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr);
1011                                 /* Add thenumber of ROW bits */
1012                                 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
1013                                 /* add the number of COLUMN bits */
1014                                 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
1015
1016                                 addrBits += 6;  /* add 64 bits per DIMM */
1017                                 addrBits -= 20; /* divide by 2^^20 */
1018                                 addrBits -= 3;  /* 8 bits per bytes */
1019
1020                                 dinfo->megabytes = 1 << addrBits;
1021                         }
1022                 }
1023         }
1024 }
1025
1026 /*
1027  *      calculate_dimm_size
1028  *
1029  *      also will output a DIMM matrix map, if debug is enabled, for viewing
1030  *      how the DIMMs are populated
1031  */
1032 static void calculate_dimm_size(struct i5000_pvt *pvt)
1033 {
1034         struct i5000_dimm_info *dinfo;
1035         int csrow, max_csrows;
1036         char *p, *mem_buffer;
1037         int space, n;
1038         int channel;
1039
1040         /* ================= Generate some debug output ================= */
1041         space = PAGE_SIZE;
1042         mem_buffer = p = kmalloc(space, GFP_KERNEL);
1043         if (p == NULL) {
1044                 i5000_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n",
1045                         __FILE__, __func__);
1046                 return;
1047         }
1048
1049         n = snprintf(p, space, "\n");
1050         p += n;
1051         space -= n;
1052
1053         /* Scan all the actual CSROWS (which is # of DIMMS * 2)
1054          * and calculate the information for each DIMM
1055          * Start with the highest csrow first, to display it first
1056          * and work toward the 0th csrow
1057          */
1058         max_csrows = pvt->maxdimmperch * 2;
1059         for (csrow = max_csrows - 1; csrow >= 0; csrow--) {
1060
1061                 /* on an odd csrow, first output a 'boundary' marker,
1062                  * then reset the message buffer  */
1063                 if (csrow & 0x1) {
1064                         n = snprintf(p, space, "---------------------------"
1065                                 "--------------------------------");
1066                         p += n;
1067                         space -= n;
1068                         debugf2("%s\n", mem_buffer);
1069                         p = mem_buffer;
1070                         space = PAGE_SIZE;
1071                 }
1072                 n = snprintf(p, space, "csrow %2d    ", csrow);
1073                 p += n;
1074                 space -= n;
1075
1076                 for (channel = 0; channel < pvt->maxch; channel++) {
1077                         dinfo = &pvt->dimm_info[csrow][channel];
1078                         handle_channel(pvt, csrow, channel, dinfo);
1079                         n = snprintf(p, space, "%4d MB   | ", dinfo->megabytes);
1080                         p += n;
1081                         space -= n;
1082                 }
1083                 n = snprintf(p, space, "\n");
1084                 p += n;
1085                 space -= n;
1086         }
1087
1088         /* Output the last bottom 'boundary' marker */
1089         n = snprintf(p, space, "---------------------------"
1090                 "--------------------------------\n");
1091         p += n;
1092         space -= n;
1093
1094         /* now output the 'channel' labels */
1095         n = snprintf(p, space, "            ");
1096         p += n;
1097         space -= n;
1098         for (channel = 0; channel < pvt->maxch; channel++) {
1099                 n = snprintf(p, space, "channel %d | ", channel);
1100                 p += n;
1101                 space -= n;
1102         }
1103         n = snprintf(p, space, "\n");
1104         p += n;
1105         space -= n;
1106
1107         /* output the last message and free buffer */
1108         debugf2("%s\n", mem_buffer);
1109         kfree(mem_buffer);
1110 }
1111
1112 /*
1113  *      i5000_get_mc_regs       read in the necessary registers and
1114  *                              cache locally
1115  *
1116  *                      Fills in the private data members
1117  */
1118 static void i5000_get_mc_regs(struct mem_ctl_info *mci)
1119 {
1120         struct i5000_pvt *pvt;
1121         u32 actual_tolm;
1122         u16 limit;
1123         int slot_row;
1124         int maxch;
1125         int maxdimmperch;
1126         int way0, way1;
1127
1128         pvt = mci->pvt_info;
1129
1130         pci_read_config_dword(pvt->system_address, AMBASE,
1131                         (u32 *) & pvt->ambase);
1132         pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32),
1133                         ((u32 *) & pvt->ambase) + sizeof(u32));
1134
1135         maxdimmperch = pvt->maxdimmperch;
1136         maxch = pvt->maxch;
1137
1138         debugf2("AMBASE= 0x%lx  MAXCH= %d  MAX-DIMM-Per-CH= %d\n",
1139                 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);
1140
1141         /* Get the Branch Map regs */
1142         pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);
1143         pvt->tolm >>= 12;
1144         debugf2("\nTOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm,
1145                 pvt->tolm);
1146
1147         actual_tolm = pvt->tolm << 28;
1148         debugf2("Actual TOLM byte addr=%u (0x%x)\n", actual_tolm, actual_tolm);
1149
1150         pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0);
1151         pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1);
1152         pci_read_config_word(pvt->branchmap_werrors, MIR2, &pvt->mir2);
1153
1154         /* Get the MIR[0-2] regs */
1155         limit = (pvt->mir0 >> 4) & 0x0FFF;
1156         way0 = pvt->mir0 & 0x1;
1157         way1 = pvt->mir0 & 0x2;
1158         debugf2("MIR0: limit= 0x%x  WAY1= %u  WAY0= %x\n", limit, way1, way0);
1159         limit = (pvt->mir1 >> 4) & 0x0FFF;
1160         way0 = pvt->mir1 & 0x1;
1161         way1 = pvt->mir1 & 0x2;
1162         debugf2("MIR1: limit= 0x%x  WAY1= %u  WAY0= %x\n", limit, way1, way0);
1163         limit = (pvt->mir2 >> 4) & 0x0FFF;
1164         way0 = pvt->mir2 & 0x1;
1165         way1 = pvt->mir2 & 0x2;
1166         debugf2("MIR2: limit= 0x%x  WAY1= %u  WAY0= %x\n", limit, way1, way0);
1167
1168         /* Get the MTR[0-3] regs */
1169         for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1170                 int where = MTR0 + (slot_row * sizeof(u32));
1171
1172                 pci_read_config_word(pvt->branch_0, where,
1173                                 &pvt->b0_mtr[slot_row]);
1174
1175                 debugf2("MTR%d where=0x%x B0 value=0x%x\n", slot_row, where,
1176                         pvt->b0_mtr[slot_row]);
1177
1178                 if (pvt->maxch >= CHANNELS_PER_BRANCH) {
1179                         pci_read_config_word(pvt->branch_1, where,
1180                                         &pvt->b1_mtr[slot_row]);
1181                         debugf2("MTR%d where=0x%x B1 value=0x%x\n", slot_row,
1182                                 where, pvt->b1_mtr[slot_row]);
1183                 } else {
1184                         pvt->b1_mtr[slot_row] = 0;
1185                 }
1186         }
1187
1188         /* Read and dump branch 0's MTRs */
1189         debugf2("\nMemory Technology Registers:\n");
1190         debugf2("   Branch 0:\n");
1191         for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1192                 decode_mtr(slot_row, pvt->b0_mtr[slot_row]);
1193         }
1194         pci_read_config_word(pvt->branch_0, AMB_PRESENT_0,
1195                         &pvt->b0_ambpresent0);
1196         debugf2("\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);
1197         pci_read_config_word(pvt->branch_0, AMB_PRESENT_1,
1198                         &pvt->b0_ambpresent1);
1199         debugf2("\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
1200
1201         /* Only if we have 2 branchs (4 channels) */
1202         if (pvt->maxch < CHANNELS_PER_BRANCH) {
1203                 pvt->b1_ambpresent0 = 0;
1204                 pvt->b1_ambpresent1 = 0;
1205         } else {
1206                 /* Read and dump  branch 1's MTRs */
1207                 debugf2("   Branch 1:\n");
1208                 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1209                         decode_mtr(slot_row, pvt->b1_mtr[slot_row]);
1210                 }
1211                 pci_read_config_word(pvt->branch_1, AMB_PRESENT_0,
1212                                 &pvt->b1_ambpresent0);
1213                 debugf2("\t\tAMB-Branch 1-present0 0x%x:\n",
1214                         pvt->b1_ambpresent0);
1215                 pci_read_config_word(pvt->branch_1, AMB_PRESENT_1,
1216                                 &pvt->b1_ambpresent1);
1217                 debugf2("\t\tAMB-Branch 1-present1 0x%x:\n",
1218                         pvt->b1_ambpresent1);
1219         }
1220
1221         /* Go and determine the size of each DIMM and place in an
1222          * orderly matrix */
1223         calculate_dimm_size(pvt);
1224 }
1225
1226 /*
1227  *      i5000_init_csrows       Initialize the 'csrows' table within
1228  *                              the mci control structure with the
1229  *                              addressing of memory.
1230  *
1231  *      return:
1232  *              0       success
1233  *              1       no actual memory found on this MC
1234  */
1235 static int i5000_init_csrows(struct mem_ctl_info *mci)
1236 {
1237         struct i5000_pvt *pvt;
1238         struct csrow_info *p_csrow;
1239         int empty, channel_count;
1240         int max_csrows;
1241         int mtr, mtr1;
1242         int csrow_megs;
1243         int channel;
1244         int csrow;
1245
1246         pvt = mci->pvt_info;
1247
1248         channel_count = pvt->maxch;
1249         max_csrows = pvt->maxdimmperch * 2;
1250
1251         empty = 1;              /* Assume NO memory */
1252
1253         for (csrow = 0; csrow < max_csrows; csrow++) {
1254                 p_csrow = &mci->csrows[csrow];
1255
1256                 p_csrow->csrow_idx = csrow;
1257
1258                 /* use branch 0 for the basis */
1259                 mtr = pvt->b0_mtr[csrow >> 1];
1260                 mtr1 = pvt->b1_mtr[csrow >> 1];
1261
1262                 /* if no DIMMS on this row, continue */
1263                 if (!MTR_DIMMS_PRESENT(mtr) && !MTR_DIMMS_PRESENT(mtr1))
1264                         continue;
1265
1266                 /* FAKE OUT VALUES, FIXME */
1267                 p_csrow->first_page = 0 + csrow * 20;
1268                 p_csrow->last_page = 9 + csrow * 20;
1269                 p_csrow->page_mask = 0xFFF;
1270
1271                 p_csrow->grain = 8;
1272
1273                 csrow_megs = 0;
1274                 for (channel = 0; channel < pvt->maxch; channel++) {
1275                         csrow_megs += pvt->dimm_info[csrow][channel].megabytes;
1276                 }
1277
1278                 p_csrow->nr_pages = csrow_megs << 8;
1279
1280                 /* Assume DDR2 for now */
1281                 p_csrow->mtype = MEM_FB_DDR2;
1282
1283                 /* ask what device type on this row */
1284                 if (MTR_DRAM_WIDTH(mtr))
1285                         p_csrow->dtype = DEV_X8;
1286                 else
1287                         p_csrow->dtype = DEV_X4;
1288
1289                 p_csrow->edac_mode = EDAC_S8ECD8ED;
1290
1291                 empty = 0;
1292         }
1293
1294         return empty;
1295 }
1296
1297 /*
1298  *      i5000_enable_error_reporting
1299  *                      Turn on the memory reporting features of the hardware
1300  */
1301 static void i5000_enable_error_reporting(struct mem_ctl_info *mci)
1302 {
1303         struct i5000_pvt *pvt;
1304         u32 fbd_error_mask;
1305
1306         pvt = mci->pvt_info;
1307
1308         /* Read the FBD Error Mask Register */
1309         pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD,
1310                         &fbd_error_mask);
1311
1312         /* Enable with a '0' */
1313         fbd_error_mask &= ~(ENABLE_EMASK_ALL);
1314
1315         pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD,
1316                         fbd_error_mask);
1317 }
1318
1319 /*
1320  * i5000_get_dimm_and_channel_counts(pdev, &num_csrows, &num_channels)
1321  *
1322  *      ask the device how many channels are present and how many CSROWS
1323  *       as well
1324  */
1325 static void i5000_get_dimm_and_channel_counts(struct pci_dev *pdev,
1326                                         int *num_dimms_per_channel,
1327                                         int *num_channels)
1328 {
1329         u8 value;
1330
1331         /* Need to retrieve just how many channels and dimms per channel are
1332          * supported on this memory controller
1333          */
1334         pci_read_config_byte(pdev, MAXDIMMPERCH, &value);
1335         *num_dimms_per_channel = (int)value *2;
1336
1337         pci_read_config_byte(pdev, MAXCH, &value);
1338         *num_channels = (int)value;
1339 }
1340
1341 /*
1342  *      i5000_probe1    Probe for ONE instance of device to see if it is
1343  *                      present.
1344  *      return:
1345  *              0 for FOUND a device
1346  *              < 0 for error code
1347  */
1348 static int i5000_probe1(struct pci_dev *pdev, int dev_idx)
1349 {
1350         struct mem_ctl_info *mci;
1351         struct i5000_pvt *pvt;
1352         int num_channels;
1353         int num_dimms_per_channel;
1354         int num_csrows;
1355
1356         debugf0("MC: " __FILE__ ": %s(), pdev bus %u dev=0x%x fn=0x%x\n",
1357                 __func__,
1358                 pdev->bus->number,
1359                 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1360
1361         /* We only are looking for func 0 of the set */
1362         if (PCI_FUNC(pdev->devfn) != 0)
1363                 return -ENODEV;
1364
1365         /* Ask the devices for the number of CSROWS and CHANNELS so
1366          * that we can calculate the memory resources, etc
1367          *
1368          * The Chipset will report what it can handle which will be greater
1369          * or equal to what the motherboard manufacturer will implement.
1370          *
1371          * As we don't have a motherboard identification routine to determine
1372          * actual number of slots/dimms per channel, we thus utilize the
1373          * resource as specified by the chipset. Thus, we might have
1374          * have more DIMMs per channel than actually on the mobo, but this
1375          * allows the driver to support upto the chipset max, without
1376          * some fancy mobo determination.
1377          */
1378         i5000_get_dimm_and_channel_counts(pdev, &num_dimms_per_channel,
1379                                         &num_channels);
1380         num_csrows = num_dimms_per_channel * 2;
1381
1382         debugf0("MC: %s(): Number of - Channels= %d  DIMMS= %d  CSROWS= %d\n",
1383                 __func__, num_channels, num_dimms_per_channel, num_csrows);
1384
1385         /* allocate a new MC control structure */
1386         mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0);
1387
1388         if (mci == NULL)
1389                 return -ENOMEM;
1390
1391         kobject_get(&mci->edac_mci_kobj);
1392         debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
1393
1394         mci->dev = &pdev->dev;  /* record ptr  to the generic device */
1395
1396         pvt = mci->pvt_info;
1397         pvt->system_address = pdev;     /* Record this device in our private */
1398         pvt->maxch = num_channels;
1399         pvt->maxdimmperch = num_dimms_per_channel;
1400
1401         /* 'get' the pci devices we want to reserve for our use */
1402         if (i5000_get_devices(mci, dev_idx))
1403                 goto fail0;
1404
1405         /* Time to get serious */
1406         i5000_get_mc_regs(mci); /* retrieve the hardware registers */
1407
1408         mci->mc_idx = 0;
1409         mci->mtype_cap = MEM_FLAG_FB_DDR2;
1410         mci->edac_ctl_cap = EDAC_FLAG_NONE;
1411         mci->edac_cap = EDAC_FLAG_NONE;
1412         mci->mod_name = "i5000_edac.c";
1413         mci->mod_ver = I5000_REVISION;
1414         mci->ctl_name = i5000_devs[dev_idx].ctl_name;
1415         mci->dev_name = pci_name(pdev);
1416         mci->ctl_page_to_phys = NULL;
1417
1418         /* Set the function pointer to an actual operation function */
1419         mci->edac_check = i5000_check_error;
1420
1421         /* initialize the MC control structure 'csrows' table
1422          * with the mapping and control information */
1423         if (i5000_init_csrows(mci)) {
1424                 debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n"
1425                         "    because i5000_init_csrows() returned nonzero "
1426                         "value\n");
1427                 mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */
1428         } else {
1429                 debugf1("MC: Enable error reporting now\n");
1430                 i5000_enable_error_reporting(mci);
1431         }
1432
1433         /* add this new MC control structure to EDAC's list of MCs */
1434         if (edac_mc_add_mc(mci)) {
1435                 debugf0("MC: " __FILE__
1436                         ": %s(): failed edac_mc_add_mc()\n", __func__);
1437                 /* FIXME: perhaps some code should go here that disables error
1438                  * reporting if we just enabled it
1439                  */
1440                 goto fail1;
1441         }
1442
1443         i5000_clear_error(mci);
1444
1445         /* allocating generic PCI control info */
1446         i5000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
1447         if (!i5000_pci) {
1448                 printk(KERN_WARNING
1449                         "%s(): Unable to create PCI control\n",
1450                         __func__);
1451                 printk(KERN_WARNING
1452                         "%s(): PCI error report via EDAC not setup\n",
1453                         __func__);
1454         }
1455
1456         return 0;
1457
1458         /* Error exit unwinding stack */
1459 fail1:
1460
1461         i5000_put_devices(mci);
1462
1463 fail0:
1464         kobject_put(&mci->edac_mci_kobj);
1465         edac_mc_free(mci);
1466         return -ENODEV;
1467 }
1468
1469 /*
1470  *      i5000_init_one  constructor for one instance of device
1471  *
1472  *      returns:
1473  *              negative on error
1474  *              count (>= 0)
1475  */
1476 static int __devinit i5000_init_one(struct pci_dev *pdev,
1477                                 const struct pci_device_id *id)
1478 {
1479         int rc;
1480
1481         debugf0("MC: " __FILE__ ": %s()\n", __func__);
1482
1483         /* wake up device */
1484         rc = pci_enable_device(pdev);
1485         if (rc == -EIO)
1486                 return rc;
1487
1488         /* now probe and enable the device */
1489         return i5000_probe1(pdev, id->driver_data);
1490 }
1491
1492 /*
1493  *      i5000_remove_one        destructor for one instance of device
1494  *
1495  */
1496 static void __devexit i5000_remove_one(struct pci_dev *pdev)
1497 {
1498         struct mem_ctl_info *mci;
1499
1500         debugf0(__FILE__ ": %s()\n", __func__);
1501
1502         if (i5000_pci)
1503                 edac_pci_release_generic_ctl(i5000_pci);
1504
1505         if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
1506                 return;
1507
1508         /* retrieve references to resources, and free those resources */
1509         i5000_put_devices(mci);
1510         kobject_put(&mci->edac_mci_kobj);
1511         edac_mc_free(mci);
1512 }
1513
1514 /*
1515  *      pci_device_id   table for which devices we are looking for
1516  *
1517  *      The "E500P" device is the first device supported.
1518  */
1519 static const struct pci_device_id i5000_pci_tbl[] __devinitdata = {
1520         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000_DEV16),
1521          .driver_data = I5000P},
1522
1523         {0,}                    /* 0 terminated list. */
1524 };
1525
1526 MODULE_DEVICE_TABLE(pci, i5000_pci_tbl);
1527
1528 /*
1529  *      i5000_driver    pci_driver structure for this module
1530  *
1531  */
1532 static struct pci_driver i5000_driver = {
1533         .name = KBUILD_BASENAME,
1534         .probe = i5000_init_one,
1535         .remove = __devexit_p(i5000_remove_one),
1536         .id_table = i5000_pci_tbl,
1537 };
1538
1539 /*
1540  *      i5000_init              Module entry function
1541  *                      Try to initialize this module for its devices
1542  */
1543 static int __init i5000_init(void)
1544 {
1545         int pci_rc;
1546
1547         debugf2("MC: " __FILE__ ": %s()\n", __func__);
1548
1549        /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1550        opstate_init();
1551
1552         pci_rc = pci_register_driver(&i5000_driver);
1553
1554         return (pci_rc < 0) ? pci_rc : 0;
1555 }
1556
1557 /*
1558  *      i5000_exit()    Module exit function
1559  *                      Unregister the driver
1560  */
1561 static void __exit i5000_exit(void)
1562 {
1563         debugf2("MC: " __FILE__ ": %s()\n", __func__);
1564         pci_unregister_driver(&i5000_driver);
1565 }
1566
1567 module_init(i5000_init);
1568 module_exit(i5000_exit);
1569
1570 MODULE_LICENSE("GPL");
1571 MODULE_AUTHOR
1572     ("Linux Networx (http://lnxi.com) Doug Thompson <norsk5@xmission.com>");
1573 MODULE_DESCRIPTION("MC Driver for Intel I5000 memory controllers - "
1574                 I5000_REVISION);
1575
1576 module_param(edac_op_state, int, 0444);
1577 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
1578 module_param(misc_messages, int, 0444);
1579 MODULE_PARM_DESC(misc_messages, "Log miscellaneous non fatal messages");
1580