EDAC, AMD: decode data cache MCEs
[linux-2.6.git] / drivers / edac / edac_mce_amd.c
1 #include <linux/module.h>
2 #include "edac_mce_amd.h"
3
4 static bool report_gart_errors;
5 static void (*nb_bus_decoder)(int node_id, struct err_regs *regs);
6
7 void amd_report_gart_errors(bool v)
8 {
9         report_gart_errors = v;
10 }
11 EXPORT_SYMBOL_GPL(amd_report_gart_errors);
12
13 void amd_register_ecc_decoder(void (*f)(int, struct err_regs *))
14 {
15         nb_bus_decoder = f;
16 }
17 EXPORT_SYMBOL_GPL(amd_register_ecc_decoder);
18
19 void amd_unregister_ecc_decoder(void (*f)(int, struct err_regs *))
20 {
21         if (nb_bus_decoder) {
22                 WARN_ON(nb_bus_decoder != f);
23
24                 nb_bus_decoder = NULL;
25         }
26 }
27 EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);
28
29 /*
30  * string representation for the different MCA reported error types, see F3x48
31  * or MSR0000_0411.
32  */
33 const char *tt_msgs[] = {        /* transaction type */
34         "instruction",
35         "data",
36         "generic",
37         "reserved"
38 };
39 EXPORT_SYMBOL_GPL(tt_msgs);
40
41 const char *ll_msgs[] = {       /* cache level */
42         "L0",
43         "L1",
44         "L2",
45         "L3/generic"
46 };
47 EXPORT_SYMBOL_GPL(ll_msgs);
48
49 const char *rrrr_msgs[] = {
50         "generic",
51         "generic read",
52         "generic write",
53         "data read",
54         "data write",
55         "inst fetch",
56         "prefetch",
57         "evict",
58         "snoop",
59         "reserved RRRR= 9",
60         "reserved RRRR= 10",
61         "reserved RRRR= 11",
62         "reserved RRRR= 12",
63         "reserved RRRR= 13",
64         "reserved RRRR= 14",
65         "reserved RRRR= 15"
66 };
67 EXPORT_SYMBOL_GPL(rrrr_msgs);
68
69 const char *pp_msgs[] = {       /* participating processor */
70         "local node originated (SRC)",
71         "local node responded to request (RES)",
72         "local node observed as 3rd party (OBS)",
73         "generic"
74 };
75 EXPORT_SYMBOL_GPL(pp_msgs);
76
77 const char *to_msgs[] = {
78         "no timeout",
79         "timed out"
80 };
81 EXPORT_SYMBOL_GPL(to_msgs);
82
83 const char *ii_msgs[] = {       /* memory or i/o */
84         "mem access",
85         "reserved",
86         "i/o access",
87         "generic"
88 };
89 EXPORT_SYMBOL_GPL(ii_msgs);
90
91 /*
92  * Map the 4 or 5 (family-specific) bits of Extended Error code to the
93  * string table.
94  */
95 const char *ext_msgs[] = {
96         "K8 ECC error",                                 /* 0_0000b */
97         "CRC error on link",                            /* 0_0001b */
98         "Sync error packets on link",                   /* 0_0010b */
99         "Master Abort during link operation",           /* 0_0011b */
100         "Target Abort during link operation",           /* 0_0100b */
101         "Invalid GART PTE entry during table walk",     /* 0_0101b */
102         "Unsupported atomic RMW command received",      /* 0_0110b */
103         "WDT error: NB transaction timeout",            /* 0_0111b */
104         "ECC/ChipKill ECC error",                       /* 0_1000b */
105         "SVM DEV Error",                                /* 0_1001b */
106         "Link Data error",                              /* 0_1010b */
107         "Link/L3/Probe Filter Protocol error",          /* 0_1011b */
108         "NB Internal Arrays Parity error",              /* 0_1100b */
109         "DRAM Address/Control Parity error",            /* 0_1101b */
110         "Link Transmission error",                      /* 0_1110b */
111         "GART/DEV Table Walk Data error"                /* 0_1111b */
112         "Res 0x100 error",                              /* 1_0000b */
113         "Res 0x101 error",                              /* 1_0001b */
114         "Res 0x102 error",                              /* 1_0010b */
115         "Res 0x103 error",                              /* 1_0011b */
116         "Res 0x104 error",                              /* 1_0100b */
117         "Res 0x105 error",                              /* 1_0101b */
118         "Res 0x106 error",                              /* 1_0110b */
119         "Res 0x107 error",                              /* 1_0111b */
120         "Res 0x108 error",                              /* 1_1000b */
121         "Res 0x109 error",                              /* 1_1001b */
122         "Res 0x10A error",                              /* 1_1010b */
123         "Res 0x10B error",                              /* 1_1011b */
124         "ECC error in L3 Cache Data",                   /* 1_1100b */
125         "L3 Cache Tag error",                           /* 1_1101b */
126         "L3 Cache LRU Parity error",                    /* 1_1110b */
127         "Probe Filter error"                            /* 1_1111b */
128 };
129 EXPORT_SYMBOL_GPL(ext_msgs);
130
131 static void amd_decode_dc_mce(u64 mc0_status)
132 {
133         u32 ec  = mc0_status & 0xffff;
134         u32 xec = (mc0_status >> 16) & 0xf;
135
136         pr_emerg(" Data Cache Error");
137
138         if (xec == 1 && TLB_ERROR(ec))
139                 pr_cont(": %s TLB multimatch.\n", LL_MSG(ec));
140         else if (xec == 0) {
141                 if (mc0_status & (1ULL << 40))
142                         pr_cont(" during Data Scrub.\n");
143                 else if (TLB_ERROR(ec))
144                         pr_cont(": %s TLB parity error.\n", LL_MSG(ec));
145                 else if (MEM_ERROR(ec)) {
146                         u8 ll   = ec & 0x3;
147                         u8 tt   = (ec >> 2) & 0x3;
148                         u8 rrrr = (ec >> 4) & 0xf;
149
150                         /* see F10h BKDG (31116), Table 92. */
151                         if (ll == 0x1) {
152                                 if (tt != 0x1)
153                                         goto wrong_dc_mce;
154
155                                 pr_cont(": Data/Tag %s error.\n", RRRR_MSG(ec));
156
157                         } else if (ll == 0x2 && rrrr == 0x3)
158                                 pr_cont(" during L1 linefill from L2.\n");
159                         else
160                                 goto wrong_dc_mce;
161                 } else if (BUS_ERROR(ec) && boot_cpu_data.x86 == 0xf)
162                         pr_cont(" during system linefill.\n");
163                 else
164                         goto wrong_dc_mce;
165         } else
166                 goto wrong_dc_mce;
167
168         return;
169
170 wrong_dc_mce:
171         pr_warning("Corrupted DC MCE info?\n");
172 }
173
174 void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors)
175 {
176         u32 ec  = ERROR_CODE(regs->nbsl);
177         u32 xec = EXT_ERROR_CODE(regs->nbsl);
178
179         if (!handle_errors)
180                 return;
181
182         pr_emerg(" Northbridge Error, node %d", node_id);
183
184         /*
185          * F10h, revD can disable ErrCpu[3:0] so check that first and also the
186          * value encoding has changed so interpret those differently
187          */
188         if ((boot_cpu_data.x86 == 0x10) &&
189             (boot_cpu_data.x86_model > 8)) {
190                 if (regs->nbsh & K8_NBSH_ERR_CPU_VAL)
191                         pr_cont(", core: %u\n", (u8)(regs->nbsh & 0xf));
192         } else {
193                 pr_cont(", core: %d\n", ilog2((regs->nbsh & 0xf)));
194         }
195
196
197         pr_emerg("%s.\n", EXT_ERR_MSG(xec));
198
199         if (BUS_ERROR(ec) && nb_bus_decoder)
200                 nb_bus_decoder(node_id, regs);
201 }
202 EXPORT_SYMBOL_GPL(amd_decode_nb_mce);
203
204 static inline void amd_decode_err_code(unsigned int ec)
205 {
206         if (TLB_ERROR(ec)) {
207                 /*
208                  * GART errors are intended to help graphics driver developers
209                  * to detect bad GART PTEs. It is recommended by AMD to disable
210                  * GART table walk error reporting by default[1] (currently
211                  * being disabled in mce_cpu_quirks()) and according to the
212                  * comment in mce_cpu_quirks(), such GART errors can be
213                  * incorrectly triggered. We may see these errors anyway and
214                  * unless requested by the user, they won't be reported.
215                  *
216                  * [1] section 13.10.1 on BIOS and Kernel Developers Guide for
217                  *     AMD NPT family 0Fh processors
218                  */
219                 if (!report_gart_errors)
220                         return;
221
222                 pr_emerg(" Transaction: %s, Cache Level %s\n",
223                          TT_MSG(ec), LL_MSG(ec));
224         } else if (MEM_ERROR(ec)) {
225                 pr_emerg(" Transaction: %s, Type: %s, Cache Level: %s",
226                          RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec));
227         } else if (BUS_ERROR(ec)) {
228                 pr_emerg(" Transaction type: %s(%s), %s, Cache Level: %s, "
229                          "Participating Processor: %s\n",
230                           RRRR_MSG(ec), II_MSG(ec), TO_MSG(ec), LL_MSG(ec),
231                           PP_MSG(ec));
232         } else
233                 pr_warning("Huh? Unknown MCE error 0x%x\n", ec);
234 }
235
236 void decode_mce(struct mce *m)
237 {
238         struct err_regs regs;
239         int node, ecc;
240
241         pr_emerg("MC%d_STATUS: ", m->bank);
242
243         pr_cont("%sorrected error, report: %s, MiscV: %svalid, "
244                  "CPU context corrupt: %s",
245                  ((m->status & MCI_STATUS_UC) ? "Unc"  : "C"),
246                  ((m->status & MCI_STATUS_EN) ? "yes"  : "no"),
247                  ((m->status & MCI_STATUS_MISCV) ? ""  : "in"),
248                  ((m->status & MCI_STATUS_PCC) ? "yes" : "no"));
249
250         /* do the two bits[14:13] together */
251         ecc = m->status & (3ULL << 45);
252         if (ecc)
253                 pr_cont(", %sECC Error", ((ecc == 2) ? "C" : "U"));
254
255         pr_cont("\n");
256
257         switch (m->bank) {
258         case 0:
259                 amd_decode_dc_mce(m->status);
260                 break;
261
262         case 4:
263                 regs.nbsl  = (u32) m->status;
264                 regs.nbsh  = (u32)(m->status >> 32);
265                 regs.nbeal = (u32) m->addr;
266                 regs.nbeah = (u32)(m->addr >> 32);
267                 node       = per_cpu(cpu_llc_id, m->extcpu);
268
269                 amd_decode_nb_mce(node, &regs, 1);
270                 break;
271
272         default:
273                 break;
274         }
275
276         amd_decode_err_code(m->status & 0xffff);
277 }