[PATCH] EDAC: mc numbers refactor 1-of-2
[linux-2.6.git] / drivers / edac / e7xxx_edac.c
1 /*
2  * Intel e7xxx Memory Controller kernel module
3  * (C) 2003 Linux Networx (http://lnxi.com)
4  * This file may be distributed under the terms of the
5  * GNU General Public License.
6  *
7  * See "enum e7xxx_chips" below for supported chipsets
8  *
9  * Written by Thayne Harbaugh
10  * Based on work by Dan Hollis <goemon at anime dot net> and others.
11  *      http://www.anime.net/~goemon/linux-ecc/
12  *
13  * Contributors:
14  *      Eric Biederman (Linux Networx)
15  *      Tom Zimmerman (Linux Networx)
16  *      Jim Garlick (Lawrence Livermore National Labs)
17  *      Dave Peterson (Lawrence Livermore National Labs)
18  *      That One Guy (Some other place)
19  *      Wang Zhenyu (intel.com)
20  *
21  * $Id: edac_e7xxx.c,v 1.5.2.9 2005/10/05 00:43:44 dsp_llnl Exp $
22  *
23  */
24
25 #include <linux/config.h>
26 #include <linux/module.h>
27 #include <linux/init.h>
28 #include <linux/pci.h>
29 #include <linux/pci_ids.h>
30 #include <linux/slab.h>
31 #include "edac_mc.h"
32
33 #define E7XXX_REVISION " Ver: 2.0.0 " __DATE__
34
35 #define e7xxx_printk(level, fmt, arg...) \
36         edac_printk(level, "e7xxx", fmt, ##arg)
37
38 #define e7xxx_mc_printk(mci, level, fmt, arg...) \
39         edac_mc_chipset_printk(mci, level, "e7xxx", fmt, ##arg)
40
41 #ifndef PCI_DEVICE_ID_INTEL_7205_0
42 #define PCI_DEVICE_ID_INTEL_7205_0      0x255d
43 #endif                          /* PCI_DEVICE_ID_INTEL_7205_0 */
44
45 #ifndef PCI_DEVICE_ID_INTEL_7205_1_ERR
46 #define PCI_DEVICE_ID_INTEL_7205_1_ERR  0x2551
47 #endif                          /* PCI_DEVICE_ID_INTEL_7205_1_ERR */
48
49 #ifndef PCI_DEVICE_ID_INTEL_7500_0
50 #define PCI_DEVICE_ID_INTEL_7500_0      0x2540
51 #endif                          /* PCI_DEVICE_ID_INTEL_7500_0 */
52
53 #ifndef PCI_DEVICE_ID_INTEL_7500_1_ERR
54 #define PCI_DEVICE_ID_INTEL_7500_1_ERR  0x2541
55 #endif                          /* PCI_DEVICE_ID_INTEL_7500_1_ERR */
56
57 #ifndef PCI_DEVICE_ID_INTEL_7501_0
58 #define PCI_DEVICE_ID_INTEL_7501_0      0x254c
59 #endif                          /* PCI_DEVICE_ID_INTEL_7501_0 */
60
61 #ifndef PCI_DEVICE_ID_INTEL_7501_1_ERR
62 #define PCI_DEVICE_ID_INTEL_7501_1_ERR  0x2541
63 #endif                          /* PCI_DEVICE_ID_INTEL_7501_1_ERR */
64
65 #ifndef PCI_DEVICE_ID_INTEL_7505_0
66 #define PCI_DEVICE_ID_INTEL_7505_0      0x2550
67 #endif                          /* PCI_DEVICE_ID_INTEL_7505_0 */
68
69 #ifndef PCI_DEVICE_ID_INTEL_7505_1_ERR
70 #define PCI_DEVICE_ID_INTEL_7505_1_ERR  0x2551
71 #endif                          /* PCI_DEVICE_ID_INTEL_7505_1_ERR */
72
73 #define E7XXX_NR_CSROWS         8       /* number of csrows */
74 #define E7XXX_NR_DIMMS          8       /* FIXME - is this correct? */
75
76 /* E7XXX register addresses - device 0 function 0 */
77 #define E7XXX_DRB               0x60    /* DRAM row boundary register (8b) */
78 #define E7XXX_DRA               0x70    /* DRAM row attribute register (8b) */
79                                         /*
80                                          * 31   Device width row 7 0=x8 1=x4
81                                          * 27   Device width row 6
82                                          * 23   Device width row 5
83                                          * 19   Device width row 4
84                                          * 15   Device width row 3
85                                          * 11   Device width row 2
86                                          *  7   Device width row 1
87                                          *  3   Device width row 0
88                                          */
89 #define E7XXX_DRC               0x7C    /* DRAM controller mode reg (32b) */
90                                         /*
91                                          * 22    Number channels 0=1,1=2
92                                          * 19:18 DRB Granularity 32/64MB
93                                          */
94 #define E7XXX_TOLM              0xC4    /* DRAM top of low memory reg (16b) */
95 #define E7XXX_REMAPBASE         0xC6    /* DRAM remap base address reg (16b) */
96 #define E7XXX_REMAPLIMIT        0xC8    /* DRAM remap limit address reg (16b) */
97
98 /* E7XXX register addresses - device 0 function 1 */
99 #define E7XXX_DRAM_FERR         0x80    /* DRAM first error register (8b) */
100 #define E7XXX_DRAM_NERR         0x82    /* DRAM next error register (8b) */
101 #define E7XXX_DRAM_CELOG_ADD    0xA0    /* DRAM first correctable memory */
102                                         /*     error address register (32b) */
103                                         /*
104                                          * 31:28 Reserved
105                                          * 27:6  CE address (4k block 33:12)
106                                          *  5:0  Reserved
107                                          */
108 #define E7XXX_DRAM_UELOG_ADD    0xB0    /* DRAM first uncorrectable memory */
109                                         /*     error address register (32b) */
110                                         /*
111                                          * 31:28 Reserved
112                                          * 27:6  CE address (4k block 33:12)
113                                          *  5:0  Reserved
114                                          */
115 #define E7XXX_DRAM_CELOG_SYNDROME 0xD0  /* DRAM first correctable memory */
116                                         /*     error syndrome register (16b) */
117
118 enum e7xxx_chips {
119         E7500 = 0,
120         E7501,
121         E7505,
122         E7205,
123 };
124
125 struct e7xxx_pvt {
126         struct pci_dev *bridge_ck;
127         u32 tolm;
128         u32 remapbase;
129         u32 remaplimit;
130         const struct e7xxx_dev_info *dev_info;
131 };
132
133 struct e7xxx_dev_info {
134         u16 err_dev;
135         const char *ctl_name;
136 };
137
138 struct e7xxx_error_info {
139         u8 dram_ferr;
140         u8 dram_nerr;
141         u32 dram_celog_add;
142         u16 dram_celog_syndrome;
143         u32 dram_uelog_add;
144 };
145
146 static const struct e7xxx_dev_info e7xxx_devs[] = {
147         [E7500] = {
148                 .err_dev = PCI_DEVICE_ID_INTEL_7500_1_ERR,
149                 .ctl_name = "E7500"
150         },
151         [E7501] = {
152                 .err_dev = PCI_DEVICE_ID_INTEL_7501_1_ERR,
153                 .ctl_name = "E7501"
154         },
155         [E7505] = {
156                 .err_dev = PCI_DEVICE_ID_INTEL_7505_1_ERR,
157                 .ctl_name = "E7505"
158         },
159         [E7205] = {
160                 .err_dev = PCI_DEVICE_ID_INTEL_7205_1_ERR,
161                 .ctl_name = "E7205"
162         },
163 };
164
165 /* FIXME - is this valid for both SECDED and S4ECD4ED? */
166 static inline int e7xxx_find_channel(u16 syndrome)
167 {
168         debugf3("%s()\n", __func__);
169
170         if ((syndrome & 0xff00) == 0)
171                 return 0;
172
173         if ((syndrome & 0x00ff) == 0)
174                 return 1;
175
176         if ((syndrome & 0xf000) == 0 || (syndrome & 0x0f00) == 0)
177                 return 0;
178
179         return 1;
180 }
181
182 static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
183                 unsigned long page)
184 {
185         u32 remap;
186         struct e7xxx_pvt *pvt = (struct e7xxx_pvt *) mci->pvt_info;
187
188         debugf3("%s()\n", __func__);
189
190         if ((page < pvt->tolm) ||
191                         ((page >= 0x100000) && (page < pvt->remapbase)))
192                 return page;
193
194         remap = (page - pvt->tolm) + pvt->remapbase;
195
196         if (remap < pvt->remaplimit)
197                 return remap;
198
199         e7xxx_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
200         return pvt->tolm - 1;
201 }
202
203 static void process_ce(struct mem_ctl_info *mci,
204                 struct e7xxx_error_info *info)
205 {
206         u32 error_1b, page;
207         u16 syndrome;
208         int row;
209         int channel;
210
211         debugf3("%s()\n", __func__);
212         /* read the error address */
213         error_1b = info->dram_celog_add;
214         /* FIXME - should use PAGE_SHIFT */
215         page = error_1b >> 6;  /* convert the address to 4k page */
216         /* read the syndrome */
217         syndrome = info->dram_celog_syndrome;
218         /* FIXME - check for -1 */
219         row = edac_mc_find_csrow_by_page(mci, page);
220         /* convert syndrome to channel */
221         channel = e7xxx_find_channel(syndrome);
222         edac_mc_handle_ce(mci, page, 0, syndrome, row, channel, "e7xxx CE");
223 }
224
225 static void process_ce_no_info(struct mem_ctl_info *mci)
226 {
227         debugf3("%s()\n", __func__);
228         edac_mc_handle_ce_no_info(mci, "e7xxx CE log register overflow");
229 }
230
231 static void process_ue(struct mem_ctl_info *mci,
232                 struct e7xxx_error_info *info)
233 {
234         u32 error_2b, block_page;
235         int row;
236
237         debugf3("%s()\n", __func__);
238         /* read the error address */
239         error_2b = info->dram_uelog_add;
240         /* FIXME - should use PAGE_SHIFT */
241         block_page = error_2b >> 6;  /* convert to 4k address */
242         row = edac_mc_find_csrow_by_page(mci, block_page);
243         edac_mc_handle_ue(mci, block_page, 0, row, "e7xxx UE");
244 }
245
246 static void process_ue_no_info(struct mem_ctl_info *mci)
247 {
248         debugf3("%s()\n", __func__);
249         edac_mc_handle_ue_no_info(mci, "e7xxx UE log register overflow");
250 }
251
252 static void e7xxx_get_error_info (struct mem_ctl_info *mci,
253                 struct e7xxx_error_info *info)
254 {
255         struct e7xxx_pvt *pvt;
256
257         pvt = (struct e7xxx_pvt *) mci->pvt_info;
258         pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR,
259                         &info->dram_ferr);
260         pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR,
261                         &info->dram_nerr);
262
263         if ((info->dram_ferr & 1) || (info->dram_nerr & 1)) {
264                 pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_CELOG_ADD,
265                                 &info->dram_celog_add);
266                 pci_read_config_word(pvt->bridge_ck,
267                                 E7XXX_DRAM_CELOG_SYNDROME,
268                                 &info->dram_celog_syndrome);
269         }
270
271         if ((info->dram_ferr & 2) || (info->dram_nerr & 2))
272                 pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_UELOG_ADD,
273                                 &info->dram_uelog_add);
274
275         if (info->dram_ferr & 3)
276                 pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03, 0x03);
277
278         if (info->dram_nerr & 3)
279                 pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03, 0x03);
280 }
281
282 static int e7xxx_process_error_info (struct mem_ctl_info *mci,
283                 struct e7xxx_error_info *info, int handle_errors)
284 {
285         int error_found;
286
287         error_found = 0;
288
289         /* decode and report errors */
290         if (info->dram_ferr & 1) {      /* check first error correctable */
291                 error_found = 1;
292
293                 if (handle_errors)
294                         process_ce(mci, info);
295         }
296
297         if (info->dram_ferr & 2) {      /* check first error uncorrectable */
298                 error_found = 1;
299
300                 if (handle_errors)
301                         process_ue(mci, info);
302         }
303
304         if (info->dram_nerr & 1) {      /* check next error correctable */
305                 error_found = 1;
306
307                 if (handle_errors) {
308                         if (info->dram_ferr & 1)
309                                 process_ce_no_info(mci);
310                         else
311                                 process_ce(mci, info);
312                 }
313         }
314
315         if (info->dram_nerr & 2) {      /* check next error uncorrectable */
316                 error_found = 1;
317
318                 if (handle_errors) {
319                         if (info->dram_ferr & 2)
320                                 process_ue_no_info(mci);
321                         else
322                                 process_ue(mci, info);
323                 }
324         }
325
326         return error_found;
327 }
328
329 static void e7xxx_check(struct mem_ctl_info *mci)
330 {
331         struct e7xxx_error_info info;
332
333         debugf3("%s()\n", __func__);
334         e7xxx_get_error_info(mci, &info);
335         e7xxx_process_error_info(mci, &info, 1);
336 }
337
338 static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
339 {
340         int rc = -ENODEV;
341         int index;
342         u16 pci_data;
343         struct mem_ctl_info *mci = NULL;
344         struct e7xxx_pvt *pvt = NULL;
345         u32 drc;
346         int drc_chan = 1;       /* Number of channels 0=1chan,1=2chan */
347         int drc_drbg = 1;       /* DRB granularity 0=32mb,1=64mb */
348         int drc_ddim;           /* DRAM Data Integrity Mode 0=none,2=edac */
349         u32 dra;
350         unsigned long last_cumul_size;
351         struct e7xxx_error_info discard;
352
353         debugf0("%s(): mci\n", __func__);
354
355         /* need to find out the number of channels */
356         pci_read_config_dword(pdev, E7XXX_DRC, &drc);
357
358         /* only e7501 can be single channel */
359         if (dev_idx == E7501) {
360                 drc_chan = ((drc >> 22) & 0x1);
361                 drc_drbg = (drc >> 18) & 0x3;
362         }
363
364         drc_ddim = (drc >> 20) & 0x3;
365         mci = edac_mc_alloc(sizeof(*pvt), E7XXX_NR_CSROWS, drc_chan + 1);
366
367         if (mci == NULL) {
368                 rc = -ENOMEM;
369                 goto fail;
370         }
371
372         debugf3("%s(): init mci\n", __func__);
373         mci->mtype_cap = MEM_FLAG_RDDR;
374         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED |
375                         EDAC_FLAG_S4ECD4ED;
376         /* FIXME - what if different memory types are in different csrows? */
377         mci->mod_name = EDAC_MOD_STR;
378         mci->mod_ver = E7XXX_REVISION;
379         mci->dev = &pdev->dev;
380
381         debugf3("%s(): init pvt\n", __func__);
382         pvt = (struct e7xxx_pvt *) mci->pvt_info;
383         pvt->dev_info = &e7xxx_devs[dev_idx];
384         pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
385                                         pvt->dev_info->err_dev,
386                                         pvt->bridge_ck);
387
388         if (!pvt->bridge_ck) {
389                 e7xxx_printk(KERN_ERR, "error reporting device not found:"
390                         "vendor %x device 0x%x (broken BIOS?)\n",
391                         PCI_VENDOR_ID_INTEL, e7xxx_devs[dev_idx].err_dev);
392                 goto fail;
393         }
394
395         debugf3("%s(): more mci init\n", __func__);
396         mci->ctl_name = pvt->dev_info->ctl_name;
397         mci->edac_check = e7xxx_check;
398         mci->ctl_page_to_phys = ctl_page_to_phys;
399
400         /* find out the device types */
401         pci_read_config_dword(pdev, E7XXX_DRA, &dra);
402
403         /*
404          * The dram row boundary (DRB) reg values are boundary address
405          * for each DRAM row with a granularity of 32 or 64MB (single/dual
406          * channel operation).  DRB regs are cumulative; therefore DRB7 will
407          * contain the total memory contained in all eight rows.
408          */
409         for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
410                 u8 value;
411                 u32 cumul_size;
412                 /* mem_dev 0=x8, 1=x4 */
413                 int mem_dev = (dra >> (index * 4 + 3)) & 0x1;
414                 struct csrow_info *csrow = &mci->csrows[index];
415
416                 pci_read_config_byte(pdev, E7XXX_DRB + index, &value);
417                 /* convert a 64 or 32 MiB DRB to a page size. */
418                 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
419                 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
420                         cumul_size);
421
422                 if (cumul_size == last_cumul_size)
423                         continue;  /* not populated */
424
425                 csrow->first_page = last_cumul_size;
426                 csrow->last_page = cumul_size - 1;
427                 csrow->nr_pages = cumul_size - last_cumul_size;
428                 last_cumul_size = cumul_size;
429                 csrow->grain = 1 << 12;  /* 4KiB - resolution of CELOG */
430                 csrow->mtype = MEM_RDDR;  /* only one type supported */
431                 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
432
433                 /*
434                  * if single channel or x8 devices then SECDED
435                  * if dual channel and x4 then S4ECD4ED
436                  */
437                 if (drc_ddim) {
438                         if (drc_chan && mem_dev) {
439                                 csrow->edac_mode = EDAC_S4ECD4ED;
440                                 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
441                         } else {
442                                 csrow->edac_mode = EDAC_SECDED;
443                                 mci->edac_cap |= EDAC_FLAG_SECDED;
444                         }
445                 } else
446                         csrow->edac_mode = EDAC_NONE;
447         }
448
449         mci->edac_cap |= EDAC_FLAG_NONE;
450
451         debugf3("%s(): tolm, remapbase, remaplimit\n", __func__);
452         /* load the top of low memory, remap base, and remap limit vars */
453         pci_read_config_word(pdev, E7XXX_TOLM, &pci_data);
454         pvt->tolm = ((u32) pci_data) << 4;
455         pci_read_config_word(pdev, E7XXX_REMAPBASE, &pci_data);
456         pvt->remapbase = ((u32) pci_data) << 14;
457         pci_read_config_word(pdev, E7XXX_REMAPLIMIT, &pci_data);
458         pvt->remaplimit = ((u32) pci_data) << 14;
459         e7xxx_printk(KERN_INFO,
460                 "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
461                 pvt->remapbase, pvt->remaplimit);
462
463         /* clear any pending errors, or initial state bits */
464         e7xxx_get_error_info(mci, &discard);
465
466         /* Here we assume that we will never see multiple instances of this
467          * type of memory controller.  The ID is therefore hardcoded to 0.
468          */
469         if (edac_mc_add_mc(mci,0)) {
470                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
471                 goto fail;
472         }
473
474         /* get this far and it's successful */
475         debugf3("%s(): success\n", __func__);
476         return 0;
477
478 fail:
479         if (mci != NULL) {
480                 if(pvt != NULL && pvt->bridge_ck)
481                         pci_dev_put(pvt->bridge_ck);
482                 edac_mc_free(mci);
483         }
484
485         return rc;
486 }
487
488 /* returns count (>= 0), or negative on error */
489 static int __devinit e7xxx_init_one(struct pci_dev *pdev,
490                 const struct pci_device_id *ent)
491 {
492         debugf0("%s()\n", __func__);
493
494         /* wake up and enable device */
495         return pci_enable_device(pdev) ?
496                 -EIO : e7xxx_probe1(pdev, ent->driver_data);
497 }
498
499 static void __devexit e7xxx_remove_one(struct pci_dev *pdev)
500 {
501         struct mem_ctl_info *mci;
502         struct e7xxx_pvt *pvt;
503
504         debugf0("%s()\n", __func__);
505
506         if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
507                 return;
508
509         pvt = (struct e7xxx_pvt *) mci->pvt_info;
510         pci_dev_put(pvt->bridge_ck);
511         edac_mc_free(mci);
512 }
513
514 static const struct pci_device_id e7xxx_pci_tbl[] __devinitdata = {
515         {
516                 PCI_VEND_DEV(INTEL, 7205_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
517                 E7205
518         },
519         {
520                 PCI_VEND_DEV(INTEL, 7500_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
521                 E7500
522         },
523         {
524                 PCI_VEND_DEV(INTEL, 7501_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
525                 E7501
526         },
527         {
528                 PCI_VEND_DEV(INTEL, 7505_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
529                 E7505
530         },
531         {
532                 0,
533         }       /* 0 terminated list. */
534 };
535
536 MODULE_DEVICE_TABLE(pci, e7xxx_pci_tbl);
537
538 static struct pci_driver e7xxx_driver = {
539         .name = EDAC_MOD_STR,
540         .probe = e7xxx_init_one,
541         .remove = __devexit_p(e7xxx_remove_one),
542         .id_table = e7xxx_pci_tbl,
543 };
544
545 static int __init e7xxx_init(void)
546 {
547         return pci_register_driver(&e7xxx_driver);
548 }
549
550 static void __exit e7xxx_exit(void)
551 {
552         pci_unregister_driver(&e7xxx_driver);
553 }
554
555 module_init(e7xxx_init);
556 module_exit(e7xxx_exit);
557
558 MODULE_LICENSE("GPL");
559 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh et al\n"
560         "Based on.work by Dan Hollis et al");
561 MODULE_DESCRIPTION("MC support for Intel e7xxx memory controllers");