DMAENGINE: ste_dma40: interrupts only on dst
[linux-2.6.git] / drivers / dma / ste_dma40_ll.c
1 /*
2  * driver/dma/ste_dma40_ll.c
3  *
4  * Copyright (C) ST-Ericsson 2007-2010
5  * License terms: GNU General Public License (GPL) version 2
6  * Author: Per Friden <per.friden@stericsson.com>
7  * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
8  */
9
10 #include <linux/kernel.h>
11 #include <plat/ste_dma40.h>
12
13 #include "ste_dma40_ll.h"
14
15 /* Sets up proper LCSP1 and LCSP3 register for a logical channel */
16 void d40_log_cfg(struct stedma40_chan_cfg *cfg,
17                  u32 *lcsp1, u32 *lcsp3)
18 {
19         u32 l3 = 0; /* dst */
20         u32 l1 = 0; /* src */
21
22         /* src is mem? -> increase address pos */
23         if (cfg->dir ==  STEDMA40_MEM_TO_PERIPH ||
24             cfg->dir ==  STEDMA40_MEM_TO_MEM)
25                 l1 |= 1 << D40_MEM_LCSP1_SCFG_INCR_POS;
26
27         /* dst is mem? -> increase address pos */
28         if (cfg->dir ==  STEDMA40_PERIPH_TO_MEM ||
29             cfg->dir ==  STEDMA40_MEM_TO_MEM)
30                 l3 |= 1 << D40_MEM_LCSP3_DCFG_INCR_POS;
31
32         /* src is hw? -> master port 1 */
33         if (cfg->dir ==  STEDMA40_PERIPH_TO_MEM ||
34             cfg->dir ==  STEDMA40_PERIPH_TO_PERIPH)
35                 l1 |= 1 << D40_MEM_LCSP1_SCFG_MST_POS;
36
37         /* dst is hw? -> master port 1 */
38         if (cfg->dir ==  STEDMA40_MEM_TO_PERIPH ||
39             cfg->dir ==  STEDMA40_PERIPH_TO_PERIPH)
40                 l3 |= 1 << D40_MEM_LCSP3_DCFG_MST_POS;
41
42         l3 |= 1 << D40_MEM_LCSP3_DCFG_TIM_POS;
43         l3 |= 1 << D40_MEM_LCSP3_DCFG_EIM_POS;
44         l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
45         l3 |= cfg->dst_info.data_width << D40_MEM_LCSP3_DCFG_ESIZE_POS;
46         l3 |= 1 << D40_MEM_LCSP3_DTCP_POS;
47
48         l1 |= 1 << D40_MEM_LCSP1_SCFG_EIM_POS;
49         l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
50         l1 |= cfg->src_info.data_width << D40_MEM_LCSP1_SCFG_ESIZE_POS;
51         l1 |= 1 << D40_MEM_LCSP1_STCP_POS;
52
53         *lcsp1 = l1;
54         *lcsp3 = l3;
55
56 }
57
58 /* Sets up SRC and DST CFG register for both logical and physical channels */
59 void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
60                  u32 *src_cfg, u32 *dst_cfg, bool is_log)
61 {
62         u32 src = 0;
63         u32 dst = 0;
64
65         if (!is_log) {
66                 /* Physical channel */
67                 if ((cfg->dir ==  STEDMA40_PERIPH_TO_MEM) ||
68                     (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
69                         /* Set master port to 1 */
70                         src |= 1 << D40_SREG_CFG_MST_POS;
71                         src |= D40_TYPE_TO_EVENT(cfg->src_dev_type);
72
73                         if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
74                                 src |= 1 << D40_SREG_CFG_PHY_TM_POS;
75                         else
76                                 src |= 3 << D40_SREG_CFG_PHY_TM_POS;
77                 }
78                 if ((cfg->dir ==  STEDMA40_MEM_TO_PERIPH) ||
79                     (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
80                         /* Set master port to 1 */
81                         dst |= 1 << D40_SREG_CFG_MST_POS;
82                         dst |= D40_TYPE_TO_EVENT(cfg->dst_dev_type);
83
84                         if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
85                                 dst |= 1 << D40_SREG_CFG_PHY_TM_POS;
86                         else
87                                 dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
88                 }
89                 /* Interrupt on end of transfer for destination */
90                 dst |= 1 << D40_SREG_CFG_TIM_POS;
91
92                 /* Generate interrupt on error */
93                 src |= 1 << D40_SREG_CFG_EIM_POS;
94                 dst |= 1 << D40_SREG_CFG_EIM_POS;
95
96                 /* PSIZE */
97                 if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
98                         src |= 1 << D40_SREG_CFG_PHY_PEN_POS;
99                         src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
100                 }
101                 if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
102                         dst |= 1 << D40_SREG_CFG_PHY_PEN_POS;
103                         dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
104                 }
105
106                 /* Element size */
107                 src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS;
108                 dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS;
109
110         } else {
111                 /* Logical channel */
112                 dst |= 1 << D40_SREG_CFG_LOG_GIM_POS;
113                 src |= 1 << D40_SREG_CFG_LOG_GIM_POS;
114         }
115
116         if (cfg->channel_type & STEDMA40_HIGH_PRIORITY_CHANNEL) {
117                 src |= 1 << D40_SREG_CFG_PRI_POS;
118                 dst |= 1 << D40_SREG_CFG_PRI_POS;
119         }
120
121         src |= cfg->src_info.endianess << D40_SREG_CFG_LBE_POS;
122         dst |= cfg->dst_info.endianess << D40_SREG_CFG_LBE_POS;
123
124         *src_cfg = src;
125         *dst_cfg = dst;
126 }
127
128 int d40_phy_fill_lli(struct d40_phy_lli *lli,
129                      dma_addr_t data,
130                      u32 data_size,
131                      int psize,
132                      dma_addr_t next_lli,
133                      u32 reg_cfg,
134                      bool term_int,
135                      u32 data_width,
136                      bool is_device)
137 {
138         int num_elems;
139
140         if (psize == STEDMA40_PSIZE_PHY_1)
141                 num_elems = 1;
142         else
143                 num_elems = 2 << psize;
144
145         /*
146          * Size is 16bit. data_width is 8, 16, 32 or 64 bit
147          * Block large than 64 KiB must be split.
148          */
149         if (data_size > (0xffff << data_width))
150                 return -EINVAL;
151
152         /* Must be aligned */
153         if (!IS_ALIGNED(data, 0x1 << data_width))
154                 return -EINVAL;
155
156         /* Transfer size can't be smaller than (num_elms * elem_size) */
157         if (data_size < num_elems * (0x1 << data_width))
158                 return -EINVAL;
159
160         /* The number of elements. IE now many chunks */
161         lli->reg_elt = (data_size >> data_width) << D40_SREG_ELEM_PHY_ECNT_POS;
162
163         /*
164          * Distance to next element sized entry.
165          * Usually the size of the element unless you want gaps.
166          */
167         if (!is_device)
168                 lli->reg_elt |= (0x1 << data_width) <<
169                         D40_SREG_ELEM_PHY_EIDX_POS;
170
171         /* Where the data is */
172         lli->reg_ptr = data;
173         lli->reg_cfg = reg_cfg;
174
175         /* If this scatter list entry is the last one, no next link */
176         if (next_lli == 0)
177                 lli->reg_lnk = 0x1 << D40_SREG_LNK_PHY_TCP_POS;
178         else
179                 lli->reg_lnk = next_lli;
180
181         /* Set/clear interrupt generation on this link item.*/
182         if (term_int)
183                 lli->reg_cfg |= 0x1 << D40_SREG_CFG_TIM_POS;
184         else
185                 lli->reg_cfg &= ~(0x1 << D40_SREG_CFG_TIM_POS);
186
187         /* Post link */
188         lli->reg_lnk |= 0 << D40_SREG_LNK_PHY_PRE_POS;
189
190         return 0;
191 }
192
193 int d40_phy_sg_to_lli(struct scatterlist *sg,
194                       int sg_len,
195                       dma_addr_t target,
196                       struct d40_phy_lli *lli,
197                       dma_addr_t lli_phys,
198                       u32 reg_cfg,
199                       u32 data_width,
200                       int psize,
201                       bool term_int)
202 {
203         int total_size = 0;
204         int i;
205         struct scatterlist *current_sg = sg;
206         dma_addr_t next_lli_phys;
207         dma_addr_t dst;
208         int err = 0;
209
210         for_each_sg(sg, current_sg, sg_len, i) {
211
212                 total_size += sg_dma_len(current_sg);
213
214                 /* If this scatter list entry is the last one, no next link */
215                 if (sg_len - 1 == i)
216                         next_lli_phys = 0;
217                 else
218                         next_lli_phys = ALIGN(lli_phys + (i + 1) *
219                                               sizeof(struct d40_phy_lli),
220                                               D40_LLI_ALIGN);
221
222                 if (target)
223                         dst = target;
224                 else
225                         dst = sg_phys(current_sg);
226
227                 err = d40_phy_fill_lli(&lli[i],
228                                        dst,
229                                        sg_dma_len(current_sg),
230                                        psize,
231                                        next_lli_phys,
232                                        reg_cfg,
233                                        !next_lli_phys,
234                                        data_width,
235                                        target == dst);
236                 if (err)
237                         goto err;
238         }
239
240         return total_size;
241  err:
242         return err;
243 }
244
245
246 void d40_phy_lli_write(void __iomem *virtbase,
247                        u32 phy_chan_num,
248                        struct d40_phy_lli *lli_dst,
249                        struct d40_phy_lli *lli_src)
250 {
251
252         writel(lli_src->reg_cfg, virtbase + D40_DREG_PCBASE +
253                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSCFG);
254         writel(lli_src->reg_elt, virtbase + D40_DREG_PCBASE +
255                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSELT);
256         writel(lli_src->reg_ptr, virtbase + D40_DREG_PCBASE +
257                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSPTR);
258         writel(lli_src->reg_lnk, virtbase + D40_DREG_PCBASE +
259                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSLNK);
260
261         writel(lli_dst->reg_cfg, virtbase + D40_DREG_PCBASE +
262                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDCFG);
263         writel(lli_dst->reg_elt, virtbase + D40_DREG_PCBASE +
264                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDELT);
265         writel(lli_dst->reg_ptr, virtbase + D40_DREG_PCBASE +
266                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDPTR);
267         writel(lli_dst->reg_lnk, virtbase + D40_DREG_PCBASE +
268                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDLNK);
269
270 }
271
272 /* DMA logical lli operations */
273
274 void d40_log_fill_lli(struct d40_log_lli *lli,
275                       dma_addr_t data, u32 data_size,
276                       u32 lli_next_off, u32 reg_cfg,
277                       u32 data_width,
278                       bool term_int, bool addr_inc)
279 {
280         lli->lcsp13 = reg_cfg;
281
282         /* The number of elements to transfer */
283         lli->lcsp02 = ((data_size >> data_width) <<
284                        D40_MEM_LCSP0_ECNT_POS) & D40_MEM_LCSP0_ECNT_MASK;
285         /* 16 LSBs address of the current element */
286         lli->lcsp02 |= data & D40_MEM_LCSP0_SPTR_MASK;
287         /* 16 MSBs address of the current element */
288         lli->lcsp13 |= data & D40_MEM_LCSP1_SPTR_MASK;
289
290         if (addr_inc)
291                 lli->lcsp13 |= D40_MEM_LCSP1_SCFG_INCR_MASK;
292
293         lli->lcsp13 |= D40_MEM_LCSP3_DTCP_MASK;
294         /* If this scatter list entry is the last one, no next link */
295         lli->lcsp13 |= (lli_next_off << D40_MEM_LCSP1_SLOS_POS) &
296                 D40_MEM_LCSP1_SLOS_MASK;
297
298         if (term_int)
299                 lli->lcsp13 |= D40_MEM_LCSP1_SCFG_TIM_MASK;
300         else
301                 lli->lcsp13 &= ~D40_MEM_LCSP1_SCFG_TIM_MASK;
302 }
303
304 int d40_log_sg_to_dev(struct d40_lcla_elem *lcla,
305                       struct scatterlist *sg,
306                       int sg_len,
307                       struct d40_log_lli_bidir *lli,
308                       struct d40_def_lcsp *lcsp,
309                       u32 src_data_width,
310                       u32 dst_data_width,
311                       enum dma_data_direction direction,
312                       bool term_int, dma_addr_t dev_addr, int max_len,
313                       int llis_per_log)
314 {
315         int total_size = 0;
316         struct scatterlist *current_sg = sg;
317         int i;
318         u32 next_lli_off_dst = 0;
319         u32 next_lli_off_src = 0;
320
321         for_each_sg(sg, current_sg, sg_len, i) {
322                 total_size += sg_dma_len(current_sg);
323
324                 /*
325                  * If this scatter list entry is the last one or
326                  * max length, terminate link.
327                  */
328                 if (sg_len - 1 == i || ((i+1) % max_len == 0)) {
329                         next_lli_off_src = 0;
330                         next_lli_off_dst = 0;
331                 } else {
332                         if (next_lli_off_dst == 0 &&
333                             next_lli_off_src == 0) {
334                                 /* The first lli will be at next_lli_off */
335                                 next_lli_off_dst = (lcla->dst_id *
336                                                     llis_per_log + 1);
337                                 next_lli_off_src = (lcla->src_id *
338                                                     llis_per_log + 1);
339                         } else {
340                                 next_lli_off_dst++;
341                                 next_lli_off_src++;
342                         }
343                 }
344
345                 if (direction == DMA_TO_DEVICE) {
346                         d40_log_fill_lli(&lli->src[i],
347                                          sg_phys(current_sg),
348                                          sg_dma_len(current_sg),
349                                          next_lli_off_src,
350                                          lcsp->lcsp1, src_data_width,
351                                          false,
352                                          true);
353                         d40_log_fill_lli(&lli->dst[i],
354                                          dev_addr,
355                                          sg_dma_len(current_sg),
356                                          next_lli_off_dst,
357                                          lcsp->lcsp3, dst_data_width,
358                                          /* No next == terminal interrupt */
359                                          term_int && !next_lli_off_dst,
360                                          false);
361                 } else {
362                         d40_log_fill_lli(&lli->dst[i],
363                                          sg_phys(current_sg),
364                                          sg_dma_len(current_sg),
365                                          next_lli_off_dst,
366                                          lcsp->lcsp3, dst_data_width,
367                                          /* No next == terminal interrupt */
368                                          term_int && !next_lli_off_dst,
369                                          true);
370                         d40_log_fill_lli(&lli->src[i],
371                                          dev_addr,
372                                          sg_dma_len(current_sg),
373                                          next_lli_off_src,
374                                          lcsp->lcsp1, src_data_width,
375                                          false,
376                                          false);
377                 }
378         }
379         return total_size;
380 }
381
382 int d40_log_sg_to_lli(int lcla_id,
383                       struct scatterlist *sg,
384                       int sg_len,
385                       struct d40_log_lli *lli_sg,
386                       u32 lcsp13, /* src or dst*/
387                       u32 data_width,
388                       bool term_int, int max_len, int llis_per_log)
389 {
390         int total_size = 0;
391         struct scatterlist *current_sg = sg;
392         int i;
393         u32 next_lli_off = 0;
394
395         for_each_sg(sg, current_sg, sg_len, i) {
396                 total_size += sg_dma_len(current_sg);
397
398                 /*
399                  * If this scatter list entry is the last one or
400                  * max length, terminate link.
401                  */
402                 if (sg_len - 1 == i || ((i+1) % max_len == 0))
403                         next_lli_off = 0;
404                 else {
405                         if (next_lli_off == 0)
406                                 /* The first lli will be at next_lli_off */
407                                 next_lli_off = lcla_id * llis_per_log + 1;
408                         else
409                                 next_lli_off++;
410                 }
411
412                 d40_log_fill_lli(&lli_sg[i],
413                                  sg_phys(current_sg),
414                                  sg_dma_len(current_sg),
415                                  next_lli_off,
416                                  lcsp13, data_width,
417                                  term_int && !next_lli_off,
418                                  true);
419         }
420         return total_size;
421 }
422
423 void d40_log_lli_write(struct d40_log_lli_full *lcpa,
424                        struct d40_log_lli *lcla_src,
425                        struct d40_log_lli *lcla_dst,
426                        struct d40_log_lli *lli_dst,
427                        struct d40_log_lli *lli_src,
428                        int llis_per_log)
429 {
430         u32 slos;
431         u32 dlos;
432         int i;
433
434         writel(lli_src->lcsp02, &lcpa->lcsp0);
435         writel(lli_src->lcsp13, &lcpa->lcsp1);
436         writel(lli_dst->lcsp02, &lcpa->lcsp2);
437         writel(lli_dst->lcsp13, &lcpa->lcsp3);
438
439         slos = lli_src->lcsp13 & D40_MEM_LCSP1_SLOS_MASK;
440         dlos = lli_dst->lcsp13 & D40_MEM_LCSP3_DLOS_MASK;
441
442         for (i = 0; (i < llis_per_log) && slos && dlos; i++) {
443                 writel(lli_src[i + 1].lcsp02, &lcla_src[i].lcsp02);
444                 writel(lli_src[i + 1].lcsp13, &lcla_src[i].lcsp13);
445                 writel(lli_dst[i + 1].lcsp02, &lcla_dst[i].lcsp02);
446                 writel(lli_dst[i + 1].lcsp13, &lcla_dst[i].lcsp13);
447
448                 slos = lli_src[i + 1].lcsp13 & D40_MEM_LCSP1_SLOS_MASK;
449                 dlos = lli_dst[i + 1].lcsp13 & D40_MEM_LCSP3_DLOS_MASK;
450         }
451 }