DMAENGINE: ste_dma40: fix bug related to callback handling
[linux-2.6.git] / drivers / dma / ste_dma40_ll.c
1 /*
2  * driver/dma/ste_dma40_ll.c
3  *
4  * Copyright (C) ST-Ericsson 2007-2010
5  * License terms: GNU General Public License (GPL) version 2
6  * Author: Per Friden <per.friden@stericsson.com>
7  * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
8  */
9
10 #include <linux/kernel.h>
11 #include <plat/ste_dma40.h>
12
13 #include "ste_dma40_ll.h"
14
15 /* Sets up proper LCSP1 and LCSP3 register for a logical channel */
16 void d40_log_cfg(struct stedma40_chan_cfg *cfg,
17                  u32 *lcsp1, u32 *lcsp3)
18 {
19         u32 l3 = 0; /* dst */
20         u32 l1 = 0; /* src */
21
22         /* src is mem? -> increase address pos */
23         if (cfg->dir ==  STEDMA40_MEM_TO_PERIPH ||
24             cfg->dir ==  STEDMA40_MEM_TO_MEM)
25                 l1 |= 1 << D40_MEM_LCSP1_SCFG_INCR_POS;
26
27         /* dst is mem? -> increase address pos */
28         if (cfg->dir ==  STEDMA40_PERIPH_TO_MEM ||
29             cfg->dir ==  STEDMA40_MEM_TO_MEM)
30                 l3 |= 1 << D40_MEM_LCSP3_DCFG_INCR_POS;
31
32         /* src is hw? -> master port 1 */
33         if (cfg->dir ==  STEDMA40_PERIPH_TO_MEM ||
34             cfg->dir ==  STEDMA40_PERIPH_TO_PERIPH)
35                 l1 |= 1 << D40_MEM_LCSP1_SCFG_MST_POS;
36
37         /* dst is hw? -> master port 1 */
38         if (cfg->dir ==  STEDMA40_MEM_TO_PERIPH ||
39             cfg->dir ==  STEDMA40_PERIPH_TO_PERIPH)
40                 l3 |= 1 << D40_MEM_LCSP3_DCFG_MST_POS;
41
42         l3 |= 1 << D40_MEM_LCSP3_DCFG_TIM_POS;
43         l3 |= 1 << D40_MEM_LCSP3_DCFG_EIM_POS;
44         l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
45         l3 |= cfg->dst_info.data_width << D40_MEM_LCSP3_DCFG_ESIZE_POS;
46         l3 |= 1 << D40_MEM_LCSP3_DTCP_POS;
47
48         l1 |= 1 << D40_MEM_LCSP1_SCFG_EIM_POS;
49         l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
50         l1 |= cfg->src_info.data_width << D40_MEM_LCSP1_SCFG_ESIZE_POS;
51         l1 |= 1 << D40_MEM_LCSP1_STCP_POS;
52
53         *lcsp1 = l1;
54         *lcsp3 = l3;
55
56 }
57
58 /* Sets up SRC and DST CFG register for both logical and physical channels */
59 void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
60                  u32 *src_cfg, u32 *dst_cfg, bool is_log)
61 {
62         u32 src = 0;
63         u32 dst = 0;
64
65         if (!is_log) {
66                 /* Physical channel */
67                 if ((cfg->dir ==  STEDMA40_PERIPH_TO_MEM) ||
68                     (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
69                         /* Set master port to 1 */
70                         src |= 1 << D40_SREG_CFG_MST_POS;
71                         src |= D40_TYPE_TO_EVENT(cfg->src_dev_type);
72
73                         if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
74                                 src |= 1 << D40_SREG_CFG_PHY_TM_POS;
75                         else
76                                 src |= 3 << D40_SREG_CFG_PHY_TM_POS;
77                 }
78                 if ((cfg->dir ==  STEDMA40_MEM_TO_PERIPH) ||
79                     (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
80                         /* Set master port to 1 */
81                         dst |= 1 << D40_SREG_CFG_MST_POS;
82                         dst |= D40_TYPE_TO_EVENT(cfg->dst_dev_type);
83
84                         if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
85                                 dst |= 1 << D40_SREG_CFG_PHY_TM_POS;
86                         else
87                                 dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
88                 }
89                 /* Interrupt on end of transfer for destination */
90                 dst |= 1 << D40_SREG_CFG_TIM_POS;
91
92                 /* Generate interrupt on error */
93                 src |= 1 << D40_SREG_CFG_EIM_POS;
94                 dst |= 1 << D40_SREG_CFG_EIM_POS;
95
96                 /* PSIZE */
97                 if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
98                         src |= 1 << D40_SREG_CFG_PHY_PEN_POS;
99                         src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
100                 }
101                 if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
102                         dst |= 1 << D40_SREG_CFG_PHY_PEN_POS;
103                         dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
104                 }
105
106                 /* Element size */
107                 src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS;
108                 dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS;
109
110         } else {
111                 /* Logical channel */
112                 dst |= 1 << D40_SREG_CFG_LOG_GIM_POS;
113                 src |= 1 << D40_SREG_CFG_LOG_GIM_POS;
114         }
115
116         if (cfg->channel_type & STEDMA40_HIGH_PRIORITY_CHANNEL) {
117                 src |= 1 << D40_SREG_CFG_PRI_POS;
118                 dst |= 1 << D40_SREG_CFG_PRI_POS;
119         }
120
121         src |= cfg->src_info.endianess << D40_SREG_CFG_LBE_POS;
122         dst |= cfg->dst_info.endianess << D40_SREG_CFG_LBE_POS;
123
124         *src_cfg = src;
125         *dst_cfg = dst;
126 }
127
128 int d40_phy_fill_lli(struct d40_phy_lli *lli,
129                      dma_addr_t data,
130                      u32 data_size,
131                      int psize,
132                      dma_addr_t next_lli,
133                      u32 reg_cfg,
134                      bool term_int,
135                      u32 data_width,
136                      bool is_device)
137 {
138         int num_elems;
139
140         if (psize == STEDMA40_PSIZE_PHY_1)
141                 num_elems = 1;
142         else
143                 num_elems = 2 << psize;
144
145         /*
146          * Size is 16bit. data_width is 8, 16, 32 or 64 bit
147          * Block large than 64 KiB must be split.
148          */
149         if (data_size > (0xffff << data_width))
150                 return -EINVAL;
151
152         /* Must be aligned */
153         if (!IS_ALIGNED(data, 0x1 << data_width))
154                 return -EINVAL;
155
156         /* Transfer size can't be smaller than (num_elms * elem_size) */
157         if (data_size < num_elems * (0x1 << data_width))
158                 return -EINVAL;
159
160         /* The number of elements. IE now many chunks */
161         lli->reg_elt = (data_size >> data_width) << D40_SREG_ELEM_PHY_ECNT_POS;
162
163         /*
164          * Distance to next element sized entry.
165          * Usually the size of the element unless you want gaps.
166          */
167         if (!is_device)
168                 lli->reg_elt |= (0x1 << data_width) <<
169                         D40_SREG_ELEM_PHY_EIDX_POS;
170
171         /* Where the data is */
172         lli->reg_ptr = data;
173         lli->reg_cfg = reg_cfg;
174
175         /* If this scatter list entry is the last one, no next link */
176         if (next_lli == 0)
177                 lli->reg_lnk = 0x1 << D40_SREG_LNK_PHY_TCP_POS;
178         else
179                 lli->reg_lnk = next_lli;
180
181         /* Set/clear interrupt generation on this link item.*/
182         if (term_int)
183                 lli->reg_cfg |= 0x1 << D40_SREG_CFG_TIM_POS;
184         else
185                 lli->reg_cfg &= ~(0x1 << D40_SREG_CFG_TIM_POS);
186
187         /* Post link */
188         lli->reg_lnk |= 0 << D40_SREG_LNK_PHY_PRE_POS;
189
190         return 0;
191 }
192
193 int d40_phy_sg_to_lli(struct scatterlist *sg,
194                       int sg_len,
195                       dma_addr_t target,
196                       struct d40_phy_lli *lli,
197                       dma_addr_t lli_phys,
198                       u32 reg_cfg,
199                       u32 data_width,
200                       int psize)
201 {
202         int total_size = 0;
203         int i;
204         struct scatterlist *current_sg = sg;
205         dma_addr_t next_lli_phys;
206         dma_addr_t dst;
207         int err = 0;
208
209         for_each_sg(sg, current_sg, sg_len, i) {
210
211                 total_size += sg_dma_len(current_sg);
212
213                 /* If this scatter list entry is the last one, no next link */
214                 if (sg_len - 1 == i)
215                         next_lli_phys = 0;
216                 else
217                         next_lli_phys = ALIGN(lli_phys + (i + 1) *
218                                               sizeof(struct d40_phy_lli),
219                                               D40_LLI_ALIGN);
220
221                 if (target)
222                         dst = target;
223                 else
224                         dst = sg_phys(current_sg);
225
226                 err = d40_phy_fill_lli(&lli[i],
227                                        dst,
228                                        sg_dma_len(current_sg),
229                                        psize,
230                                        next_lli_phys,
231                                        reg_cfg,
232                                        !next_lli_phys,
233                                        data_width,
234                                        target == dst);
235                 if (err)
236                         goto err;
237         }
238
239         return total_size;
240  err:
241         return err;
242 }
243
244
245 void d40_phy_lli_write(void __iomem *virtbase,
246                        u32 phy_chan_num,
247                        struct d40_phy_lli *lli_dst,
248                        struct d40_phy_lli *lli_src)
249 {
250
251         writel(lli_src->reg_cfg, virtbase + D40_DREG_PCBASE +
252                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSCFG);
253         writel(lli_src->reg_elt, virtbase + D40_DREG_PCBASE +
254                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSELT);
255         writel(lli_src->reg_ptr, virtbase + D40_DREG_PCBASE +
256                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSPTR);
257         writel(lli_src->reg_lnk, virtbase + D40_DREG_PCBASE +
258                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSLNK);
259
260         writel(lli_dst->reg_cfg, virtbase + D40_DREG_PCBASE +
261                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDCFG);
262         writel(lli_dst->reg_elt, virtbase + D40_DREG_PCBASE +
263                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDELT);
264         writel(lli_dst->reg_ptr, virtbase + D40_DREG_PCBASE +
265                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDPTR);
266         writel(lli_dst->reg_lnk, virtbase + D40_DREG_PCBASE +
267                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDLNK);
268
269 }
270
271 /* DMA logical lli operations */
272
273 void d40_log_fill_lli(struct d40_log_lli *lli,
274                       dma_addr_t data, u32 data_size,
275                       u32 lli_next_off, u32 reg_cfg,
276                       u32 data_width,
277                       bool term_int, bool addr_inc)
278 {
279         lli->lcsp13 = reg_cfg;
280
281         /* The number of elements to transfer */
282         lli->lcsp02 = ((data_size >> data_width) <<
283                        D40_MEM_LCSP0_ECNT_POS) & D40_MEM_LCSP0_ECNT_MASK;
284         /* 16 LSBs address of the current element */
285         lli->lcsp02 |= data & D40_MEM_LCSP0_SPTR_MASK;
286         /* 16 MSBs address of the current element */
287         lli->lcsp13 |= data & D40_MEM_LCSP1_SPTR_MASK;
288
289         if (addr_inc)
290                 lli->lcsp13 |= D40_MEM_LCSP1_SCFG_INCR_MASK;
291
292         lli->lcsp13 |= D40_MEM_LCSP3_DTCP_MASK;
293         /* If this scatter list entry is the last one, no next link */
294         lli->lcsp13 |= (lli_next_off << D40_MEM_LCSP1_SLOS_POS) &
295                 D40_MEM_LCSP1_SLOS_MASK;
296
297         if (term_int)
298                 lli->lcsp13 |= D40_MEM_LCSP1_SCFG_TIM_MASK;
299         else
300                 lli->lcsp13 &= ~D40_MEM_LCSP1_SCFG_TIM_MASK;
301 }
302
303 int d40_log_sg_to_dev(struct d40_lcla_elem *lcla,
304                       struct scatterlist *sg,
305                       int sg_len,
306                       struct d40_log_lli_bidir *lli,
307                       struct d40_def_lcsp *lcsp,
308                       u32 src_data_width,
309                       u32 dst_data_width,
310                       enum dma_data_direction direction,
311                       dma_addr_t dev_addr, int max_len,
312                       int llis_per_log)
313 {
314         int total_size = 0;
315         struct scatterlist *current_sg = sg;
316         int i;
317         u32 next_lli_off_dst = 0;
318         u32 next_lli_off_src = 0;
319
320         for_each_sg(sg, current_sg, sg_len, i) {
321                 total_size += sg_dma_len(current_sg);
322
323                 /*
324                  * If this scatter list entry is the last one or
325                  * max length, terminate link.
326                  */
327                 if (sg_len - 1 == i || ((i+1) % max_len == 0)) {
328                         next_lli_off_src = 0;
329                         next_lli_off_dst = 0;
330                 } else {
331                         if (next_lli_off_dst == 0 &&
332                             next_lli_off_src == 0) {
333                                 /* The first lli will be at next_lli_off */
334                                 next_lli_off_dst = (lcla->dst_id *
335                                                     llis_per_log + 1);
336                                 next_lli_off_src = (lcla->src_id *
337                                                     llis_per_log + 1);
338                         } else {
339                                 next_lli_off_dst++;
340                                 next_lli_off_src++;
341                         }
342                 }
343
344                 if (direction == DMA_TO_DEVICE) {
345                         d40_log_fill_lli(&lli->src[i],
346                                          sg_phys(current_sg),
347                                          sg_dma_len(current_sg),
348                                          next_lli_off_src,
349                                          lcsp->lcsp1, src_data_width,
350                                          false,
351                                          true);
352                         d40_log_fill_lli(&lli->dst[i],
353                                          dev_addr,
354                                          sg_dma_len(current_sg),
355                                          next_lli_off_dst,
356                                          lcsp->lcsp3, dst_data_width,
357                                          /* No next == terminal interrupt */
358                                          !next_lli_off_dst,
359                                          false);
360                 } else {
361                         d40_log_fill_lli(&lli->dst[i],
362                                          sg_phys(current_sg),
363                                          sg_dma_len(current_sg),
364                                          next_lli_off_dst,
365                                          lcsp->lcsp3, dst_data_width,
366                                          /* No next == terminal interrupt */
367                                          !next_lli_off_dst,
368                                          true);
369                         d40_log_fill_lli(&lli->src[i],
370                                          dev_addr,
371                                          sg_dma_len(current_sg),
372                                          next_lli_off_src,
373                                          lcsp->lcsp1, src_data_width,
374                                          false,
375                                          false);
376                 }
377         }
378         return total_size;
379 }
380
381 int d40_log_sg_to_lli(int lcla_id,
382                       struct scatterlist *sg,
383                       int sg_len,
384                       struct d40_log_lli *lli_sg,
385                       u32 lcsp13, /* src or dst*/
386                       u32 data_width,
387                       int max_len, int llis_per_log)
388 {
389         int total_size = 0;
390         struct scatterlist *current_sg = sg;
391         int i;
392         u32 next_lli_off = 0;
393
394         for_each_sg(sg, current_sg, sg_len, i) {
395                 total_size += sg_dma_len(current_sg);
396
397                 /*
398                  * If this scatter list entry is the last one or
399                  * max length, terminate link.
400                  */
401                 if (sg_len - 1 == i || ((i+1) % max_len == 0))
402                         next_lli_off = 0;
403                 else {
404                         if (next_lli_off == 0)
405                                 /* The first lli will be at next_lli_off */
406                                 next_lli_off = lcla_id * llis_per_log + 1;
407                         else
408                                 next_lli_off++;
409                 }
410
411                 d40_log_fill_lli(&lli_sg[i],
412                                  sg_phys(current_sg),
413                                  sg_dma_len(current_sg),
414                                  next_lli_off,
415                                  lcsp13, data_width,
416                                  !next_lli_off,
417                                  true);
418         }
419         return total_size;
420 }
421
422 int d40_log_lli_write(struct d40_log_lli_full *lcpa,
423                        struct d40_log_lli *lcla_src,
424                        struct d40_log_lli *lcla_dst,
425                        struct d40_log_lli *lli_dst,
426                        struct d40_log_lli *lli_src,
427                        int llis_per_log)
428 {
429         u32 slos;
430         u32 dlos;
431         int i;
432
433         writel(lli_src->lcsp02, &lcpa->lcsp0);
434         writel(lli_src->lcsp13, &lcpa->lcsp1);
435         writel(lli_dst->lcsp02, &lcpa->lcsp2);
436         writel(lli_dst->lcsp13, &lcpa->lcsp3);
437
438         slos = lli_src->lcsp13 & D40_MEM_LCSP1_SLOS_MASK;
439         dlos = lli_dst->lcsp13 & D40_MEM_LCSP3_DLOS_MASK;
440
441         for (i = 0; (i < llis_per_log) && slos && dlos; i++) {
442                 writel(lli_src[i + 1].lcsp02, &lcla_src[i].lcsp02);
443                 writel(lli_src[i + 1].lcsp13, &lcla_src[i].lcsp13);
444                 writel(lli_dst[i + 1].lcsp02, &lcla_dst[i].lcsp02);
445                 writel(lli_dst[i + 1].lcsp13, &lcla_dst[i].lcsp13);
446
447                 slos = lli_src[i + 1].lcsp13 & D40_MEM_LCSP1_SLOS_MASK;
448                 dlos = lli_dst[i + 1].lcsp13 & D40_MEM_LCSP3_DLOS_MASK;
449         }
450
451         return i;
452
453 }