DMAENGINE: ste_dma40: rewrote LCLA entries allocation code
[linux-2.6.git] / drivers / dma / ste_dma40_ll.c
1 /*
2  * Copyright (C) ST-Ericsson SA 2007-2010
3  * Author: Per Friden <per.friden@stericsson.com> for ST-Ericsson
4  * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
5  * License terms: GNU General Public License (GPL) version 2
6  */
7
8 #include <linux/kernel.h>
9 #include <plat/ste_dma40.h>
10
11 #include "ste_dma40_ll.h"
12
13 /* Sets up proper LCSP1 and LCSP3 register for a logical channel */
14 void d40_log_cfg(struct stedma40_chan_cfg *cfg,
15                  u32 *lcsp1, u32 *lcsp3)
16 {
17         u32 l3 = 0; /* dst */
18         u32 l1 = 0; /* src */
19
20         /* src is mem? -> increase address pos */
21         if (cfg->dir ==  STEDMA40_MEM_TO_PERIPH ||
22             cfg->dir ==  STEDMA40_MEM_TO_MEM)
23                 l1 |= 1 << D40_MEM_LCSP1_SCFG_INCR_POS;
24
25         /* dst is mem? -> increase address pos */
26         if (cfg->dir ==  STEDMA40_PERIPH_TO_MEM ||
27             cfg->dir ==  STEDMA40_MEM_TO_MEM)
28                 l3 |= 1 << D40_MEM_LCSP3_DCFG_INCR_POS;
29
30         /* src is hw? -> master port 1 */
31         if (cfg->dir ==  STEDMA40_PERIPH_TO_MEM ||
32             cfg->dir ==  STEDMA40_PERIPH_TO_PERIPH)
33                 l1 |= 1 << D40_MEM_LCSP1_SCFG_MST_POS;
34
35         /* dst is hw? -> master port 1 */
36         if (cfg->dir ==  STEDMA40_MEM_TO_PERIPH ||
37             cfg->dir ==  STEDMA40_PERIPH_TO_PERIPH)
38                 l3 |= 1 << D40_MEM_LCSP3_DCFG_MST_POS;
39
40         l3 |= 1 << D40_MEM_LCSP3_DCFG_EIM_POS;
41         l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
42         l3 |= cfg->dst_info.data_width << D40_MEM_LCSP3_DCFG_ESIZE_POS;
43
44         l1 |= 1 << D40_MEM_LCSP1_SCFG_EIM_POS;
45         l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
46         l1 |= cfg->src_info.data_width << D40_MEM_LCSP1_SCFG_ESIZE_POS;
47
48         *lcsp1 = l1;
49         *lcsp3 = l3;
50
51 }
52
53 /* Sets up SRC and DST CFG register for both logical and physical channels */
54 void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
55                  u32 *src_cfg, u32 *dst_cfg, bool is_log)
56 {
57         u32 src = 0;
58         u32 dst = 0;
59
60         if (!is_log) {
61                 /* Physical channel */
62                 if ((cfg->dir ==  STEDMA40_PERIPH_TO_MEM) ||
63                     (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
64                         /* Set master port to 1 */
65                         src |= 1 << D40_SREG_CFG_MST_POS;
66                         src |= D40_TYPE_TO_EVENT(cfg->src_dev_type);
67
68                         if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
69                                 src |= 1 << D40_SREG_CFG_PHY_TM_POS;
70                         else
71                                 src |= 3 << D40_SREG_CFG_PHY_TM_POS;
72                 }
73                 if ((cfg->dir ==  STEDMA40_MEM_TO_PERIPH) ||
74                     (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
75                         /* Set master port to 1 */
76                         dst |= 1 << D40_SREG_CFG_MST_POS;
77                         dst |= D40_TYPE_TO_EVENT(cfg->dst_dev_type);
78
79                         if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
80                                 dst |= 1 << D40_SREG_CFG_PHY_TM_POS;
81                         else
82                                 dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
83                 }
84                 /* Interrupt on end of transfer for destination */
85                 dst |= 1 << D40_SREG_CFG_TIM_POS;
86
87                 /* Generate interrupt on error */
88                 src |= 1 << D40_SREG_CFG_EIM_POS;
89                 dst |= 1 << D40_SREG_CFG_EIM_POS;
90
91                 /* PSIZE */
92                 if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
93                         src |= 1 << D40_SREG_CFG_PHY_PEN_POS;
94                         src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
95                 }
96                 if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
97                         dst |= 1 << D40_SREG_CFG_PHY_PEN_POS;
98                         dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
99                 }
100
101                 /* Element size */
102                 src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS;
103                 dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS;
104
105         } else {
106                 /* Logical channel */
107                 dst |= 1 << D40_SREG_CFG_LOG_GIM_POS;
108                 src |= 1 << D40_SREG_CFG_LOG_GIM_POS;
109         }
110
111         if (cfg->channel_type & STEDMA40_HIGH_PRIORITY_CHANNEL) {
112                 src |= 1 << D40_SREG_CFG_PRI_POS;
113                 dst |= 1 << D40_SREG_CFG_PRI_POS;
114         }
115
116         src |= cfg->src_info.endianess << D40_SREG_CFG_LBE_POS;
117         dst |= cfg->dst_info.endianess << D40_SREG_CFG_LBE_POS;
118
119         *src_cfg = src;
120         *dst_cfg = dst;
121 }
122
123 int d40_phy_fill_lli(struct d40_phy_lli *lli,
124                      dma_addr_t data,
125                      u32 data_size,
126                      int psize,
127                      dma_addr_t next_lli,
128                      u32 reg_cfg,
129                      bool term_int,
130                      u32 data_width,
131                      bool is_device)
132 {
133         int num_elems;
134
135         if (psize == STEDMA40_PSIZE_PHY_1)
136                 num_elems = 1;
137         else
138                 num_elems = 2 << psize;
139
140         /*
141          * Size is 16bit. data_width is 8, 16, 32 or 64 bit
142          * Block large than 64 KiB must be split.
143          */
144         if (data_size > (0xffff << data_width))
145                 return -EINVAL;
146
147         /* Must be aligned */
148         if (!IS_ALIGNED(data, 0x1 << data_width))
149                 return -EINVAL;
150
151         /* Transfer size can't be smaller than (num_elms * elem_size) */
152         if (data_size < num_elems * (0x1 << data_width))
153                 return -EINVAL;
154
155         /* The number of elements. IE now many chunks */
156         lli->reg_elt = (data_size >> data_width) << D40_SREG_ELEM_PHY_ECNT_POS;
157
158         /*
159          * Distance to next element sized entry.
160          * Usually the size of the element unless you want gaps.
161          */
162         if (!is_device)
163                 lli->reg_elt |= (0x1 << data_width) <<
164                         D40_SREG_ELEM_PHY_EIDX_POS;
165
166         /* Where the data is */
167         lli->reg_ptr = data;
168         lli->reg_cfg = reg_cfg;
169
170         /* If this scatter list entry is the last one, no next link */
171         if (next_lli == 0)
172                 lli->reg_lnk = 0x1 << D40_SREG_LNK_PHY_TCP_POS;
173         else
174                 lli->reg_lnk = next_lli;
175
176         /* Set/clear interrupt generation on this link item.*/
177         if (term_int)
178                 lli->reg_cfg |= 0x1 << D40_SREG_CFG_TIM_POS;
179         else
180                 lli->reg_cfg &= ~(0x1 << D40_SREG_CFG_TIM_POS);
181
182         /* Post link */
183         lli->reg_lnk |= 0 << D40_SREG_LNK_PHY_PRE_POS;
184
185         return 0;
186 }
187
188 int d40_phy_sg_to_lli(struct scatterlist *sg,
189                       int sg_len,
190                       dma_addr_t target,
191                       struct d40_phy_lli *lli,
192                       dma_addr_t lli_phys,
193                       u32 reg_cfg,
194                       u32 data_width,
195                       int psize)
196 {
197         int total_size = 0;
198         int i;
199         struct scatterlist *current_sg = sg;
200         dma_addr_t next_lli_phys;
201         dma_addr_t dst;
202         int err = 0;
203
204         for_each_sg(sg, current_sg, sg_len, i) {
205
206                 total_size += sg_dma_len(current_sg);
207
208                 /* If this scatter list entry is the last one, no next link */
209                 if (sg_len - 1 == i)
210                         next_lli_phys = 0;
211                 else
212                         next_lli_phys = ALIGN(lli_phys + (i + 1) *
213                                               sizeof(struct d40_phy_lli),
214                                               D40_LLI_ALIGN);
215
216                 if (target)
217                         dst = target;
218                 else
219                         dst = sg_phys(current_sg);
220
221                 err = d40_phy_fill_lli(&lli[i],
222                                        dst,
223                                        sg_dma_len(current_sg),
224                                        psize,
225                                        next_lli_phys,
226                                        reg_cfg,
227                                        !next_lli_phys,
228                                        data_width,
229                                        target == dst);
230                 if (err)
231                         goto err;
232         }
233
234         return total_size;
235 err:
236         return err;
237 }
238
239
240 void d40_phy_lli_write(void __iomem *virtbase,
241                        u32 phy_chan_num,
242                        struct d40_phy_lli *lli_dst,
243                        struct d40_phy_lli *lli_src)
244 {
245
246         writel(lli_src->reg_cfg, virtbase + D40_DREG_PCBASE +
247                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSCFG);
248         writel(lli_src->reg_elt, virtbase + D40_DREG_PCBASE +
249                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSELT);
250         writel(lli_src->reg_ptr, virtbase + D40_DREG_PCBASE +
251                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSPTR);
252         writel(lli_src->reg_lnk, virtbase + D40_DREG_PCBASE +
253                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSLNK);
254
255         writel(lli_dst->reg_cfg, virtbase + D40_DREG_PCBASE +
256                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDCFG);
257         writel(lli_dst->reg_elt, virtbase + D40_DREG_PCBASE +
258                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDELT);
259         writel(lli_dst->reg_ptr, virtbase + D40_DREG_PCBASE +
260                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDPTR);
261         writel(lli_dst->reg_lnk, virtbase + D40_DREG_PCBASE +
262                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDLNK);
263
264 }
265
266 /* DMA logical lli operations */
267
268 static void d40_log_lli_link(struct d40_log_lli *lli_dst,
269                              struct d40_log_lli *lli_src,
270                              int next)
271 {
272         u32 slos = 0;
273         u32 dlos = 0;
274
275         if (next != -EINVAL) {
276                 slos = next * 2;
277                 dlos = next * 2 + 1;
278         } else {
279                 lli_dst->lcsp13 |= D40_MEM_LCSP1_SCFG_TIM_MASK;
280                 lli_dst->lcsp13 |= D40_MEM_LCSP3_DTCP_MASK;
281         }
282
283         lli_src->lcsp13 = (lli_src->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |
284                 (slos << D40_MEM_LCSP1_SLOS_POS);
285
286         lli_dst->lcsp13 = (lli_dst->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |
287                 (dlos << D40_MEM_LCSP1_SLOS_POS);
288 }
289
290 void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa,
291                            struct d40_log_lli *lli_dst,
292                            struct d40_log_lli *lli_src,
293                            int next)
294 {
295         d40_log_lli_link(lli_dst, lli_src, next);
296
297         writel(lli_src->lcsp02, &lcpa[0].lcsp0);
298         writel(lli_src->lcsp13, &lcpa[0].lcsp1);
299         writel(lli_dst->lcsp02, &lcpa[0].lcsp2);
300         writel(lli_dst->lcsp13, &lcpa[0].lcsp3);
301 }
302
303 void d40_log_lli_lcla_write(struct d40_log_lli *lcla,
304                            struct d40_log_lli *lli_dst,
305                            struct d40_log_lli *lli_src,
306                            int next)
307 {
308         d40_log_lli_link(lli_dst, lli_src, next);
309
310         writel(lli_src->lcsp02, &lcla[0].lcsp02);
311         writel(lli_src->lcsp13, &lcla[0].lcsp13);
312         writel(lli_dst->lcsp02, &lcla[1].lcsp02);
313         writel(lli_dst->lcsp13, &lcla[1].lcsp13);
314 }
315
316 void d40_log_fill_lli(struct d40_log_lli *lli,
317                       dma_addr_t data, u32 data_size,
318                       u32 reg_cfg,
319                       u32 data_width,
320                       bool addr_inc)
321 {
322         lli->lcsp13 = reg_cfg;
323
324         /* The number of elements to transfer */
325         lli->lcsp02 = ((data_size >> data_width) <<
326                        D40_MEM_LCSP0_ECNT_POS) & D40_MEM_LCSP0_ECNT_MASK;
327         /* 16 LSBs address of the current element */
328         lli->lcsp02 |= data & D40_MEM_LCSP0_SPTR_MASK;
329         /* 16 MSBs address of the current element */
330         lli->lcsp13 |= data & D40_MEM_LCSP1_SPTR_MASK;
331
332         if (addr_inc)
333                 lli->lcsp13 |= D40_MEM_LCSP1_SCFG_INCR_MASK;
334
335 }
336
337 int d40_log_sg_to_dev(struct scatterlist *sg,
338                       int sg_len,
339                       struct d40_log_lli_bidir *lli,
340                       struct d40_def_lcsp *lcsp,
341                       u32 src_data_width,
342                       u32 dst_data_width,
343                       enum dma_data_direction direction,
344                       dma_addr_t dev_addr)
345 {
346         int total_size = 0;
347         struct scatterlist *current_sg = sg;
348         int i;
349
350         for_each_sg(sg, current_sg, sg_len, i) {
351                 total_size += sg_dma_len(current_sg);
352
353                 if (direction == DMA_TO_DEVICE) {
354                         d40_log_fill_lli(&lli->src[i],
355                                          sg_phys(current_sg),
356                                          sg_dma_len(current_sg),
357                                          lcsp->lcsp1, src_data_width,
358                                          true);
359                         d40_log_fill_lli(&lli->dst[i],
360                                          dev_addr,
361                                          sg_dma_len(current_sg),
362                                          lcsp->lcsp3, dst_data_width,
363                                          false);
364                 } else {
365                         d40_log_fill_lli(&lli->dst[i],
366                                          sg_phys(current_sg),
367                                          sg_dma_len(current_sg),
368                                          lcsp->lcsp3, dst_data_width,
369                                          true);
370                         d40_log_fill_lli(&lli->src[i],
371                                          dev_addr,
372                                          sg_dma_len(current_sg),
373                                          lcsp->lcsp1, src_data_width,
374                                          false);
375                 }
376         }
377         return total_size;
378 }
379
380 int d40_log_sg_to_lli(struct scatterlist *sg,
381                       int sg_len,
382                       struct d40_log_lli *lli_sg,
383                       u32 lcsp13, /* src or dst*/
384                       u32 data_width)
385 {
386         int total_size = 0;
387         struct scatterlist *current_sg = sg;
388         int i;
389
390         for_each_sg(sg, current_sg, sg_len, i) {
391                 total_size += sg_dma_len(current_sg);
392
393                 d40_log_fill_lli(&lli_sg[i],
394                                  sg_phys(current_sg),
395                                  sg_dma_len(current_sg),
396                                  lcsp13, data_width,
397                                  true);
398         }
399         return total_size;
400 }