dma40: combine mem and slave prep_sg functions
[linux-2.6.git] / drivers / dma / ste_dma40.c
1 /*
2  * Copyright (C) Ericsson AB 2007-2008
3  * Copyright (C) ST-Ericsson SA 2008-2010
4  * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
5  * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
6  * License terms: GNU General Public License (GPL) version 2
7  */
8
9 #include <linux/kernel.h>
10 #include <linux/slab.h>
11 #include <linux/dmaengine.h>
12 #include <linux/platform_device.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/err.h>
16
17 #include <plat/ste_dma40.h>
18
19 #include "ste_dma40_ll.h"
20
21 #define D40_NAME "dma40"
22
23 #define D40_PHY_CHAN -1
24
25 /* For masking out/in 2 bit channel positions */
26 #define D40_CHAN_POS(chan)  (2 * (chan / 2))
27 #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
28
29 /* Maximum iterations taken before giving up suspending a channel */
30 #define D40_SUSPEND_MAX_IT 500
31
32 /* Hardware requirement on LCLA alignment */
33 #define LCLA_ALIGNMENT 0x40000
34
35 /* Max number of links per event group */
36 #define D40_LCLA_LINK_PER_EVENT_GRP 128
37 #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
38
39 /* Attempts before giving up to trying to get pages that are aligned */
40 #define MAX_LCLA_ALLOC_ATTEMPTS 256
41
42 /* Bit markings for allocation map */
43 #define D40_ALLOC_FREE          (1 << 31)
44 #define D40_ALLOC_PHY           (1 << 30)
45 #define D40_ALLOC_LOG_FREE      0
46
47 /* Hardware designer of the block */
48 #define D40_HW_DESIGNER 0x8
49
50 /**
51  * enum 40_command - The different commands and/or statuses.
52  *
53  * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
54  * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
55  * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
56  * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
57  */
58 enum d40_command {
59         D40_DMA_STOP            = 0,
60         D40_DMA_RUN             = 1,
61         D40_DMA_SUSPEND_REQ     = 2,
62         D40_DMA_SUSPENDED       = 3
63 };
64
65 /**
66  * struct d40_lli_pool - Structure for keeping LLIs in memory
67  *
68  * @base: Pointer to memory area when the pre_alloc_lli's are not large
69  * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
70  * pre_alloc_lli is used.
71  * @dma_addr: DMA address, if mapped
72  * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
73  * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
74  * one buffer to one buffer.
75  */
76 struct d40_lli_pool {
77         void    *base;
78         int      size;
79         dma_addr_t      dma_addr;
80         /* Space for dst and src, plus an extra for padding */
81         u8       pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
82 };
83
84 /**
85  * struct d40_desc - A descriptor is one DMA job.
86  *
87  * @lli_phy: LLI settings for physical channel. Both src and dst=
88  * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
89  * lli_len equals one.
90  * @lli_log: Same as above but for logical channels.
91  * @lli_pool: The pool with two entries pre-allocated.
92  * @lli_len: Number of llis of current descriptor.
93  * @lli_current: Number of transfered llis.
94  * @lcla_alloc: Number of LCLA entries allocated.
95  * @txd: DMA engine struct. Used for among other things for communication
96  * during a transfer.
97  * @node: List entry.
98  * @is_in_client_list: true if the client owns this descriptor.
99  * the previous one.
100  *
101  * This descriptor is used for both logical and physical transfers.
102  */
103 struct d40_desc {
104         /* LLI physical */
105         struct d40_phy_lli_bidir         lli_phy;
106         /* LLI logical */
107         struct d40_log_lli_bidir         lli_log;
108
109         struct d40_lli_pool              lli_pool;
110         int                              lli_len;
111         int                              lli_current;
112         int                              lcla_alloc;
113
114         struct dma_async_tx_descriptor   txd;
115         struct list_head                 node;
116
117         bool                             is_in_client_list;
118 };
119
120 /**
121  * struct d40_lcla_pool - LCLA pool settings and data.
122  *
123  * @base: The virtual address of LCLA. 18 bit aligned.
124  * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
125  * This pointer is only there for clean-up on error.
126  * @pages: The number of pages needed for all physical channels.
127  * Only used later for clean-up on error
128  * @lock: Lock to protect the content in this struct.
129  * @alloc_map: big map over which LCLA entry is own by which job.
130  */
131 struct d40_lcla_pool {
132         void            *base;
133         dma_addr_t      dma_addr;
134         void            *base_unaligned;
135         int              pages;
136         spinlock_t       lock;
137         struct d40_desc **alloc_map;
138 };
139
140 /**
141  * struct d40_phy_res - struct for handling eventlines mapped to physical
142  * channels.
143  *
144  * @lock: A lock protection this entity.
145  * @num: The physical channel number of this entity.
146  * @allocated_src: Bit mapped to show which src event line's are mapped to
147  * this physical channel. Can also be free or physically allocated.
148  * @allocated_dst: Same as for src but is dst.
149  * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
150  * event line number.
151  */
152 struct d40_phy_res {
153         spinlock_t lock;
154         int        num;
155         u32        allocated_src;
156         u32        allocated_dst;
157 };
158
159 struct d40_base;
160
161 /**
162  * struct d40_chan - Struct that describes a channel.
163  *
164  * @lock: A spinlock to protect this struct.
165  * @log_num: The logical number, if any of this channel.
166  * @completed: Starts with 1, after first interrupt it is set to dma engine's
167  * current cookie.
168  * @pending_tx: The number of pending transfers. Used between interrupt handler
169  * and tasklet.
170  * @busy: Set to true when transfer is ongoing on this channel.
171  * @phy_chan: Pointer to physical channel which this instance runs on. If this
172  * point is NULL, then the channel is not allocated.
173  * @chan: DMA engine handle.
174  * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
175  * transfer and call client callback.
176  * @client: Cliented owned descriptor list.
177  * @active: Active descriptor.
178  * @queue: Queued jobs.
179  * @dma_cfg: The client configuration of this dma channel.
180  * @configured: whether the dma_cfg configuration is valid
181  * @base: Pointer to the device instance struct.
182  * @src_def_cfg: Default cfg register setting for src.
183  * @dst_def_cfg: Default cfg register setting for dst.
184  * @log_def: Default logical channel settings.
185  * @lcla: Space for one dst src pair for logical channel transfers.
186  * @lcpa: Pointer to dst and src lcpa settings.
187  *
188  * This struct can either "be" a logical or a physical channel.
189  */
190 struct d40_chan {
191         spinlock_t                       lock;
192         int                              log_num;
193         /* ID of the most recent completed transfer */
194         int                              completed;
195         int                              pending_tx;
196         bool                             busy;
197         struct d40_phy_res              *phy_chan;
198         struct dma_chan                  chan;
199         struct tasklet_struct            tasklet;
200         struct list_head                 client;
201         struct list_head                 active;
202         struct list_head                 queue;
203         struct stedma40_chan_cfg         dma_cfg;
204         bool                             configured;
205         struct d40_base                 *base;
206         /* Default register configurations */
207         u32                              src_def_cfg;
208         u32                              dst_def_cfg;
209         struct d40_def_lcsp              log_def;
210         struct d40_log_lli_full         *lcpa;
211         /* Runtime reconfiguration */
212         dma_addr_t                      runtime_addr;
213         enum dma_data_direction         runtime_direction;
214 };
215
216 /**
217  * struct d40_base - The big global struct, one for each probe'd instance.
218  *
219  * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
220  * @execmd_lock: Lock for execute command usage since several channels share
221  * the same physical register.
222  * @dev: The device structure.
223  * @virtbase: The virtual base address of the DMA's register.
224  * @rev: silicon revision detected.
225  * @clk: Pointer to the DMA clock structure.
226  * @phy_start: Physical memory start of the DMA registers.
227  * @phy_size: Size of the DMA register map.
228  * @irq: The IRQ number.
229  * @num_phy_chans: The number of physical channels. Read from HW. This
230  * is the number of available channels for this driver, not counting "Secure
231  * mode" allocated physical channels.
232  * @num_log_chans: The number of logical channels. Calculated from
233  * num_phy_chans.
234  * @dma_both: dma_device channels that can do both memcpy and slave transfers.
235  * @dma_slave: dma_device channels that can do only do slave transfers.
236  * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
237  * @log_chans: Room for all possible logical channels in system.
238  * @lookup_log_chans: Used to map interrupt number to logical channel. Points
239  * to log_chans entries.
240  * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
241  * to phy_chans entries.
242  * @plat_data: Pointer to provided platform_data which is the driver
243  * configuration.
244  * @phy_res: Vector containing all physical channels.
245  * @lcla_pool: lcla pool settings and data.
246  * @lcpa_base: The virtual mapped address of LCPA.
247  * @phy_lcpa: The physical address of the LCPA.
248  * @lcpa_size: The size of the LCPA area.
249  * @desc_slab: cache for descriptors.
250  */
251 struct d40_base {
252         spinlock_t                       interrupt_lock;
253         spinlock_t                       execmd_lock;
254         struct device                    *dev;
255         void __iomem                     *virtbase;
256         u8                                rev:4;
257         struct clk                       *clk;
258         phys_addr_t                       phy_start;
259         resource_size_t                   phy_size;
260         int                               irq;
261         int                               num_phy_chans;
262         int                               num_log_chans;
263         struct dma_device                 dma_both;
264         struct dma_device                 dma_slave;
265         struct dma_device                 dma_memcpy;
266         struct d40_chan                  *phy_chans;
267         struct d40_chan                  *log_chans;
268         struct d40_chan                 **lookup_log_chans;
269         struct d40_chan                 **lookup_phy_chans;
270         struct stedma40_platform_data    *plat_data;
271         /* Physical half channels */
272         struct d40_phy_res               *phy_res;
273         struct d40_lcla_pool              lcla_pool;
274         void                             *lcpa_base;
275         dma_addr_t                        phy_lcpa;
276         resource_size_t                   lcpa_size;
277         struct kmem_cache                *desc_slab;
278 };
279
280 /**
281  * struct d40_interrupt_lookup - lookup table for interrupt handler
282  *
283  * @src: Interrupt mask register.
284  * @clr: Interrupt clear register.
285  * @is_error: true if this is an error interrupt.
286  * @offset: start delta in the lookup_log_chans in d40_base. If equals to
287  * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
288  */
289 struct d40_interrupt_lookup {
290         u32 src;
291         u32 clr;
292         bool is_error;
293         int offset;
294 };
295
296 /**
297  * struct d40_reg_val - simple lookup struct
298  *
299  * @reg: The register.
300  * @val: The value that belongs to the register in reg.
301  */
302 struct d40_reg_val {
303         unsigned int reg;
304         unsigned int val;
305 };
306
307 static struct device *chan2dev(struct d40_chan *d40c)
308 {
309         return &d40c->chan.dev->device;
310 }
311
312 static bool chan_is_physical(struct d40_chan *chan)
313 {
314         return chan->log_num == D40_PHY_CHAN;
315 }
316
317 static bool chan_is_logical(struct d40_chan *chan)
318 {
319         return !chan_is_physical(chan);
320 }
321
322 static void __iomem *chan_base(struct d40_chan *chan)
323 {
324         return chan->base->virtbase + D40_DREG_PCBASE +
325                chan->phy_chan->num * D40_DREG_PCDELTA;
326 }
327
328 #define d40_err(dev, format, arg...)            \
329         dev_err(dev, "[%s] " format, __func__, ## arg)
330
331 #define chan_err(d40c, format, arg...)          \
332         d40_err(chan2dev(d40c), format, ## arg)
333
334 static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d,
335                               int lli_len)
336 {
337         bool is_log = chan_is_logical(d40c);
338         u32 align;
339         void *base;
340
341         if (is_log)
342                 align = sizeof(struct d40_log_lli);
343         else
344                 align = sizeof(struct d40_phy_lli);
345
346         if (lli_len == 1) {
347                 base = d40d->lli_pool.pre_alloc_lli;
348                 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
349                 d40d->lli_pool.base = NULL;
350         } else {
351                 d40d->lli_pool.size = lli_len * 2 * align;
352
353                 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
354                 d40d->lli_pool.base = base;
355
356                 if (d40d->lli_pool.base == NULL)
357                         return -ENOMEM;
358         }
359
360         if (is_log) {
361                 d40d->lli_log.src = PTR_ALIGN(base, align);
362                 d40d->lli_log.dst = d40d->lli_log.src + lli_len;
363
364                 d40d->lli_pool.dma_addr = 0;
365         } else {
366                 d40d->lli_phy.src = PTR_ALIGN(base, align);
367                 d40d->lli_phy.dst = d40d->lli_phy.src + lli_len;
368
369                 d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev,
370                                                          d40d->lli_phy.src,
371                                                          d40d->lli_pool.size,
372                                                          DMA_TO_DEVICE);
373
374                 if (dma_mapping_error(d40c->base->dev,
375                                       d40d->lli_pool.dma_addr)) {
376                         kfree(d40d->lli_pool.base);
377                         d40d->lli_pool.base = NULL;
378                         d40d->lli_pool.dma_addr = 0;
379                         return -ENOMEM;
380                 }
381         }
382
383         return 0;
384 }
385
386 static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d)
387 {
388         if (d40d->lli_pool.dma_addr)
389                 dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr,
390                                  d40d->lli_pool.size, DMA_TO_DEVICE);
391
392         kfree(d40d->lli_pool.base);
393         d40d->lli_pool.base = NULL;
394         d40d->lli_pool.size = 0;
395         d40d->lli_log.src = NULL;
396         d40d->lli_log.dst = NULL;
397         d40d->lli_phy.src = NULL;
398         d40d->lli_phy.dst = NULL;
399 }
400
401 static int d40_lcla_alloc_one(struct d40_chan *d40c,
402                               struct d40_desc *d40d)
403 {
404         unsigned long flags;
405         int i;
406         int ret = -EINVAL;
407         int p;
408
409         spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
410
411         p = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP;
412
413         /*
414          * Allocate both src and dst at the same time, therefore the half
415          * start on 1 since 0 can't be used since zero is used as end marker.
416          */
417         for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
418                 if (!d40c->base->lcla_pool.alloc_map[p + i]) {
419                         d40c->base->lcla_pool.alloc_map[p + i] = d40d;
420                         d40d->lcla_alloc++;
421                         ret = i;
422                         break;
423                 }
424         }
425
426         spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
427
428         return ret;
429 }
430
431 static int d40_lcla_free_all(struct d40_chan *d40c,
432                              struct d40_desc *d40d)
433 {
434         unsigned long flags;
435         int i;
436         int ret = -EINVAL;
437
438         if (chan_is_physical(d40c))
439                 return 0;
440
441         spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
442
443         for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
444                 if (d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
445                                                     D40_LCLA_LINK_PER_EVENT_GRP + i] == d40d) {
446                         d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
447                                                         D40_LCLA_LINK_PER_EVENT_GRP + i] = NULL;
448                         d40d->lcla_alloc--;
449                         if (d40d->lcla_alloc == 0) {
450                                 ret = 0;
451                                 break;
452                         }
453                 }
454         }
455
456         spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
457
458         return ret;
459
460 }
461
462 static void d40_desc_remove(struct d40_desc *d40d)
463 {
464         list_del(&d40d->node);
465 }
466
467 static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
468 {
469         struct d40_desc *desc = NULL;
470
471         if (!list_empty(&d40c->client)) {
472                 struct d40_desc *d;
473                 struct d40_desc *_d;
474
475                 list_for_each_entry_safe(d, _d, &d40c->client, node)
476                         if (async_tx_test_ack(&d->txd)) {
477                                 d40_pool_lli_free(d40c, d);
478                                 d40_desc_remove(d);
479                                 desc = d;
480                                 memset(desc, 0, sizeof(*desc));
481                                 break;
482                         }
483         }
484
485         if (!desc)
486                 desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT);
487
488         if (desc)
489                 INIT_LIST_HEAD(&desc->node);
490
491         return desc;
492 }
493
494 static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
495 {
496
497         d40_pool_lli_free(d40c, d40d);
498         d40_lcla_free_all(d40c, d40d);
499         kmem_cache_free(d40c->base->desc_slab, d40d);
500 }
501
502 static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
503 {
504         list_add_tail(&desc->node, &d40c->active);
505 }
506
507 static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
508 {
509         int curr_lcla = -EINVAL, next_lcla;
510
511         if (chan_is_physical(d40c)) {
512                 d40_phy_lli_write(d40c->base->virtbase,
513                                   d40c->phy_chan->num,
514                                   d40d->lli_phy.dst,
515                                   d40d->lli_phy.src);
516                 d40d->lli_current = d40d->lli_len;
517         } else {
518
519                 if ((d40d->lli_len - d40d->lli_current) > 1)
520                         curr_lcla = d40_lcla_alloc_one(d40c, d40d);
521
522                 d40_log_lli_lcpa_write(d40c->lcpa,
523                                        &d40d->lli_log.dst[d40d->lli_current],
524                                        &d40d->lli_log.src[d40d->lli_current],
525                                        curr_lcla);
526
527                 d40d->lli_current++;
528                 for (; d40d->lli_current < d40d->lli_len; d40d->lli_current++) {
529                         unsigned int lcla_offset = d40c->phy_chan->num * 1024 +
530                                                    8 * curr_lcla * 2;
531                         struct d40_lcla_pool *pool = &d40c->base->lcla_pool;
532                         struct d40_log_lli *lcla = pool->base + lcla_offset;
533
534                         if (d40d->lli_current + 1 < d40d->lli_len)
535                                 next_lcla = d40_lcla_alloc_one(d40c, d40d);
536                         else
537                                 next_lcla = -EINVAL;
538
539                         d40_log_lli_lcla_write(lcla,
540                                                &d40d->lli_log.dst[d40d->lli_current],
541                                                &d40d->lli_log.src[d40d->lli_current],
542                                                next_lcla);
543
544                         dma_sync_single_range_for_device(d40c->base->dev,
545                                                 pool->dma_addr, lcla_offset,
546                                                 2 * sizeof(struct d40_log_lli),
547                                                 DMA_TO_DEVICE);
548
549                         curr_lcla = next_lcla;
550
551                         if (curr_lcla == -EINVAL) {
552                                 d40d->lli_current++;
553                                 break;
554                         }
555
556                 }
557         }
558 }
559
560 static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
561 {
562         struct d40_desc *d;
563
564         if (list_empty(&d40c->active))
565                 return NULL;
566
567         d = list_first_entry(&d40c->active,
568                              struct d40_desc,
569                              node);
570         return d;
571 }
572
573 static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
574 {
575         list_add_tail(&desc->node, &d40c->queue);
576 }
577
578 static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
579 {
580         struct d40_desc *d;
581
582         if (list_empty(&d40c->queue))
583                 return NULL;
584
585         d = list_first_entry(&d40c->queue,
586                              struct d40_desc,
587                              node);
588         return d;
589 }
590
591 static int d40_psize_2_burst_size(bool is_log, int psize)
592 {
593         if (is_log) {
594                 if (psize == STEDMA40_PSIZE_LOG_1)
595                         return 1;
596         } else {
597                 if (psize == STEDMA40_PSIZE_PHY_1)
598                         return 1;
599         }
600
601         return 2 << psize;
602 }
603
604 /*
605  * The dma only supports transmitting packages up to
606  * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of
607  * dma elements required to send the entire sg list
608  */
609 static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
610 {
611         int dmalen;
612         u32 max_w = max(data_width1, data_width2);
613         u32 min_w = min(data_width1, data_width2);
614         u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
615
616         if (seg_max > STEDMA40_MAX_SEG_SIZE)
617                 seg_max -= (1 << max_w);
618
619         if (!IS_ALIGNED(size, 1 << max_w))
620                 return -EINVAL;
621
622         if (size <= seg_max)
623                 dmalen = 1;
624         else {
625                 dmalen = size / seg_max;
626                 if (dmalen * seg_max < size)
627                         dmalen++;
628         }
629         return dmalen;
630 }
631
632 static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
633                            u32 data_width1, u32 data_width2)
634 {
635         struct scatterlist *sg;
636         int i;
637         int len = 0;
638         int ret;
639
640         for_each_sg(sgl, sg, sg_len, i) {
641                 ret = d40_size_2_dmalen(sg_dma_len(sg),
642                                         data_width1, data_width2);
643                 if (ret < 0)
644                         return ret;
645                 len += ret;
646         }
647         return len;
648 }
649
650 /* Support functions for logical channels */
651
652 static int d40_channel_execute_command(struct d40_chan *d40c,
653                                        enum d40_command command)
654 {
655         u32 status;
656         int i;
657         void __iomem *active_reg;
658         int ret = 0;
659         unsigned long flags;
660         u32 wmask;
661
662         spin_lock_irqsave(&d40c->base->execmd_lock, flags);
663
664         if (d40c->phy_chan->num % 2 == 0)
665                 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
666         else
667                 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
668
669         if (command == D40_DMA_SUSPEND_REQ) {
670                 status = (readl(active_reg) &
671                           D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
672                         D40_CHAN_POS(d40c->phy_chan->num);
673
674                 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
675                         goto done;
676         }
677
678         wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
679         writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
680                active_reg);
681
682         if (command == D40_DMA_SUSPEND_REQ) {
683
684                 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
685                         status = (readl(active_reg) &
686                                   D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
687                                 D40_CHAN_POS(d40c->phy_chan->num);
688
689                         cpu_relax();
690                         /*
691                          * Reduce the number of bus accesses while
692                          * waiting for the DMA to suspend.
693                          */
694                         udelay(3);
695
696                         if (status == D40_DMA_STOP ||
697                             status == D40_DMA_SUSPENDED)
698                                 break;
699                 }
700
701                 if (i == D40_SUSPEND_MAX_IT) {
702                         chan_err(d40c,
703                                 "unable to suspend the chl %d (log: %d) status %x\n",
704                                 d40c->phy_chan->num, d40c->log_num,
705                                 status);
706                         dump_stack();
707                         ret = -EBUSY;
708                 }
709
710         }
711 done:
712         spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
713         return ret;
714 }
715
716 static void d40_term_all(struct d40_chan *d40c)
717 {
718         struct d40_desc *d40d;
719
720         /* Release active descriptors */
721         while ((d40d = d40_first_active_get(d40c))) {
722                 d40_desc_remove(d40d);
723                 d40_desc_free(d40c, d40d);
724         }
725
726         /* Release queued descriptors waiting for transfer */
727         while ((d40d = d40_first_queued(d40c))) {
728                 d40_desc_remove(d40d);
729                 d40_desc_free(d40c, d40d);
730         }
731
732
733         d40c->pending_tx = 0;
734         d40c->busy = false;
735 }
736
737 static void __d40_config_set_event(struct d40_chan *d40c, bool enable,
738                                    u32 event, int reg)
739 {
740         void __iomem *addr = chan_base(d40c) + reg;
741         int tries;
742
743         if (!enable) {
744                 writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
745                        | ~D40_EVENTLINE_MASK(event), addr);
746                 return;
747         }
748
749         /*
750          * The hardware sometimes doesn't register the enable when src and dst
751          * event lines are active on the same logical channel.  Retry to ensure
752          * it does.  Usually only one retry is sufficient.
753          */
754         tries = 100;
755         while (--tries) {
756                 writel((D40_ACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
757                        | ~D40_EVENTLINE_MASK(event), addr);
758
759                 if (readl(addr) & D40_EVENTLINE_MASK(event))
760                         break;
761         }
762
763         if (tries != 99)
764                 dev_dbg(chan2dev(d40c),
765                         "[%s] workaround enable S%cLNK (%d tries)\n",
766                         __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
767                         100 - tries);
768
769         WARN_ON(!tries);
770 }
771
772 static void d40_config_set_event(struct d40_chan *d40c, bool do_enable)
773 {
774         unsigned long flags;
775
776         spin_lock_irqsave(&d40c->phy_chan->lock, flags);
777
778         /* Enable event line connected to device (or memcpy) */
779         if ((d40c->dma_cfg.dir ==  STEDMA40_PERIPH_TO_MEM) ||
780             (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) {
781                 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
782
783                 __d40_config_set_event(d40c, do_enable, event,
784                                        D40_CHAN_REG_SSLNK);
785         }
786
787         if (d40c->dma_cfg.dir !=  STEDMA40_PERIPH_TO_MEM) {
788                 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
789
790                 __d40_config_set_event(d40c, do_enable, event,
791                                        D40_CHAN_REG_SDLNK);
792         }
793
794         spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
795 }
796
797 static u32 d40_chan_has_events(struct d40_chan *d40c)
798 {
799         void __iomem *chanbase = chan_base(d40c);
800         u32 val;
801
802         val = readl(chanbase + D40_CHAN_REG_SSLNK);
803         val |= readl(chanbase + D40_CHAN_REG_SDLNK);
804
805         return val;
806 }
807
808 static u32 d40_get_prmo(struct d40_chan *d40c)
809 {
810         static const unsigned int phy_map[] = {
811                 [STEDMA40_PCHAN_BASIC_MODE]
812                         = D40_DREG_PRMO_PCHAN_BASIC,
813                 [STEDMA40_PCHAN_MODULO_MODE]
814                         = D40_DREG_PRMO_PCHAN_MODULO,
815                 [STEDMA40_PCHAN_DOUBLE_DST_MODE]
816                         = D40_DREG_PRMO_PCHAN_DOUBLE_DST,
817         };
818         static const unsigned int log_map[] = {
819                 [STEDMA40_LCHAN_SRC_PHY_DST_LOG]
820                         = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG,
821                 [STEDMA40_LCHAN_SRC_LOG_DST_PHY]
822                         = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY,
823                 [STEDMA40_LCHAN_SRC_LOG_DST_LOG]
824                         = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
825         };
826
827         if (chan_is_physical(d40c))
828                 return phy_map[d40c->dma_cfg.mode_opt];
829         else
830                 return log_map[d40c->dma_cfg.mode_opt];
831 }
832
833 static void d40_config_write(struct d40_chan *d40c)
834 {
835         u32 addr_base;
836         u32 var;
837
838         /* Odd addresses are even addresses + 4 */
839         addr_base = (d40c->phy_chan->num % 2) * 4;
840         /* Setup channel mode to logical or physical */
841         var = ((u32)(chan_is_logical(d40c)) + 1) <<
842                 D40_CHAN_POS(d40c->phy_chan->num);
843         writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
844
845         /* Setup operational mode option register */
846         var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num);
847
848         writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
849
850         if (chan_is_logical(d40c)) {
851                 int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
852                            & D40_SREG_ELEM_LOG_LIDX_MASK;
853                 void __iomem *chanbase = chan_base(d40c);
854
855                 /* Set default config for CFG reg */
856                 writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
857                 writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
858
859                 /* Set LIDX for lcla */
860                 writel(lidx, chanbase + D40_CHAN_REG_SSELT);
861                 writel(lidx, chanbase + D40_CHAN_REG_SDELT);
862         }
863 }
864
865 static u32 d40_residue(struct d40_chan *d40c)
866 {
867         u32 num_elt;
868
869         if (chan_is_logical(d40c))
870                 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
871                         >> D40_MEM_LCSP2_ECNT_POS;
872         else {
873                 u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT);
874                 num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK)
875                           >> D40_SREG_ELEM_PHY_ECNT_POS;
876         }
877
878         return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
879 }
880
881 static bool d40_tx_is_linked(struct d40_chan *d40c)
882 {
883         bool is_link;
884
885         if (chan_is_logical(d40c))
886                 is_link = readl(&d40c->lcpa->lcsp3) &  D40_MEM_LCSP3_DLOS_MASK;
887         else
888                 is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
889                           & D40_SREG_LNK_PHYS_LNK_MASK;
890
891         return is_link;
892 }
893
894 static int d40_pause(struct dma_chan *chan)
895 {
896         struct d40_chan *d40c =
897                 container_of(chan, struct d40_chan, chan);
898         int res = 0;
899         unsigned long flags;
900
901         if (!d40c->busy)
902                 return 0;
903
904         spin_lock_irqsave(&d40c->lock, flags);
905
906         res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
907         if (res == 0) {
908                 if (chan_is_logical(d40c)) {
909                         d40_config_set_event(d40c, false);
910                         /* Resume the other logical channels if any */
911                         if (d40_chan_has_events(d40c))
912                                 res = d40_channel_execute_command(d40c,
913                                                                   D40_DMA_RUN);
914                 }
915         }
916
917         spin_unlock_irqrestore(&d40c->lock, flags);
918         return res;
919 }
920
921 static int d40_resume(struct dma_chan *chan)
922 {
923         struct d40_chan *d40c =
924                 container_of(chan, struct d40_chan, chan);
925         int res = 0;
926         unsigned long flags;
927
928         if (!d40c->busy)
929                 return 0;
930
931         spin_lock_irqsave(&d40c->lock, flags);
932
933         if (d40c->base->rev == 0)
934                 if (chan_is_logical(d40c)) {
935                         res = d40_channel_execute_command(d40c,
936                                                           D40_DMA_SUSPEND_REQ);
937                         goto no_suspend;
938                 }
939
940         /* If bytes left to transfer or linked tx resume job */
941         if (d40_residue(d40c) || d40_tx_is_linked(d40c)) {
942
943                 if (chan_is_logical(d40c))
944                         d40_config_set_event(d40c, true);
945
946                 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
947         }
948
949 no_suspend:
950         spin_unlock_irqrestore(&d40c->lock, flags);
951         return res;
952 }
953
954 static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
955 {
956         struct d40_chan *d40c = container_of(tx->chan,
957                                              struct d40_chan,
958                                              chan);
959         struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
960         unsigned long flags;
961
962         spin_lock_irqsave(&d40c->lock, flags);
963
964         d40c->chan.cookie++;
965
966         if (d40c->chan.cookie < 0)
967                 d40c->chan.cookie = 1;
968
969         d40d->txd.cookie = d40c->chan.cookie;
970
971         d40_desc_queue(d40c, d40d);
972
973         spin_unlock_irqrestore(&d40c->lock, flags);
974
975         return tx->cookie;
976 }
977
978 static int d40_start(struct d40_chan *d40c)
979 {
980         if (d40c->base->rev == 0) {
981                 int err;
982
983                 if (chan_is_logical(d40c)) {
984                         err = d40_channel_execute_command(d40c,
985                                                           D40_DMA_SUSPEND_REQ);
986                         if (err)
987                                 return err;
988                 }
989         }
990
991         if (chan_is_logical(d40c))
992                 d40_config_set_event(d40c, true);
993
994         return d40_channel_execute_command(d40c, D40_DMA_RUN);
995 }
996
997 static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
998 {
999         struct d40_desc *d40d;
1000         int err;
1001
1002         /* Start queued jobs, if any */
1003         d40d = d40_first_queued(d40c);
1004
1005         if (d40d != NULL) {
1006                 d40c->busy = true;
1007
1008                 /* Remove from queue */
1009                 d40_desc_remove(d40d);
1010
1011                 /* Add to active queue */
1012                 d40_desc_submit(d40c, d40d);
1013
1014                 /* Initiate DMA job */
1015                 d40_desc_load(d40c, d40d);
1016
1017                 /* Start dma job */
1018                 err = d40_start(d40c);
1019
1020                 if (err)
1021                         return NULL;
1022         }
1023
1024         return d40d;
1025 }
1026
1027 /* called from interrupt context */
1028 static void dma_tc_handle(struct d40_chan *d40c)
1029 {
1030         struct d40_desc *d40d;
1031
1032         /* Get first active entry from list */
1033         d40d = d40_first_active_get(d40c);
1034
1035         if (d40d == NULL)
1036                 return;
1037
1038         d40_lcla_free_all(d40c, d40d);
1039
1040         if (d40d->lli_current < d40d->lli_len) {
1041                 d40_desc_load(d40c, d40d);
1042                 /* Start dma job */
1043                 (void) d40_start(d40c);
1044                 return;
1045         }
1046
1047         if (d40_queue_start(d40c) == NULL)
1048                 d40c->busy = false;
1049
1050         d40c->pending_tx++;
1051         tasklet_schedule(&d40c->tasklet);
1052
1053 }
1054
1055 static void dma_tasklet(unsigned long data)
1056 {
1057         struct d40_chan *d40c = (struct d40_chan *) data;
1058         struct d40_desc *d40d;
1059         unsigned long flags;
1060         dma_async_tx_callback callback;
1061         void *callback_param;
1062
1063         spin_lock_irqsave(&d40c->lock, flags);
1064
1065         /* Get first active entry from list */
1066         d40d = d40_first_active_get(d40c);
1067
1068         if (d40d == NULL)
1069                 goto err;
1070
1071         d40c->completed = d40d->txd.cookie;
1072
1073         /*
1074          * If terminating a channel pending_tx is set to zero.
1075          * This prevents any finished active jobs to return to the client.
1076          */
1077         if (d40c->pending_tx == 0) {
1078                 spin_unlock_irqrestore(&d40c->lock, flags);
1079                 return;
1080         }
1081
1082         /* Callback to client */
1083         callback = d40d->txd.callback;
1084         callback_param = d40d->txd.callback_param;
1085
1086         if (async_tx_test_ack(&d40d->txd)) {
1087                 d40_pool_lli_free(d40c, d40d);
1088                 d40_desc_remove(d40d);
1089                 d40_desc_free(d40c, d40d);
1090         } else {
1091                 if (!d40d->is_in_client_list) {
1092                         d40_desc_remove(d40d);
1093                         d40_lcla_free_all(d40c, d40d);
1094                         list_add_tail(&d40d->node, &d40c->client);
1095                         d40d->is_in_client_list = true;
1096                 }
1097         }
1098
1099         d40c->pending_tx--;
1100
1101         if (d40c->pending_tx)
1102                 tasklet_schedule(&d40c->tasklet);
1103
1104         spin_unlock_irqrestore(&d40c->lock, flags);
1105
1106         if (callback && (d40d->txd.flags & DMA_PREP_INTERRUPT))
1107                 callback(callback_param);
1108
1109         return;
1110
1111  err:
1112         /* Rescue manouver if receiving double interrupts */
1113         if (d40c->pending_tx > 0)
1114                 d40c->pending_tx--;
1115         spin_unlock_irqrestore(&d40c->lock, flags);
1116 }
1117
1118 static irqreturn_t d40_handle_interrupt(int irq, void *data)
1119 {
1120         static const struct d40_interrupt_lookup il[] = {
1121                 {D40_DREG_LCTIS0, D40_DREG_LCICR0, false,  0},
1122                 {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
1123                 {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
1124                 {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
1125                 {D40_DREG_LCEIS0, D40_DREG_LCICR0, true,   0},
1126                 {D40_DREG_LCEIS1, D40_DREG_LCICR1, true,  32},
1127                 {D40_DREG_LCEIS2, D40_DREG_LCICR2, true,  64},
1128                 {D40_DREG_LCEIS3, D40_DREG_LCICR3, true,  96},
1129                 {D40_DREG_PCTIS,  D40_DREG_PCICR,  false, D40_PHY_CHAN},
1130                 {D40_DREG_PCEIS,  D40_DREG_PCICR,  true,  D40_PHY_CHAN},
1131         };
1132
1133         int i;
1134         u32 regs[ARRAY_SIZE(il)];
1135         u32 idx;
1136         u32 row;
1137         long chan = -1;
1138         struct d40_chan *d40c;
1139         unsigned long flags;
1140         struct d40_base *base = data;
1141
1142         spin_lock_irqsave(&base->interrupt_lock, flags);
1143
1144         /* Read interrupt status of both logical and physical channels */
1145         for (i = 0; i < ARRAY_SIZE(il); i++)
1146                 regs[i] = readl(base->virtbase + il[i].src);
1147
1148         for (;;) {
1149
1150                 chan = find_next_bit((unsigned long *)regs,
1151                                      BITS_PER_LONG * ARRAY_SIZE(il), chan + 1);
1152
1153                 /* No more set bits found? */
1154                 if (chan == BITS_PER_LONG * ARRAY_SIZE(il))
1155                         break;
1156
1157                 row = chan / BITS_PER_LONG;
1158                 idx = chan & (BITS_PER_LONG - 1);
1159
1160                 /* ACK interrupt */
1161                 writel(1 << idx, base->virtbase + il[row].clr);
1162
1163                 if (il[row].offset == D40_PHY_CHAN)
1164                         d40c = base->lookup_phy_chans[idx];
1165                 else
1166                         d40c = base->lookup_log_chans[il[row].offset + idx];
1167                 spin_lock(&d40c->lock);
1168
1169                 if (!il[row].is_error)
1170                         dma_tc_handle(d40c);
1171                 else
1172                         d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n",
1173                                 chan, il[row].offset, idx);
1174
1175                 spin_unlock(&d40c->lock);
1176         }
1177
1178         spin_unlock_irqrestore(&base->interrupt_lock, flags);
1179
1180         return IRQ_HANDLED;
1181 }
1182
1183 static int d40_validate_conf(struct d40_chan *d40c,
1184                              struct stedma40_chan_cfg *conf)
1185 {
1186         int res = 0;
1187         u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type);
1188         u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type);
1189         bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
1190
1191         if (!conf->dir) {
1192                 chan_err(d40c, "Invalid direction.\n");
1193                 res = -EINVAL;
1194         }
1195
1196         if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY &&
1197             d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 &&
1198             d40c->runtime_addr == 0) {
1199
1200                 chan_err(d40c, "Invalid TX channel address (%d)\n",
1201                          conf->dst_dev_type);
1202                 res = -EINVAL;
1203         }
1204
1205         if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY &&
1206             d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 &&
1207             d40c->runtime_addr == 0) {
1208                 chan_err(d40c, "Invalid RX channel address (%d)\n",
1209                         conf->src_dev_type);
1210                 res = -EINVAL;
1211         }
1212
1213         if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
1214             dst_event_group == STEDMA40_DEV_DST_MEMORY) {
1215                 chan_err(d40c, "Invalid dst\n");
1216                 res = -EINVAL;
1217         }
1218
1219         if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
1220             src_event_group == STEDMA40_DEV_SRC_MEMORY) {
1221                 chan_err(d40c, "Invalid src\n");
1222                 res = -EINVAL;
1223         }
1224
1225         if (src_event_group == STEDMA40_DEV_SRC_MEMORY &&
1226             dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) {
1227                 chan_err(d40c, "No event line\n");
1228                 res = -EINVAL;
1229         }
1230
1231         if (conf->dir == STEDMA40_PERIPH_TO_PERIPH &&
1232             (src_event_group != dst_event_group)) {
1233                 chan_err(d40c, "Invalid event group\n");
1234                 res = -EINVAL;
1235         }
1236
1237         if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
1238                 /*
1239                  * DMAC HW supports it. Will be added to this driver,
1240                  * in case any dma client requires it.
1241                  */
1242                 chan_err(d40c, "periph to periph not supported\n");
1243                 res = -EINVAL;
1244         }
1245
1246         if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
1247             (1 << conf->src_info.data_width) !=
1248             d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
1249             (1 << conf->dst_info.data_width)) {
1250                 /*
1251                  * The DMAC hardware only supports
1252                  * src (burst x width) == dst (burst x width)
1253                  */
1254
1255                 chan_err(d40c, "src (burst x width) != dst (burst x width)\n");
1256                 res = -EINVAL;
1257         }
1258
1259         return res;
1260 }
1261
1262 static bool d40_alloc_mask_set(struct d40_phy_res *phy, bool is_src,
1263                                int log_event_line, bool is_log)
1264 {
1265         unsigned long flags;
1266         spin_lock_irqsave(&phy->lock, flags);
1267         if (!is_log) {
1268                 /* Physical interrupts are masked per physical full channel */
1269                 if (phy->allocated_src == D40_ALLOC_FREE &&
1270                     phy->allocated_dst == D40_ALLOC_FREE) {
1271                         phy->allocated_dst = D40_ALLOC_PHY;
1272                         phy->allocated_src = D40_ALLOC_PHY;
1273                         goto found;
1274                 } else
1275                         goto not_found;
1276         }
1277
1278         /* Logical channel */
1279         if (is_src) {
1280                 if (phy->allocated_src == D40_ALLOC_PHY)
1281                         goto not_found;
1282
1283                 if (phy->allocated_src == D40_ALLOC_FREE)
1284                         phy->allocated_src = D40_ALLOC_LOG_FREE;
1285
1286                 if (!(phy->allocated_src & (1 << log_event_line))) {
1287                         phy->allocated_src |= 1 << log_event_line;
1288                         goto found;
1289                 } else
1290                         goto not_found;
1291         } else {
1292                 if (phy->allocated_dst == D40_ALLOC_PHY)
1293                         goto not_found;
1294
1295                 if (phy->allocated_dst == D40_ALLOC_FREE)
1296                         phy->allocated_dst = D40_ALLOC_LOG_FREE;
1297
1298                 if (!(phy->allocated_dst & (1 << log_event_line))) {
1299                         phy->allocated_dst |= 1 << log_event_line;
1300                         goto found;
1301                 } else
1302                         goto not_found;
1303         }
1304
1305 not_found:
1306         spin_unlock_irqrestore(&phy->lock, flags);
1307         return false;
1308 found:
1309         spin_unlock_irqrestore(&phy->lock, flags);
1310         return true;
1311 }
1312
1313 static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
1314                                int log_event_line)
1315 {
1316         unsigned long flags;
1317         bool is_free = false;
1318
1319         spin_lock_irqsave(&phy->lock, flags);
1320         if (!log_event_line) {
1321                 phy->allocated_dst = D40_ALLOC_FREE;
1322                 phy->allocated_src = D40_ALLOC_FREE;
1323                 is_free = true;
1324                 goto out;
1325         }
1326
1327         /* Logical channel */
1328         if (is_src) {
1329                 phy->allocated_src &= ~(1 << log_event_line);
1330                 if (phy->allocated_src == D40_ALLOC_LOG_FREE)
1331                         phy->allocated_src = D40_ALLOC_FREE;
1332         } else {
1333                 phy->allocated_dst &= ~(1 << log_event_line);
1334                 if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
1335                         phy->allocated_dst = D40_ALLOC_FREE;
1336         }
1337
1338         is_free = ((phy->allocated_src | phy->allocated_dst) ==
1339                    D40_ALLOC_FREE);
1340
1341 out:
1342         spin_unlock_irqrestore(&phy->lock, flags);
1343
1344         return is_free;
1345 }
1346
1347 static int d40_allocate_channel(struct d40_chan *d40c)
1348 {
1349         int dev_type;
1350         int event_group;
1351         int event_line;
1352         struct d40_phy_res *phys;
1353         int i;
1354         int j;
1355         int log_num;
1356         bool is_src;
1357         bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
1358
1359         phys = d40c->base->phy_res;
1360
1361         if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1362                 dev_type = d40c->dma_cfg.src_dev_type;
1363                 log_num = 2 * dev_type;
1364                 is_src = true;
1365         } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1366                    d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1367                 /* dst event lines are used for logical memcpy */
1368                 dev_type = d40c->dma_cfg.dst_dev_type;
1369                 log_num = 2 * dev_type + 1;
1370                 is_src = false;
1371         } else
1372                 return -EINVAL;
1373
1374         event_group = D40_TYPE_TO_GROUP(dev_type);
1375         event_line = D40_TYPE_TO_EVENT(dev_type);
1376
1377         if (!is_log) {
1378                 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1379                         /* Find physical half channel */
1380                         for (i = 0; i < d40c->base->num_phy_chans; i++) {
1381
1382                                 if (d40_alloc_mask_set(&phys[i], is_src,
1383                                                        0, is_log))
1384                                         goto found_phy;
1385                         }
1386                 } else
1387                         for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1388                                 int phy_num = j  + event_group * 2;
1389                                 for (i = phy_num; i < phy_num + 2; i++) {
1390                                         if (d40_alloc_mask_set(&phys[i],
1391                                                                is_src,
1392                                                                0,
1393                                                                is_log))
1394                                                 goto found_phy;
1395                                 }
1396                         }
1397                 return -EINVAL;
1398 found_phy:
1399                 d40c->phy_chan = &phys[i];
1400                 d40c->log_num = D40_PHY_CHAN;
1401                 goto out;
1402         }
1403         if (dev_type == -1)
1404                 return -EINVAL;
1405
1406         /* Find logical channel */
1407         for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1408                 int phy_num = j + event_group * 2;
1409                 /*
1410                  * Spread logical channels across all available physical rather
1411                  * than pack every logical channel at the first available phy
1412                  * channels.
1413                  */
1414                 if (is_src) {
1415                         for (i = phy_num; i < phy_num + 2; i++) {
1416                                 if (d40_alloc_mask_set(&phys[i], is_src,
1417                                                        event_line, is_log))
1418                                         goto found_log;
1419                         }
1420                 } else {
1421                         for (i = phy_num + 1; i >= phy_num; i--) {
1422                                 if (d40_alloc_mask_set(&phys[i], is_src,
1423                                                        event_line, is_log))
1424                                         goto found_log;
1425                         }
1426                 }
1427         }
1428         return -EINVAL;
1429
1430 found_log:
1431         d40c->phy_chan = &phys[i];
1432         d40c->log_num = log_num;
1433 out:
1434
1435         if (is_log)
1436                 d40c->base->lookup_log_chans[d40c->log_num] = d40c;
1437         else
1438                 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
1439
1440         return 0;
1441
1442 }
1443
1444 static int d40_config_memcpy(struct d40_chan *d40c)
1445 {
1446         dma_cap_mask_t cap = d40c->chan.device->cap_mask;
1447
1448         if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
1449                 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log;
1450                 d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY;
1451                 d40c->dma_cfg.dst_dev_type = d40c->base->plat_data->
1452                         memcpy[d40c->chan.chan_id];
1453
1454         } else if (dma_has_cap(DMA_MEMCPY, cap) &&
1455                    dma_has_cap(DMA_SLAVE, cap)) {
1456                 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy;
1457         } else {
1458                 chan_err(d40c, "No memcpy\n");
1459                 return -EINVAL;
1460         }
1461
1462         return 0;
1463 }
1464
1465
1466 static int d40_free_dma(struct d40_chan *d40c)
1467 {
1468
1469         int res = 0;
1470         u32 event;
1471         struct d40_phy_res *phy = d40c->phy_chan;
1472         bool is_src;
1473         struct d40_desc *d;
1474         struct d40_desc *_d;
1475
1476
1477         /* Terminate all queued and active transfers */
1478         d40_term_all(d40c);
1479
1480         /* Release client owned descriptors */
1481         if (!list_empty(&d40c->client))
1482                 list_for_each_entry_safe(d, _d, &d40c->client, node) {
1483                         d40_pool_lli_free(d40c, d);
1484                         d40_desc_remove(d);
1485                         d40_desc_free(d40c, d);
1486                 }
1487
1488         if (phy == NULL) {
1489                 chan_err(d40c, "phy == null\n");
1490                 return -EINVAL;
1491         }
1492
1493         if (phy->allocated_src == D40_ALLOC_FREE &&
1494             phy->allocated_dst == D40_ALLOC_FREE) {
1495                 chan_err(d40c, "channel already free\n");
1496                 return -EINVAL;
1497         }
1498
1499         if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1500             d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1501                 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
1502                 is_src = false;
1503         } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1504                 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
1505                 is_src = true;
1506         } else {
1507                 chan_err(d40c, "Unknown direction\n");
1508                 return -EINVAL;
1509         }
1510
1511         res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1512         if (res) {
1513                 chan_err(d40c, "suspend failed\n");
1514                 return res;
1515         }
1516
1517         if (chan_is_logical(d40c)) {
1518                 /* Release logical channel, deactivate the event line */
1519
1520                 d40_config_set_event(d40c, false);
1521                 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
1522
1523                 /*
1524                  * Check if there are more logical allocation
1525                  * on this phy channel.
1526                  */
1527                 if (!d40_alloc_mask_free(phy, is_src, event)) {
1528                         /* Resume the other logical channels if any */
1529                         if (d40_chan_has_events(d40c)) {
1530                                 res = d40_channel_execute_command(d40c,
1531                                                                   D40_DMA_RUN);
1532                                 if (res) {
1533                                         chan_err(d40c,
1534                                                 "Executing RUN command\n");
1535                                         return res;
1536                                 }
1537                         }
1538                         return 0;
1539                 }
1540         } else {
1541                 (void) d40_alloc_mask_free(phy, is_src, 0);
1542         }
1543
1544         /* Release physical channel */
1545         res = d40_channel_execute_command(d40c, D40_DMA_STOP);
1546         if (res) {
1547                 chan_err(d40c, "Failed to stop channel\n");
1548                 return res;
1549         }
1550         d40c->phy_chan = NULL;
1551         d40c->configured = false;
1552         d40c->base->lookup_phy_chans[phy->num] = NULL;
1553
1554         return 0;
1555 }
1556
1557 static bool d40_is_paused(struct d40_chan *d40c)
1558 {
1559         void __iomem *chanbase = chan_base(d40c);
1560         bool is_paused = false;
1561         unsigned long flags;
1562         void __iomem *active_reg;
1563         u32 status;
1564         u32 event;
1565
1566         spin_lock_irqsave(&d40c->lock, flags);
1567
1568         if (chan_is_physical(d40c)) {
1569                 if (d40c->phy_chan->num % 2 == 0)
1570                         active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1571                 else
1572                         active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1573
1574                 status = (readl(active_reg) &
1575                           D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1576                         D40_CHAN_POS(d40c->phy_chan->num);
1577                 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1578                         is_paused = true;
1579
1580                 goto _exit;
1581         }
1582
1583         if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1584             d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1585                 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
1586                 status = readl(chanbase + D40_CHAN_REG_SDLNK);
1587         } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1588                 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
1589                 status = readl(chanbase + D40_CHAN_REG_SSLNK);
1590         } else {
1591                 chan_err(d40c, "Unknown direction\n");
1592                 goto _exit;
1593         }
1594
1595         status = (status & D40_EVENTLINE_MASK(event)) >>
1596                 D40_EVENTLINE_POS(event);
1597
1598         if (status != D40_DMA_RUN)
1599                 is_paused = true;
1600 _exit:
1601         spin_unlock_irqrestore(&d40c->lock, flags);
1602         return is_paused;
1603
1604 }
1605
1606
1607 static u32 stedma40_residue(struct dma_chan *chan)
1608 {
1609         struct d40_chan *d40c =
1610                 container_of(chan, struct d40_chan, chan);
1611         u32 bytes_left;
1612         unsigned long flags;
1613
1614         spin_lock_irqsave(&d40c->lock, flags);
1615         bytes_left = d40_residue(d40c);
1616         spin_unlock_irqrestore(&d40c->lock, flags);
1617
1618         return bytes_left;
1619 }
1620
1621 static int
1622 d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc,
1623                 struct scatterlist *sg_src, struct scatterlist *sg_dst,
1624                 unsigned int sg_len, enum dma_data_direction direction,
1625                 dma_addr_t dev_addr)
1626 {
1627         struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
1628         struct stedma40_half_channel_info *src_info = &cfg->src_info;
1629         struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
1630
1631         if (direction == DMA_NONE) {
1632                 /* memcpy */
1633                 (void) d40_log_sg_to_lli(sg_src, sg_len,
1634                                          desc->lli_log.src,
1635                                          chan->log_def.lcsp1,
1636                                          src_info->data_width,
1637                                          dst_info->data_width);
1638
1639                 (void) d40_log_sg_to_lli(sg_dst, sg_len,
1640                                          desc->lli_log.dst,
1641                                          chan->log_def.lcsp3,
1642                                          dst_info->data_width,
1643                                          src_info->data_width);
1644         } else {
1645                 unsigned int total_size;
1646
1647                 total_size = d40_log_sg_to_dev(sg_src, sg_len,
1648                                                &desc->lli_log,
1649                                                &chan->log_def,
1650                                                src_info->data_width,
1651                                                dst_info->data_width,
1652                                                direction, dev_addr);
1653                 if (total_size < 0)
1654                         return -EINVAL;
1655         }
1656
1657         return 0;
1658 }
1659
1660 static int
1661 d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc,
1662                 struct scatterlist *sg_src, struct scatterlist *sg_dst,
1663                 unsigned int sg_len, enum dma_data_direction direction,
1664                 dma_addr_t dev_addr)
1665 {
1666         dma_addr_t src_dev_addr = direction == DMA_FROM_DEVICE ? dev_addr : 0;
1667         dma_addr_t dst_dev_addr = direction == DMA_TO_DEVICE ? dev_addr : 0;
1668         struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
1669         struct stedma40_half_channel_info *src_info = &cfg->src_info;
1670         struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
1671         int ret;
1672
1673         ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr,
1674                                 desc->lli_phy.src,
1675                                 virt_to_phys(desc->lli_phy.src),
1676                                 chan->src_def_cfg,
1677                                 src_info->data_width,
1678                                 dst_info->data_width,
1679                                 src_info->psize);
1680
1681         ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr,
1682                                 desc->lli_phy.dst,
1683                                 virt_to_phys(desc->lli_phy.dst),
1684                                 chan->dst_def_cfg,
1685                                 dst_info->data_width,
1686                                 src_info->data_width,
1687                                 dst_info->psize);
1688
1689         dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr,
1690                                    desc->lli_pool.size, DMA_TO_DEVICE);
1691
1692         return ret < 0 ? ret : 0;
1693 }
1694
1695
1696 static struct d40_desc *
1697 d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg,
1698               unsigned int sg_len, unsigned long dma_flags)
1699 {
1700         struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
1701         struct d40_desc *desc;
1702         int ret;
1703
1704         desc = d40_desc_get(chan);
1705         if (!desc)
1706                 return NULL;
1707
1708         desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width,
1709                                         cfg->dst_info.data_width);
1710         if (desc->lli_len < 0) {
1711                 chan_err(chan, "Unaligned size\n");
1712                 goto err;
1713         }
1714
1715         ret = d40_pool_lli_alloc(chan, desc, desc->lli_len);
1716         if (ret < 0) {
1717                 chan_err(chan, "Could not allocate lli\n");
1718                 goto err;
1719         }
1720
1721
1722         desc->lli_current = 0;
1723         desc->txd.flags = dma_flags;
1724         desc->txd.tx_submit = d40_tx_submit;
1725
1726         dma_async_tx_descriptor_init(&desc->txd, &chan->chan);
1727
1728         return desc;
1729
1730 err:
1731         d40_desc_free(chan, desc);
1732         return NULL;
1733 }
1734
1735 static dma_addr_t
1736 d40_get_dev_addr(struct d40_chan *chan, enum dma_data_direction direction)
1737 {
1738         struct stedma40_platform_data *plat = chan->base->plat_data;
1739         struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
1740         dma_addr_t addr;
1741
1742         if (chan->runtime_addr)
1743                 return chan->runtime_addr;
1744
1745         if (direction == DMA_FROM_DEVICE)
1746                 addr = plat->dev_rx[cfg->src_dev_type];
1747         else if (direction == DMA_TO_DEVICE)
1748                 addr = plat->dev_tx[cfg->dst_dev_type];
1749
1750         return addr;
1751 }
1752
1753 static struct dma_async_tx_descriptor *
1754 d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
1755             struct scatterlist *sg_dst, unsigned int sg_len,
1756             enum dma_data_direction direction, unsigned long dma_flags)
1757 {
1758         struct d40_chan *chan = container_of(dchan, struct d40_chan, chan);
1759         dma_addr_t dev_addr = 0;
1760         struct d40_desc *desc;
1761         unsigned long flags;
1762         int ret;
1763
1764         if (!chan->phy_chan) {
1765                 chan_err(chan, "Cannot prepare unallocated channel\n");
1766                 return NULL;
1767         }
1768
1769         spin_lock_irqsave(&chan->lock, flags);
1770
1771         desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags);
1772         if (desc == NULL)
1773                 goto err;
1774
1775         if (direction != DMA_NONE)
1776                 dev_addr = d40_get_dev_addr(chan, direction);
1777
1778         if (chan_is_logical(chan))
1779                 ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
1780                                       sg_len, direction, dev_addr);
1781         else
1782                 ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst,
1783                                       sg_len, direction, dev_addr);
1784
1785         if (ret) {
1786                 chan_err(chan, "Failed to prepare %s sg job: %d\n",
1787                          chan_is_logical(chan) ? "log" : "phy", ret);
1788                 goto err;
1789         }
1790
1791         spin_unlock_irqrestore(&chan->lock, flags);
1792
1793         return &desc->txd;
1794
1795 err:
1796         if (desc)
1797                 d40_desc_free(chan, desc);
1798         spin_unlock_irqrestore(&chan->lock, flags);
1799         return NULL;
1800 }
1801
1802 bool stedma40_filter(struct dma_chan *chan, void *data)
1803 {
1804         struct stedma40_chan_cfg *info = data;
1805         struct d40_chan *d40c =
1806                 container_of(chan, struct d40_chan, chan);
1807         int err;
1808
1809         if (data) {
1810                 err = d40_validate_conf(d40c, info);
1811                 if (!err)
1812                         d40c->dma_cfg = *info;
1813         } else
1814                 err = d40_config_memcpy(d40c);
1815
1816         if (!err)
1817                 d40c->configured = true;
1818
1819         return err == 0;
1820 }
1821 EXPORT_SYMBOL(stedma40_filter);
1822
1823 static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src)
1824 {
1825         bool realtime = d40c->dma_cfg.realtime;
1826         bool highprio = d40c->dma_cfg.high_priority;
1827         u32 prioreg = highprio ? D40_DREG_PSEG1 : D40_DREG_PCEG1;
1828         u32 rtreg = realtime ? D40_DREG_RSEG1 : D40_DREG_RCEG1;
1829         u32 event = D40_TYPE_TO_EVENT(dev_type);
1830         u32 group = D40_TYPE_TO_GROUP(dev_type);
1831         u32 bit = 1 << event;
1832
1833         /* Destination event lines are stored in the upper halfword */
1834         if (!src)
1835                 bit <<= 16;
1836
1837         writel(bit, d40c->base->virtbase + prioreg + group * 4);
1838         writel(bit, d40c->base->virtbase + rtreg + group * 4);
1839 }
1840
1841 static void d40_set_prio_realtime(struct d40_chan *d40c)
1842 {
1843         if (d40c->base->rev < 3)
1844                 return;
1845
1846         if ((d40c->dma_cfg.dir ==  STEDMA40_PERIPH_TO_MEM) ||
1847             (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
1848                 __d40_set_prio_rt(d40c, d40c->dma_cfg.src_dev_type, true);
1849
1850         if ((d40c->dma_cfg.dir ==  STEDMA40_MEM_TO_PERIPH) ||
1851             (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
1852                 __d40_set_prio_rt(d40c, d40c->dma_cfg.dst_dev_type, false);
1853 }
1854
1855 /* DMA ENGINE functions */
1856 static int d40_alloc_chan_resources(struct dma_chan *chan)
1857 {
1858         int err;
1859         unsigned long flags;
1860         struct d40_chan *d40c =
1861                 container_of(chan, struct d40_chan, chan);
1862         bool is_free_phy;
1863         spin_lock_irqsave(&d40c->lock, flags);
1864
1865         d40c->completed = chan->cookie = 1;
1866
1867         /* If no dma configuration is set use default configuration (memcpy) */
1868         if (!d40c->configured) {
1869                 err = d40_config_memcpy(d40c);
1870                 if (err) {
1871                         chan_err(d40c, "Failed to configure memcpy channel\n");
1872                         goto fail;
1873                 }
1874         }
1875         is_free_phy = (d40c->phy_chan == NULL);
1876
1877         err = d40_allocate_channel(d40c);
1878         if (err) {
1879                 chan_err(d40c, "Failed to allocate channel\n");
1880                 goto fail;
1881         }
1882
1883         /* Fill in basic CFG register values */
1884         d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
1885                     &d40c->dst_def_cfg, chan_is_logical(d40c));
1886
1887         d40_set_prio_realtime(d40c);
1888
1889         if (chan_is_logical(d40c)) {
1890                 d40_log_cfg(&d40c->dma_cfg,
1891                             &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
1892
1893                 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
1894                         d40c->lcpa = d40c->base->lcpa_base +
1895                           d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE;
1896                 else
1897                         d40c->lcpa = d40c->base->lcpa_base +
1898                           d40c->dma_cfg.dst_dev_type *
1899                           D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
1900         }
1901
1902         /*
1903          * Only write channel configuration to the DMA if the physical
1904          * resource is free. In case of multiple logical channels
1905          * on the same physical resource, only the first write is necessary.
1906          */
1907         if (is_free_phy)
1908                 d40_config_write(d40c);
1909 fail:
1910         spin_unlock_irqrestore(&d40c->lock, flags);
1911         return err;
1912 }
1913
1914 static void d40_free_chan_resources(struct dma_chan *chan)
1915 {
1916         struct d40_chan *d40c =
1917                 container_of(chan, struct d40_chan, chan);
1918         int err;
1919         unsigned long flags;
1920
1921         if (d40c->phy_chan == NULL) {
1922                 chan_err(d40c, "Cannot free unallocated channel\n");
1923                 return;
1924         }
1925
1926
1927         spin_lock_irqsave(&d40c->lock, flags);
1928
1929         err = d40_free_dma(d40c);
1930
1931         if (err)
1932                 chan_err(d40c, "Failed to free channel\n");
1933         spin_unlock_irqrestore(&d40c->lock, flags);
1934 }
1935
1936 static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
1937                                                        dma_addr_t dst,
1938                                                        dma_addr_t src,
1939                                                        size_t size,
1940                                                        unsigned long dma_flags)
1941 {
1942         struct scatterlist dst_sg;
1943         struct scatterlist src_sg;
1944
1945         sg_init_table(&dst_sg, 1);
1946         sg_init_table(&src_sg, 1);
1947
1948         sg_dma_address(&dst_sg) = dst;
1949         sg_dma_address(&src_sg) = src;
1950
1951         sg_dma_len(&dst_sg) = size;
1952         sg_dma_len(&src_sg) = size;
1953
1954         return d40_prep_sg(chan, &src_sg, &dst_sg, 1, DMA_NONE, dma_flags);
1955 }
1956
1957 static struct dma_async_tx_descriptor *
1958 d40_prep_memcpy_sg(struct dma_chan *chan,
1959                    struct scatterlist *dst_sg, unsigned int dst_nents,
1960                    struct scatterlist *src_sg, unsigned int src_nents,
1961                    unsigned long dma_flags)
1962 {
1963         if (dst_nents != src_nents)
1964                 return NULL;
1965
1966         return d40_prep_sg(chan, src_sg, dst_sg, src_nents, DMA_NONE, dma_flags);
1967 }
1968
1969 static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
1970                                                          struct scatterlist *sgl,
1971                                                          unsigned int sg_len,
1972                                                          enum dma_data_direction direction,
1973                                                          unsigned long dma_flags)
1974 {
1975         if (direction != DMA_FROM_DEVICE && direction != DMA_TO_DEVICE)
1976                 return NULL;
1977
1978         return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags);
1979 }
1980
1981 static enum dma_status d40_tx_status(struct dma_chan *chan,
1982                                      dma_cookie_t cookie,
1983                                      struct dma_tx_state *txstate)
1984 {
1985         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
1986         dma_cookie_t last_used;
1987         dma_cookie_t last_complete;
1988         int ret;
1989
1990         if (d40c->phy_chan == NULL) {
1991                 chan_err(d40c, "Cannot read status of unallocated channel\n");
1992                 return -EINVAL;
1993         }
1994
1995         last_complete = d40c->completed;
1996         last_used = chan->cookie;
1997
1998         if (d40_is_paused(d40c))
1999                 ret = DMA_PAUSED;
2000         else
2001                 ret = dma_async_is_complete(cookie, last_complete, last_used);
2002
2003         dma_set_tx_state(txstate, last_complete, last_used,
2004                          stedma40_residue(chan));
2005
2006         return ret;
2007 }
2008
2009 static void d40_issue_pending(struct dma_chan *chan)
2010 {
2011         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2012         unsigned long flags;
2013
2014         if (d40c->phy_chan == NULL) {
2015                 chan_err(d40c, "Channel is not allocated!\n");
2016                 return;
2017         }
2018
2019         spin_lock_irqsave(&d40c->lock, flags);
2020
2021         /* Busy means that pending jobs are already being processed */
2022         if (!d40c->busy)
2023                 (void) d40_queue_start(d40c);
2024
2025         spin_unlock_irqrestore(&d40c->lock, flags);
2026 }
2027
2028 /* Runtime reconfiguration extension */
2029 static void d40_set_runtime_config(struct dma_chan *chan,
2030                                struct dma_slave_config *config)
2031 {
2032         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2033         struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
2034         enum dma_slave_buswidth config_addr_width;
2035         dma_addr_t config_addr;
2036         u32 config_maxburst;
2037         enum stedma40_periph_data_width addr_width;
2038         int psize;
2039
2040         if (config->direction == DMA_FROM_DEVICE) {
2041                 dma_addr_t dev_addr_rx =
2042                         d40c->base->plat_data->dev_rx[cfg->src_dev_type];
2043
2044                 config_addr = config->src_addr;
2045                 if (dev_addr_rx)
2046                         dev_dbg(d40c->base->dev,
2047                                 "channel has a pre-wired RX address %08x "
2048                                 "overriding with %08x\n",
2049                                 dev_addr_rx, config_addr);
2050                 if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
2051                         dev_dbg(d40c->base->dev,
2052                                 "channel was not configured for peripheral "
2053                                 "to memory transfer (%d) overriding\n",
2054                                 cfg->dir);
2055                 cfg->dir = STEDMA40_PERIPH_TO_MEM;
2056
2057                 config_addr_width = config->src_addr_width;
2058                 config_maxburst = config->src_maxburst;
2059
2060         } else if (config->direction == DMA_TO_DEVICE) {
2061                 dma_addr_t dev_addr_tx =
2062                         d40c->base->plat_data->dev_tx[cfg->dst_dev_type];
2063
2064                 config_addr = config->dst_addr;
2065                 if (dev_addr_tx)
2066                         dev_dbg(d40c->base->dev,
2067                                 "channel has a pre-wired TX address %08x "
2068                                 "overriding with %08x\n",
2069                                 dev_addr_tx, config_addr);
2070                 if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
2071                         dev_dbg(d40c->base->dev,
2072                                 "channel was not configured for memory "
2073                                 "to peripheral transfer (%d) overriding\n",
2074                                 cfg->dir);
2075                 cfg->dir = STEDMA40_MEM_TO_PERIPH;
2076
2077                 config_addr_width = config->dst_addr_width;
2078                 config_maxburst = config->dst_maxburst;
2079
2080         } else {
2081                 dev_err(d40c->base->dev,
2082                         "unrecognized channel direction %d\n",
2083                         config->direction);
2084                 return;
2085         }
2086
2087         switch (config_addr_width) {
2088         case DMA_SLAVE_BUSWIDTH_1_BYTE:
2089                 addr_width = STEDMA40_BYTE_WIDTH;
2090                 break;
2091         case DMA_SLAVE_BUSWIDTH_2_BYTES:
2092                 addr_width = STEDMA40_HALFWORD_WIDTH;
2093                 break;
2094         case DMA_SLAVE_BUSWIDTH_4_BYTES:
2095                 addr_width = STEDMA40_WORD_WIDTH;
2096                 break;
2097         case DMA_SLAVE_BUSWIDTH_8_BYTES:
2098                 addr_width = STEDMA40_DOUBLEWORD_WIDTH;
2099                 break;
2100         default:
2101                 dev_err(d40c->base->dev,
2102                         "illegal peripheral address width "
2103                         "requested (%d)\n",
2104                         config->src_addr_width);
2105                 return;
2106         }
2107
2108         if (chan_is_logical(d40c)) {
2109                 if (config_maxburst >= 16)
2110                         psize = STEDMA40_PSIZE_LOG_16;
2111                 else if (config_maxburst >= 8)
2112                         psize = STEDMA40_PSIZE_LOG_8;
2113                 else if (config_maxburst >= 4)
2114                         psize = STEDMA40_PSIZE_LOG_4;
2115                 else
2116                         psize = STEDMA40_PSIZE_LOG_1;
2117         } else {
2118                 if (config_maxburst >= 16)
2119                         psize = STEDMA40_PSIZE_PHY_16;
2120                 else if (config_maxburst >= 8)
2121                         psize = STEDMA40_PSIZE_PHY_8;
2122                 else if (config_maxburst >= 4)
2123                         psize = STEDMA40_PSIZE_PHY_4;
2124                 else if (config_maxburst >= 2)
2125                         psize = STEDMA40_PSIZE_PHY_2;
2126                 else
2127                         psize = STEDMA40_PSIZE_PHY_1;
2128         }
2129
2130         /* Set up all the endpoint configs */
2131         cfg->src_info.data_width = addr_width;
2132         cfg->src_info.psize = psize;
2133         cfg->src_info.big_endian = false;
2134         cfg->src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2135         cfg->dst_info.data_width = addr_width;
2136         cfg->dst_info.psize = psize;
2137         cfg->dst_info.big_endian = false;
2138         cfg->dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2139
2140         /* Fill in register values */
2141         if (chan_is_logical(d40c))
2142                 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2143         else
2144                 d40_phy_cfg(cfg, &d40c->src_def_cfg,
2145                             &d40c->dst_def_cfg, false);
2146
2147         /* These settings will take precedence later */
2148         d40c->runtime_addr = config_addr;
2149         d40c->runtime_direction = config->direction;
2150         dev_dbg(d40c->base->dev,
2151                 "configured channel %s for %s, data width %d, "
2152                 "maxburst %d bytes, LE, no flow control\n",
2153                 dma_chan_name(chan),
2154                 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
2155                 config_addr_width,
2156                 config_maxburst);
2157 }
2158
2159 static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
2160                        unsigned long arg)
2161 {
2162         unsigned long flags;
2163         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2164
2165         if (d40c->phy_chan == NULL) {
2166                 chan_err(d40c, "Channel is not allocated!\n");
2167                 return -EINVAL;
2168         }
2169
2170         switch (cmd) {
2171         case DMA_TERMINATE_ALL:
2172                 spin_lock_irqsave(&d40c->lock, flags);
2173                 d40_term_all(d40c);
2174                 spin_unlock_irqrestore(&d40c->lock, flags);
2175                 return 0;
2176         case DMA_PAUSE:
2177                 return d40_pause(chan);
2178         case DMA_RESUME:
2179                 return d40_resume(chan);
2180         case DMA_SLAVE_CONFIG:
2181                 d40_set_runtime_config(chan,
2182                         (struct dma_slave_config *) arg);
2183                 return 0;
2184         default:
2185                 break;
2186         }
2187
2188         /* Other commands are unimplemented */
2189         return -ENXIO;
2190 }
2191
2192 /* Initialization functions */
2193
2194 static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
2195                                  struct d40_chan *chans, int offset,
2196                                  int num_chans)
2197 {
2198         int i = 0;
2199         struct d40_chan *d40c;
2200
2201         INIT_LIST_HEAD(&dma->channels);
2202
2203         for (i = offset; i < offset + num_chans; i++) {
2204                 d40c = &chans[i];
2205                 d40c->base = base;
2206                 d40c->chan.device = dma;
2207
2208                 spin_lock_init(&d40c->lock);
2209
2210                 d40c->log_num = D40_PHY_CHAN;
2211
2212                 INIT_LIST_HEAD(&d40c->active);
2213                 INIT_LIST_HEAD(&d40c->queue);
2214                 INIT_LIST_HEAD(&d40c->client);
2215
2216                 tasklet_init(&d40c->tasklet, dma_tasklet,
2217                              (unsigned long) d40c);
2218
2219                 list_add_tail(&d40c->chan.device_node,
2220                               &dma->channels);
2221         }
2222 }
2223
2224 static int __init d40_dmaengine_init(struct d40_base *base,
2225                                      int num_reserved_chans)
2226 {
2227         int err ;
2228
2229         d40_chan_init(base, &base->dma_slave, base->log_chans,
2230                       0, base->num_log_chans);
2231
2232         dma_cap_zero(base->dma_slave.cap_mask);
2233         dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
2234
2235         base->dma_slave.device_alloc_chan_resources = d40_alloc_chan_resources;
2236         base->dma_slave.device_free_chan_resources = d40_free_chan_resources;
2237         base->dma_slave.device_prep_dma_memcpy = d40_prep_memcpy;
2238         base->dma_slave.device_prep_dma_sg = d40_prep_memcpy_sg;
2239         base->dma_slave.device_prep_slave_sg = d40_prep_slave_sg;
2240         base->dma_slave.device_tx_status = d40_tx_status;
2241         base->dma_slave.device_issue_pending = d40_issue_pending;
2242         base->dma_slave.device_control = d40_control;
2243         base->dma_slave.dev = base->dev;
2244
2245         err = dma_async_device_register(&base->dma_slave);
2246
2247         if (err) {
2248                 d40_err(base->dev, "Failed to register slave channels\n");
2249                 goto failure1;
2250         }
2251
2252         d40_chan_init(base, &base->dma_memcpy, base->log_chans,
2253                       base->num_log_chans, base->plat_data->memcpy_len);
2254
2255         dma_cap_zero(base->dma_memcpy.cap_mask);
2256         dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
2257         dma_cap_set(DMA_SG, base->dma_slave.cap_mask);
2258
2259         base->dma_memcpy.device_alloc_chan_resources = d40_alloc_chan_resources;
2260         base->dma_memcpy.device_free_chan_resources = d40_free_chan_resources;
2261         base->dma_memcpy.device_prep_dma_memcpy = d40_prep_memcpy;
2262         base->dma_slave.device_prep_dma_sg = d40_prep_memcpy_sg;
2263         base->dma_memcpy.device_prep_slave_sg = d40_prep_slave_sg;
2264         base->dma_memcpy.device_tx_status = d40_tx_status;
2265         base->dma_memcpy.device_issue_pending = d40_issue_pending;
2266         base->dma_memcpy.device_control = d40_control;
2267         base->dma_memcpy.dev = base->dev;
2268         /*
2269          * This controller can only access address at even
2270          * 32bit boundaries, i.e. 2^2
2271          */
2272         base->dma_memcpy.copy_align = 2;
2273
2274         err = dma_async_device_register(&base->dma_memcpy);
2275
2276         if (err) {
2277                 d40_err(base->dev,
2278                         "Failed to regsiter memcpy only channels\n");
2279                 goto failure2;
2280         }
2281
2282         d40_chan_init(base, &base->dma_both, base->phy_chans,
2283                       0, num_reserved_chans);
2284
2285         dma_cap_zero(base->dma_both.cap_mask);
2286         dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
2287         dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
2288         dma_cap_set(DMA_SG, base->dma_slave.cap_mask);
2289
2290         base->dma_both.device_alloc_chan_resources = d40_alloc_chan_resources;
2291         base->dma_both.device_free_chan_resources = d40_free_chan_resources;
2292         base->dma_both.device_prep_dma_memcpy = d40_prep_memcpy;
2293         base->dma_slave.device_prep_dma_sg = d40_prep_memcpy_sg;
2294         base->dma_both.device_prep_slave_sg = d40_prep_slave_sg;
2295         base->dma_both.device_tx_status = d40_tx_status;
2296         base->dma_both.device_issue_pending = d40_issue_pending;
2297         base->dma_both.device_control = d40_control;
2298         base->dma_both.dev = base->dev;
2299         base->dma_both.copy_align = 2;
2300         err = dma_async_device_register(&base->dma_both);
2301
2302         if (err) {
2303                 d40_err(base->dev,
2304                         "Failed to register logical and physical capable channels\n");
2305                 goto failure3;
2306         }
2307         return 0;
2308 failure3:
2309         dma_async_device_unregister(&base->dma_memcpy);
2310 failure2:
2311         dma_async_device_unregister(&base->dma_slave);
2312 failure1:
2313         return err;
2314 }
2315
2316 /* Initialization functions. */
2317
2318 static int __init d40_phy_res_init(struct d40_base *base)
2319 {
2320         int i;
2321         int num_phy_chans_avail = 0;
2322         u32 val[2];
2323         int odd_even_bit = -2;
2324
2325         val[0] = readl(base->virtbase + D40_DREG_PRSME);
2326         val[1] = readl(base->virtbase + D40_DREG_PRSMO);
2327
2328         for (i = 0; i < base->num_phy_chans; i++) {
2329                 base->phy_res[i].num = i;
2330                 odd_even_bit += 2 * ((i % 2) == 0);
2331                 if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
2332                         /* Mark security only channels as occupied */
2333                         base->phy_res[i].allocated_src = D40_ALLOC_PHY;
2334                         base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
2335                 } else {
2336                         base->phy_res[i].allocated_src = D40_ALLOC_FREE;
2337                         base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
2338                         num_phy_chans_avail++;
2339                 }
2340                 spin_lock_init(&base->phy_res[i].lock);
2341         }
2342
2343         /* Mark disabled channels as occupied */
2344         for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
2345                 int chan = base->plat_data->disabled_channels[i];
2346
2347                 base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
2348                 base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
2349                 num_phy_chans_avail--;
2350         }
2351
2352         dev_info(base->dev, "%d of %d physical DMA channels available\n",
2353                  num_phy_chans_avail, base->num_phy_chans);
2354
2355         /* Verify settings extended vs standard */
2356         val[0] = readl(base->virtbase + D40_DREG_PRTYP);
2357
2358         for (i = 0; i < base->num_phy_chans; i++) {
2359
2360                 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
2361                     (val[0] & 0x3) != 1)
2362                         dev_info(base->dev,
2363                                  "[%s] INFO: channel %d is misconfigured (%d)\n",
2364                                  __func__, i, val[0] & 0x3);
2365
2366                 val[0] = val[0] >> 2;
2367         }
2368
2369         return num_phy_chans_avail;
2370 }
2371
2372 static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
2373 {
2374         static const struct d40_reg_val dma_id_regs[] = {
2375                 /* Peripheral Id */
2376                 { .reg = D40_DREG_PERIPHID0, .val = 0x0040},
2377                 { .reg = D40_DREG_PERIPHID1, .val = 0x0000},
2378                 /*
2379                  * D40_DREG_PERIPHID2 Depends on HW revision:
2380                  *  DB8500ed has 0x0008,
2381                  *  ? has 0x0018,
2382                  *  DB8500v1 has 0x0028
2383                  *  DB8500v2 has 0x0038
2384                  */
2385                 { .reg = D40_DREG_PERIPHID3, .val = 0x0000},
2386
2387                 /* PCell Id */
2388                 { .reg = D40_DREG_CELLID0, .val = 0x000d},
2389                 { .reg = D40_DREG_CELLID1, .val = 0x00f0},
2390                 { .reg = D40_DREG_CELLID2, .val = 0x0005},
2391                 { .reg = D40_DREG_CELLID3, .val = 0x00b1}
2392         };
2393         struct stedma40_platform_data *plat_data;
2394         struct clk *clk = NULL;
2395         void __iomem *virtbase = NULL;
2396         struct resource *res = NULL;
2397         struct d40_base *base = NULL;
2398         int num_log_chans = 0;
2399         int num_phy_chans;
2400         int i;
2401         u32 val;
2402         u32 rev;
2403
2404         clk = clk_get(&pdev->dev, NULL);
2405
2406         if (IS_ERR(clk)) {
2407                 d40_err(&pdev->dev, "No matching clock found\n");
2408                 goto failure;
2409         }
2410
2411         clk_enable(clk);
2412
2413         /* Get IO for DMAC base address */
2414         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
2415         if (!res)
2416                 goto failure;
2417
2418         if (request_mem_region(res->start, resource_size(res),
2419                                D40_NAME " I/O base") == NULL)
2420                 goto failure;
2421
2422         virtbase = ioremap(res->start, resource_size(res));
2423         if (!virtbase)
2424                 goto failure;
2425
2426         /* HW version check */
2427         for (i = 0; i < ARRAY_SIZE(dma_id_regs); i++) {
2428                 if (dma_id_regs[i].val !=
2429                     readl(virtbase + dma_id_regs[i].reg)) {
2430                         d40_err(&pdev->dev,
2431                                 "Unknown hardware! Expected 0x%x at 0x%x but got 0x%x\n",
2432                                 dma_id_regs[i].val,
2433                                 dma_id_regs[i].reg,
2434                                 readl(virtbase + dma_id_regs[i].reg));
2435                         goto failure;
2436                 }
2437         }
2438
2439         /* Get silicon revision and designer */
2440         val = readl(virtbase + D40_DREG_PERIPHID2);
2441
2442         if ((val & D40_DREG_PERIPHID2_DESIGNER_MASK) !=
2443             D40_HW_DESIGNER) {
2444                 d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n",
2445                         val & D40_DREG_PERIPHID2_DESIGNER_MASK,
2446                         D40_HW_DESIGNER);
2447                 goto failure;
2448         }
2449
2450         rev = (val & D40_DREG_PERIPHID2_REV_MASK) >>
2451                 D40_DREG_PERIPHID2_REV_POS;
2452
2453         /* The number of physical channels on this HW */
2454         num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
2455
2456         dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n",
2457                  rev, res->start);
2458
2459         plat_data = pdev->dev.platform_data;
2460
2461         /* Count the number of logical channels in use */
2462         for (i = 0; i < plat_data->dev_len; i++)
2463                 if (plat_data->dev_rx[i] != 0)
2464                         num_log_chans++;
2465
2466         for (i = 0; i < plat_data->dev_len; i++)
2467                 if (plat_data->dev_tx[i] != 0)
2468                         num_log_chans++;
2469
2470         base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
2471                        (num_phy_chans + num_log_chans + plat_data->memcpy_len) *
2472                        sizeof(struct d40_chan), GFP_KERNEL);
2473
2474         if (base == NULL) {
2475                 d40_err(&pdev->dev, "Out of memory\n");
2476                 goto failure;
2477         }
2478
2479         base->rev = rev;
2480         base->clk = clk;
2481         base->num_phy_chans = num_phy_chans;
2482         base->num_log_chans = num_log_chans;
2483         base->phy_start = res->start;
2484         base->phy_size = resource_size(res);
2485         base->virtbase = virtbase;
2486         base->plat_data = plat_data;
2487         base->dev = &pdev->dev;
2488         base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
2489         base->log_chans = &base->phy_chans[num_phy_chans];
2490
2491         base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res),
2492                                 GFP_KERNEL);
2493         if (!base->phy_res)
2494                 goto failure;
2495
2496         base->lookup_phy_chans = kzalloc(num_phy_chans *
2497                                          sizeof(struct d40_chan *),
2498                                          GFP_KERNEL);
2499         if (!base->lookup_phy_chans)
2500                 goto failure;
2501
2502         if (num_log_chans + plat_data->memcpy_len) {
2503                 /*
2504                  * The max number of logical channels are event lines for all
2505                  * src devices and dst devices
2506                  */
2507                 base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 *
2508                                                  sizeof(struct d40_chan *),
2509                                                  GFP_KERNEL);
2510                 if (!base->lookup_log_chans)
2511                         goto failure;
2512         }
2513
2514         base->lcla_pool.alloc_map = kzalloc(num_phy_chans *
2515                                             sizeof(struct d40_desc *) *
2516                                             D40_LCLA_LINK_PER_EVENT_GRP,
2517                                             GFP_KERNEL);
2518         if (!base->lcla_pool.alloc_map)
2519                 goto failure;
2520
2521         base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
2522                                             0, SLAB_HWCACHE_ALIGN,
2523                                             NULL);
2524         if (base->desc_slab == NULL)
2525                 goto failure;
2526
2527         return base;
2528
2529 failure:
2530         if (!IS_ERR(clk)) {
2531                 clk_disable(clk);
2532                 clk_put(clk);
2533         }
2534         if (virtbase)
2535                 iounmap(virtbase);
2536         if (res)
2537                 release_mem_region(res->start,
2538                                    resource_size(res));
2539         if (virtbase)
2540                 iounmap(virtbase);
2541
2542         if (base) {
2543                 kfree(base->lcla_pool.alloc_map);
2544                 kfree(base->lookup_log_chans);
2545                 kfree(base->lookup_phy_chans);
2546                 kfree(base->phy_res);
2547                 kfree(base);
2548         }
2549
2550         return NULL;
2551 }
2552
2553 static void __init d40_hw_init(struct d40_base *base)
2554 {
2555
2556         static const struct d40_reg_val dma_init_reg[] = {
2557                 /* Clock every part of the DMA block from start */
2558                 { .reg = D40_DREG_GCC,    .val = 0x0000ff01},
2559
2560                 /* Interrupts on all logical channels */
2561                 { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
2562                 { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
2563                 { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
2564                 { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
2565                 { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
2566                 { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
2567                 { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
2568                 { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
2569                 { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
2570                 { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
2571                 { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
2572                 { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
2573         };
2574         int i;
2575         u32 prmseo[2] = {0, 0};
2576         u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
2577         u32 pcmis = 0;
2578         u32 pcicr = 0;
2579
2580         for (i = 0; i < ARRAY_SIZE(dma_init_reg); i++)
2581                 writel(dma_init_reg[i].val,
2582                        base->virtbase + dma_init_reg[i].reg);
2583
2584         /* Configure all our dma channels to default settings */
2585         for (i = 0; i < base->num_phy_chans; i++) {
2586
2587                 activeo[i % 2] = activeo[i % 2] << 2;
2588
2589                 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
2590                     == D40_ALLOC_PHY) {
2591                         activeo[i % 2] |= 3;
2592                         continue;
2593                 }
2594
2595                 /* Enable interrupt # */
2596                 pcmis = (pcmis << 1) | 1;
2597
2598                 /* Clear interrupt # */
2599                 pcicr = (pcicr << 1) | 1;
2600
2601                 /* Set channel to physical mode */
2602                 prmseo[i % 2] = prmseo[i % 2] << 2;
2603                 prmseo[i % 2] |= 1;
2604
2605         }
2606
2607         writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
2608         writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
2609         writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
2610         writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
2611
2612         /* Write which interrupt to enable */
2613         writel(pcmis, base->virtbase + D40_DREG_PCMIS);
2614
2615         /* Write which interrupt to clear */
2616         writel(pcicr, base->virtbase + D40_DREG_PCICR);
2617
2618 }
2619
2620 static int __init d40_lcla_allocate(struct d40_base *base)
2621 {
2622         struct d40_lcla_pool *pool = &base->lcla_pool;
2623         unsigned long *page_list;
2624         int i, j;
2625         int ret = 0;
2626
2627         /*
2628          * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
2629          * To full fill this hardware requirement without wasting 256 kb
2630          * we allocate pages until we get an aligned one.
2631          */
2632         page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
2633                             GFP_KERNEL);
2634
2635         if (!page_list) {
2636                 ret = -ENOMEM;
2637                 goto failure;
2638         }
2639
2640         /* Calculating how many pages that are required */
2641         base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
2642
2643         for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
2644                 page_list[i] = __get_free_pages(GFP_KERNEL,
2645                                                 base->lcla_pool.pages);
2646                 if (!page_list[i]) {
2647
2648                         d40_err(base->dev, "Failed to allocate %d pages.\n",
2649                                 base->lcla_pool.pages);
2650
2651                         for (j = 0; j < i; j++)
2652                                 free_pages(page_list[j], base->lcla_pool.pages);
2653                         goto failure;
2654                 }
2655
2656                 if ((virt_to_phys((void *)page_list[i]) &
2657                      (LCLA_ALIGNMENT - 1)) == 0)
2658                         break;
2659         }
2660
2661         for (j = 0; j < i; j++)
2662                 free_pages(page_list[j], base->lcla_pool.pages);
2663
2664         if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
2665                 base->lcla_pool.base = (void *)page_list[i];
2666         } else {
2667                 /*
2668                  * After many attempts and no succees with finding the correct
2669                  * alignment, try with allocating a big buffer.
2670                  */
2671                 dev_warn(base->dev,
2672                          "[%s] Failed to get %d pages @ 18 bit align.\n",
2673                          __func__, base->lcla_pool.pages);
2674                 base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
2675                                                          base->num_phy_chans +
2676                                                          LCLA_ALIGNMENT,
2677                                                          GFP_KERNEL);
2678                 if (!base->lcla_pool.base_unaligned) {
2679                         ret = -ENOMEM;
2680                         goto failure;
2681                 }
2682
2683                 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
2684                                                  LCLA_ALIGNMENT);
2685         }
2686
2687         pool->dma_addr = dma_map_single(base->dev, pool->base,
2688                                         SZ_1K * base->num_phy_chans,
2689                                         DMA_TO_DEVICE);
2690         if (dma_mapping_error(base->dev, pool->dma_addr)) {
2691                 pool->dma_addr = 0;
2692                 ret = -ENOMEM;
2693                 goto failure;
2694         }
2695
2696         writel(virt_to_phys(base->lcla_pool.base),
2697                base->virtbase + D40_DREG_LCLA);
2698 failure:
2699         kfree(page_list);
2700         return ret;
2701 }
2702
2703 static int __init d40_probe(struct platform_device *pdev)
2704 {
2705         int err;
2706         int ret = -ENOENT;
2707         struct d40_base *base;
2708         struct resource *res = NULL;
2709         int num_reserved_chans;
2710         u32 val;
2711
2712         base = d40_hw_detect_init(pdev);
2713
2714         if (!base)
2715                 goto failure;
2716
2717         num_reserved_chans = d40_phy_res_init(base);
2718
2719         platform_set_drvdata(pdev, base);
2720
2721         spin_lock_init(&base->interrupt_lock);
2722         spin_lock_init(&base->execmd_lock);
2723
2724         /* Get IO for logical channel parameter address */
2725         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
2726         if (!res) {
2727                 ret = -ENOENT;
2728                 d40_err(&pdev->dev, "No \"lcpa\" memory resource\n");
2729                 goto failure;
2730         }
2731         base->lcpa_size = resource_size(res);
2732         base->phy_lcpa = res->start;
2733
2734         if (request_mem_region(res->start, resource_size(res),
2735                                D40_NAME " I/O lcpa") == NULL) {
2736                 ret = -EBUSY;
2737                 d40_err(&pdev->dev,
2738                         "Failed to request LCPA region 0x%x-0x%x\n",
2739                         res->start, res->end);
2740                 goto failure;
2741         }
2742
2743         /* We make use of ESRAM memory for this. */
2744         val = readl(base->virtbase + D40_DREG_LCPA);
2745         if (res->start != val && val != 0) {
2746                 dev_warn(&pdev->dev,
2747                          "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
2748                          __func__, val, res->start);
2749         } else
2750                 writel(res->start, base->virtbase + D40_DREG_LCPA);
2751
2752         base->lcpa_base = ioremap(res->start, resource_size(res));
2753         if (!base->lcpa_base) {
2754                 ret = -ENOMEM;
2755                 d40_err(&pdev->dev, "Failed to ioremap LCPA region\n");
2756                 goto failure;
2757         }
2758
2759         ret = d40_lcla_allocate(base);
2760         if (ret) {
2761                 d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
2762                 goto failure;
2763         }
2764
2765         spin_lock_init(&base->lcla_pool.lock);
2766
2767         base->irq = platform_get_irq(pdev, 0);
2768
2769         ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
2770         if (ret) {
2771                 d40_err(&pdev->dev, "No IRQ defined\n");
2772                 goto failure;
2773         }
2774
2775         err = d40_dmaengine_init(base, num_reserved_chans);
2776         if (err)
2777                 goto failure;
2778
2779         d40_hw_init(base);
2780
2781         dev_info(base->dev, "initialized\n");
2782         return 0;
2783
2784 failure:
2785         if (base) {
2786                 if (base->desc_slab)
2787                         kmem_cache_destroy(base->desc_slab);
2788                 if (base->virtbase)
2789                         iounmap(base->virtbase);
2790
2791                 if (base->lcla_pool.dma_addr)
2792                         dma_unmap_single(base->dev, base->lcla_pool.dma_addr,
2793                                          SZ_1K * base->num_phy_chans,
2794                                          DMA_TO_DEVICE);
2795
2796                 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
2797                         free_pages((unsigned long)base->lcla_pool.base,
2798                                    base->lcla_pool.pages);
2799
2800                 kfree(base->lcla_pool.base_unaligned);
2801
2802                 if (base->phy_lcpa)
2803                         release_mem_region(base->phy_lcpa,
2804                                            base->lcpa_size);
2805                 if (base->phy_start)
2806                         release_mem_region(base->phy_start,
2807                                            base->phy_size);
2808                 if (base->clk) {
2809                         clk_disable(base->clk);
2810                         clk_put(base->clk);
2811                 }
2812
2813                 kfree(base->lcla_pool.alloc_map);
2814                 kfree(base->lookup_log_chans);
2815                 kfree(base->lookup_phy_chans);
2816                 kfree(base->phy_res);
2817                 kfree(base);
2818         }
2819
2820         d40_err(&pdev->dev, "probe failed\n");
2821         return ret;
2822 }
2823
2824 static struct platform_driver d40_driver = {
2825         .driver = {
2826                 .owner = THIS_MODULE,
2827                 .name  = D40_NAME,
2828         },
2829 };
2830
2831 static int __init stedma40_init(void)
2832 {
2833         return platform_driver_probe(&d40_driver, d40_probe);
2834 }
2835 arch_initcall(stedma40_init);