DMAENGINE: ste_dma40: No need reading, masking and setting a set register
[linux-2.6.git] / drivers / dma / ste_dma40.c
1 /*
2  * driver/dma/ste_dma40.c
3  *
4  * Copyright (C) ST-Ericsson 2007-2010
5  * License terms: GNU General Public License (GPL) version 2
6  * Author: Per Friden <per.friden@stericsson.com>
7  * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
8  *
9  */
10
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/dmaengine.h>
14 #include <linux/platform_device.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17
18 #include <plat/ste_dma40.h>
19
20 #include "ste_dma40_ll.h"
21
22 #define D40_NAME "dma40"
23
24 #define D40_PHY_CHAN -1
25
26 /* For masking out/in 2 bit channel positions */
27 #define D40_CHAN_POS(chan)  (2 * (chan / 2))
28 #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
29
30 /* Maximum iterations taken before giving up suspending a channel */
31 #define D40_SUSPEND_MAX_IT 500
32
33 /* Hardware requirement on LCLA alignment */
34 #define LCLA_ALIGNMENT 0x40000
35 /* Attempts before giving up to trying to get pages that are aligned */
36 #define MAX_LCLA_ALLOC_ATTEMPTS 256
37
38 /* Bit markings for allocation map */
39 #define D40_ALLOC_FREE          (1 << 31)
40 #define D40_ALLOC_PHY           (1 << 30)
41 #define D40_ALLOC_LOG_FREE      0
42
43 /* Hardware designer of the block */
44 #define D40_PERIPHID2_DESIGNER 0x8
45
46 /**
47  * enum 40_command - The different commands and/or statuses.
48  *
49  * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
50  * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
51  * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
52  * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
53  */
54 enum d40_command {
55         D40_DMA_STOP            = 0,
56         D40_DMA_RUN             = 1,
57         D40_DMA_SUSPEND_REQ     = 2,
58         D40_DMA_SUSPENDED       = 3
59 };
60
61 /**
62  * struct d40_lli_pool - Structure for keeping LLIs in memory
63  *
64  * @base: Pointer to memory area when the pre_alloc_lli's are not large
65  * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
66  * pre_alloc_lli is used.
67  * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
68  * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
69  * one buffer to one buffer.
70  */
71 struct d40_lli_pool {
72         void    *base;
73         int      size;
74         /* Space for dst and src, plus an extra for padding */
75         u8       pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
76 };
77
78 /**
79  * struct d40_desc - A descriptor is one DMA job.
80  *
81  * @lli_phy: LLI settings for physical channel. Both src and dst=
82  * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
83  * lli_len equals one.
84  * @lli_log: Same as above but for logical channels.
85  * @lli_pool: The pool with two entries pre-allocated.
86  * @lli_len: Number of llis of current descriptor.
87  * @lli_count: Number of transfered llis.
88  * @lli_tx_len: Max number of LLIs per transfer, there can be
89  * many transfer for one descriptor.
90  * @txd: DMA engine struct. Used for among other things for communication
91  * during a transfer.
92  * @node: List entry.
93  * @dir: The transfer direction of this job.
94  * @is_in_client_list: true if the client owns this descriptor.
95  *
96  * This descriptor is used for both logical and physical transfers.
97  */
98
99 struct d40_desc {
100         /* LLI physical */
101         struct d40_phy_lli_bidir         lli_phy;
102         /* LLI logical */
103         struct d40_log_lli_bidir         lli_log;
104
105         struct d40_lli_pool              lli_pool;
106         int                              lli_len;
107         int                              lli_count;
108         u32                              lli_tx_len;
109
110         struct dma_async_tx_descriptor   txd;
111         struct list_head                 node;
112
113         enum dma_data_direction          dir;
114         bool                             is_in_client_list;
115 };
116
117 /**
118  * struct d40_lcla_pool - LCLA pool settings and data.
119  *
120  * @base: The virtual address of LCLA. 18 bit aligned.
121  * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
122  * This pointer is only there for clean-up on error.
123  * @pages: The number of pages needed for all physical channels.
124  * Only used later for clean-up on error
125  * @lock: Lock to protect the content in this struct.
126  * @alloc_map: Bitmap mapping between physical channel and LCLA entries.
127  * @num_blocks: The number of entries of alloc_map. Equals to the
128  * number of physical channels.
129  */
130 struct d40_lcla_pool {
131         void            *base;
132         void            *base_unaligned;
133         int              pages;
134         spinlock_t       lock;
135         u32             *alloc_map;
136         int              num_blocks;
137 };
138
139 /**
140  * struct d40_phy_res - struct for handling eventlines mapped to physical
141  * channels.
142  *
143  * @lock: A lock protection this entity.
144  * @num: The physical channel number of this entity.
145  * @allocated_src: Bit mapped to show which src event line's are mapped to
146  * this physical channel. Can also be free or physically allocated.
147  * @allocated_dst: Same as for src but is dst.
148  * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
149  * event line number. Both allocated_src and allocated_dst can not be
150  * allocated to a physical channel, since the interrupt handler has then
151  * no way of figure out which one the interrupt belongs to.
152  */
153 struct d40_phy_res {
154         spinlock_t lock;
155         int        num;
156         u32        allocated_src;
157         u32        allocated_dst;
158 };
159
160 struct d40_base;
161
162 /**
163  * struct d40_chan - Struct that describes a channel.
164  *
165  * @lock: A spinlock to protect this struct.
166  * @log_num: The logical number, if any of this channel.
167  * @completed: Starts with 1, after first interrupt it is set to dma engine's
168  * current cookie.
169  * @pending_tx: The number of pending transfers. Used between interrupt handler
170  * and tasklet.
171  * @busy: Set to true when transfer is ongoing on this channel.
172  * @phy_chan: Pointer to physical channel which this instance runs on. If this
173  * point is NULL, then the channel is not allocated.
174  * @chan: DMA engine handle.
175  * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
176  * transfer and call client callback.
177  * @client: Cliented owned descriptor list.
178  * @active: Active descriptor.
179  * @queue: Queued jobs.
180  * @dma_cfg: The client configuration of this dma channel.
181  * @base: Pointer to the device instance struct.
182  * @src_def_cfg: Default cfg register setting for src.
183  * @dst_def_cfg: Default cfg register setting for dst.
184  * @log_def: Default logical channel settings.
185  * @lcla: Space for one dst src pair for logical channel transfers.
186  * @lcpa: Pointer to dst and src lcpa settings.
187  *
188  * This struct can either "be" a logical or a physical channel.
189  */
190 struct d40_chan {
191         spinlock_t                       lock;
192         int                              log_num;
193         /* ID of the most recent completed transfer */
194         int                              completed;
195         int                              pending_tx;
196         bool                             busy;
197         struct d40_phy_res              *phy_chan;
198         struct dma_chan                  chan;
199         struct tasklet_struct            tasklet;
200         struct list_head                 client;
201         struct list_head                 active;
202         struct list_head                 queue;
203         struct stedma40_chan_cfg         dma_cfg;
204         struct d40_base                 *base;
205         /* Default register configurations */
206         u32                              src_def_cfg;
207         u32                              dst_def_cfg;
208         struct d40_def_lcsp              log_def;
209         struct d40_lcla_elem             lcla;
210         struct d40_log_lli_full         *lcpa;
211         /* Runtime reconfiguration */
212         dma_addr_t                      runtime_addr;
213         enum dma_data_direction         runtime_direction;
214 };
215
216 /**
217  * struct d40_base - The big global struct, one for each probe'd instance.
218  *
219  * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
220  * @execmd_lock: Lock for execute command usage since several channels share
221  * the same physical register.
222  * @dev: The device structure.
223  * @virtbase: The virtual base address of the DMA's register.
224  * @rev: silicon revision detected.
225  * @clk: Pointer to the DMA clock structure.
226  * @phy_start: Physical memory start of the DMA registers.
227  * @phy_size: Size of the DMA register map.
228  * @irq: The IRQ number.
229  * @num_phy_chans: The number of physical channels. Read from HW. This
230  * is the number of available channels for this driver, not counting "Secure
231  * mode" allocated physical channels.
232  * @num_log_chans: The number of logical channels. Calculated from
233  * num_phy_chans.
234  * @dma_both: dma_device channels that can do both memcpy and slave transfers.
235  * @dma_slave: dma_device channels that can do only do slave transfers.
236  * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
237  * @phy_chans: Room for all possible physical channels in system.
238  * @log_chans: Room for all possible logical channels in system.
239  * @lookup_log_chans: Used to map interrupt number to logical channel. Points
240  * to log_chans entries.
241  * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
242  * to phy_chans entries.
243  * @plat_data: Pointer to provided platform_data which is the driver
244  * configuration.
245  * @phy_res: Vector containing all physical channels.
246  * @lcla_pool: lcla pool settings and data.
247  * @lcpa_base: The virtual mapped address of LCPA.
248  * @phy_lcpa: The physical address of the LCPA.
249  * @lcpa_size: The size of the LCPA area.
250  * @desc_slab: cache for descriptors.
251  */
252 struct d40_base {
253         spinlock_t                       interrupt_lock;
254         spinlock_t                       execmd_lock;
255         struct device                    *dev;
256         void __iomem                     *virtbase;
257         u8                                rev:4;
258         struct clk                       *clk;
259         phys_addr_t                       phy_start;
260         resource_size_t                   phy_size;
261         int                               irq;
262         int                               num_phy_chans;
263         int                               num_log_chans;
264         struct dma_device                 dma_both;
265         struct dma_device                 dma_slave;
266         struct dma_device                 dma_memcpy;
267         struct d40_chan                  *phy_chans;
268         struct d40_chan                  *log_chans;
269         struct d40_chan                 **lookup_log_chans;
270         struct d40_chan                 **lookup_phy_chans;
271         struct stedma40_platform_data    *plat_data;
272         /* Physical half channels */
273         struct d40_phy_res               *phy_res;
274         struct d40_lcla_pool              lcla_pool;
275         void                             *lcpa_base;
276         dma_addr_t                        phy_lcpa;
277         resource_size_t                   lcpa_size;
278         struct kmem_cache                *desc_slab;
279 };
280
281 /**
282  * struct d40_interrupt_lookup - lookup table for interrupt handler
283  *
284  * @src: Interrupt mask register.
285  * @clr: Interrupt clear register.
286  * @is_error: true if this is an error interrupt.
287  * @offset: start delta in the lookup_log_chans in d40_base. If equals to
288  * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
289  */
290 struct d40_interrupt_lookup {
291         u32 src;
292         u32 clr;
293         bool is_error;
294         int offset;
295 };
296
297 /**
298  * struct d40_reg_val - simple lookup struct
299  *
300  * @reg: The register.
301  * @val: The value that belongs to the register in reg.
302  */
303 struct d40_reg_val {
304         unsigned int reg;
305         unsigned int val;
306 };
307
308 static int d40_pool_lli_alloc(struct d40_desc *d40d,
309                               int lli_len, bool is_log)
310 {
311         u32 align;
312         void *base;
313
314         if (is_log)
315                 align = sizeof(struct d40_log_lli);
316         else
317                 align = sizeof(struct d40_phy_lli);
318
319         if (lli_len == 1) {
320                 base = d40d->lli_pool.pre_alloc_lli;
321                 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
322                 d40d->lli_pool.base = NULL;
323         } else {
324                 d40d->lli_pool.size = ALIGN(lli_len * 2 * align, align);
325
326                 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
327                 d40d->lli_pool.base = base;
328
329                 if (d40d->lli_pool.base == NULL)
330                         return -ENOMEM;
331         }
332
333         if (is_log) {
334                 d40d->lli_log.src = PTR_ALIGN((struct d40_log_lli *) base,
335                                               align);
336                 d40d->lli_log.dst = PTR_ALIGN(d40d->lli_log.src + lli_len,
337                                               align);
338         } else {
339                 d40d->lli_phy.src = PTR_ALIGN((struct d40_phy_lli *)base,
340                                               align);
341                 d40d->lli_phy.dst = PTR_ALIGN(d40d->lli_phy.src + lli_len,
342                                               align);
343
344                 d40d->lli_phy.src_addr = virt_to_phys(d40d->lli_phy.src);
345                 d40d->lli_phy.dst_addr = virt_to_phys(d40d->lli_phy.dst);
346         }
347
348         return 0;
349 }
350
351 static void d40_pool_lli_free(struct d40_desc *d40d)
352 {
353         kfree(d40d->lli_pool.base);
354         d40d->lli_pool.base = NULL;
355         d40d->lli_pool.size = 0;
356         d40d->lli_log.src = NULL;
357         d40d->lli_log.dst = NULL;
358         d40d->lli_phy.src = NULL;
359         d40d->lli_phy.dst = NULL;
360         d40d->lli_phy.src_addr = 0;
361         d40d->lli_phy.dst_addr = 0;
362 }
363
364 static dma_cookie_t d40_assign_cookie(struct d40_chan *d40c,
365                                       struct d40_desc *desc)
366 {
367         dma_cookie_t cookie = d40c->chan.cookie;
368
369         if (++cookie < 0)
370                 cookie = 1;
371
372         d40c->chan.cookie = cookie;
373         desc->txd.cookie = cookie;
374
375         return cookie;
376 }
377
378 static void d40_desc_remove(struct d40_desc *d40d)
379 {
380         list_del(&d40d->node);
381 }
382
383 static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
384 {
385         struct d40_desc *d;
386         struct d40_desc *_d;
387
388         if (!list_empty(&d40c->client)) {
389                 list_for_each_entry_safe(d, _d, &d40c->client, node)
390                         if (async_tx_test_ack(&d->txd)) {
391                                 d40_pool_lli_free(d);
392                                 d40_desc_remove(d);
393                                 break;
394                         }
395         } else {
396                 d = kmem_cache_alloc(d40c->base->desc_slab, GFP_NOWAIT);
397                 if (d != NULL) {
398                         memset(d, 0, sizeof(struct d40_desc));
399                         INIT_LIST_HEAD(&d->node);
400                 }
401         }
402         return d;
403 }
404
405 static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
406 {
407         kmem_cache_free(d40c->base->desc_slab, d40d);
408 }
409
410 static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
411 {
412         list_add_tail(&desc->node, &d40c->active);
413 }
414
415 static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
416 {
417         struct d40_desc *d;
418
419         if (list_empty(&d40c->active))
420                 return NULL;
421
422         d = list_first_entry(&d40c->active,
423                              struct d40_desc,
424                              node);
425         return d;
426 }
427
428 static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
429 {
430         list_add_tail(&desc->node, &d40c->queue);
431 }
432
433 static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
434 {
435         struct d40_desc *d;
436
437         if (list_empty(&d40c->queue))
438                 return NULL;
439
440         d = list_first_entry(&d40c->queue,
441                              struct d40_desc,
442                              node);
443         return d;
444 }
445
446 /* Support functions for logical channels */
447
448 static int d40_lcla_id_get(struct d40_chan *d40c)
449 {
450         int src_id = 0;
451         int dst_id = 0;
452         struct d40_log_lli *lcla_lidx_base =
453                 d40c->base->lcla_pool.base + d40c->phy_chan->num * 1024;
454         int i;
455         int lli_per_log = d40c->base->plat_data->llis_per_log;
456         unsigned long flags;
457
458         if (d40c->lcla.src_id >= 0 && d40c->lcla.dst_id >= 0)
459                 return 0;
460
461         if (d40c->base->lcla_pool.num_blocks > 32)
462                 return -EINVAL;
463
464         spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
465
466         for (i = 0; i < d40c->base->lcla_pool.num_blocks; i++) {
467                 if (!(d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] &
468                       (0x1 << i))) {
469                         d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] |=
470                                 (0x1 << i);
471                         break;
472                 }
473         }
474         src_id = i;
475         if (src_id >= d40c->base->lcla_pool.num_blocks)
476                 goto err;
477
478         for (; i < d40c->base->lcla_pool.num_blocks; i++) {
479                 if (!(d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] &
480                       (0x1 << i))) {
481                         d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] |=
482                                 (0x1 << i);
483                         break;
484                 }
485         }
486
487         dst_id = i;
488         if (dst_id == src_id)
489                 goto err;
490
491         d40c->lcla.src_id = src_id;
492         d40c->lcla.dst_id = dst_id;
493         d40c->lcla.dst = lcla_lidx_base + dst_id * lli_per_log + 1;
494         d40c->lcla.src = lcla_lidx_base + src_id * lli_per_log + 1;
495
496         spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
497         return 0;
498 err:
499         spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
500         return -EINVAL;
501 }
502
503
504 static int d40_channel_execute_command(struct d40_chan *d40c,
505                                        enum d40_command command)
506 {
507         int status, i;
508         void __iomem *active_reg;
509         int ret = 0;
510         unsigned long flags;
511         u32 wmask;
512
513         spin_lock_irqsave(&d40c->base->execmd_lock, flags);
514
515         if (d40c->phy_chan->num % 2 == 0)
516                 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
517         else
518                 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
519
520         if (command == D40_DMA_SUSPEND_REQ) {
521                 status = (readl(active_reg) &
522                           D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
523                         D40_CHAN_POS(d40c->phy_chan->num);
524
525                 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
526                         goto done;
527         }
528
529         wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
530         writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
531                active_reg);
532
533         if (command == D40_DMA_SUSPEND_REQ) {
534
535                 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
536                         status = (readl(active_reg) &
537                                   D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
538                                 D40_CHAN_POS(d40c->phy_chan->num);
539
540                         cpu_relax();
541                         /*
542                          * Reduce the number of bus accesses while
543                          * waiting for the DMA to suspend.
544                          */
545                         udelay(3);
546
547                         if (status == D40_DMA_STOP ||
548                             status == D40_DMA_SUSPENDED)
549                                 break;
550                 }
551
552                 if (i == D40_SUSPEND_MAX_IT) {
553                         dev_err(&d40c->chan.dev->device,
554                                 "[%s]: unable to suspend the chl %d (log: %d) status %x\n",
555                                 __func__, d40c->phy_chan->num, d40c->log_num,
556                                 status);
557                         dump_stack();
558                         ret = -EBUSY;
559                 }
560
561         }
562 done:
563         spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
564         return ret;
565 }
566
567 static void d40_term_all(struct d40_chan *d40c)
568 {
569         struct d40_desc *d40d;
570         unsigned long flags;
571
572         /* Release active descriptors */
573         while ((d40d = d40_first_active_get(d40c))) {
574                 d40_desc_remove(d40d);
575
576                 /* Return desc to free-list */
577                 d40_desc_free(d40c, d40d);
578         }
579
580         /* Release queued descriptors waiting for transfer */
581         while ((d40d = d40_first_queued(d40c))) {
582                 d40_desc_remove(d40d);
583
584                 /* Return desc to free-list */
585                 d40_desc_free(d40c, d40d);
586         }
587
588         spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
589
590         d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] &=
591                 (~(0x1 << d40c->lcla.dst_id));
592         d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] &=
593                 (~(0x1 << d40c->lcla.src_id));
594
595         d40c->lcla.src_id = -1;
596         d40c->lcla.dst_id = -1;
597
598         spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
599
600         d40c->pending_tx = 0;
601         d40c->busy = false;
602 }
603
604 static void d40_config_set_event(struct d40_chan *d40c, bool do_enable)
605 {
606         u32 val;
607         unsigned long flags;
608
609         /* Notice, that disable requires the physical channel to be stopped */
610         if (do_enable)
611                 val = D40_ACTIVATE_EVENTLINE;
612         else
613                 val = D40_DEACTIVATE_EVENTLINE;
614
615         spin_lock_irqsave(&d40c->phy_chan->lock, flags);
616
617         /* Enable event line connected to device (or memcpy) */
618         if ((d40c->dma_cfg.dir ==  STEDMA40_PERIPH_TO_MEM) ||
619             (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) {
620                 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
621
622                 writel((val << D40_EVENTLINE_POS(event)) |
623                        ~D40_EVENTLINE_MASK(event),
624                        d40c->base->virtbase + D40_DREG_PCBASE +
625                        d40c->phy_chan->num * D40_DREG_PCDELTA +
626                        D40_CHAN_REG_SSLNK);
627         }
628         if (d40c->dma_cfg.dir !=  STEDMA40_PERIPH_TO_MEM) {
629                 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
630
631                 writel((val << D40_EVENTLINE_POS(event)) |
632                        ~D40_EVENTLINE_MASK(event),
633                        d40c->base->virtbase + D40_DREG_PCBASE +
634                        d40c->phy_chan->num * D40_DREG_PCDELTA +
635                        D40_CHAN_REG_SDLNK);
636         }
637
638         spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
639 }
640
641 static u32 d40_chan_has_events(struct d40_chan *d40c)
642 {
643         u32 val;
644
645         val = readl(d40c->base->virtbase + D40_DREG_PCBASE +
646                     d40c->phy_chan->num * D40_DREG_PCDELTA +
647                     D40_CHAN_REG_SSLNK);
648
649         val |= readl(d40c->base->virtbase + D40_DREG_PCBASE +
650                      d40c->phy_chan->num * D40_DREG_PCDELTA +
651                      D40_CHAN_REG_SDLNK);
652         return val;
653 }
654
655 static void d40_config_enable_lidx(struct d40_chan *d40c)
656 {
657         /* Set LIDX for lcla */
658         writel((d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS) &
659                D40_SREG_ELEM_LOG_LIDX_MASK,
660                d40c->base->virtbase + D40_DREG_PCBASE +
661                d40c->phy_chan->num * D40_DREG_PCDELTA + D40_CHAN_REG_SDELT);
662
663         writel((d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS) &
664                D40_SREG_ELEM_LOG_LIDX_MASK,
665                d40c->base->virtbase + D40_DREG_PCBASE +
666                d40c->phy_chan->num * D40_DREG_PCDELTA + D40_CHAN_REG_SSELT);
667 }
668
669 static int d40_config_write(struct d40_chan *d40c)
670 {
671         u32 addr_base;
672         u32 var;
673         int res;
674
675         res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
676         if (res)
677                 return res;
678
679         /* Odd addresses are even addresses + 4 */
680         addr_base = (d40c->phy_chan->num % 2) * 4;
681         /* Setup channel mode to logical or physical */
682         var = ((u32)(d40c->log_num != D40_PHY_CHAN) + 1) <<
683                 D40_CHAN_POS(d40c->phy_chan->num);
684         writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
685
686         /* Setup operational mode option register */
687         var = ((d40c->dma_cfg.channel_type >> STEDMA40_INFO_CH_MODE_OPT_POS) &
688                0x3) << D40_CHAN_POS(d40c->phy_chan->num);
689
690         writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
691
692         if (d40c->log_num != D40_PHY_CHAN) {
693                 /* Set default config for CFG reg */
694                 writel(d40c->src_def_cfg,
695                        d40c->base->virtbase + D40_DREG_PCBASE +
696                        d40c->phy_chan->num * D40_DREG_PCDELTA +
697                        D40_CHAN_REG_SSCFG);
698                 writel(d40c->dst_def_cfg,
699                        d40c->base->virtbase + D40_DREG_PCBASE +
700                        d40c->phy_chan->num * D40_DREG_PCDELTA +
701                        D40_CHAN_REG_SDCFG);
702
703                 d40_config_enable_lidx(d40c);
704         }
705         return res;
706 }
707
708 static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
709 {
710         if (d40d->lli_phy.dst && d40d->lli_phy.src) {
711                 d40_phy_lli_write(d40c->base->virtbase,
712                                   d40c->phy_chan->num,
713                                   d40d->lli_phy.dst,
714                                   d40d->lli_phy.src);
715         } else if (d40d->lli_log.dst && d40d->lli_log.src) {
716                 struct d40_log_lli *src = d40d->lli_log.src;
717                 struct d40_log_lli *dst = d40d->lli_log.dst;
718                 int s;
719
720                 src += d40d->lli_count;
721                 dst += d40d->lli_count;
722                 s = d40_log_lli_write(d40c->lcpa,
723                                       d40c->lcla.src, d40c->lcla.dst,
724                                       dst, src,
725                                       d40c->base->plat_data->llis_per_log);
726
727                 /* If s equals to zero, the job is not linked */
728                 if (s > 0) {
729                         (void) dma_map_single(d40c->base->dev, d40c->lcla.src,
730                                               s * sizeof(struct d40_log_lli),
731                                               DMA_TO_DEVICE);
732                         (void) dma_map_single(d40c->base->dev, d40c->lcla.dst,
733                                               s * sizeof(struct d40_log_lli),
734                                               DMA_TO_DEVICE);
735                 }
736         }
737         d40d->lli_count += d40d->lli_tx_len;
738 }
739
740 static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
741 {
742         struct d40_chan *d40c = container_of(tx->chan,
743                                              struct d40_chan,
744                                              chan);
745         struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
746         unsigned long flags;
747
748         spin_lock_irqsave(&d40c->lock, flags);
749
750         tx->cookie = d40_assign_cookie(d40c, d40d);
751
752         d40_desc_queue(d40c, d40d);
753
754         spin_unlock_irqrestore(&d40c->lock, flags);
755
756         return tx->cookie;
757 }
758
759 static int d40_start(struct d40_chan *d40c)
760 {
761         if (d40c->base->rev == 0) {
762                 int err;
763
764                 if (d40c->log_num != D40_PHY_CHAN) {
765                         err = d40_channel_execute_command(d40c,
766                                                           D40_DMA_SUSPEND_REQ);
767                         if (err)
768                                 return err;
769                 }
770         }
771
772         if (d40c->log_num != D40_PHY_CHAN)
773                 d40_config_set_event(d40c, true);
774
775         return d40_channel_execute_command(d40c, D40_DMA_RUN);
776 }
777
778 static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
779 {
780         struct d40_desc *d40d;
781         int err;
782
783         /* Start queued jobs, if any */
784         d40d = d40_first_queued(d40c);
785
786         if (d40d != NULL) {
787                 d40c->busy = true;
788
789                 /* Remove from queue */
790                 d40_desc_remove(d40d);
791
792                 /* Add to active queue */
793                 d40_desc_submit(d40c, d40d);
794
795                 /* Initiate DMA job */
796                 d40_desc_load(d40c, d40d);
797
798                 /* Start dma job */
799                 err = d40_start(d40c);
800
801                 if (err)
802                         return NULL;
803         }
804
805         return d40d;
806 }
807
808 /* called from interrupt context */
809 static void dma_tc_handle(struct d40_chan *d40c)
810 {
811         struct d40_desc *d40d;
812
813         if (!d40c->phy_chan)
814                 return;
815
816         /* Get first active entry from list */
817         d40d = d40_first_active_get(d40c);
818
819         if (d40d == NULL)
820                 return;
821
822         if (d40d->lli_count < d40d->lli_len) {
823
824                 d40_desc_load(d40c, d40d);
825                 /* Start dma job */
826                 (void) d40_start(d40c);
827                 return;
828         }
829
830         if (d40_queue_start(d40c) == NULL)
831                 d40c->busy = false;
832
833         d40c->pending_tx++;
834         tasklet_schedule(&d40c->tasklet);
835
836 }
837
838 static void dma_tasklet(unsigned long data)
839 {
840         struct d40_chan *d40c = (struct d40_chan *) data;
841         struct d40_desc *d40d_fin;
842         unsigned long flags;
843         dma_async_tx_callback callback;
844         void *callback_param;
845
846         spin_lock_irqsave(&d40c->lock, flags);
847
848         /* Get first active entry from list */
849         d40d_fin = d40_first_active_get(d40c);
850
851         if (d40d_fin == NULL)
852                 goto err;
853
854         d40c->completed = d40d_fin->txd.cookie;
855
856         /*
857          * If terminating a channel pending_tx is set to zero.
858          * This prevents any finished active jobs to return to the client.
859          */
860         if (d40c->pending_tx == 0) {
861                 spin_unlock_irqrestore(&d40c->lock, flags);
862                 return;
863         }
864
865         /* Callback to client */
866         callback = d40d_fin->txd.callback;
867         callback_param = d40d_fin->txd.callback_param;
868
869         if (async_tx_test_ack(&d40d_fin->txd)) {
870                 d40_pool_lli_free(d40d_fin);
871                 d40_desc_remove(d40d_fin);
872                 /* Return desc to free-list */
873                 d40_desc_free(d40c, d40d_fin);
874         } else {
875                 if (!d40d_fin->is_in_client_list) {
876                         d40_desc_remove(d40d_fin);
877                         list_add_tail(&d40d_fin->node, &d40c->client);
878                         d40d_fin->is_in_client_list = true;
879                 }
880         }
881
882         d40c->pending_tx--;
883
884         if (d40c->pending_tx)
885                 tasklet_schedule(&d40c->tasklet);
886
887         spin_unlock_irqrestore(&d40c->lock, flags);
888
889         if (callback)
890                 callback(callback_param);
891
892         return;
893
894  err:
895         /* Rescue manouver if receiving double interrupts */
896         if (d40c->pending_tx > 0)
897                 d40c->pending_tx--;
898         spin_unlock_irqrestore(&d40c->lock, flags);
899 }
900
901 static irqreturn_t d40_handle_interrupt(int irq, void *data)
902 {
903         static const struct d40_interrupt_lookup il[] = {
904                 {D40_DREG_LCTIS0, D40_DREG_LCICR0, false,  0},
905                 {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
906                 {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
907                 {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
908                 {D40_DREG_LCEIS0, D40_DREG_LCICR0, true,   0},
909                 {D40_DREG_LCEIS1, D40_DREG_LCICR1, true,  32},
910                 {D40_DREG_LCEIS2, D40_DREG_LCICR2, true,  64},
911                 {D40_DREG_LCEIS3, D40_DREG_LCICR3, true,  96},
912                 {D40_DREG_PCTIS,  D40_DREG_PCICR,  false, D40_PHY_CHAN},
913                 {D40_DREG_PCEIS,  D40_DREG_PCICR,  true,  D40_PHY_CHAN},
914         };
915
916         int i;
917         u32 regs[ARRAY_SIZE(il)];
918         u32 idx;
919         u32 row;
920         long chan = -1;
921         struct d40_chan *d40c;
922         unsigned long flags;
923         struct d40_base *base = data;
924
925         spin_lock_irqsave(&base->interrupt_lock, flags);
926
927         /* Read interrupt status of both logical and physical channels */
928         for (i = 0; i < ARRAY_SIZE(il); i++)
929                 regs[i] = readl(base->virtbase + il[i].src);
930
931         for (;;) {
932
933                 chan = find_next_bit((unsigned long *)regs,
934                                      BITS_PER_LONG * ARRAY_SIZE(il), chan + 1);
935
936                 /* No more set bits found? */
937                 if (chan == BITS_PER_LONG * ARRAY_SIZE(il))
938                         break;
939
940                 row = chan / BITS_PER_LONG;
941                 idx = chan & (BITS_PER_LONG - 1);
942
943                 /* ACK interrupt */
944                 writel(1 << idx, base->virtbase + il[row].clr);
945
946                 if (il[row].offset == D40_PHY_CHAN)
947                         d40c = base->lookup_phy_chans[idx];
948                 else
949                         d40c = base->lookup_log_chans[il[row].offset + idx];
950                 spin_lock(&d40c->lock);
951
952                 if (!il[row].is_error)
953                         dma_tc_handle(d40c);
954                 else
955                         dev_err(base->dev,
956                                 "[%s] IRQ chan: %ld offset %d idx %d\n",
957                                 __func__, chan, il[row].offset, idx);
958
959                 spin_unlock(&d40c->lock);
960         }
961
962         spin_unlock_irqrestore(&base->interrupt_lock, flags);
963
964         return IRQ_HANDLED;
965 }
966
967
968 static int d40_validate_conf(struct d40_chan *d40c,
969                              struct stedma40_chan_cfg *conf)
970 {
971         int res = 0;
972         u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type);
973         u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type);
974         bool is_log = (conf->channel_type & STEDMA40_CHANNEL_IN_OPER_MODE)
975                 == STEDMA40_CHANNEL_IN_LOG_MODE;
976
977         if (!conf->dir) {
978                 dev_err(&d40c->chan.dev->device, "[%s] Invalid direction.\n",
979                         __func__);
980                 res = -EINVAL;
981         }
982
983         if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY &&
984             d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 &&
985             d40c->runtime_addr == 0) {
986
987                 dev_err(&d40c->chan.dev->device,
988                         "[%s] Invalid TX channel address (%d)\n",
989                         __func__, conf->dst_dev_type);
990                 res = -EINVAL;
991         }
992
993         if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY &&
994             d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 &&
995             d40c->runtime_addr == 0) {
996                 dev_err(&d40c->chan.dev->device,
997                         "[%s] Invalid RX channel address (%d)\n",
998                         __func__, conf->src_dev_type);
999                 res = -EINVAL;
1000         }
1001
1002         if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
1003             dst_event_group == STEDMA40_DEV_DST_MEMORY) {
1004                 dev_err(&d40c->chan.dev->device, "[%s] Invalid dst\n",
1005                         __func__);
1006                 res = -EINVAL;
1007         }
1008
1009         if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
1010             src_event_group == STEDMA40_DEV_SRC_MEMORY) {
1011                 dev_err(&d40c->chan.dev->device, "[%s] Invalid src\n",
1012                         __func__);
1013                 res = -EINVAL;
1014         }
1015
1016         if (src_event_group == STEDMA40_DEV_SRC_MEMORY &&
1017             dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) {
1018                 dev_err(&d40c->chan.dev->device,
1019                         "[%s] No event line\n", __func__);
1020                 res = -EINVAL;
1021         }
1022
1023         if (conf->dir == STEDMA40_PERIPH_TO_PERIPH &&
1024             (src_event_group != dst_event_group)) {
1025                 dev_err(&d40c->chan.dev->device,
1026                         "[%s] Invalid event group\n", __func__);
1027                 res = -EINVAL;
1028         }
1029
1030         if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
1031                 /*
1032                  * DMAC HW supports it. Will be added to this driver,
1033                  * in case any dma client requires it.
1034                  */
1035                 dev_err(&d40c->chan.dev->device,
1036                         "[%s] periph to periph not supported\n",
1037                         __func__);
1038                 res = -EINVAL;
1039         }
1040
1041         return res;
1042 }
1043
1044 static bool d40_alloc_mask_set(struct d40_phy_res *phy, bool is_src,
1045                                int log_event_line, bool is_log)
1046 {
1047         unsigned long flags;
1048         spin_lock_irqsave(&phy->lock, flags);
1049         if (!is_log) {
1050                 /* Physical interrupts are masked per physical full channel */
1051                 if (phy->allocated_src == D40_ALLOC_FREE &&
1052                     phy->allocated_dst == D40_ALLOC_FREE) {
1053                         phy->allocated_dst = D40_ALLOC_PHY;
1054                         phy->allocated_src = D40_ALLOC_PHY;
1055                         goto found;
1056                 } else
1057                         goto not_found;
1058         }
1059
1060         /* Logical channel */
1061         if (is_src) {
1062                 if (phy->allocated_src == D40_ALLOC_PHY)
1063                         goto not_found;
1064
1065                 if (phy->allocated_src == D40_ALLOC_FREE)
1066                         phy->allocated_src = D40_ALLOC_LOG_FREE;
1067
1068                 if (!(phy->allocated_src & (1 << log_event_line))) {
1069                         phy->allocated_src |= 1 << log_event_line;
1070                         goto found;
1071                 } else
1072                         goto not_found;
1073         } else {
1074                 if (phy->allocated_dst == D40_ALLOC_PHY)
1075                         goto not_found;
1076
1077                 if (phy->allocated_dst == D40_ALLOC_FREE)
1078                         phy->allocated_dst = D40_ALLOC_LOG_FREE;
1079
1080                 if (!(phy->allocated_dst & (1 << log_event_line))) {
1081                         phy->allocated_dst |= 1 << log_event_line;
1082                         goto found;
1083                 } else
1084                         goto not_found;
1085         }
1086
1087 not_found:
1088         spin_unlock_irqrestore(&phy->lock, flags);
1089         return false;
1090 found:
1091         spin_unlock_irqrestore(&phy->lock, flags);
1092         return true;
1093 }
1094
1095 static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
1096                                int log_event_line)
1097 {
1098         unsigned long flags;
1099         bool is_free = false;
1100
1101         spin_lock_irqsave(&phy->lock, flags);
1102         if (!log_event_line) {
1103                 /* Physical interrupts are masked per physical full channel */
1104                 phy->allocated_dst = D40_ALLOC_FREE;
1105                 phy->allocated_src = D40_ALLOC_FREE;
1106                 is_free = true;
1107                 goto out;
1108         }
1109
1110         /* Logical channel */
1111         if (is_src) {
1112                 phy->allocated_src &= ~(1 << log_event_line);
1113                 if (phy->allocated_src == D40_ALLOC_LOG_FREE)
1114                         phy->allocated_src = D40_ALLOC_FREE;
1115         } else {
1116                 phy->allocated_dst &= ~(1 << log_event_line);
1117                 if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
1118                         phy->allocated_dst = D40_ALLOC_FREE;
1119         }
1120
1121         is_free = ((phy->allocated_src | phy->allocated_dst) ==
1122                    D40_ALLOC_FREE);
1123
1124 out:
1125         spin_unlock_irqrestore(&phy->lock, flags);
1126
1127         return is_free;
1128 }
1129
1130 static int d40_allocate_channel(struct d40_chan *d40c)
1131 {
1132         int dev_type;
1133         int event_group;
1134         int event_line;
1135         struct d40_phy_res *phys;
1136         int i;
1137         int j;
1138         int log_num;
1139         bool is_src;
1140         bool is_log = (d40c->dma_cfg.channel_type &
1141                        STEDMA40_CHANNEL_IN_OPER_MODE)
1142                 == STEDMA40_CHANNEL_IN_LOG_MODE;
1143
1144
1145         phys = d40c->base->phy_res;
1146
1147         if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1148                 dev_type = d40c->dma_cfg.src_dev_type;
1149                 log_num = 2 * dev_type;
1150                 is_src = true;
1151         } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1152                    d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1153                 /* dst event lines are used for logical memcpy */
1154                 dev_type = d40c->dma_cfg.dst_dev_type;
1155                 log_num = 2 * dev_type + 1;
1156                 is_src = false;
1157         } else
1158                 return -EINVAL;
1159
1160         event_group = D40_TYPE_TO_GROUP(dev_type);
1161         event_line = D40_TYPE_TO_EVENT(dev_type);
1162
1163         if (!is_log) {
1164                 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1165                         /* Find physical half channel */
1166                         for (i = 0; i < d40c->base->num_phy_chans; i++) {
1167
1168                                 if (d40_alloc_mask_set(&phys[i], is_src,
1169                                                        0, is_log))
1170                                         goto found_phy;
1171                         }
1172                 } else
1173                         for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1174                                 int phy_num = j  + event_group * 2;
1175                                 for (i = phy_num; i < phy_num + 2; i++) {
1176                                         if (d40_alloc_mask_set(&phys[i],
1177                                                                is_src,
1178                                                                0,
1179                                                                is_log))
1180                                                 goto found_phy;
1181                                 }
1182                         }
1183                 return -EINVAL;
1184 found_phy:
1185                 d40c->phy_chan = &phys[i];
1186                 d40c->log_num = D40_PHY_CHAN;
1187                 goto out;
1188         }
1189         if (dev_type == -1)
1190                 return -EINVAL;
1191
1192         /* Find logical channel */
1193         for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1194                 int phy_num = j + event_group * 2;
1195                 /*
1196                  * Spread logical channels across all available physical rather
1197                  * than pack every logical channel at the first available phy
1198                  * channels.
1199                  */
1200                 if (is_src) {
1201                         for (i = phy_num; i < phy_num + 2; i++) {
1202                                 if (d40_alloc_mask_set(&phys[i], is_src,
1203                                                        event_line, is_log))
1204                                         goto found_log;
1205                         }
1206                 } else {
1207                         for (i = phy_num + 1; i >= phy_num; i--) {
1208                                 if (d40_alloc_mask_set(&phys[i], is_src,
1209                                                        event_line, is_log))
1210                                         goto found_log;
1211                         }
1212                 }
1213         }
1214         return -EINVAL;
1215
1216 found_log:
1217         d40c->phy_chan = &phys[i];
1218         d40c->log_num = log_num;
1219 out:
1220
1221         if (is_log)
1222                 d40c->base->lookup_log_chans[d40c->log_num] = d40c;
1223         else
1224                 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
1225
1226         return 0;
1227
1228 }
1229
1230 static int d40_config_memcpy(struct d40_chan *d40c)
1231 {
1232         dma_cap_mask_t cap = d40c->chan.device->cap_mask;
1233
1234         if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
1235                 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log;
1236                 d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY;
1237                 d40c->dma_cfg.dst_dev_type = d40c->base->plat_data->
1238                         memcpy[d40c->chan.chan_id];
1239
1240         } else if (dma_has_cap(DMA_MEMCPY, cap) &&
1241                    dma_has_cap(DMA_SLAVE, cap)) {
1242                 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy;
1243         } else {
1244                 dev_err(&d40c->chan.dev->device, "[%s] No memcpy\n",
1245                         __func__);
1246                 return -EINVAL;
1247         }
1248
1249         return 0;
1250 }
1251
1252
1253 static int d40_free_dma(struct d40_chan *d40c)
1254 {
1255
1256         int res = 0;
1257         u32 event;
1258         struct d40_phy_res *phy = d40c->phy_chan;
1259         bool is_src;
1260         struct d40_desc *d;
1261         struct d40_desc *_d;
1262
1263
1264         /* Terminate all queued and active transfers */
1265         d40_term_all(d40c);
1266
1267         /* Release client owned descriptors */
1268         if (!list_empty(&d40c->client))
1269                 list_for_each_entry_safe(d, _d, &d40c->client, node) {
1270                         d40_pool_lli_free(d);
1271                         d40_desc_remove(d);
1272                         /* Return desc to free-list */
1273                         d40_desc_free(d40c, d);
1274                 }
1275
1276         if (phy == NULL) {
1277                 dev_err(&d40c->chan.dev->device, "[%s] phy == null\n",
1278                         __func__);
1279                 return -EINVAL;
1280         }
1281
1282         if (phy->allocated_src == D40_ALLOC_FREE &&
1283             phy->allocated_dst == D40_ALLOC_FREE) {
1284                 dev_err(&d40c->chan.dev->device, "[%s] channel already free\n",
1285                         __func__);
1286                 return -EINVAL;
1287         }
1288
1289         if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1290             d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1291                 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
1292                 is_src = false;
1293         } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1294                 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
1295                 is_src = true;
1296         } else {
1297                 dev_err(&d40c->chan.dev->device,
1298                         "[%s] Unknown direction\n", __func__);
1299                 return -EINVAL;
1300         }
1301
1302         res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1303         if (res) {
1304                 dev_err(&d40c->chan.dev->device, "[%s] suspend failed\n",
1305                         __func__);
1306                 return res;
1307         }
1308
1309         if (d40c->log_num != D40_PHY_CHAN) {
1310                 /* Release logical channel, deactivate the event line */
1311
1312                 d40_config_set_event(d40c, false);
1313                 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
1314
1315                 /*
1316                  * Check if there are more logical allocation
1317                  * on this phy channel.
1318                  */
1319                 if (!d40_alloc_mask_free(phy, is_src, event)) {
1320                         /* Resume the other logical channels if any */
1321                         if (d40_chan_has_events(d40c)) {
1322                                 res = d40_channel_execute_command(d40c,
1323                                                                   D40_DMA_RUN);
1324                                 if (res) {
1325                                         dev_err(&d40c->chan.dev->device,
1326                                                 "[%s] Executing RUN command\n",
1327                                                 __func__);
1328                                         return res;
1329                                 }
1330                         }
1331                         return 0;
1332                 }
1333         } else {
1334                 (void) d40_alloc_mask_free(phy, is_src, 0);
1335         }
1336
1337         /* Release physical channel */
1338         res = d40_channel_execute_command(d40c, D40_DMA_STOP);
1339         if (res) {
1340                 dev_err(&d40c->chan.dev->device,
1341                         "[%s] Failed to stop channel\n", __func__);
1342                 return res;
1343         }
1344         d40c->phy_chan = NULL;
1345         /* Invalidate channel type */
1346         d40c->dma_cfg.channel_type = 0;
1347         d40c->base->lookup_phy_chans[phy->num] = NULL;
1348
1349         return 0;
1350 }
1351
1352 static int d40_pause(struct dma_chan *chan)
1353 {
1354         struct d40_chan *d40c =
1355                 container_of(chan, struct d40_chan, chan);
1356         int res;
1357         unsigned long flags;
1358
1359         spin_lock_irqsave(&d40c->lock, flags);
1360
1361         res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1362         if (res == 0) {
1363                 if (d40c->log_num != D40_PHY_CHAN) {
1364                         d40_config_set_event(d40c, false);
1365                         /* Resume the other logical channels if any */
1366                         if (d40_chan_has_events(d40c))
1367                                 res = d40_channel_execute_command(d40c,
1368                                                                   D40_DMA_RUN);
1369                 }
1370         }
1371
1372         spin_unlock_irqrestore(&d40c->lock, flags);
1373         return res;
1374 }
1375
1376 static bool d40_is_paused(struct d40_chan *d40c)
1377 {
1378         bool is_paused = false;
1379         unsigned long flags;
1380         void __iomem *active_reg;
1381         u32 status;
1382         u32 event;
1383
1384         spin_lock_irqsave(&d40c->lock, flags);
1385
1386         if (d40c->log_num == D40_PHY_CHAN) {
1387                 if (d40c->phy_chan->num % 2 == 0)
1388                         active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1389                 else
1390                         active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1391
1392                 status = (readl(active_reg) &
1393                           D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1394                         D40_CHAN_POS(d40c->phy_chan->num);
1395                 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1396                         is_paused = true;
1397
1398                 goto _exit;
1399         }
1400
1401         if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1402             d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM)
1403                 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
1404         else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
1405                 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
1406         else {
1407                 dev_err(&d40c->chan.dev->device,
1408                         "[%s] Unknown direction\n", __func__);
1409                 goto _exit;
1410         }
1411         status = d40_chan_has_events(d40c);
1412         status = (status & D40_EVENTLINE_MASK(event)) >>
1413                 D40_EVENTLINE_POS(event);
1414
1415         if (status != D40_DMA_RUN)
1416                 is_paused = true;
1417 _exit:
1418         spin_unlock_irqrestore(&d40c->lock, flags);
1419         return is_paused;
1420
1421 }
1422
1423
1424 static bool d40_tx_is_linked(struct d40_chan *d40c)
1425 {
1426         bool is_link;
1427
1428         if (d40c->log_num != D40_PHY_CHAN)
1429                 is_link = readl(&d40c->lcpa->lcsp3) &  D40_MEM_LCSP3_DLOS_MASK;
1430         else
1431                 is_link = readl(d40c->base->virtbase + D40_DREG_PCBASE +
1432                                 d40c->phy_chan->num * D40_DREG_PCDELTA +
1433                                 D40_CHAN_REG_SDLNK) &
1434                         D40_SREG_LNK_PHYS_LNK_MASK;
1435         return is_link;
1436 }
1437
1438 static u32 d40_residue(struct d40_chan *d40c)
1439 {
1440         u32 num_elt;
1441
1442         if (d40c->log_num != D40_PHY_CHAN)
1443                 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
1444                         >> D40_MEM_LCSP2_ECNT_POS;
1445         else
1446                 num_elt = (readl(d40c->base->virtbase + D40_DREG_PCBASE +
1447                                  d40c->phy_chan->num * D40_DREG_PCDELTA +
1448                                  D40_CHAN_REG_SDELT) &
1449                            D40_SREG_ELEM_PHY_ECNT_MASK) >>
1450                         D40_SREG_ELEM_PHY_ECNT_POS;
1451         return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
1452 }
1453
1454 static int d40_resume(struct dma_chan *chan)
1455 {
1456         struct d40_chan *d40c =
1457                 container_of(chan, struct d40_chan, chan);
1458         int res = 0;
1459         unsigned long flags;
1460
1461         spin_lock_irqsave(&d40c->lock, flags);
1462
1463         if (d40c->base->rev == 0)
1464                 if (d40c->log_num != D40_PHY_CHAN) {
1465                         res = d40_channel_execute_command(d40c,
1466                                                           D40_DMA_SUSPEND_REQ);
1467                         goto no_suspend;
1468                 }
1469
1470         /* If bytes left to transfer or linked tx resume job */
1471         if (d40_residue(d40c) || d40_tx_is_linked(d40c)) {
1472                 if (d40c->log_num != D40_PHY_CHAN)
1473                         d40_config_set_event(d40c, true);
1474                 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
1475         }
1476
1477 no_suspend:
1478         spin_unlock_irqrestore(&d40c->lock, flags);
1479         return res;
1480 }
1481
1482 static u32 stedma40_residue(struct dma_chan *chan)
1483 {
1484         struct d40_chan *d40c =
1485                 container_of(chan, struct d40_chan, chan);
1486         u32 bytes_left;
1487         unsigned long flags;
1488
1489         spin_lock_irqsave(&d40c->lock, flags);
1490         bytes_left = d40_residue(d40c);
1491         spin_unlock_irqrestore(&d40c->lock, flags);
1492
1493         return bytes_left;
1494 }
1495
1496 /* Public DMA functions in addition to the DMA engine framework */
1497
1498 int stedma40_set_psize(struct dma_chan *chan,
1499                        int src_psize,
1500                        int dst_psize)
1501 {
1502         struct d40_chan *d40c =
1503                 container_of(chan, struct d40_chan, chan);
1504         unsigned long flags;
1505
1506         spin_lock_irqsave(&d40c->lock, flags);
1507
1508         if (d40c->log_num != D40_PHY_CHAN) {
1509                 d40c->log_def.lcsp1 &= ~D40_MEM_LCSP1_SCFG_PSIZE_MASK;
1510                 d40c->log_def.lcsp3 &= ~D40_MEM_LCSP1_SCFG_PSIZE_MASK;
1511                 d40c->log_def.lcsp1 |= src_psize <<
1512                         D40_MEM_LCSP1_SCFG_PSIZE_POS;
1513                 d40c->log_def.lcsp3 |= dst_psize <<
1514                         D40_MEM_LCSP1_SCFG_PSIZE_POS;
1515                 goto out;
1516         }
1517
1518         if (src_psize == STEDMA40_PSIZE_PHY_1)
1519                 d40c->src_def_cfg &= ~(1 << D40_SREG_CFG_PHY_PEN_POS);
1520         else {
1521                 d40c->src_def_cfg |= 1 << D40_SREG_CFG_PHY_PEN_POS;
1522                 d40c->src_def_cfg &= ~(STEDMA40_PSIZE_PHY_16 <<
1523                                        D40_SREG_CFG_PSIZE_POS);
1524                 d40c->src_def_cfg |= src_psize << D40_SREG_CFG_PSIZE_POS;
1525         }
1526
1527         if (dst_psize == STEDMA40_PSIZE_PHY_1)
1528                 d40c->dst_def_cfg &= ~(1 << D40_SREG_CFG_PHY_PEN_POS);
1529         else {
1530                 d40c->dst_def_cfg |= 1 << D40_SREG_CFG_PHY_PEN_POS;
1531                 d40c->dst_def_cfg &= ~(STEDMA40_PSIZE_PHY_16 <<
1532                                        D40_SREG_CFG_PSIZE_POS);
1533                 d40c->dst_def_cfg |= dst_psize << D40_SREG_CFG_PSIZE_POS;
1534         }
1535 out:
1536         spin_unlock_irqrestore(&d40c->lock, flags);
1537         return 0;
1538 }
1539 EXPORT_SYMBOL(stedma40_set_psize);
1540
1541 struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
1542                                                    struct scatterlist *sgl_dst,
1543                                                    struct scatterlist *sgl_src,
1544                                                    unsigned int sgl_len,
1545                                                    unsigned long dma_flags)
1546 {
1547         int res;
1548         struct d40_desc *d40d;
1549         struct d40_chan *d40c = container_of(chan, struct d40_chan,
1550                                              chan);
1551         unsigned long flags;
1552
1553         if (d40c->phy_chan == NULL) {
1554                 dev_err(&d40c->chan.dev->device,
1555                         "[%s] Unallocated channel.\n", __func__);
1556                 return ERR_PTR(-EINVAL);
1557         }
1558
1559         spin_lock_irqsave(&d40c->lock, flags);
1560         d40d = d40_desc_get(d40c);
1561
1562         if (d40d == NULL)
1563                 goto err;
1564
1565         d40d->lli_len = sgl_len;
1566         d40d->lli_tx_len = d40d->lli_len;
1567         d40d->txd.flags = dma_flags;
1568
1569         if (d40c->log_num != D40_PHY_CHAN) {
1570                 if (d40d->lli_len > d40c->base->plat_data->llis_per_log)
1571                         d40d->lli_tx_len = d40c->base->plat_data->llis_per_log;
1572
1573                 if (sgl_len > 1)
1574                         /*
1575                          * Check if there is space available in lcla. If not,
1576                          * split list into 1-length and run only in lcpa
1577                          * space.
1578                          */
1579                         if (d40_lcla_id_get(d40c) != 0)
1580                                 d40d->lli_tx_len = 1;
1581
1582                 if (d40_pool_lli_alloc(d40d, sgl_len, true) < 0) {
1583                         dev_err(&d40c->chan.dev->device,
1584                                 "[%s] Out of memory\n", __func__);
1585                         goto err;
1586                 }
1587
1588                 (void) d40_log_sg_to_lli(d40c->lcla.src_id,
1589                                          sgl_src,
1590                                          sgl_len,
1591                                          d40d->lli_log.src,
1592                                          d40c->log_def.lcsp1,
1593                                          d40c->dma_cfg.src_info.data_width,
1594                                          dma_flags & DMA_PREP_INTERRUPT,
1595                                          d40d->lli_tx_len,
1596                                          d40c->base->plat_data->llis_per_log);
1597
1598                 (void) d40_log_sg_to_lli(d40c->lcla.dst_id,
1599                                          sgl_dst,
1600                                          sgl_len,
1601                                          d40d->lli_log.dst,
1602                                          d40c->log_def.lcsp3,
1603                                          d40c->dma_cfg.dst_info.data_width,
1604                                          dma_flags & DMA_PREP_INTERRUPT,
1605                                          d40d->lli_tx_len,
1606                                          d40c->base->plat_data->llis_per_log);
1607
1608
1609         } else {
1610                 if (d40_pool_lli_alloc(d40d, sgl_len, false) < 0) {
1611                         dev_err(&d40c->chan.dev->device,
1612                                 "[%s] Out of memory\n", __func__);
1613                         goto err;
1614                 }
1615
1616                 res = d40_phy_sg_to_lli(sgl_src,
1617                                         sgl_len,
1618                                         0,
1619                                         d40d->lli_phy.src,
1620                                         d40d->lli_phy.src_addr,
1621                                         d40c->src_def_cfg,
1622                                         d40c->dma_cfg.src_info.data_width,
1623                                         d40c->dma_cfg.src_info.psize,
1624                                         true);
1625
1626                 if (res < 0)
1627                         goto err;
1628
1629                 res = d40_phy_sg_to_lli(sgl_dst,
1630                                         sgl_len,
1631                                         0,
1632                                         d40d->lli_phy.dst,
1633                                         d40d->lli_phy.dst_addr,
1634                                         d40c->dst_def_cfg,
1635                                         d40c->dma_cfg.dst_info.data_width,
1636                                         d40c->dma_cfg.dst_info.psize,
1637                                         true);
1638
1639                 if (res < 0)
1640                         goto err;
1641
1642                 (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src,
1643                                       d40d->lli_pool.size, DMA_TO_DEVICE);
1644         }
1645
1646         dma_async_tx_descriptor_init(&d40d->txd, chan);
1647
1648         d40d->txd.tx_submit = d40_tx_submit;
1649
1650         spin_unlock_irqrestore(&d40c->lock, flags);
1651
1652         return &d40d->txd;
1653 err:
1654         spin_unlock_irqrestore(&d40c->lock, flags);
1655         return NULL;
1656 }
1657 EXPORT_SYMBOL(stedma40_memcpy_sg);
1658
1659 bool stedma40_filter(struct dma_chan *chan, void *data)
1660 {
1661         struct stedma40_chan_cfg *info = data;
1662         struct d40_chan *d40c =
1663                 container_of(chan, struct d40_chan, chan);
1664         int err;
1665
1666         if (data) {
1667                 err = d40_validate_conf(d40c, info);
1668                 if (!err)
1669                         d40c->dma_cfg = *info;
1670         } else
1671                 err = d40_config_memcpy(d40c);
1672
1673         return err == 0;
1674 }
1675 EXPORT_SYMBOL(stedma40_filter);
1676
1677 /* DMA ENGINE functions */
1678 static int d40_alloc_chan_resources(struct dma_chan *chan)
1679 {
1680         int err;
1681         unsigned long flags;
1682         struct d40_chan *d40c =
1683                 container_of(chan, struct d40_chan, chan);
1684         bool is_free_phy;
1685         spin_lock_irqsave(&d40c->lock, flags);
1686
1687         d40c->completed = chan->cookie = 1;
1688
1689         /*
1690          * If no dma configuration is set (channel_type == 0)
1691          * use default configuration (memcpy)
1692          */
1693         if (d40c->dma_cfg.channel_type == 0) {
1694                 err = d40_config_memcpy(d40c);
1695                 if (err) {
1696                         dev_err(&d40c->chan.dev->device,
1697                                 "[%s] Failed to configure memcpy channel\n",
1698                                 __func__);
1699                         goto fail;
1700                 }
1701         }
1702         is_free_phy = (d40c->phy_chan == NULL);
1703
1704         err = d40_allocate_channel(d40c);
1705         if (err) {
1706                 dev_err(&d40c->chan.dev->device,
1707                         "[%s] Failed to allocate channel\n", __func__);
1708                 goto fail;
1709         }
1710
1711         /* Fill in basic CFG register values */
1712         d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
1713                     &d40c->dst_def_cfg, d40c->log_num != D40_PHY_CHAN);
1714
1715         if (d40c->log_num != D40_PHY_CHAN) {
1716                 d40_log_cfg(&d40c->dma_cfg,
1717                             &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
1718
1719                 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
1720                         d40c->lcpa = d40c->base->lcpa_base +
1721                           d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE;
1722                 else
1723                         d40c->lcpa = d40c->base->lcpa_base +
1724                           d40c->dma_cfg.dst_dev_type *
1725                           D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
1726         }
1727
1728         /*
1729          * Only write channel configuration to the DMA if the physical
1730          * resource is free. In case of multiple logical channels
1731          * on the same physical resource, only the first write is necessary.
1732          */
1733         if (is_free_phy) {
1734                 err = d40_config_write(d40c);
1735                 if (err) {
1736                         dev_err(&d40c->chan.dev->device,
1737                                 "[%s] Failed to configure channel\n",
1738                                 __func__);
1739                 }
1740         }
1741 fail:
1742         spin_unlock_irqrestore(&d40c->lock, flags);
1743         return err;
1744 }
1745
1746 static void d40_free_chan_resources(struct dma_chan *chan)
1747 {
1748         struct d40_chan *d40c =
1749                 container_of(chan, struct d40_chan, chan);
1750         int err;
1751         unsigned long flags;
1752
1753         if (d40c->phy_chan == NULL) {
1754                 dev_err(&d40c->chan.dev->device,
1755                         "[%s] Cannot free unallocated channel\n", __func__);
1756                 return;
1757         }
1758
1759
1760         spin_lock_irqsave(&d40c->lock, flags);
1761
1762         err = d40_free_dma(d40c);
1763
1764         if (err)
1765                 dev_err(&d40c->chan.dev->device,
1766                         "[%s] Failed to free channel\n", __func__);
1767         spin_unlock_irqrestore(&d40c->lock, flags);
1768 }
1769
1770 static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
1771                                                        dma_addr_t dst,
1772                                                        dma_addr_t src,
1773                                                        size_t size,
1774                                                        unsigned long dma_flags)
1775 {
1776         struct d40_desc *d40d;
1777         struct d40_chan *d40c = container_of(chan, struct d40_chan,
1778                                              chan);
1779         unsigned long flags;
1780         int err = 0;
1781
1782         if (d40c->phy_chan == NULL) {
1783                 dev_err(&d40c->chan.dev->device,
1784                         "[%s] Channel is not allocated.\n", __func__);
1785                 return ERR_PTR(-EINVAL);
1786         }
1787
1788         spin_lock_irqsave(&d40c->lock, flags);
1789         d40d = d40_desc_get(d40c);
1790
1791         if (d40d == NULL) {
1792                 dev_err(&d40c->chan.dev->device,
1793                         "[%s] Descriptor is NULL\n", __func__);
1794                 goto err;
1795         }
1796
1797         d40d->txd.flags = dma_flags;
1798
1799         dma_async_tx_descriptor_init(&d40d->txd, chan);
1800
1801         d40d->txd.tx_submit = d40_tx_submit;
1802
1803         if (d40c->log_num != D40_PHY_CHAN) {
1804
1805                 if (d40_pool_lli_alloc(d40d, 1, true) < 0) {
1806                         dev_err(&d40c->chan.dev->device,
1807                                 "[%s] Out of memory\n", __func__);
1808                         goto err;
1809                 }
1810                 d40d->lli_len = 1;
1811                 d40d->lli_tx_len = 1;
1812
1813                 d40_log_fill_lli(d40d->lli_log.src,
1814                                  src,
1815                                  size,
1816                                  0,
1817                                  d40c->log_def.lcsp1,
1818                                  d40c->dma_cfg.src_info.data_width,
1819                                  false, true);
1820
1821                 d40_log_fill_lli(d40d->lli_log.dst,
1822                                  dst,
1823                                  size,
1824                                  0,
1825                                  d40c->log_def.lcsp3,
1826                                  d40c->dma_cfg.dst_info.data_width,
1827                                  true, true);
1828
1829         } else {
1830
1831                 if (d40_pool_lli_alloc(d40d, 1, false) < 0) {
1832                         dev_err(&d40c->chan.dev->device,
1833                                 "[%s] Out of memory\n", __func__);
1834                         goto err;
1835                 }
1836
1837                 err = d40_phy_fill_lli(d40d->lli_phy.src,
1838                                        src,
1839                                        size,
1840                                        d40c->dma_cfg.src_info.psize,
1841                                        0,
1842                                        d40c->src_def_cfg,
1843                                        true,
1844                                        d40c->dma_cfg.src_info.data_width,
1845                                        false);
1846                 if (err)
1847                         goto err_fill_lli;
1848
1849                 err = d40_phy_fill_lli(d40d->lli_phy.dst,
1850                                        dst,
1851                                        size,
1852                                        d40c->dma_cfg.dst_info.psize,
1853                                        0,
1854                                        d40c->dst_def_cfg,
1855                                        true,
1856                                        d40c->dma_cfg.dst_info.data_width,
1857                                        false);
1858
1859                 if (err)
1860                         goto err_fill_lli;
1861
1862                 (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src,
1863                                       d40d->lli_pool.size, DMA_TO_DEVICE);
1864         }
1865
1866         spin_unlock_irqrestore(&d40c->lock, flags);
1867         return &d40d->txd;
1868
1869 err_fill_lli:
1870         dev_err(&d40c->chan.dev->device,
1871                 "[%s] Failed filling in PHY LLI\n", __func__);
1872         d40_pool_lli_free(d40d);
1873 err:
1874         spin_unlock_irqrestore(&d40c->lock, flags);
1875         return NULL;
1876 }
1877
1878 static int d40_prep_slave_sg_log(struct d40_desc *d40d,
1879                                  struct d40_chan *d40c,
1880                                  struct scatterlist *sgl,
1881                                  unsigned int sg_len,
1882                                  enum dma_data_direction direction,
1883                                  unsigned long dma_flags)
1884 {
1885         dma_addr_t dev_addr = 0;
1886         int total_size;
1887
1888         if (d40_pool_lli_alloc(d40d, sg_len, true) < 0) {
1889                 dev_err(&d40c->chan.dev->device,
1890                         "[%s] Out of memory\n", __func__);
1891                 return -ENOMEM;
1892         }
1893
1894         d40d->lli_len = sg_len;
1895         if (d40d->lli_len <= d40c->base->plat_data->llis_per_log)
1896                 d40d->lli_tx_len = d40d->lli_len;
1897         else
1898                 d40d->lli_tx_len = d40c->base->plat_data->llis_per_log;
1899
1900         if (sg_len > 1)
1901                 /*
1902                  * Check if there is space available in lcla.
1903                  * If not, split list into 1-length and run only
1904                  * in lcpa space.
1905                  */
1906                 if (d40_lcla_id_get(d40c) != 0)
1907                         d40d->lli_tx_len = 1;
1908
1909         if (direction == DMA_FROM_DEVICE)
1910                 if (d40c->runtime_addr)
1911                         dev_addr = d40c->runtime_addr;
1912                 else
1913                         dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type];
1914         else if (direction == DMA_TO_DEVICE)
1915                 if (d40c->runtime_addr)
1916                         dev_addr = d40c->runtime_addr;
1917                 else
1918                         dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type];
1919
1920         else
1921                 return -EINVAL;
1922
1923         total_size = d40_log_sg_to_dev(&d40c->lcla,
1924                                        sgl, sg_len,
1925                                        &d40d->lli_log,
1926                                        &d40c->log_def,
1927                                        d40c->dma_cfg.src_info.data_width,
1928                                        d40c->dma_cfg.dst_info.data_width,
1929                                        direction,
1930                                        dma_flags & DMA_PREP_INTERRUPT,
1931                                        dev_addr, d40d->lli_tx_len,
1932                                        d40c->base->plat_data->llis_per_log);
1933
1934         if (total_size < 0)
1935                 return -EINVAL;
1936
1937         return 0;
1938 }
1939
1940 static int d40_prep_slave_sg_phy(struct d40_desc *d40d,
1941                                  struct d40_chan *d40c,
1942                                  struct scatterlist *sgl,
1943                                  unsigned int sgl_len,
1944                                  enum dma_data_direction direction,
1945                                  unsigned long dma_flags)
1946 {
1947         dma_addr_t src_dev_addr;
1948         dma_addr_t dst_dev_addr;
1949         int res;
1950
1951         if (d40_pool_lli_alloc(d40d, sgl_len, false) < 0) {
1952                 dev_err(&d40c->chan.dev->device,
1953                         "[%s] Out of memory\n", __func__);
1954                 return -ENOMEM;
1955         }
1956
1957         d40d->lli_len = sgl_len;
1958         d40d->lli_tx_len = sgl_len;
1959
1960         if (direction == DMA_FROM_DEVICE) {
1961                 dst_dev_addr = 0;
1962                 if (d40c->runtime_addr)
1963                         src_dev_addr = d40c->runtime_addr;
1964                 else
1965                         src_dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type];
1966         } else if (direction == DMA_TO_DEVICE) {
1967                 if (d40c->runtime_addr)
1968                         dst_dev_addr = d40c->runtime_addr;
1969                 else
1970                         dst_dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type];
1971                 src_dev_addr = 0;
1972         } else
1973                 return -EINVAL;
1974
1975         res = d40_phy_sg_to_lli(sgl,
1976                                 sgl_len,
1977                                 src_dev_addr,
1978                                 d40d->lli_phy.src,
1979                                 d40d->lli_phy.src_addr,
1980                                 d40c->src_def_cfg,
1981                                 d40c->dma_cfg.src_info.data_width,
1982                                 d40c->dma_cfg.src_info.psize,
1983                                 true);
1984         if (res < 0)
1985                 return res;
1986
1987         res = d40_phy_sg_to_lli(sgl,
1988                                 sgl_len,
1989                                 dst_dev_addr,
1990                                 d40d->lli_phy.dst,
1991                                 d40d->lli_phy.dst_addr,
1992                                 d40c->dst_def_cfg,
1993                                 d40c->dma_cfg.dst_info.data_width,
1994                                 d40c->dma_cfg.dst_info.psize,
1995                                  true);
1996         if (res < 0)
1997                 return res;
1998
1999         (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src,
2000                               d40d->lli_pool.size, DMA_TO_DEVICE);
2001         return 0;
2002 }
2003
2004 static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
2005                                                          struct scatterlist *sgl,
2006                                                          unsigned int sg_len,
2007                                                          enum dma_data_direction direction,
2008                                                          unsigned long dma_flags)
2009 {
2010         struct d40_desc *d40d;
2011         struct d40_chan *d40c = container_of(chan, struct d40_chan,
2012                                              chan);
2013         unsigned long flags;
2014         int err;
2015
2016         if (d40c->phy_chan == NULL) {
2017                 dev_err(&d40c->chan.dev->device,
2018                         "[%s] Cannot prepare unallocated channel\n", __func__);
2019                 return ERR_PTR(-EINVAL);
2020         }
2021
2022         if (d40c->dma_cfg.pre_transfer)
2023                 d40c->dma_cfg.pre_transfer(chan,
2024                                            d40c->dma_cfg.pre_transfer_data,
2025                                            sg_dma_len(sgl));
2026
2027         spin_lock_irqsave(&d40c->lock, flags);
2028         d40d = d40_desc_get(d40c);
2029         spin_unlock_irqrestore(&d40c->lock, flags);
2030
2031         if (d40d == NULL)
2032                 return NULL;
2033
2034         if (d40c->log_num != D40_PHY_CHAN)
2035                 err = d40_prep_slave_sg_log(d40d, d40c, sgl, sg_len,
2036                                             direction, dma_flags);
2037         else
2038                 err = d40_prep_slave_sg_phy(d40d, d40c, sgl, sg_len,
2039                                             direction, dma_flags);
2040         if (err) {
2041                 dev_err(&d40c->chan.dev->device,
2042                         "[%s] Failed to prepare %s slave sg job: %d\n",
2043                         __func__,
2044                         d40c->log_num != D40_PHY_CHAN ? "log" : "phy", err);
2045                 return NULL;
2046         }
2047
2048         d40d->txd.flags = dma_flags;
2049
2050         dma_async_tx_descriptor_init(&d40d->txd, chan);
2051
2052         d40d->txd.tx_submit = d40_tx_submit;
2053
2054         return &d40d->txd;
2055 }
2056
2057 static enum dma_status d40_tx_status(struct dma_chan *chan,
2058                                      dma_cookie_t cookie,
2059                                      struct dma_tx_state *txstate)
2060 {
2061         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2062         dma_cookie_t last_used;
2063         dma_cookie_t last_complete;
2064         int ret;
2065
2066         if (d40c->phy_chan == NULL) {
2067                 dev_err(&d40c->chan.dev->device,
2068                         "[%s] Cannot read status of unallocated channel\n",
2069                         __func__);
2070                 return -EINVAL;
2071         }
2072
2073         last_complete = d40c->completed;
2074         last_used = chan->cookie;
2075
2076         if (d40_is_paused(d40c))
2077                 ret = DMA_PAUSED;
2078         else
2079                 ret = dma_async_is_complete(cookie, last_complete, last_used);
2080
2081         dma_set_tx_state(txstate, last_complete, last_used,
2082                          stedma40_residue(chan));
2083
2084         return ret;
2085 }
2086
2087 static void d40_issue_pending(struct dma_chan *chan)
2088 {
2089         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2090         unsigned long flags;
2091
2092         if (d40c->phy_chan == NULL) {
2093                 dev_err(&d40c->chan.dev->device,
2094                         "[%s] Channel is not allocated!\n", __func__);
2095                 return;
2096         }
2097
2098         spin_lock_irqsave(&d40c->lock, flags);
2099
2100         /* Busy means that pending jobs are already being processed */
2101         if (!d40c->busy)
2102                 (void) d40_queue_start(d40c);
2103
2104         spin_unlock_irqrestore(&d40c->lock, flags);
2105 }
2106
2107 /* Runtime reconfiguration extension */
2108 static void d40_set_runtime_config(struct dma_chan *chan,
2109                                struct dma_slave_config *config)
2110 {
2111         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2112         struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
2113         enum dma_slave_buswidth config_addr_width;
2114         dma_addr_t config_addr;
2115         u32 config_maxburst;
2116         enum stedma40_periph_data_width addr_width;
2117         int psize;
2118
2119         if (config->direction == DMA_FROM_DEVICE) {
2120                 dma_addr_t dev_addr_rx =
2121                         d40c->base->plat_data->dev_rx[cfg->src_dev_type];
2122
2123                 config_addr = config->src_addr;
2124                 if (dev_addr_rx)
2125                         dev_dbg(d40c->base->dev,
2126                                 "channel has a pre-wired RX address %08x "
2127                                 "overriding with %08x\n",
2128                                 dev_addr_rx, config_addr);
2129                 if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
2130                         dev_dbg(d40c->base->dev,
2131                                 "channel was not configured for peripheral "
2132                                 "to memory transfer (%d) overriding\n",
2133                                 cfg->dir);
2134                 cfg->dir = STEDMA40_PERIPH_TO_MEM;
2135
2136                 config_addr_width = config->src_addr_width;
2137                 config_maxburst = config->src_maxburst;
2138
2139         } else if (config->direction == DMA_TO_DEVICE) {
2140                 dma_addr_t dev_addr_tx =
2141                         d40c->base->plat_data->dev_tx[cfg->dst_dev_type];
2142
2143                 config_addr = config->dst_addr;
2144                 if (dev_addr_tx)
2145                         dev_dbg(d40c->base->dev,
2146                                 "channel has a pre-wired TX address %08x "
2147                                 "overriding with %08x\n",
2148                                 dev_addr_tx, config_addr);
2149                 if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
2150                         dev_dbg(d40c->base->dev,
2151                                 "channel was not configured for memory "
2152                                 "to peripheral transfer (%d) overriding\n",
2153                                 cfg->dir);
2154                 cfg->dir = STEDMA40_MEM_TO_PERIPH;
2155
2156                 config_addr_width = config->dst_addr_width;
2157                 config_maxburst = config->dst_maxburst;
2158
2159         } else {
2160                 dev_err(d40c->base->dev,
2161                         "unrecognized channel direction %d\n",
2162                         config->direction);
2163                 return;
2164         }
2165
2166         switch (config_addr_width) {
2167         case DMA_SLAVE_BUSWIDTH_1_BYTE:
2168                 addr_width = STEDMA40_BYTE_WIDTH;
2169                 break;
2170         case DMA_SLAVE_BUSWIDTH_2_BYTES:
2171                 addr_width = STEDMA40_HALFWORD_WIDTH;
2172                 break;
2173         case DMA_SLAVE_BUSWIDTH_4_BYTES:
2174                 addr_width = STEDMA40_WORD_WIDTH;
2175                 break;
2176         case DMA_SLAVE_BUSWIDTH_8_BYTES:
2177                 addr_width = STEDMA40_DOUBLEWORD_WIDTH;
2178                 break;
2179         default:
2180                 dev_err(d40c->base->dev,
2181                         "illegal peripheral address width "
2182                         "requested (%d)\n",
2183                         config->src_addr_width);
2184                 return;
2185         }
2186
2187         if (config_maxburst >= 16)
2188                 psize = STEDMA40_PSIZE_LOG_16;
2189         else if (config_maxburst >= 8)
2190                 psize = STEDMA40_PSIZE_LOG_8;
2191         else if (config_maxburst >= 4)
2192                 psize = STEDMA40_PSIZE_LOG_4;
2193         else
2194                 psize = STEDMA40_PSIZE_LOG_1;
2195
2196         /* Set up all the endpoint configs */
2197         cfg->src_info.data_width = addr_width;
2198         cfg->src_info.psize = psize;
2199         cfg->src_info.endianess = STEDMA40_LITTLE_ENDIAN;
2200         cfg->src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2201         cfg->dst_info.data_width = addr_width;
2202         cfg->dst_info.psize = psize;
2203         cfg->dst_info.endianess = STEDMA40_LITTLE_ENDIAN;
2204         cfg->dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2205
2206         /* These settings will take precedence later */
2207         d40c->runtime_addr = config_addr;
2208         d40c->runtime_direction = config->direction;
2209         dev_dbg(d40c->base->dev,
2210                 "configured channel %s for %s, data width %d, "
2211                 "maxburst %d bytes, LE, no flow control\n",
2212                 dma_chan_name(chan),
2213                 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
2214                 config_addr_width,
2215                 config_maxburst);
2216 }
2217
2218 static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
2219                        unsigned long arg)
2220 {
2221         unsigned long flags;
2222         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2223
2224         if (d40c->phy_chan == NULL) {
2225                 dev_err(&d40c->chan.dev->device,
2226                         "[%s] Channel is not allocated!\n", __func__);
2227                 return -EINVAL;
2228         }
2229
2230         switch (cmd) {
2231         case DMA_TERMINATE_ALL:
2232                 spin_lock_irqsave(&d40c->lock, flags);
2233                 d40_term_all(d40c);
2234                 spin_unlock_irqrestore(&d40c->lock, flags);
2235                 return 0;
2236         case DMA_PAUSE:
2237                 return d40_pause(chan);
2238         case DMA_RESUME:
2239                 return d40_resume(chan);
2240         case DMA_SLAVE_CONFIG:
2241                 d40_set_runtime_config(chan,
2242                         (struct dma_slave_config *) arg);
2243                 return 0;
2244         default:
2245                 break;
2246         }
2247
2248         /* Other commands are unimplemented */
2249         return -ENXIO;
2250 }
2251
2252 /* Initialization functions */
2253
2254 static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
2255                                  struct d40_chan *chans, int offset,
2256                                  int num_chans)
2257 {
2258         int i = 0;
2259         struct d40_chan *d40c;
2260
2261         INIT_LIST_HEAD(&dma->channels);
2262
2263         for (i = offset; i < offset + num_chans; i++) {
2264                 d40c = &chans[i];
2265                 d40c->base = base;
2266                 d40c->chan.device = dma;
2267
2268                 /* Invalidate lcla element */
2269                 d40c->lcla.src_id = -1;
2270                 d40c->lcla.dst_id = -1;
2271
2272                 spin_lock_init(&d40c->lock);
2273
2274                 d40c->log_num = D40_PHY_CHAN;
2275
2276                 INIT_LIST_HEAD(&d40c->active);
2277                 INIT_LIST_HEAD(&d40c->queue);
2278                 INIT_LIST_HEAD(&d40c->client);
2279
2280                 tasklet_init(&d40c->tasklet, dma_tasklet,
2281                              (unsigned long) d40c);
2282
2283                 list_add_tail(&d40c->chan.device_node,
2284                               &dma->channels);
2285         }
2286 }
2287
2288 static int __init d40_dmaengine_init(struct d40_base *base,
2289                                      int num_reserved_chans)
2290 {
2291         int err ;
2292
2293         d40_chan_init(base, &base->dma_slave, base->log_chans,
2294                       0, base->num_log_chans);
2295
2296         dma_cap_zero(base->dma_slave.cap_mask);
2297         dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
2298
2299         base->dma_slave.device_alloc_chan_resources = d40_alloc_chan_resources;
2300         base->dma_slave.device_free_chan_resources = d40_free_chan_resources;
2301         base->dma_slave.device_prep_dma_memcpy = d40_prep_memcpy;
2302         base->dma_slave.device_prep_slave_sg = d40_prep_slave_sg;
2303         base->dma_slave.device_tx_status = d40_tx_status;
2304         base->dma_slave.device_issue_pending = d40_issue_pending;
2305         base->dma_slave.device_control = d40_control;
2306         base->dma_slave.dev = base->dev;
2307
2308         err = dma_async_device_register(&base->dma_slave);
2309
2310         if (err) {
2311                 dev_err(base->dev,
2312                         "[%s] Failed to register slave channels\n",
2313                         __func__);
2314                 goto failure1;
2315         }
2316
2317         d40_chan_init(base, &base->dma_memcpy, base->log_chans,
2318                       base->num_log_chans, base->plat_data->memcpy_len);
2319
2320         dma_cap_zero(base->dma_memcpy.cap_mask);
2321         dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
2322
2323         base->dma_memcpy.device_alloc_chan_resources = d40_alloc_chan_resources;
2324         base->dma_memcpy.device_free_chan_resources = d40_free_chan_resources;
2325         base->dma_memcpy.device_prep_dma_memcpy = d40_prep_memcpy;
2326         base->dma_memcpy.device_prep_slave_sg = d40_prep_slave_sg;
2327         base->dma_memcpy.device_tx_status = d40_tx_status;
2328         base->dma_memcpy.device_issue_pending = d40_issue_pending;
2329         base->dma_memcpy.device_control = d40_control;
2330         base->dma_memcpy.dev = base->dev;
2331         /*
2332          * This controller can only access address at even
2333          * 32bit boundaries, i.e. 2^2
2334          */
2335         base->dma_memcpy.copy_align = 2;
2336
2337         err = dma_async_device_register(&base->dma_memcpy);
2338
2339         if (err) {
2340                 dev_err(base->dev,
2341                         "[%s] Failed to regsiter memcpy only channels\n",
2342                         __func__);
2343                 goto failure2;
2344         }
2345
2346         d40_chan_init(base, &base->dma_both, base->phy_chans,
2347                       0, num_reserved_chans);
2348
2349         dma_cap_zero(base->dma_both.cap_mask);
2350         dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
2351         dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
2352
2353         base->dma_both.device_alloc_chan_resources = d40_alloc_chan_resources;
2354         base->dma_both.device_free_chan_resources = d40_free_chan_resources;
2355         base->dma_both.device_prep_dma_memcpy = d40_prep_memcpy;
2356         base->dma_both.device_prep_slave_sg = d40_prep_slave_sg;
2357         base->dma_both.device_tx_status = d40_tx_status;
2358         base->dma_both.device_issue_pending = d40_issue_pending;
2359         base->dma_both.device_control = d40_control;
2360         base->dma_both.dev = base->dev;
2361         base->dma_both.copy_align = 2;
2362         err = dma_async_device_register(&base->dma_both);
2363
2364         if (err) {
2365                 dev_err(base->dev,
2366                         "[%s] Failed to register logical and physical capable channels\n",
2367                         __func__);
2368                 goto failure3;
2369         }
2370         return 0;
2371 failure3:
2372         dma_async_device_unregister(&base->dma_memcpy);
2373 failure2:
2374         dma_async_device_unregister(&base->dma_slave);
2375 failure1:
2376         return err;
2377 }
2378
2379 /* Initialization functions. */
2380
2381 static int __init d40_phy_res_init(struct d40_base *base)
2382 {
2383         int i;
2384         int num_phy_chans_avail = 0;
2385         u32 val[2];
2386         int odd_even_bit = -2;
2387
2388         val[0] = readl(base->virtbase + D40_DREG_PRSME);
2389         val[1] = readl(base->virtbase + D40_DREG_PRSMO);
2390
2391         for (i = 0; i < base->num_phy_chans; i++) {
2392                 base->phy_res[i].num = i;
2393                 odd_even_bit += 2 * ((i % 2) == 0);
2394                 if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
2395                         /* Mark security only channels as occupied */
2396                         base->phy_res[i].allocated_src = D40_ALLOC_PHY;
2397                         base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
2398                 } else {
2399                         base->phy_res[i].allocated_src = D40_ALLOC_FREE;
2400                         base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
2401                         num_phy_chans_avail++;
2402                 }
2403                 spin_lock_init(&base->phy_res[i].lock);
2404         }
2405
2406         /* Mark disabled channels as occupied */
2407         for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
2408                         base->phy_res[i].allocated_src = D40_ALLOC_PHY;
2409                         base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
2410                         num_phy_chans_avail--;
2411         }
2412
2413         dev_info(base->dev, "%d of %d physical DMA channels available\n",
2414                  num_phy_chans_avail, base->num_phy_chans);
2415
2416         /* Verify settings extended vs standard */
2417         val[0] = readl(base->virtbase + D40_DREG_PRTYP);
2418
2419         for (i = 0; i < base->num_phy_chans; i++) {
2420
2421                 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
2422                     (val[0] & 0x3) != 1)
2423                         dev_info(base->dev,
2424                                  "[%s] INFO: channel %d is misconfigured (%d)\n",
2425                                  __func__, i, val[0] & 0x3);
2426
2427                 val[0] = val[0] >> 2;
2428         }
2429
2430         return num_phy_chans_avail;
2431 }
2432
2433 static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
2434 {
2435         static const struct d40_reg_val dma_id_regs[] = {
2436                 /* Peripheral Id */
2437                 { .reg = D40_DREG_PERIPHID0, .val = 0x0040},
2438                 { .reg = D40_DREG_PERIPHID1, .val = 0x0000},
2439                 /*
2440                  * D40_DREG_PERIPHID2 Depends on HW revision:
2441                  *  MOP500/HREF ED has 0x0008,
2442                  *  ? has 0x0018,
2443                  *  HREF V1 has 0x0028
2444                  */
2445                 { .reg = D40_DREG_PERIPHID3, .val = 0x0000},
2446
2447                 /* PCell Id */
2448                 { .reg = D40_DREG_CELLID0, .val = 0x000d},
2449                 { .reg = D40_DREG_CELLID1, .val = 0x00f0},
2450                 { .reg = D40_DREG_CELLID2, .val = 0x0005},
2451                 { .reg = D40_DREG_CELLID3, .val = 0x00b1}
2452         };
2453         struct stedma40_platform_data *plat_data;
2454         struct clk *clk = NULL;
2455         void __iomem *virtbase = NULL;
2456         struct resource *res = NULL;
2457         struct d40_base *base = NULL;
2458         int num_log_chans = 0;
2459         int num_phy_chans;
2460         int i;
2461         u32 val;
2462
2463         clk = clk_get(&pdev->dev, NULL);
2464
2465         if (IS_ERR(clk)) {
2466                 dev_err(&pdev->dev, "[%s] No matching clock found\n",
2467                         __func__);
2468                 goto failure;
2469         }
2470
2471         clk_enable(clk);
2472
2473         /* Get IO for DMAC base address */
2474         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
2475         if (!res)
2476                 goto failure;
2477
2478         if (request_mem_region(res->start, resource_size(res),
2479                                D40_NAME " I/O base") == NULL)
2480                 goto failure;
2481
2482         virtbase = ioremap(res->start, resource_size(res));
2483         if (!virtbase)
2484                 goto failure;
2485
2486         /* HW version check */
2487         for (i = 0; i < ARRAY_SIZE(dma_id_regs); i++) {
2488                 if (dma_id_regs[i].val !=
2489                     readl(virtbase + dma_id_regs[i].reg)) {
2490                         dev_err(&pdev->dev,
2491                                 "[%s] Unknown hardware! Expected 0x%x at 0x%x but got 0x%x\n",
2492                                 __func__,
2493                                 dma_id_regs[i].val,
2494                                 dma_id_regs[i].reg,
2495                                 readl(virtbase + dma_id_regs[i].reg));
2496                         goto failure;
2497                 }
2498         }
2499
2500         /* Get silicon revision */
2501         val = readl(virtbase + D40_DREG_PERIPHID2);
2502
2503         if ((val & 0xf) != D40_PERIPHID2_DESIGNER) {
2504                 dev_err(&pdev->dev,
2505                         "[%s] Unknown designer! Got %x wanted %x\n",
2506                         __func__, val & 0xf, D40_PERIPHID2_DESIGNER);
2507                 goto failure;
2508         }
2509
2510         /* The number of physical channels on this HW */
2511         num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
2512
2513         dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n",
2514                  (val >> 4) & 0xf, res->start);
2515
2516         plat_data = pdev->dev.platform_data;
2517
2518         /* Count the number of logical channels in use */
2519         for (i = 0; i < plat_data->dev_len; i++)
2520                 if (plat_data->dev_rx[i] != 0)
2521                         num_log_chans++;
2522
2523         for (i = 0; i < plat_data->dev_len; i++)
2524                 if (plat_data->dev_tx[i] != 0)
2525                         num_log_chans++;
2526
2527         base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
2528                        (num_phy_chans + num_log_chans + plat_data->memcpy_len) *
2529                        sizeof(struct d40_chan), GFP_KERNEL);
2530
2531         if (base == NULL) {
2532                 dev_err(&pdev->dev, "[%s] Out of memory\n", __func__);
2533                 goto failure;
2534         }
2535
2536         base->rev = (val >> 4) & 0xf;
2537         base->clk = clk;
2538         base->num_phy_chans = num_phy_chans;
2539         base->num_log_chans = num_log_chans;
2540         base->phy_start = res->start;
2541         base->phy_size = resource_size(res);
2542         base->virtbase = virtbase;
2543         base->plat_data = plat_data;
2544         base->dev = &pdev->dev;
2545         base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
2546         base->log_chans = &base->phy_chans[num_phy_chans];
2547
2548         base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res),
2549                                 GFP_KERNEL);
2550         if (!base->phy_res)
2551                 goto failure;
2552
2553         base->lookup_phy_chans = kzalloc(num_phy_chans *
2554                                          sizeof(struct d40_chan *),
2555                                          GFP_KERNEL);
2556         if (!base->lookup_phy_chans)
2557                 goto failure;
2558
2559         if (num_log_chans + plat_data->memcpy_len) {
2560                 /*
2561                  * The max number of logical channels are event lines for all
2562                  * src devices and dst devices
2563                  */
2564                 base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 *
2565                                                  sizeof(struct d40_chan *),
2566                                                  GFP_KERNEL);
2567                 if (!base->lookup_log_chans)
2568                         goto failure;
2569         }
2570         base->lcla_pool.alloc_map = kzalloc(num_phy_chans * sizeof(u32),
2571                                             GFP_KERNEL);
2572         if (!base->lcla_pool.alloc_map)
2573                 goto failure;
2574
2575         base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
2576                                             0, SLAB_HWCACHE_ALIGN,
2577                                             NULL);
2578         if (base->desc_slab == NULL)
2579                 goto failure;
2580
2581         return base;
2582
2583 failure:
2584         if (clk) {
2585                 clk_disable(clk);
2586                 clk_put(clk);
2587         }
2588         if (virtbase)
2589                 iounmap(virtbase);
2590         if (res)
2591                 release_mem_region(res->start,
2592                                    resource_size(res));
2593         if (virtbase)
2594                 iounmap(virtbase);
2595
2596         if (base) {
2597                 kfree(base->lcla_pool.alloc_map);
2598                 kfree(base->lookup_log_chans);
2599                 kfree(base->lookup_phy_chans);
2600                 kfree(base->phy_res);
2601                 kfree(base);
2602         }
2603
2604         return NULL;
2605 }
2606
2607 static void __init d40_hw_init(struct d40_base *base)
2608 {
2609
2610         static const struct d40_reg_val dma_init_reg[] = {
2611                 /* Clock every part of the DMA block from start */
2612                 { .reg = D40_DREG_GCC,    .val = 0x0000ff01},
2613
2614                 /* Interrupts on all logical channels */
2615                 { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
2616                 { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
2617                 { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
2618                 { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
2619                 { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
2620                 { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
2621                 { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
2622                 { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
2623                 { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
2624                 { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
2625                 { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
2626                 { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
2627         };
2628         int i;
2629         u32 prmseo[2] = {0, 0};
2630         u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
2631         u32 pcmis = 0;
2632         u32 pcicr = 0;
2633
2634         for (i = 0; i < ARRAY_SIZE(dma_init_reg); i++)
2635                 writel(dma_init_reg[i].val,
2636                        base->virtbase + dma_init_reg[i].reg);
2637
2638         /* Configure all our dma channels to default settings */
2639         for (i = 0; i < base->num_phy_chans; i++) {
2640
2641                 activeo[i % 2] = activeo[i % 2] << 2;
2642
2643                 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
2644                     == D40_ALLOC_PHY) {
2645                         activeo[i % 2] |= 3;
2646                         continue;
2647                 }
2648
2649                 /* Enable interrupt # */
2650                 pcmis = (pcmis << 1) | 1;
2651
2652                 /* Clear interrupt # */
2653                 pcicr = (pcicr << 1) | 1;
2654
2655                 /* Set channel to physical mode */
2656                 prmseo[i % 2] = prmseo[i % 2] << 2;
2657                 prmseo[i % 2] |= 1;
2658
2659         }
2660
2661         writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
2662         writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
2663         writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
2664         writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
2665
2666         /* Write which interrupt to enable */
2667         writel(pcmis, base->virtbase + D40_DREG_PCMIS);
2668
2669         /* Write which interrupt to clear */
2670         writel(pcicr, base->virtbase + D40_DREG_PCICR);
2671
2672 }
2673
2674 static int __init d40_lcla_allocate(struct d40_base *base)
2675 {
2676         unsigned long *page_list;
2677         int i, j;
2678         int ret = 0;
2679
2680         /*
2681          * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
2682          * To full fill this hardware requirement without wasting 256 kb
2683          * we allocate pages until we get an aligned one.
2684          */
2685         page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
2686                             GFP_KERNEL);
2687
2688         if (!page_list) {
2689                 ret = -ENOMEM;
2690                 goto failure;
2691         }
2692
2693         /* Calculating how many pages that are required */
2694         base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
2695
2696         for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
2697                 page_list[i] = __get_free_pages(GFP_KERNEL,
2698                                                 base->lcla_pool.pages);
2699                 if (!page_list[i]) {
2700
2701                         dev_err(base->dev,
2702                                 "[%s] Failed to allocate %d pages.\n",
2703                                 __func__, base->lcla_pool.pages);
2704
2705                         for (j = 0; j < i; j++)
2706                                 free_pages(page_list[j], base->lcla_pool.pages);
2707                         goto failure;
2708                 }
2709
2710                 if ((virt_to_phys((void *)page_list[i]) &
2711                      (LCLA_ALIGNMENT - 1)) == 0)
2712                         break;
2713         }
2714
2715         for (j = 0; j < i; j++)
2716                 free_pages(page_list[j], base->lcla_pool.pages);
2717
2718         if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
2719                 base->lcla_pool.base = (void *)page_list[i];
2720         } else {
2721                 /* After many attempts, no succees with finding the correct
2722                  * alignment try with allocating a big buffer */
2723                 dev_warn(base->dev,
2724                          "[%s] Failed to get %d pages @ 18 bit align.\n",
2725                          __func__, base->lcla_pool.pages);
2726                 base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
2727                                                          base->num_phy_chans +
2728                                                          LCLA_ALIGNMENT,
2729                                                          GFP_KERNEL);
2730                 if (!base->lcla_pool.base_unaligned) {
2731                         ret = -ENOMEM;
2732                         goto failure;
2733                 }
2734
2735                 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
2736                                                  LCLA_ALIGNMENT);
2737         }
2738
2739         writel(virt_to_phys(base->lcla_pool.base),
2740                base->virtbase + D40_DREG_LCLA);
2741 failure:
2742         kfree(page_list);
2743         return ret;
2744 }
2745
2746 static int __init d40_probe(struct platform_device *pdev)
2747 {
2748         int err;
2749         int ret = -ENOENT;
2750         struct d40_base *base;
2751         struct resource *res = NULL;
2752         int num_reserved_chans;
2753         u32 val;
2754
2755         base = d40_hw_detect_init(pdev);
2756
2757         if (!base)
2758                 goto failure;
2759
2760         num_reserved_chans = d40_phy_res_init(base);
2761
2762         platform_set_drvdata(pdev, base);
2763
2764         spin_lock_init(&base->interrupt_lock);
2765         spin_lock_init(&base->execmd_lock);
2766
2767         /* Get IO for logical channel parameter address */
2768         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
2769         if (!res) {
2770                 ret = -ENOENT;
2771                 dev_err(&pdev->dev,
2772                         "[%s] No \"lcpa\" memory resource\n",
2773                         __func__);
2774                 goto failure;
2775         }
2776         base->lcpa_size = resource_size(res);
2777         base->phy_lcpa = res->start;
2778
2779         if (request_mem_region(res->start, resource_size(res),
2780                                D40_NAME " I/O lcpa") == NULL) {
2781                 ret = -EBUSY;
2782                 dev_err(&pdev->dev,
2783                         "[%s] Failed to request LCPA region 0x%x-0x%x\n",
2784                         __func__, res->start, res->end);
2785                 goto failure;
2786         }
2787
2788         /* We make use of ESRAM memory for this. */
2789         val = readl(base->virtbase + D40_DREG_LCPA);
2790         if (res->start != val && val != 0) {
2791                 dev_warn(&pdev->dev,
2792                          "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
2793                          __func__, val, res->start);
2794         } else
2795                 writel(res->start, base->virtbase + D40_DREG_LCPA);
2796
2797         base->lcpa_base = ioremap(res->start, resource_size(res));
2798         if (!base->lcpa_base) {
2799                 ret = -ENOMEM;
2800                 dev_err(&pdev->dev,
2801                         "[%s] Failed to ioremap LCPA region\n",
2802                         __func__);
2803                 goto failure;
2804         }
2805
2806         ret = d40_lcla_allocate(base);
2807         if (ret) {
2808                 dev_err(&pdev->dev, "[%s] Failed to allocate LCLA area\n",
2809                         __func__);
2810                 goto failure;
2811         }
2812
2813         spin_lock_init(&base->lcla_pool.lock);
2814
2815         base->lcla_pool.num_blocks = base->num_phy_chans;
2816
2817         base->irq = platform_get_irq(pdev, 0);
2818
2819         ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
2820
2821         if (ret) {
2822                 dev_err(&pdev->dev, "[%s] No IRQ defined\n", __func__);
2823                 goto failure;
2824         }
2825
2826         err = d40_dmaengine_init(base, num_reserved_chans);
2827         if (err)
2828                 goto failure;
2829
2830         d40_hw_init(base);
2831
2832         dev_info(base->dev, "initialized\n");
2833         return 0;
2834
2835 failure:
2836         if (base) {
2837                 if (base->desc_slab)
2838                         kmem_cache_destroy(base->desc_slab);
2839                 if (base->virtbase)
2840                         iounmap(base->virtbase);
2841                 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
2842                         free_pages((unsigned long)base->lcla_pool.base,
2843                                    base->lcla_pool.pages);
2844                 if (base->lcla_pool.base_unaligned)
2845                         kfree(base->lcla_pool.base_unaligned);
2846                 if (base->phy_lcpa)
2847                         release_mem_region(base->phy_lcpa,
2848                                            base->lcpa_size);
2849                 if (base->phy_start)
2850                         release_mem_region(base->phy_start,
2851                                            base->phy_size);
2852                 if (base->clk) {
2853                         clk_disable(base->clk);
2854                         clk_put(base->clk);
2855                 }
2856
2857                 kfree(base->lcla_pool.alloc_map);
2858                 kfree(base->lookup_log_chans);
2859                 kfree(base->lookup_phy_chans);
2860                 kfree(base->phy_res);
2861                 kfree(base);
2862         }
2863
2864         dev_err(&pdev->dev, "[%s] probe failed\n", __func__);
2865         return ret;
2866 }
2867
2868 static struct platform_driver d40_driver = {
2869         .driver = {
2870                 .owner = THIS_MODULE,
2871                 .name  = D40_NAME,
2872         },
2873 };
2874
2875 int __init stedma40_init(void)
2876 {
2877         return platform_driver_probe(&d40_driver, d40_probe);
2878 }
2879 arch_initcall(stedma40_init);