Merge branch 'sh/stable-updates'
[linux-2.6.git] / drivers / dma / shdma.c
1 /*
2  * Renesas SuperH DMA Engine support
3  *
4  * base is drivers/dma/flsdma.c
5  *
6  * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
7  * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
8  * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
9  *
10  * This is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * - DMA of SuperH does not have Hardware DMA chain mode.
16  * - MAX DMA size is 16MB.
17  *
18  */
19
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/slab.h>
23 #include <linux/interrupt.h>
24 #include <linux/dmaengine.h>
25 #include <linux/delay.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/sh_dma.h>
30
31 #include "shdma.h"
32
33 /* DMA descriptor control */
34 enum sh_dmae_desc_status {
35         DESC_IDLE,
36         DESC_PREPARED,
37         DESC_SUBMITTED,
38         DESC_COMPLETED, /* completed, have to call callback */
39         DESC_WAITING,   /* callback called, waiting for ack / re-submit */
40 };
41
42 #define NR_DESCS_PER_CHANNEL 32
43 /* Default MEMCPY transfer size = 2^2 = 4 bytes */
44 #define LOG2_DEFAULT_XFER_SIZE  2
45
46 /* A bitmask with bits enough for enum sh_dmae_slave_chan_id */
47 static unsigned long sh_dmae_slave_used[BITS_TO_LONGS(SH_DMA_SLAVE_NUMBER)];
48
49 static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all);
50
51 static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg)
52 {
53         __raw_writel(data, sh_dc->base + reg / sizeof(u32));
54 }
55
56 static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
57 {
58         return __raw_readl(sh_dc->base + reg / sizeof(u32));
59 }
60
61 static u16 dmaor_read(struct sh_dmae_device *shdev)
62 {
63         return __raw_readw(shdev->chan_reg + DMAOR / sizeof(u32));
64 }
65
66 static void dmaor_write(struct sh_dmae_device *shdev, u16 data)
67 {
68         __raw_writew(data, shdev->chan_reg + DMAOR / sizeof(u32));
69 }
70
71 /*
72  * Reset DMA controller
73  *
74  * SH7780 has two DMAOR register
75  */
76 static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev)
77 {
78         unsigned short dmaor = dmaor_read(shdev);
79
80         dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME));
81 }
82
83 static int sh_dmae_rst(struct sh_dmae_device *shdev)
84 {
85         unsigned short dmaor;
86
87         sh_dmae_ctl_stop(shdev);
88         dmaor = dmaor_read(shdev) | shdev->pdata->dmaor_init;
89
90         dmaor_write(shdev, dmaor);
91         if (dmaor_read(shdev) & (DMAOR_AE | DMAOR_NMIF)) {
92                 pr_warning("dma-sh: Can't initialize DMAOR.\n");
93                 return -EINVAL;
94         }
95         return 0;
96 }
97
98 static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
99 {
100         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
101
102         if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE)
103                 return true; /* working */
104
105         return false; /* waiting */
106 }
107
108 static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr)
109 {
110         struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
111                                                 struct sh_dmae_device, common);
112         struct sh_dmae_pdata *pdata = shdev->pdata;
113         int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) |
114                 ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift);
115
116         if (cnt >= pdata->ts_shift_num)
117                 cnt = 0;
118
119         return pdata->ts_shift[cnt];
120 }
121
122 static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size)
123 {
124         struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
125                                                 struct sh_dmae_device, common);
126         struct sh_dmae_pdata *pdata = shdev->pdata;
127         int i;
128
129         for (i = 0; i < pdata->ts_shift_num; i++)
130                 if (pdata->ts_shift[i] == l2size)
131                         break;
132
133         if (i == pdata->ts_shift_num)
134                 i = 0;
135
136         return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) |
137                 ((i << pdata->ts_high_shift) & pdata->ts_high_mask);
138 }
139
140 static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
141 {
142         sh_dmae_writel(sh_chan, hw->sar, SAR);
143         sh_dmae_writel(sh_chan, hw->dar, DAR);
144         sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR);
145 }
146
147 static void dmae_start(struct sh_dmae_chan *sh_chan)
148 {
149         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
150
151         chcr |= CHCR_DE | CHCR_IE;
152         sh_dmae_writel(sh_chan, chcr & ~CHCR_TE, CHCR);
153 }
154
155 static void dmae_halt(struct sh_dmae_chan *sh_chan)
156 {
157         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
158
159         chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
160         sh_dmae_writel(sh_chan, chcr, CHCR);
161 }
162
163 static void dmae_init(struct sh_dmae_chan *sh_chan)
164 {
165         /*
166          * Default configuration for dual address memory-memory transfer.
167          * 0x400 represents auto-request.
168          */
169         u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan,
170                                                    LOG2_DEFAULT_XFER_SIZE);
171         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
172         sh_dmae_writel(sh_chan, chcr, CHCR);
173 }
174
175 static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
176 {
177         /* When DMA was working, can not set data to CHCR */
178         if (dmae_is_busy(sh_chan))
179                 return -EBUSY;
180
181         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val);
182         sh_dmae_writel(sh_chan, val, CHCR);
183
184         return 0;
185 }
186
187 static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
188 {
189         struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
190                                                 struct sh_dmae_device, common);
191         struct sh_dmae_pdata *pdata = shdev->pdata;
192         const struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->id];
193         u16 __iomem *addr = shdev->dmars + chan_pdata->dmars / sizeof(u16);
194         int shift = chan_pdata->dmars_bit;
195
196         if (dmae_is_busy(sh_chan))
197                 return -EBUSY;
198
199         __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift),
200                      addr);
201
202         return 0;
203 }
204
205 static dma_cookie_t sh_dmae_tx_submit(struct dma_async_tx_descriptor *tx)
206 {
207         struct sh_desc *desc = tx_to_sh_desc(tx), *chunk, *last = desc, *c;
208         struct sh_dmae_chan *sh_chan = to_sh_chan(tx->chan);
209         dma_async_tx_callback callback = tx->callback;
210         dma_cookie_t cookie;
211
212         spin_lock_bh(&sh_chan->desc_lock);
213
214         cookie = sh_chan->common.cookie;
215         cookie++;
216         if (cookie < 0)
217                 cookie = 1;
218
219         sh_chan->common.cookie = cookie;
220         tx->cookie = cookie;
221
222         /* Mark all chunks of this descriptor as submitted, move to the queue */
223         list_for_each_entry_safe(chunk, c, desc->node.prev, node) {
224                 /*
225                  * All chunks are on the global ld_free, so, we have to find
226                  * the end of the chain ourselves
227                  */
228                 if (chunk != desc && (chunk->mark == DESC_IDLE ||
229                                       chunk->async_tx.cookie > 0 ||
230                                       chunk->async_tx.cookie == -EBUSY ||
231                                       &chunk->node == &sh_chan->ld_free))
232                         break;
233                 chunk->mark = DESC_SUBMITTED;
234                 /* Callback goes to the last chunk */
235                 chunk->async_tx.callback = NULL;
236                 chunk->cookie = cookie;
237                 list_move_tail(&chunk->node, &sh_chan->ld_queue);
238                 last = chunk;
239         }
240
241         last->async_tx.callback = callback;
242         last->async_tx.callback_param = tx->callback_param;
243
244         dev_dbg(sh_chan->dev, "submit #%d@%p on %d: %x[%d] -> %x\n",
245                 tx->cookie, &last->async_tx, sh_chan->id,
246                 desc->hw.sar, desc->hw.tcr, desc->hw.dar);
247
248         spin_unlock_bh(&sh_chan->desc_lock);
249
250         return cookie;
251 }
252
253 /* Called with desc_lock held */
254 static struct sh_desc *sh_dmae_get_desc(struct sh_dmae_chan *sh_chan)
255 {
256         struct sh_desc *desc;
257
258         list_for_each_entry(desc, &sh_chan->ld_free, node)
259                 if (desc->mark != DESC_PREPARED) {
260                         BUG_ON(desc->mark != DESC_IDLE);
261                         list_del(&desc->node);
262                         return desc;
263                 }
264
265         return NULL;
266 }
267
268 static const struct sh_dmae_slave_config *sh_dmae_find_slave(
269         struct sh_dmae_chan *sh_chan, struct sh_dmae_slave *param)
270 {
271         struct dma_device *dma_dev = sh_chan->common.device;
272         struct sh_dmae_device *shdev = container_of(dma_dev,
273                                         struct sh_dmae_device, common);
274         struct sh_dmae_pdata *pdata = shdev->pdata;
275         int i;
276
277         if (param->slave_id >= SH_DMA_SLAVE_NUMBER)
278                 return NULL;
279
280         for (i = 0; i < pdata->slave_num; i++)
281                 if (pdata->slave[i].slave_id == param->slave_id)
282                         return pdata->slave + i;
283
284         return NULL;
285 }
286
287 static int sh_dmae_alloc_chan_resources(struct dma_chan *chan)
288 {
289         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
290         struct sh_desc *desc;
291         struct sh_dmae_slave *param = chan->private;
292         int ret;
293
294         pm_runtime_get_sync(sh_chan->dev);
295
296         /*
297          * This relies on the guarantee from dmaengine that alloc_chan_resources
298          * never runs concurrently with itself or free_chan_resources.
299          */
300         if (param) {
301                 const struct sh_dmae_slave_config *cfg;
302
303                 cfg = sh_dmae_find_slave(sh_chan, param);
304                 if (!cfg) {
305                         ret = -EINVAL;
306                         goto efindslave;
307                 }
308
309                 if (test_and_set_bit(param->slave_id, sh_dmae_slave_used)) {
310                         ret = -EBUSY;
311                         goto etestused;
312                 }
313
314                 param->config = cfg;
315
316                 dmae_set_dmars(sh_chan, cfg->mid_rid);
317                 dmae_set_chcr(sh_chan, cfg->chcr);
318         } else if ((sh_dmae_readl(sh_chan, CHCR) & 0xf00) != 0x400) {
319                 dmae_init(sh_chan);
320         }
321
322         spin_lock_bh(&sh_chan->desc_lock);
323         while (sh_chan->descs_allocated < NR_DESCS_PER_CHANNEL) {
324                 spin_unlock_bh(&sh_chan->desc_lock);
325                 desc = kzalloc(sizeof(struct sh_desc), GFP_KERNEL);
326                 if (!desc) {
327                         spin_lock_bh(&sh_chan->desc_lock);
328                         break;
329                 }
330                 dma_async_tx_descriptor_init(&desc->async_tx,
331                                         &sh_chan->common);
332                 desc->async_tx.tx_submit = sh_dmae_tx_submit;
333                 desc->mark = DESC_IDLE;
334
335                 spin_lock_bh(&sh_chan->desc_lock);
336                 list_add(&desc->node, &sh_chan->ld_free);
337                 sh_chan->descs_allocated++;
338         }
339         spin_unlock_bh(&sh_chan->desc_lock);
340
341         if (!sh_chan->descs_allocated) {
342                 ret = -ENOMEM;
343                 goto edescalloc;
344         }
345
346         return sh_chan->descs_allocated;
347
348 edescalloc:
349         if (param)
350                 clear_bit(param->slave_id, sh_dmae_slave_used);
351 etestused:
352 efindslave:
353         pm_runtime_put(sh_chan->dev);
354         return ret;
355 }
356
357 /*
358  * sh_dma_free_chan_resources - Free all resources of the channel.
359  */
360 static void sh_dmae_free_chan_resources(struct dma_chan *chan)
361 {
362         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
363         struct sh_desc *desc, *_desc;
364         LIST_HEAD(list);
365         int descs = sh_chan->descs_allocated;
366
367         dmae_halt(sh_chan);
368
369         /* Prepared and not submitted descriptors can still be on the queue */
370         if (!list_empty(&sh_chan->ld_queue))
371                 sh_dmae_chan_ld_cleanup(sh_chan, true);
372
373         if (chan->private) {
374                 /* The caller is holding dma_list_mutex */
375                 struct sh_dmae_slave *param = chan->private;
376                 clear_bit(param->slave_id, sh_dmae_slave_used);
377         }
378
379         spin_lock_bh(&sh_chan->desc_lock);
380
381         list_splice_init(&sh_chan->ld_free, &list);
382         sh_chan->descs_allocated = 0;
383
384         spin_unlock_bh(&sh_chan->desc_lock);
385
386         if (descs > 0)
387                 pm_runtime_put(sh_chan->dev);
388
389         list_for_each_entry_safe(desc, _desc, &list, node)
390                 kfree(desc);
391 }
392
393 /**
394  * sh_dmae_add_desc - get, set up and return one transfer descriptor
395  * @sh_chan:    DMA channel
396  * @flags:      DMA transfer flags
397  * @dest:       destination DMA address, incremented when direction equals
398  *              DMA_FROM_DEVICE or DMA_BIDIRECTIONAL
399  * @src:        source DMA address, incremented when direction equals
400  *              DMA_TO_DEVICE or DMA_BIDIRECTIONAL
401  * @len:        DMA transfer length
402  * @first:      if NULL, set to the current descriptor and cookie set to -EBUSY
403  * @direction:  needed for slave DMA to decide which address to keep constant,
404  *              equals DMA_BIDIRECTIONAL for MEMCPY
405  * Returns 0 or an error
406  * Locks: called with desc_lock held
407  */
408 static struct sh_desc *sh_dmae_add_desc(struct sh_dmae_chan *sh_chan,
409         unsigned long flags, dma_addr_t *dest, dma_addr_t *src, size_t *len,
410         struct sh_desc **first, enum dma_data_direction direction)
411 {
412         struct sh_desc *new;
413         size_t copy_size;
414
415         if (!*len)
416                 return NULL;
417
418         /* Allocate the link descriptor from the free list */
419         new = sh_dmae_get_desc(sh_chan);
420         if (!new) {
421                 dev_err(sh_chan->dev, "No free link descriptor available\n");
422                 return NULL;
423         }
424
425         copy_size = min(*len, (size_t)SH_DMA_TCR_MAX + 1);
426
427         new->hw.sar = *src;
428         new->hw.dar = *dest;
429         new->hw.tcr = copy_size;
430
431         if (!*first) {
432                 /* First desc */
433                 new->async_tx.cookie = -EBUSY;
434                 *first = new;
435         } else {
436                 /* Other desc - invisible to the user */
437                 new->async_tx.cookie = -EINVAL;
438         }
439
440         dev_dbg(sh_chan->dev,
441                 "chaining (%u/%u)@%x -> %x with %p, cookie %d, shift %d\n",
442                 copy_size, *len, *src, *dest, &new->async_tx,
443                 new->async_tx.cookie, sh_chan->xmit_shift);
444
445         new->mark = DESC_PREPARED;
446         new->async_tx.flags = flags;
447         new->direction = direction;
448
449         *len -= copy_size;
450         if (direction == DMA_BIDIRECTIONAL || direction == DMA_TO_DEVICE)
451                 *src += copy_size;
452         if (direction == DMA_BIDIRECTIONAL || direction == DMA_FROM_DEVICE)
453                 *dest += copy_size;
454
455         return new;
456 }
457
458 /*
459  * sh_dmae_prep_sg - prepare transfer descriptors from an SG list
460  *
461  * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also
462  * converted to scatter-gather to guarantee consistent locking and a correct
463  * list manipulation. For slave DMA direction carries the usual meaning, and,
464  * logically, the SG list is RAM and the addr variable contains slave address,
465  * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_BIDIRECTIONAL
466  * and the SG list contains only one element and points at the source buffer.
467  */
468 static struct dma_async_tx_descriptor *sh_dmae_prep_sg(struct sh_dmae_chan *sh_chan,
469         struct scatterlist *sgl, unsigned int sg_len, dma_addr_t *addr,
470         enum dma_data_direction direction, unsigned long flags)
471 {
472         struct scatterlist *sg;
473         struct sh_desc *first = NULL, *new = NULL /* compiler... */;
474         LIST_HEAD(tx_list);
475         int chunks = 0;
476         int i;
477
478         if (!sg_len)
479                 return NULL;
480
481         for_each_sg(sgl, sg, sg_len, i)
482                 chunks += (sg_dma_len(sg) + SH_DMA_TCR_MAX) /
483                         (SH_DMA_TCR_MAX + 1);
484
485         /* Have to lock the whole loop to protect against concurrent release */
486         spin_lock_bh(&sh_chan->desc_lock);
487
488         /*
489          * Chaining:
490          * first descriptor is what user is dealing with in all API calls, its
491          *      cookie is at first set to -EBUSY, at tx-submit to a positive
492          *      number
493          * if more than one chunk is needed further chunks have cookie = -EINVAL
494          * the last chunk, if not equal to the first, has cookie = -ENOSPC
495          * all chunks are linked onto the tx_list head with their .node heads
496          *      only during this function, then they are immediately spliced
497          *      back onto the free list in form of a chain
498          */
499         for_each_sg(sgl, sg, sg_len, i) {
500                 dma_addr_t sg_addr = sg_dma_address(sg);
501                 size_t len = sg_dma_len(sg);
502
503                 if (!len)
504                         goto err_get_desc;
505
506                 do {
507                         dev_dbg(sh_chan->dev, "Add SG #%d@%p[%d], dma %llx\n",
508                                 i, sg, len, (unsigned long long)sg_addr);
509
510                         if (direction == DMA_FROM_DEVICE)
511                                 new = sh_dmae_add_desc(sh_chan, flags,
512                                                 &sg_addr, addr, &len, &first,
513                                                 direction);
514                         else
515                                 new = sh_dmae_add_desc(sh_chan, flags,
516                                                 addr, &sg_addr, &len, &first,
517                                                 direction);
518                         if (!new)
519                                 goto err_get_desc;
520
521                         new->chunks = chunks--;
522                         list_add_tail(&new->node, &tx_list);
523                 } while (len);
524         }
525
526         if (new != first)
527                 new->async_tx.cookie = -ENOSPC;
528
529         /* Put them back on the free list, so, they don't get lost */
530         list_splice_tail(&tx_list, &sh_chan->ld_free);
531
532         spin_unlock_bh(&sh_chan->desc_lock);
533
534         return &first->async_tx;
535
536 err_get_desc:
537         list_for_each_entry(new, &tx_list, node)
538                 new->mark = DESC_IDLE;
539         list_splice(&tx_list, &sh_chan->ld_free);
540
541         spin_unlock_bh(&sh_chan->desc_lock);
542
543         return NULL;
544 }
545
546 static struct dma_async_tx_descriptor *sh_dmae_prep_memcpy(
547         struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
548         size_t len, unsigned long flags)
549 {
550         struct sh_dmae_chan *sh_chan;
551         struct scatterlist sg;
552
553         if (!chan || !len)
554                 return NULL;
555
556         chan->private = NULL;
557
558         sh_chan = to_sh_chan(chan);
559
560         sg_init_table(&sg, 1);
561         sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_src)), len,
562                     offset_in_page(dma_src));
563         sg_dma_address(&sg) = dma_src;
564         sg_dma_len(&sg) = len;
565
566         return sh_dmae_prep_sg(sh_chan, &sg, 1, &dma_dest, DMA_BIDIRECTIONAL,
567                                flags);
568 }
569
570 static struct dma_async_tx_descriptor *sh_dmae_prep_slave_sg(
571         struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
572         enum dma_data_direction direction, unsigned long flags)
573 {
574         struct sh_dmae_slave *param;
575         struct sh_dmae_chan *sh_chan;
576         dma_addr_t slave_addr;
577
578         if (!chan)
579                 return NULL;
580
581         sh_chan = to_sh_chan(chan);
582         param = chan->private;
583         slave_addr = param->config->addr;
584
585         /* Someone calling slave DMA on a public channel? */
586         if (!param || !sg_len) {
587                 dev_warn(sh_chan->dev, "%s: bad parameter: %p, %d, %d\n",
588                          __func__, param, sg_len, param ? param->slave_id : -1);
589                 return NULL;
590         }
591
592         /*
593          * if (param != NULL), this is a successfully requested slave channel,
594          * therefore param->config != NULL too.
595          */
596         return sh_dmae_prep_sg(sh_chan, sgl, sg_len, &slave_addr,
597                                direction, flags);
598 }
599
600 static void sh_dmae_terminate_all(struct dma_chan *chan)
601 {
602         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
603
604         if (!chan)
605                 return;
606
607         dmae_halt(sh_chan);
608
609         spin_lock_bh(&sh_chan->desc_lock);
610         if (!list_empty(&sh_chan->ld_queue)) {
611                 /* Record partial transfer */
612                 struct sh_desc *desc = list_entry(sh_chan->ld_queue.next,
613                                                   struct sh_desc, node);
614                 desc->partial = (desc->hw.tcr - sh_dmae_readl(sh_chan, TCR)) <<
615                         sh_chan->xmit_shift;
616
617         }
618         spin_unlock_bh(&sh_chan->desc_lock);
619
620         sh_dmae_chan_ld_cleanup(sh_chan, true);
621 }
622
623 static dma_async_tx_callback __ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
624 {
625         struct sh_desc *desc, *_desc;
626         /* Is the "exposed" head of a chain acked? */
627         bool head_acked = false;
628         dma_cookie_t cookie = 0;
629         dma_async_tx_callback callback = NULL;
630         void *param = NULL;
631
632         spin_lock_bh(&sh_chan->desc_lock);
633         list_for_each_entry_safe(desc, _desc, &sh_chan->ld_queue, node) {
634                 struct dma_async_tx_descriptor *tx = &desc->async_tx;
635
636                 BUG_ON(tx->cookie > 0 && tx->cookie != desc->cookie);
637                 BUG_ON(desc->mark != DESC_SUBMITTED &&
638                        desc->mark != DESC_COMPLETED &&
639                        desc->mark != DESC_WAITING);
640
641                 /*
642                  * queue is ordered, and we use this loop to (1) clean up all
643                  * completed descriptors, and to (2) update descriptor flags of
644                  * any chunks in a (partially) completed chain
645                  */
646                 if (!all && desc->mark == DESC_SUBMITTED &&
647                     desc->cookie != cookie)
648                         break;
649
650                 if (tx->cookie > 0)
651                         cookie = tx->cookie;
652
653                 if (desc->mark == DESC_COMPLETED && desc->chunks == 1) {
654                         if (sh_chan->completed_cookie != desc->cookie - 1)
655                                 dev_dbg(sh_chan->dev,
656                                         "Completing cookie %d, expected %d\n",
657                                         desc->cookie,
658                                         sh_chan->completed_cookie + 1);
659                         sh_chan->completed_cookie = desc->cookie;
660                 }
661
662                 /* Call callback on the last chunk */
663                 if (desc->mark == DESC_COMPLETED && tx->callback) {
664                         desc->mark = DESC_WAITING;
665                         callback = tx->callback;
666                         param = tx->callback_param;
667                         dev_dbg(sh_chan->dev, "descriptor #%d@%p on %d callback\n",
668                                 tx->cookie, tx, sh_chan->id);
669                         BUG_ON(desc->chunks != 1);
670                         break;
671                 }
672
673                 if (tx->cookie > 0 || tx->cookie == -EBUSY) {
674                         if (desc->mark == DESC_COMPLETED) {
675                                 BUG_ON(tx->cookie < 0);
676                                 desc->mark = DESC_WAITING;
677                         }
678                         head_acked = async_tx_test_ack(tx);
679                 } else {
680                         switch (desc->mark) {
681                         case DESC_COMPLETED:
682                                 desc->mark = DESC_WAITING;
683                                 /* Fall through */
684                         case DESC_WAITING:
685                                 if (head_acked)
686                                         async_tx_ack(&desc->async_tx);
687                         }
688                 }
689
690                 dev_dbg(sh_chan->dev, "descriptor %p #%d completed.\n",
691                         tx, tx->cookie);
692
693                 if (((desc->mark == DESC_COMPLETED ||
694                       desc->mark == DESC_WAITING) &&
695                      async_tx_test_ack(&desc->async_tx)) || all) {
696                         /* Remove from ld_queue list */
697                         desc->mark = DESC_IDLE;
698                         list_move(&desc->node, &sh_chan->ld_free);
699                 }
700         }
701         spin_unlock_bh(&sh_chan->desc_lock);
702
703         if (callback)
704                 callback(param);
705
706         return callback;
707 }
708
709 /*
710  * sh_chan_ld_cleanup - Clean up link descriptors
711  *
712  * This function cleans up the ld_queue of DMA channel.
713  */
714 static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
715 {
716         while (__ld_cleanup(sh_chan, all))
717                 ;
718 }
719
720 static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan)
721 {
722         struct sh_desc *desc;
723
724         spin_lock_bh(&sh_chan->desc_lock);
725         /* DMA work check */
726         if (dmae_is_busy(sh_chan)) {
727                 spin_unlock_bh(&sh_chan->desc_lock);
728                 return;
729         }
730
731         /* Find the first not transferred desciptor */
732         list_for_each_entry(desc, &sh_chan->ld_queue, node)
733                 if (desc->mark == DESC_SUBMITTED) {
734                         dev_dbg(sh_chan->dev, "Queue #%d to %d: %u@%x -> %x\n",
735                                 desc->async_tx.cookie, sh_chan->id,
736                                 desc->hw.tcr, desc->hw.sar, desc->hw.dar);
737                         /* Get the ld start address from ld_queue */
738                         dmae_set_reg(sh_chan, &desc->hw);
739                         dmae_start(sh_chan);
740                         break;
741                 }
742
743         spin_unlock_bh(&sh_chan->desc_lock);
744 }
745
746 static void sh_dmae_memcpy_issue_pending(struct dma_chan *chan)
747 {
748         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
749         sh_chan_xfer_ld_queue(sh_chan);
750 }
751
752 static enum dma_status sh_dmae_is_complete(struct dma_chan *chan,
753                                         dma_cookie_t cookie,
754                                         dma_cookie_t *done,
755                                         dma_cookie_t *used)
756 {
757         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
758         dma_cookie_t last_used;
759         dma_cookie_t last_complete;
760         enum dma_status status;
761
762         sh_dmae_chan_ld_cleanup(sh_chan, false);
763
764         last_used = chan->cookie;
765         last_complete = sh_chan->completed_cookie;
766         BUG_ON(last_complete < 0);
767
768         if (done)
769                 *done = last_complete;
770
771         if (used)
772                 *used = last_used;
773
774         spin_lock_bh(&sh_chan->desc_lock);
775
776         status = dma_async_is_complete(cookie, last_complete, last_used);
777
778         /*
779          * If we don't find cookie on the queue, it has been aborted and we have
780          * to report error
781          */
782         if (status != DMA_SUCCESS) {
783                 struct sh_desc *desc;
784                 status = DMA_ERROR;
785                 list_for_each_entry(desc, &sh_chan->ld_queue, node)
786                         if (desc->cookie == cookie) {
787                                 status = DMA_IN_PROGRESS;
788                                 break;
789                         }
790         }
791
792         spin_unlock_bh(&sh_chan->desc_lock);
793
794         return status;
795 }
796
797 static irqreturn_t sh_dmae_interrupt(int irq, void *data)
798 {
799         irqreturn_t ret = IRQ_NONE;
800         struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data;
801         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
802
803         if (chcr & CHCR_TE) {
804                 /* DMA stop */
805                 dmae_halt(sh_chan);
806
807                 ret = IRQ_HANDLED;
808                 tasklet_schedule(&sh_chan->tasklet);
809         }
810
811         return ret;
812 }
813
814 #if defined(CONFIG_CPU_SH4)
815 static irqreturn_t sh_dmae_err(int irq, void *data)
816 {
817         struct sh_dmae_device *shdev = (struct sh_dmae_device *)data;
818         int i;
819
820         /* halt the dma controller */
821         sh_dmae_ctl_stop(shdev);
822
823         /* We cannot detect, which channel caused the error, have to reset all */
824         for (i = 0; i < SH_DMAC_MAX_CHANNELS; i++) {
825                 struct sh_dmae_chan *sh_chan = shdev->chan[i];
826                 if (sh_chan) {
827                         struct sh_desc *desc;
828                         /* Stop the channel */
829                         dmae_halt(sh_chan);
830                         /* Complete all  */
831                         list_for_each_entry(desc, &sh_chan->ld_queue, node) {
832                                 struct dma_async_tx_descriptor *tx = &desc->async_tx;
833                                 desc->mark = DESC_IDLE;
834                                 if (tx->callback)
835                                         tx->callback(tx->callback_param);
836                         }
837                         list_splice_init(&sh_chan->ld_queue, &sh_chan->ld_free);
838                 }
839         }
840         sh_dmae_rst(shdev);
841
842         return IRQ_HANDLED;
843 }
844 #endif
845
846 static void dmae_do_tasklet(unsigned long data)
847 {
848         struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data;
849         struct sh_desc *desc;
850         u32 sar_buf = sh_dmae_readl(sh_chan, SAR);
851         u32 dar_buf = sh_dmae_readl(sh_chan, DAR);
852
853         spin_lock(&sh_chan->desc_lock);
854         list_for_each_entry(desc, &sh_chan->ld_queue, node) {
855                 if (desc->mark == DESC_SUBMITTED &&
856                     ((desc->direction == DMA_FROM_DEVICE &&
857                       (desc->hw.dar + desc->hw.tcr) == dar_buf) ||
858                      (desc->hw.sar + desc->hw.tcr) == sar_buf)) {
859                         dev_dbg(sh_chan->dev, "done #%d@%p dst %u\n",
860                                 desc->async_tx.cookie, &desc->async_tx,
861                                 desc->hw.dar);
862                         desc->mark = DESC_COMPLETED;
863                         break;
864                 }
865         }
866         spin_unlock(&sh_chan->desc_lock);
867
868         /* Next desc */
869         sh_chan_xfer_ld_queue(sh_chan);
870         sh_dmae_chan_ld_cleanup(sh_chan, false);
871 }
872
873 static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id,
874                                         int irq, unsigned long flags)
875 {
876         int err;
877         const struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id];
878         struct platform_device *pdev = to_platform_device(shdev->common.dev);
879         struct sh_dmae_chan *new_sh_chan;
880
881         /* alloc channel */
882         new_sh_chan = kzalloc(sizeof(struct sh_dmae_chan), GFP_KERNEL);
883         if (!new_sh_chan) {
884                 dev_err(shdev->common.dev,
885                         "No free memory for allocating dma channels!\n");
886                 return -ENOMEM;
887         }
888
889         /* copy struct dma_device */
890         new_sh_chan->common.device = &shdev->common;
891
892         new_sh_chan->dev = shdev->common.dev;
893         new_sh_chan->id = id;
894         new_sh_chan->irq = irq;
895         new_sh_chan->base = shdev->chan_reg + chan_pdata->offset / sizeof(u32);
896
897         /* Init DMA tasklet */
898         tasklet_init(&new_sh_chan->tasklet, dmae_do_tasklet,
899                         (unsigned long)new_sh_chan);
900
901         /* Init the channel */
902         dmae_init(new_sh_chan);
903
904         spin_lock_init(&new_sh_chan->desc_lock);
905
906         /* Init descripter manage list */
907         INIT_LIST_HEAD(&new_sh_chan->ld_queue);
908         INIT_LIST_HEAD(&new_sh_chan->ld_free);
909
910         /* Add the channel to DMA device channel list */
911         list_add_tail(&new_sh_chan->common.device_node,
912                         &shdev->common.channels);
913         shdev->common.chancnt++;
914
915         if (pdev->id >= 0)
916                 snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
917                          "sh-dmae%d.%d", pdev->id, new_sh_chan->id);
918         else
919                 snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
920                          "sh-dma%d", new_sh_chan->id);
921
922         /* set up channel irq */
923         err = request_irq(irq, &sh_dmae_interrupt, flags,
924                           new_sh_chan->dev_id, new_sh_chan);
925         if (err) {
926                 dev_err(shdev->common.dev, "DMA channel %d request_irq error "
927                         "with return %d\n", id, err);
928                 goto err_no_irq;
929         }
930
931         shdev->chan[id] = new_sh_chan;
932         return 0;
933
934 err_no_irq:
935         /* remove from dmaengine device node */
936         list_del(&new_sh_chan->common.device_node);
937         kfree(new_sh_chan);
938         return err;
939 }
940
941 static void sh_dmae_chan_remove(struct sh_dmae_device *shdev)
942 {
943         int i;
944
945         for (i = shdev->common.chancnt - 1 ; i >= 0 ; i--) {
946                 if (shdev->chan[i]) {
947                         struct sh_dmae_chan *sh_chan = shdev->chan[i];
948
949                         free_irq(sh_chan->irq, sh_chan);
950
951                         list_del(&sh_chan->common.device_node);
952                         kfree(sh_chan);
953                         shdev->chan[i] = NULL;
954                 }
955         }
956         shdev->common.chancnt = 0;
957 }
958
959 static int __init sh_dmae_probe(struct platform_device *pdev)
960 {
961         struct sh_dmae_pdata *pdata = pdev->dev.platform_data;
962         unsigned long irqflags = IRQF_DISABLED,
963                 chan_flag[SH_DMAC_MAX_CHANNELS] = {};
964         int errirq, chan_irq[SH_DMAC_MAX_CHANNELS];
965         int err, i, irq_cnt = 0, irqres = 0;
966         struct sh_dmae_device *shdev;
967         struct resource *chan, *dmars, *errirq_res, *chanirq_res;
968
969         /* get platform data */
970         if (!pdata || !pdata->channel_num)
971                 return -ENODEV;
972
973         chan = platform_get_resource(pdev, IORESOURCE_MEM, 0);
974         /* DMARS area is optional, if absent, this controller cannot do slave DMA */
975         dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1);
976         /*
977          * IRQ resources:
978          * 1. there always must be at least one IRQ IO-resource. On SH4 it is
979          *    the error IRQ, in which case it is the only IRQ in this resource:
980          *    start == end. If it is the only IRQ resource, all channels also
981          *    use the same IRQ.
982          * 2. DMA channel IRQ resources can be specified one per resource or in
983          *    ranges (start != end)
984          * 3. iff all events (channels and, optionally, error) on this
985          *    controller use the same IRQ, only one IRQ resource can be
986          *    specified, otherwise there must be one IRQ per channel, even if
987          *    some of them are equal
988          * 4. if all IRQs on this controller are equal or if some specific IRQs
989          *    specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be
990          *    requested with the IRQF_SHARED flag
991          */
992         errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
993         if (!chan || !errirq_res)
994                 return -ENODEV;
995
996         if (!request_mem_region(chan->start, resource_size(chan), pdev->name)) {
997                 dev_err(&pdev->dev, "DMAC register region already claimed\n");
998                 return -EBUSY;
999         }
1000
1001         if (dmars && !request_mem_region(dmars->start, resource_size(dmars), pdev->name)) {
1002                 dev_err(&pdev->dev, "DMAC DMARS region already claimed\n");
1003                 err = -EBUSY;
1004                 goto ermrdmars;
1005         }
1006
1007         err = -ENOMEM;
1008         shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL);
1009         if (!shdev) {
1010                 dev_err(&pdev->dev, "Not enough memory\n");
1011                 goto ealloc;
1012         }
1013
1014         shdev->chan_reg = ioremap(chan->start, resource_size(chan));
1015         if (!shdev->chan_reg)
1016                 goto emapchan;
1017         if (dmars) {
1018                 shdev->dmars = ioremap(dmars->start, resource_size(dmars));
1019                 if (!shdev->dmars)
1020                         goto emapdmars;
1021         }
1022
1023         /* platform data */
1024         shdev->pdata = pdata;
1025
1026         pm_runtime_enable(&pdev->dev);
1027         pm_runtime_get_sync(&pdev->dev);
1028
1029         /* reset dma controller */
1030         err = sh_dmae_rst(shdev);
1031         if (err)
1032                 goto rst_err;
1033
1034         INIT_LIST_HEAD(&shdev->common.channels);
1035
1036         dma_cap_set(DMA_MEMCPY, shdev->common.cap_mask);
1037         if (dmars)
1038                 dma_cap_set(DMA_SLAVE, shdev->common.cap_mask);
1039
1040         shdev->common.device_alloc_chan_resources
1041                 = sh_dmae_alloc_chan_resources;
1042         shdev->common.device_free_chan_resources = sh_dmae_free_chan_resources;
1043         shdev->common.device_prep_dma_memcpy = sh_dmae_prep_memcpy;
1044         shdev->common.device_is_tx_complete = sh_dmae_is_complete;
1045         shdev->common.device_issue_pending = sh_dmae_memcpy_issue_pending;
1046
1047         /* Compulsory for DMA_SLAVE fields */
1048         shdev->common.device_prep_slave_sg = sh_dmae_prep_slave_sg;
1049         shdev->common.device_terminate_all = sh_dmae_terminate_all;
1050
1051         shdev->common.dev = &pdev->dev;
1052         /* Default transfer size of 32 bytes requires 32-byte alignment */
1053         shdev->common.copy_align = LOG2_DEFAULT_XFER_SIZE;
1054
1055 #if defined(CONFIG_CPU_SH4)
1056         chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1057
1058         if (!chanirq_res)
1059                 chanirq_res = errirq_res;
1060         else
1061                 irqres++;
1062
1063         if (chanirq_res == errirq_res ||
1064             (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE)
1065                 irqflags = IRQF_SHARED;
1066
1067         errirq = errirq_res->start;
1068
1069         err = request_irq(errirq, sh_dmae_err, irqflags,
1070                           "DMAC Address Error", shdev);
1071         if (err) {
1072                 dev_err(&pdev->dev,
1073                         "DMA failed requesting irq #%d, error %d\n",
1074                         errirq, err);
1075                 goto eirq_err;
1076         }
1077
1078 #else
1079         chanirq_res = errirq_res;
1080 #endif /* CONFIG_CPU_SH4 */
1081
1082         if (chanirq_res->start == chanirq_res->end &&
1083             !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
1084                 /* Special case - all multiplexed */
1085                 for (; irq_cnt < pdata->channel_num; irq_cnt++) {
1086                         chan_irq[irq_cnt] = chanirq_res->start;
1087                         chan_flag[irq_cnt] = IRQF_SHARED;
1088                 }
1089         } else {
1090                 do {
1091                         for (i = chanirq_res->start; i <= chanirq_res->end; i++) {
1092                                 if ((errirq_res->flags & IORESOURCE_BITS) ==
1093                                     IORESOURCE_IRQ_SHAREABLE)
1094                                         chan_flag[irq_cnt] = IRQF_SHARED;
1095                                 else
1096                                         chan_flag[irq_cnt] = IRQF_DISABLED;
1097                                 dev_dbg(&pdev->dev,
1098                                         "Found IRQ %d for channel %d\n",
1099                                         i, irq_cnt);
1100                                 chan_irq[irq_cnt++] = i;
1101                         }
1102                         chanirq_res = platform_get_resource(pdev,
1103                                                 IORESOURCE_IRQ, ++irqres);
1104                 } while (irq_cnt < pdata->channel_num && chanirq_res);
1105         }
1106
1107         if (irq_cnt < pdata->channel_num)
1108                 goto eirqres;
1109
1110         /* Create DMA Channel */
1111         for (i = 0; i < pdata->channel_num; i++) {
1112                 err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]);
1113                 if (err)
1114                         goto chan_probe_err;
1115         }
1116
1117         pm_runtime_put(&pdev->dev);
1118
1119         platform_set_drvdata(pdev, shdev);
1120         dma_async_device_register(&shdev->common);
1121
1122         return err;
1123
1124 chan_probe_err:
1125         sh_dmae_chan_remove(shdev);
1126 eirqres:
1127 #if defined(CONFIG_CPU_SH4)
1128         free_irq(errirq, shdev);
1129 eirq_err:
1130 #endif
1131 rst_err:
1132         pm_runtime_put(&pdev->dev);
1133         if (dmars)
1134                 iounmap(shdev->dmars);
1135 emapdmars:
1136         iounmap(shdev->chan_reg);
1137 emapchan:
1138         kfree(shdev);
1139 ealloc:
1140         if (dmars)
1141                 release_mem_region(dmars->start, resource_size(dmars));
1142 ermrdmars:
1143         release_mem_region(chan->start, resource_size(chan));
1144
1145         return err;
1146 }
1147
1148 static int __exit sh_dmae_remove(struct platform_device *pdev)
1149 {
1150         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
1151         struct resource *res;
1152         int errirq = platform_get_irq(pdev, 0);
1153
1154         dma_async_device_unregister(&shdev->common);
1155
1156         if (errirq > 0)
1157                 free_irq(errirq, shdev);
1158
1159         /* channel data remove */
1160         sh_dmae_chan_remove(shdev);
1161
1162         pm_runtime_disable(&pdev->dev);
1163
1164         if (shdev->dmars)
1165                 iounmap(shdev->dmars);
1166         iounmap(shdev->chan_reg);
1167
1168         kfree(shdev);
1169
1170         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1171         if (res)
1172                 release_mem_region(res->start, resource_size(res));
1173         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1174         if (res)
1175                 release_mem_region(res->start, resource_size(res));
1176
1177         return 0;
1178 }
1179
1180 static void sh_dmae_shutdown(struct platform_device *pdev)
1181 {
1182         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
1183         sh_dmae_ctl_stop(shdev);
1184 }
1185
1186 static struct platform_driver sh_dmae_driver = {
1187         .remove         = __exit_p(sh_dmae_remove),
1188         .shutdown       = sh_dmae_shutdown,
1189         .driver = {
1190                 .name   = "sh-dma-engine",
1191         },
1192 };
1193
1194 static int __init sh_dmae_init(void)
1195 {
1196         return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe);
1197 }
1198 module_init(sh_dmae_init);
1199
1200 static void __exit sh_dmae_exit(void)
1201 {
1202         platform_driver_unregister(&sh_dmae_driver);
1203 }
1204 module_exit(sh_dmae_exit);
1205
1206 MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>");
1207 MODULE_DESCRIPTION("Renesas SH DMA Engine driver");
1208 MODULE_LICENSE("GPL");