DMAENGINE: generic slave control v2
[linux-2.6.git] / drivers / dma / shdma.c
1 /*
2  * Renesas SuperH DMA Engine support
3  *
4  * base is drivers/dma/flsdma.c
5  *
6  * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
7  * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
8  * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
9  *
10  * This is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * - DMA of SuperH does not have Hardware DMA chain mode.
16  * - MAX DMA size is 16MB.
17  *
18  */
19
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/interrupt.h>
23 #include <linux/dmaengine.h>
24 #include <linux/delay.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28
29 #include <asm/dmaengine.h>
30
31 #include "shdma.h"
32
33 /* DMA descriptor control */
34 enum sh_dmae_desc_status {
35         DESC_IDLE,
36         DESC_PREPARED,
37         DESC_SUBMITTED,
38         DESC_COMPLETED, /* completed, have to call callback */
39         DESC_WAITING,   /* callback called, waiting for ack / re-submit */
40 };
41
42 #define NR_DESCS_PER_CHANNEL 32
43 /* Default MEMCPY transfer size = 2^2 = 4 bytes */
44 #define LOG2_DEFAULT_XFER_SIZE  2
45
46 /* A bitmask with bits enough for enum sh_dmae_slave_chan_id */
47 static unsigned long sh_dmae_slave_used[BITS_TO_LONGS(SHDMA_SLAVE_NUMBER)];
48
49 static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all);
50
51 static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg)
52 {
53         __raw_writel(data, sh_dc->base + reg / sizeof(u32));
54 }
55
56 static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
57 {
58         return __raw_readl(sh_dc->base + reg / sizeof(u32));
59 }
60
61 static u16 dmaor_read(struct sh_dmae_device *shdev)
62 {
63         return __raw_readw(shdev->chan_reg + DMAOR / sizeof(u32));
64 }
65
66 static void dmaor_write(struct sh_dmae_device *shdev, u16 data)
67 {
68         __raw_writew(data, shdev->chan_reg + DMAOR / sizeof(u32));
69 }
70
71 /*
72  * Reset DMA controller
73  *
74  * SH7780 has two DMAOR register
75  */
76 static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev)
77 {
78         unsigned short dmaor = dmaor_read(shdev);
79
80         dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME));
81 }
82
83 static int sh_dmae_rst(struct sh_dmae_device *shdev)
84 {
85         unsigned short dmaor;
86
87         sh_dmae_ctl_stop(shdev);
88         dmaor = dmaor_read(shdev) | shdev->pdata->dmaor_init;
89
90         dmaor_write(shdev, dmaor);
91         if (dmaor_read(shdev) & (DMAOR_AE | DMAOR_NMIF)) {
92                 pr_warning("dma-sh: Can't initialize DMAOR.\n");
93                 return -EINVAL;
94         }
95         return 0;
96 }
97
98 static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
99 {
100         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
101
102         if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE)
103                 return true; /* working */
104
105         return false; /* waiting */
106 }
107
108 static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr)
109 {
110         struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
111                                                 struct sh_dmae_device, common);
112         struct sh_dmae_pdata *pdata = shdev->pdata;
113         int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) |
114                 ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift);
115
116         if (cnt >= pdata->ts_shift_num)
117                 cnt = 0;
118
119         return pdata->ts_shift[cnt];
120 }
121
122 static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size)
123 {
124         struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
125                                                 struct sh_dmae_device, common);
126         struct sh_dmae_pdata *pdata = shdev->pdata;
127         int i;
128
129         for (i = 0; i < pdata->ts_shift_num; i++)
130                 if (pdata->ts_shift[i] == l2size)
131                         break;
132
133         if (i == pdata->ts_shift_num)
134                 i = 0;
135
136         return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) |
137                 ((i << pdata->ts_high_shift) & pdata->ts_high_mask);
138 }
139
140 static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
141 {
142         sh_dmae_writel(sh_chan, hw->sar, SAR);
143         sh_dmae_writel(sh_chan, hw->dar, DAR);
144         sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR);
145 }
146
147 static void dmae_start(struct sh_dmae_chan *sh_chan)
148 {
149         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
150
151         chcr |= CHCR_DE | CHCR_IE;
152         sh_dmae_writel(sh_chan, chcr & ~CHCR_TE, CHCR);
153 }
154
155 static void dmae_halt(struct sh_dmae_chan *sh_chan)
156 {
157         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
158
159         chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
160         sh_dmae_writel(sh_chan, chcr, CHCR);
161 }
162
163 static void dmae_init(struct sh_dmae_chan *sh_chan)
164 {
165         /*
166          * Default configuration for dual address memory-memory transfer.
167          * 0x400 represents auto-request.
168          */
169         u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan,
170                                                    LOG2_DEFAULT_XFER_SIZE);
171         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
172         sh_dmae_writel(sh_chan, chcr, CHCR);
173 }
174
175 static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
176 {
177         /* When DMA was working, can not set data to CHCR */
178         if (dmae_is_busy(sh_chan))
179                 return -EBUSY;
180
181         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val);
182         sh_dmae_writel(sh_chan, val, CHCR);
183
184         return 0;
185 }
186
187 static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
188 {
189         struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
190                                                 struct sh_dmae_device, common);
191         struct sh_dmae_pdata *pdata = shdev->pdata;
192         struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->id];
193         u16 __iomem *addr = shdev->dmars + chan_pdata->dmars / sizeof(u16);
194         int shift = chan_pdata->dmars_bit;
195
196         if (dmae_is_busy(sh_chan))
197                 return -EBUSY;
198
199         __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift),
200                      addr);
201
202         return 0;
203 }
204
205 static dma_cookie_t sh_dmae_tx_submit(struct dma_async_tx_descriptor *tx)
206 {
207         struct sh_desc *desc = tx_to_sh_desc(tx), *chunk, *last = desc, *c;
208         struct sh_dmae_chan *sh_chan = to_sh_chan(tx->chan);
209         dma_async_tx_callback callback = tx->callback;
210         dma_cookie_t cookie;
211
212         spin_lock_bh(&sh_chan->desc_lock);
213
214         cookie = sh_chan->common.cookie;
215         cookie++;
216         if (cookie < 0)
217                 cookie = 1;
218
219         sh_chan->common.cookie = cookie;
220         tx->cookie = cookie;
221
222         /* Mark all chunks of this descriptor as submitted, move to the queue */
223         list_for_each_entry_safe(chunk, c, desc->node.prev, node) {
224                 /*
225                  * All chunks are on the global ld_free, so, we have to find
226                  * the end of the chain ourselves
227                  */
228                 if (chunk != desc && (chunk->mark == DESC_IDLE ||
229                                       chunk->async_tx.cookie > 0 ||
230                                       chunk->async_tx.cookie == -EBUSY ||
231                                       &chunk->node == &sh_chan->ld_free))
232                         break;
233                 chunk->mark = DESC_SUBMITTED;
234                 /* Callback goes to the last chunk */
235                 chunk->async_tx.callback = NULL;
236                 chunk->cookie = cookie;
237                 list_move_tail(&chunk->node, &sh_chan->ld_queue);
238                 last = chunk;
239         }
240
241         last->async_tx.callback = callback;
242         last->async_tx.callback_param = tx->callback_param;
243
244         dev_dbg(sh_chan->dev, "submit #%d@%p on %d: %x[%d] -> %x\n",
245                 tx->cookie, &last->async_tx, sh_chan->id,
246                 desc->hw.sar, desc->hw.tcr, desc->hw.dar);
247
248         spin_unlock_bh(&sh_chan->desc_lock);
249
250         return cookie;
251 }
252
253 /* Called with desc_lock held */
254 static struct sh_desc *sh_dmae_get_desc(struct sh_dmae_chan *sh_chan)
255 {
256         struct sh_desc *desc;
257
258         list_for_each_entry(desc, &sh_chan->ld_free, node)
259                 if (desc->mark != DESC_PREPARED) {
260                         BUG_ON(desc->mark != DESC_IDLE);
261                         list_del(&desc->node);
262                         return desc;
263                 }
264
265         return NULL;
266 }
267
268 static struct sh_dmae_slave_config *sh_dmae_find_slave(
269         struct sh_dmae_chan *sh_chan, enum sh_dmae_slave_chan_id slave_id)
270 {
271         struct dma_device *dma_dev = sh_chan->common.device;
272         struct sh_dmae_device *shdev = container_of(dma_dev,
273                                         struct sh_dmae_device, common);
274         struct sh_dmae_pdata *pdata = shdev->pdata;
275         int i;
276
277         if ((unsigned)slave_id >= SHDMA_SLAVE_NUMBER)
278                 return NULL;
279
280         for (i = 0; i < pdata->slave_num; i++)
281                 if (pdata->slave[i].slave_id == slave_id)
282                         return pdata->slave + i;
283
284         return NULL;
285 }
286
287 static int sh_dmae_alloc_chan_resources(struct dma_chan *chan)
288 {
289         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
290         struct sh_desc *desc;
291         struct sh_dmae_slave *param = chan->private;
292
293         pm_runtime_get_sync(sh_chan->dev);
294
295         /*
296          * This relies on the guarantee from dmaengine that alloc_chan_resources
297          * never runs concurrently with itself or free_chan_resources.
298          */
299         if (param) {
300                 struct sh_dmae_slave_config *cfg;
301
302                 cfg = sh_dmae_find_slave(sh_chan, param->slave_id);
303                 if (!cfg)
304                         return -EINVAL;
305
306                 if (test_and_set_bit(param->slave_id, sh_dmae_slave_used))
307                         return -EBUSY;
308
309                 param->config = cfg;
310
311                 dmae_set_dmars(sh_chan, cfg->mid_rid);
312                 dmae_set_chcr(sh_chan, cfg->chcr);
313         } else if ((sh_dmae_readl(sh_chan, CHCR) & 0xf00) != 0x400) {
314                 dmae_init(sh_chan);
315         }
316
317         spin_lock_bh(&sh_chan->desc_lock);
318         while (sh_chan->descs_allocated < NR_DESCS_PER_CHANNEL) {
319                 spin_unlock_bh(&sh_chan->desc_lock);
320                 desc = kzalloc(sizeof(struct sh_desc), GFP_KERNEL);
321                 if (!desc) {
322                         spin_lock_bh(&sh_chan->desc_lock);
323                         break;
324                 }
325                 dma_async_tx_descriptor_init(&desc->async_tx,
326                                         &sh_chan->common);
327                 desc->async_tx.tx_submit = sh_dmae_tx_submit;
328                 desc->mark = DESC_IDLE;
329
330                 spin_lock_bh(&sh_chan->desc_lock);
331                 list_add(&desc->node, &sh_chan->ld_free);
332                 sh_chan->descs_allocated++;
333         }
334         spin_unlock_bh(&sh_chan->desc_lock);
335
336         if (!sh_chan->descs_allocated)
337                 pm_runtime_put(sh_chan->dev);
338
339         return sh_chan->descs_allocated;
340 }
341
342 /*
343  * sh_dma_free_chan_resources - Free all resources of the channel.
344  */
345 static void sh_dmae_free_chan_resources(struct dma_chan *chan)
346 {
347         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
348         struct sh_desc *desc, *_desc;
349         LIST_HEAD(list);
350         int descs = sh_chan->descs_allocated;
351
352         dmae_halt(sh_chan);
353
354         /* Prepared and not submitted descriptors can still be on the queue */
355         if (!list_empty(&sh_chan->ld_queue))
356                 sh_dmae_chan_ld_cleanup(sh_chan, true);
357
358         if (chan->private) {
359                 /* The caller is holding dma_list_mutex */
360                 struct sh_dmae_slave *param = chan->private;
361                 clear_bit(param->slave_id, sh_dmae_slave_used);
362         }
363
364         spin_lock_bh(&sh_chan->desc_lock);
365
366         list_splice_init(&sh_chan->ld_free, &list);
367         sh_chan->descs_allocated = 0;
368
369         spin_unlock_bh(&sh_chan->desc_lock);
370
371         if (descs > 0)
372                 pm_runtime_put(sh_chan->dev);
373
374         list_for_each_entry_safe(desc, _desc, &list, node)
375                 kfree(desc);
376 }
377
378 /**
379  * sh_dmae_add_desc - get, set up and return one transfer descriptor
380  * @sh_chan:    DMA channel
381  * @flags:      DMA transfer flags
382  * @dest:       destination DMA address, incremented when direction equals
383  *              DMA_FROM_DEVICE or DMA_BIDIRECTIONAL
384  * @src:        source DMA address, incremented when direction equals
385  *              DMA_TO_DEVICE or DMA_BIDIRECTIONAL
386  * @len:        DMA transfer length
387  * @first:      if NULL, set to the current descriptor and cookie set to -EBUSY
388  * @direction:  needed for slave DMA to decide which address to keep constant,
389  *              equals DMA_BIDIRECTIONAL for MEMCPY
390  * Returns 0 or an error
391  * Locks: called with desc_lock held
392  */
393 static struct sh_desc *sh_dmae_add_desc(struct sh_dmae_chan *sh_chan,
394         unsigned long flags, dma_addr_t *dest, dma_addr_t *src, size_t *len,
395         struct sh_desc **first, enum dma_data_direction direction)
396 {
397         struct sh_desc *new;
398         size_t copy_size;
399
400         if (!*len)
401                 return NULL;
402
403         /* Allocate the link descriptor from the free list */
404         new = sh_dmae_get_desc(sh_chan);
405         if (!new) {
406                 dev_err(sh_chan->dev, "No free link descriptor available\n");
407                 return NULL;
408         }
409
410         copy_size = min(*len, (size_t)SH_DMA_TCR_MAX + 1);
411
412         new->hw.sar = *src;
413         new->hw.dar = *dest;
414         new->hw.tcr = copy_size;
415
416         if (!*first) {
417                 /* First desc */
418                 new->async_tx.cookie = -EBUSY;
419                 *first = new;
420         } else {
421                 /* Other desc - invisible to the user */
422                 new->async_tx.cookie = -EINVAL;
423         }
424
425         dev_dbg(sh_chan->dev,
426                 "chaining (%u/%u)@%x -> %x with %p, cookie %d, shift %d\n",
427                 copy_size, *len, *src, *dest, &new->async_tx,
428                 new->async_tx.cookie, sh_chan->xmit_shift);
429
430         new->mark = DESC_PREPARED;
431         new->async_tx.flags = flags;
432         new->direction = direction;
433
434         *len -= copy_size;
435         if (direction == DMA_BIDIRECTIONAL || direction == DMA_TO_DEVICE)
436                 *src += copy_size;
437         if (direction == DMA_BIDIRECTIONAL || direction == DMA_FROM_DEVICE)
438                 *dest += copy_size;
439
440         return new;
441 }
442
443 /*
444  * sh_dmae_prep_sg - prepare transfer descriptors from an SG list
445  *
446  * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also
447  * converted to scatter-gather to guarantee consistent locking and a correct
448  * list manipulation. For slave DMA direction carries the usual meaning, and,
449  * logically, the SG list is RAM and the addr variable contains slave address,
450  * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_BIDIRECTIONAL
451  * and the SG list contains only one element and points at the source buffer.
452  */
453 static struct dma_async_tx_descriptor *sh_dmae_prep_sg(struct sh_dmae_chan *sh_chan,
454         struct scatterlist *sgl, unsigned int sg_len, dma_addr_t *addr,
455         enum dma_data_direction direction, unsigned long flags)
456 {
457         struct scatterlist *sg;
458         struct sh_desc *first = NULL, *new = NULL /* compiler... */;
459         LIST_HEAD(tx_list);
460         int chunks = 0;
461         int i;
462
463         if (!sg_len)
464                 return NULL;
465
466         for_each_sg(sgl, sg, sg_len, i)
467                 chunks += (sg_dma_len(sg) + SH_DMA_TCR_MAX) /
468                         (SH_DMA_TCR_MAX + 1);
469
470         /* Have to lock the whole loop to protect against concurrent release */
471         spin_lock_bh(&sh_chan->desc_lock);
472
473         /*
474          * Chaining:
475          * first descriptor is what user is dealing with in all API calls, its
476          *      cookie is at first set to -EBUSY, at tx-submit to a positive
477          *      number
478          * if more than one chunk is needed further chunks have cookie = -EINVAL
479          * the last chunk, if not equal to the first, has cookie = -ENOSPC
480          * all chunks are linked onto the tx_list head with their .node heads
481          *      only during this function, then they are immediately spliced
482          *      back onto the free list in form of a chain
483          */
484         for_each_sg(sgl, sg, sg_len, i) {
485                 dma_addr_t sg_addr = sg_dma_address(sg);
486                 size_t len = sg_dma_len(sg);
487
488                 if (!len)
489                         goto err_get_desc;
490
491                 do {
492                         dev_dbg(sh_chan->dev, "Add SG #%d@%p[%d], dma %llx\n",
493                                 i, sg, len, (unsigned long long)sg_addr);
494
495                         if (direction == DMA_FROM_DEVICE)
496                                 new = sh_dmae_add_desc(sh_chan, flags,
497                                                 &sg_addr, addr, &len, &first,
498                                                 direction);
499                         else
500                                 new = sh_dmae_add_desc(sh_chan, flags,
501                                                 addr, &sg_addr, &len, &first,
502                                                 direction);
503                         if (!new)
504                                 goto err_get_desc;
505
506                         new->chunks = chunks--;
507                         list_add_tail(&new->node, &tx_list);
508                 } while (len);
509         }
510
511         if (new != first)
512                 new->async_tx.cookie = -ENOSPC;
513
514         /* Put them back on the free list, so, they don't get lost */
515         list_splice_tail(&tx_list, &sh_chan->ld_free);
516
517         spin_unlock_bh(&sh_chan->desc_lock);
518
519         return &first->async_tx;
520
521 err_get_desc:
522         list_for_each_entry(new, &tx_list, node)
523                 new->mark = DESC_IDLE;
524         list_splice(&tx_list, &sh_chan->ld_free);
525
526         spin_unlock_bh(&sh_chan->desc_lock);
527
528         return NULL;
529 }
530
531 static struct dma_async_tx_descriptor *sh_dmae_prep_memcpy(
532         struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
533         size_t len, unsigned long flags)
534 {
535         struct sh_dmae_chan *sh_chan;
536         struct scatterlist sg;
537
538         if (!chan || !len)
539                 return NULL;
540
541         chan->private = NULL;
542
543         sh_chan = to_sh_chan(chan);
544
545         sg_init_table(&sg, 1);
546         sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_src)), len,
547                     offset_in_page(dma_src));
548         sg_dma_address(&sg) = dma_src;
549         sg_dma_len(&sg) = len;
550
551         return sh_dmae_prep_sg(sh_chan, &sg, 1, &dma_dest, DMA_BIDIRECTIONAL,
552                                flags);
553 }
554
555 static struct dma_async_tx_descriptor *sh_dmae_prep_slave_sg(
556         struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
557         enum dma_data_direction direction, unsigned long flags)
558 {
559         struct sh_dmae_slave *param;
560         struct sh_dmae_chan *sh_chan;
561
562         if (!chan)
563                 return NULL;
564
565         sh_chan = to_sh_chan(chan);
566         param = chan->private;
567
568         /* Someone calling slave DMA on a public channel? */
569         if (!param || !sg_len) {
570                 dev_warn(sh_chan->dev, "%s: bad parameter: %p, %d, %d\n",
571                          __func__, param, sg_len, param ? param->slave_id : -1);
572                 return NULL;
573         }
574
575         /*
576          * if (param != NULL), this is a successfully requested slave channel,
577          * therefore param->config != NULL too.
578          */
579         return sh_dmae_prep_sg(sh_chan, sgl, sg_len, &param->config->addr,
580                                direction, flags);
581 }
582
583 static int sh_dmae_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd)
584 {
585         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
586
587         /* Only supports DMA_TERMINATE_ALL */
588         if (cmd != DMA_TERMINATE_ALL)
589                 return -ENXIO;
590
591         if (!chan)
592                 return -EINVAL;
593
594         dmae_halt(sh_chan);
595
596         spin_lock_bh(&sh_chan->desc_lock);
597         if (!list_empty(&sh_chan->ld_queue)) {
598                 /* Record partial transfer */
599                 struct sh_desc *desc = list_entry(sh_chan->ld_queue.next,
600                                                   struct sh_desc, node);
601                 desc->partial = (desc->hw.tcr - sh_dmae_readl(sh_chan, TCR)) <<
602                         sh_chan->xmit_shift;
603
604         }
605         spin_unlock_bh(&sh_chan->desc_lock);
606
607         sh_dmae_chan_ld_cleanup(sh_chan, true);
608
609         return 0;
610 }
611
612 static dma_async_tx_callback __ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
613 {
614         struct sh_desc *desc, *_desc;
615         /* Is the "exposed" head of a chain acked? */
616         bool head_acked = false;
617         dma_cookie_t cookie = 0;
618         dma_async_tx_callback callback = NULL;
619         void *param = NULL;
620
621         spin_lock_bh(&sh_chan->desc_lock);
622         list_for_each_entry_safe(desc, _desc, &sh_chan->ld_queue, node) {
623                 struct dma_async_tx_descriptor *tx = &desc->async_tx;
624
625                 BUG_ON(tx->cookie > 0 && tx->cookie != desc->cookie);
626                 BUG_ON(desc->mark != DESC_SUBMITTED &&
627                        desc->mark != DESC_COMPLETED &&
628                        desc->mark != DESC_WAITING);
629
630                 /*
631                  * queue is ordered, and we use this loop to (1) clean up all
632                  * completed descriptors, and to (2) update descriptor flags of
633                  * any chunks in a (partially) completed chain
634                  */
635                 if (!all && desc->mark == DESC_SUBMITTED &&
636                     desc->cookie != cookie)
637                         break;
638
639                 if (tx->cookie > 0)
640                         cookie = tx->cookie;
641
642                 if (desc->mark == DESC_COMPLETED && desc->chunks == 1) {
643                         if (sh_chan->completed_cookie != desc->cookie - 1)
644                                 dev_dbg(sh_chan->dev,
645                                         "Completing cookie %d, expected %d\n",
646                                         desc->cookie,
647                                         sh_chan->completed_cookie + 1);
648                         sh_chan->completed_cookie = desc->cookie;
649                 }
650
651                 /* Call callback on the last chunk */
652                 if (desc->mark == DESC_COMPLETED && tx->callback) {
653                         desc->mark = DESC_WAITING;
654                         callback = tx->callback;
655                         param = tx->callback_param;
656                         dev_dbg(sh_chan->dev, "descriptor #%d@%p on %d callback\n",
657                                 tx->cookie, tx, sh_chan->id);
658                         BUG_ON(desc->chunks != 1);
659                         break;
660                 }
661
662                 if (tx->cookie > 0 || tx->cookie == -EBUSY) {
663                         if (desc->mark == DESC_COMPLETED) {
664                                 BUG_ON(tx->cookie < 0);
665                                 desc->mark = DESC_WAITING;
666                         }
667                         head_acked = async_tx_test_ack(tx);
668                 } else {
669                         switch (desc->mark) {
670                         case DESC_COMPLETED:
671                                 desc->mark = DESC_WAITING;
672                                 /* Fall through */
673                         case DESC_WAITING:
674                                 if (head_acked)
675                                         async_tx_ack(&desc->async_tx);
676                         }
677                 }
678
679                 dev_dbg(sh_chan->dev, "descriptor %p #%d completed.\n",
680                         tx, tx->cookie);
681
682                 if (((desc->mark == DESC_COMPLETED ||
683                       desc->mark == DESC_WAITING) &&
684                      async_tx_test_ack(&desc->async_tx)) || all) {
685                         /* Remove from ld_queue list */
686                         desc->mark = DESC_IDLE;
687                         list_move(&desc->node, &sh_chan->ld_free);
688                 }
689         }
690         spin_unlock_bh(&sh_chan->desc_lock);
691
692         if (callback)
693                 callback(param);
694
695         return callback;
696 }
697
698 /*
699  * sh_chan_ld_cleanup - Clean up link descriptors
700  *
701  * This function cleans up the ld_queue of DMA channel.
702  */
703 static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
704 {
705         while (__ld_cleanup(sh_chan, all))
706                 ;
707 }
708
709 static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan)
710 {
711         struct sh_desc *desc;
712
713         spin_lock_bh(&sh_chan->desc_lock);
714         /* DMA work check */
715         if (dmae_is_busy(sh_chan)) {
716                 spin_unlock_bh(&sh_chan->desc_lock);
717                 return;
718         }
719
720         /* Find the first not transferred desciptor */
721         list_for_each_entry(desc, &sh_chan->ld_queue, node)
722                 if (desc->mark == DESC_SUBMITTED) {
723                         dev_dbg(sh_chan->dev, "Queue #%d to %d: %u@%x -> %x\n",
724                                 desc->async_tx.cookie, sh_chan->id,
725                                 desc->hw.tcr, desc->hw.sar, desc->hw.dar);
726                         /* Get the ld start address from ld_queue */
727                         dmae_set_reg(sh_chan, &desc->hw);
728                         dmae_start(sh_chan);
729                         break;
730                 }
731
732         spin_unlock_bh(&sh_chan->desc_lock);
733 }
734
735 static void sh_dmae_memcpy_issue_pending(struct dma_chan *chan)
736 {
737         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
738         sh_chan_xfer_ld_queue(sh_chan);
739 }
740
741 static enum dma_status sh_dmae_is_complete(struct dma_chan *chan,
742                                         dma_cookie_t cookie,
743                                         dma_cookie_t *done,
744                                         dma_cookie_t *used)
745 {
746         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
747         dma_cookie_t last_used;
748         dma_cookie_t last_complete;
749         enum dma_status status;
750
751         sh_dmae_chan_ld_cleanup(sh_chan, false);
752
753         last_used = chan->cookie;
754         last_complete = sh_chan->completed_cookie;
755         BUG_ON(last_complete < 0);
756
757         if (done)
758                 *done = last_complete;
759
760         if (used)
761                 *used = last_used;
762
763         spin_lock_bh(&sh_chan->desc_lock);
764
765         status = dma_async_is_complete(cookie, last_complete, last_used);
766
767         /*
768          * If we don't find cookie on the queue, it has been aborted and we have
769          * to report error
770          */
771         if (status != DMA_SUCCESS) {
772                 struct sh_desc *desc;
773                 status = DMA_ERROR;
774                 list_for_each_entry(desc, &sh_chan->ld_queue, node)
775                         if (desc->cookie == cookie) {
776                                 status = DMA_IN_PROGRESS;
777                                 break;
778                         }
779         }
780
781         spin_unlock_bh(&sh_chan->desc_lock);
782
783         return status;
784 }
785
786 static irqreturn_t sh_dmae_interrupt(int irq, void *data)
787 {
788         irqreturn_t ret = IRQ_NONE;
789         struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data;
790         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
791
792         if (chcr & CHCR_TE) {
793                 /* DMA stop */
794                 dmae_halt(sh_chan);
795
796                 ret = IRQ_HANDLED;
797                 tasklet_schedule(&sh_chan->tasklet);
798         }
799
800         return ret;
801 }
802
803 #if defined(CONFIG_CPU_SH4)
804 static irqreturn_t sh_dmae_err(int irq, void *data)
805 {
806         struct sh_dmae_device *shdev = (struct sh_dmae_device *)data;
807         int i;
808
809         /* halt the dma controller */
810         sh_dmae_ctl_stop(shdev);
811
812         /* We cannot detect, which channel caused the error, have to reset all */
813         for (i = 0; i < SH_DMAC_MAX_CHANNELS; i++) {
814                 struct sh_dmae_chan *sh_chan = shdev->chan[i];
815                 if (sh_chan) {
816                         struct sh_desc *desc;
817                         /* Stop the channel */
818                         dmae_halt(sh_chan);
819                         /* Complete all  */
820                         list_for_each_entry(desc, &sh_chan->ld_queue, node) {
821                                 struct dma_async_tx_descriptor *tx = &desc->async_tx;
822                                 desc->mark = DESC_IDLE;
823                                 if (tx->callback)
824                                         tx->callback(tx->callback_param);
825                         }
826                         list_splice_init(&sh_chan->ld_queue, &sh_chan->ld_free);
827                 }
828         }
829         sh_dmae_rst(shdev);
830
831         return IRQ_HANDLED;
832 }
833 #endif
834
835 static void dmae_do_tasklet(unsigned long data)
836 {
837         struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data;
838         struct sh_desc *desc;
839         u32 sar_buf = sh_dmae_readl(sh_chan, SAR);
840         u32 dar_buf = sh_dmae_readl(sh_chan, DAR);
841
842         spin_lock(&sh_chan->desc_lock);
843         list_for_each_entry(desc, &sh_chan->ld_queue, node) {
844                 if (desc->mark == DESC_SUBMITTED &&
845                     ((desc->direction == DMA_FROM_DEVICE &&
846                       (desc->hw.dar + desc->hw.tcr) == dar_buf) ||
847                      (desc->hw.sar + desc->hw.tcr) == sar_buf)) {
848                         dev_dbg(sh_chan->dev, "done #%d@%p dst %u\n",
849                                 desc->async_tx.cookie, &desc->async_tx,
850                                 desc->hw.dar);
851                         desc->mark = DESC_COMPLETED;
852                         break;
853                 }
854         }
855         spin_unlock(&sh_chan->desc_lock);
856
857         /* Next desc */
858         sh_chan_xfer_ld_queue(sh_chan);
859         sh_dmae_chan_ld_cleanup(sh_chan, false);
860 }
861
862 static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id,
863                                         int irq, unsigned long flags)
864 {
865         int err;
866         struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id];
867         struct platform_device *pdev = to_platform_device(shdev->common.dev);
868         struct sh_dmae_chan *new_sh_chan;
869
870         /* alloc channel */
871         new_sh_chan = kzalloc(sizeof(struct sh_dmae_chan), GFP_KERNEL);
872         if (!new_sh_chan) {
873                 dev_err(shdev->common.dev,
874                         "No free memory for allocating dma channels!\n");
875                 return -ENOMEM;
876         }
877
878         /* copy struct dma_device */
879         new_sh_chan->common.device = &shdev->common;
880
881         new_sh_chan->dev = shdev->common.dev;
882         new_sh_chan->id = id;
883         new_sh_chan->irq = irq;
884         new_sh_chan->base = shdev->chan_reg + chan_pdata->offset / sizeof(u32);
885
886         /* Init DMA tasklet */
887         tasklet_init(&new_sh_chan->tasklet, dmae_do_tasklet,
888                         (unsigned long)new_sh_chan);
889
890         /* Init the channel */
891         dmae_init(new_sh_chan);
892
893         spin_lock_init(&new_sh_chan->desc_lock);
894
895         /* Init descripter manage list */
896         INIT_LIST_HEAD(&new_sh_chan->ld_queue);
897         INIT_LIST_HEAD(&new_sh_chan->ld_free);
898
899         /* Add the channel to DMA device channel list */
900         list_add_tail(&new_sh_chan->common.device_node,
901                         &shdev->common.channels);
902         shdev->common.chancnt++;
903
904         if (pdev->id >= 0)
905                 snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
906                          "sh-dmae%d.%d", pdev->id, new_sh_chan->id);
907         else
908                 snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
909                          "sh-dma%d", new_sh_chan->id);
910
911         /* set up channel irq */
912         err = request_irq(irq, &sh_dmae_interrupt, flags,
913                           new_sh_chan->dev_id, new_sh_chan);
914         if (err) {
915                 dev_err(shdev->common.dev, "DMA channel %d request_irq error "
916                         "with return %d\n", id, err);
917                 goto err_no_irq;
918         }
919
920         shdev->chan[id] = new_sh_chan;
921         return 0;
922
923 err_no_irq:
924         /* remove from dmaengine device node */
925         list_del(&new_sh_chan->common.device_node);
926         kfree(new_sh_chan);
927         return err;
928 }
929
930 static void sh_dmae_chan_remove(struct sh_dmae_device *shdev)
931 {
932         int i;
933
934         for (i = shdev->common.chancnt - 1 ; i >= 0 ; i--) {
935                 if (shdev->chan[i]) {
936                         struct sh_dmae_chan *sh_chan = shdev->chan[i];
937
938                         free_irq(sh_chan->irq, sh_chan);
939
940                         list_del(&sh_chan->common.device_node);
941                         kfree(sh_chan);
942                         shdev->chan[i] = NULL;
943                 }
944         }
945         shdev->common.chancnt = 0;
946 }
947
948 static int __init sh_dmae_probe(struct platform_device *pdev)
949 {
950         struct sh_dmae_pdata *pdata = pdev->dev.platform_data;
951         unsigned long irqflags = IRQF_DISABLED,
952                 chan_flag[SH_DMAC_MAX_CHANNELS] = {};
953         int errirq, chan_irq[SH_DMAC_MAX_CHANNELS];
954         int err, i, irq_cnt = 0, irqres = 0;
955         struct sh_dmae_device *shdev;
956         struct resource *chan, *dmars, *errirq_res, *chanirq_res;
957
958         /* get platform data */
959         if (!pdata || !pdata->channel_num)
960                 return -ENODEV;
961
962         chan = platform_get_resource(pdev, IORESOURCE_MEM, 0);
963         /* DMARS area is optional, if absent, this controller cannot do slave DMA */
964         dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1);
965         /*
966          * IRQ resources:
967          * 1. there always must be at least one IRQ IO-resource. On SH4 it is
968          *    the error IRQ, in which case it is the only IRQ in this resource:
969          *    start == end. If it is the only IRQ resource, all channels also
970          *    use the same IRQ.
971          * 2. DMA channel IRQ resources can be specified one per resource or in
972          *    ranges (start != end)
973          * 3. iff all events (channels and, optionally, error) on this
974          *    controller use the same IRQ, only one IRQ resource can be
975          *    specified, otherwise there must be one IRQ per channel, even if
976          *    some of them are equal
977          * 4. if all IRQs on this controller are equal or if some specific IRQs
978          *    specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be
979          *    requested with the IRQF_SHARED flag
980          */
981         errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
982         if (!chan || !errirq_res)
983                 return -ENODEV;
984
985         if (!request_mem_region(chan->start, resource_size(chan), pdev->name)) {
986                 dev_err(&pdev->dev, "DMAC register region already claimed\n");
987                 return -EBUSY;
988         }
989
990         if (dmars && !request_mem_region(dmars->start, resource_size(dmars), pdev->name)) {
991                 dev_err(&pdev->dev, "DMAC DMARS region already claimed\n");
992                 err = -EBUSY;
993                 goto ermrdmars;
994         }
995
996         err = -ENOMEM;
997         shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL);
998         if (!shdev) {
999                 dev_err(&pdev->dev, "Not enough memory\n");
1000                 goto ealloc;
1001         }
1002
1003         shdev->chan_reg = ioremap(chan->start, resource_size(chan));
1004         if (!shdev->chan_reg)
1005                 goto emapchan;
1006         if (dmars) {
1007                 shdev->dmars = ioremap(dmars->start, resource_size(dmars));
1008                 if (!shdev->dmars)
1009                         goto emapdmars;
1010         }
1011
1012         /* platform data */
1013         shdev->pdata = pdata;
1014
1015         pm_runtime_enable(&pdev->dev);
1016         pm_runtime_get_sync(&pdev->dev);
1017
1018         /* reset dma controller */
1019         err = sh_dmae_rst(shdev);
1020         if (err)
1021                 goto rst_err;
1022
1023         INIT_LIST_HEAD(&shdev->common.channels);
1024
1025         dma_cap_set(DMA_MEMCPY, shdev->common.cap_mask);
1026         if (dmars)
1027                 dma_cap_set(DMA_SLAVE, shdev->common.cap_mask);
1028
1029         shdev->common.device_alloc_chan_resources
1030                 = sh_dmae_alloc_chan_resources;
1031         shdev->common.device_free_chan_resources = sh_dmae_free_chan_resources;
1032         shdev->common.device_prep_dma_memcpy = sh_dmae_prep_memcpy;
1033         shdev->common.device_is_tx_complete = sh_dmae_is_complete;
1034         shdev->common.device_issue_pending = sh_dmae_memcpy_issue_pending;
1035
1036         /* Compulsory for DMA_SLAVE fields */
1037         shdev->common.device_prep_slave_sg = sh_dmae_prep_slave_sg;
1038         shdev->common.device_control = sh_dmae_control;
1039
1040         shdev->common.dev = &pdev->dev;
1041         /* Default transfer size of 32 bytes requires 32-byte alignment */
1042         shdev->common.copy_align = LOG2_DEFAULT_XFER_SIZE;
1043
1044 #if defined(CONFIG_CPU_SH4)
1045         chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1046
1047         if (!chanirq_res)
1048                 chanirq_res = errirq_res;
1049         else
1050                 irqres++;
1051
1052         if (chanirq_res == errirq_res ||
1053             (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE)
1054                 irqflags = IRQF_SHARED;
1055
1056         errirq = errirq_res->start;
1057
1058         err = request_irq(errirq, sh_dmae_err, irqflags,
1059                           "DMAC Address Error", shdev);
1060         if (err) {
1061                 dev_err(&pdev->dev,
1062                         "DMA failed requesting irq #%d, error %d\n",
1063                         errirq, err);
1064                 goto eirq_err;
1065         }
1066
1067 #else
1068         chanirq_res = errirq_res;
1069 #endif /* CONFIG_CPU_SH4 */
1070
1071         if (chanirq_res->start == chanirq_res->end &&
1072             !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
1073                 /* Special case - all multiplexed */
1074                 for (; irq_cnt < pdata->channel_num; irq_cnt++) {
1075                         chan_irq[irq_cnt] = chanirq_res->start;
1076                         chan_flag[irq_cnt] = IRQF_SHARED;
1077                 }
1078         } else {
1079                 do {
1080                         for (i = chanirq_res->start; i <= chanirq_res->end; i++) {
1081                                 if ((errirq_res->flags & IORESOURCE_BITS) ==
1082                                     IORESOURCE_IRQ_SHAREABLE)
1083                                         chan_flag[irq_cnt] = IRQF_SHARED;
1084                                 else
1085                                         chan_flag[irq_cnt] = IRQF_DISABLED;
1086                                 dev_dbg(&pdev->dev,
1087                                         "Found IRQ %d for channel %d\n",
1088                                         i, irq_cnt);
1089                                 chan_irq[irq_cnt++] = i;
1090                         }
1091                         chanirq_res = platform_get_resource(pdev,
1092                                                 IORESOURCE_IRQ, ++irqres);
1093                 } while (irq_cnt < pdata->channel_num && chanirq_res);
1094         }
1095
1096         if (irq_cnt < pdata->channel_num)
1097                 goto eirqres;
1098
1099         /* Create DMA Channel */
1100         for (i = 0; i < pdata->channel_num; i++) {
1101                 err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]);
1102                 if (err)
1103                         goto chan_probe_err;
1104         }
1105
1106         pm_runtime_put(&pdev->dev);
1107
1108         platform_set_drvdata(pdev, shdev);
1109         dma_async_device_register(&shdev->common);
1110
1111         return err;
1112
1113 chan_probe_err:
1114         sh_dmae_chan_remove(shdev);
1115 eirqres:
1116 #if defined(CONFIG_CPU_SH4)
1117         free_irq(errirq, shdev);
1118 eirq_err:
1119 #endif
1120 rst_err:
1121         pm_runtime_put(&pdev->dev);
1122         if (dmars)
1123                 iounmap(shdev->dmars);
1124 emapdmars:
1125         iounmap(shdev->chan_reg);
1126 emapchan:
1127         kfree(shdev);
1128 ealloc:
1129         if (dmars)
1130                 release_mem_region(dmars->start, resource_size(dmars));
1131 ermrdmars:
1132         release_mem_region(chan->start, resource_size(chan));
1133
1134         return err;
1135 }
1136
1137 static int __exit sh_dmae_remove(struct platform_device *pdev)
1138 {
1139         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
1140         struct resource *res;
1141         int errirq = platform_get_irq(pdev, 0);
1142
1143         dma_async_device_unregister(&shdev->common);
1144
1145         if (errirq > 0)
1146                 free_irq(errirq, shdev);
1147
1148         /* channel data remove */
1149         sh_dmae_chan_remove(shdev);
1150
1151         pm_runtime_disable(&pdev->dev);
1152
1153         if (shdev->dmars)
1154                 iounmap(shdev->dmars);
1155         iounmap(shdev->chan_reg);
1156
1157         kfree(shdev);
1158
1159         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1160         if (res)
1161                 release_mem_region(res->start, resource_size(res));
1162         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1163         if (res)
1164                 release_mem_region(res->start, resource_size(res));
1165
1166         return 0;
1167 }
1168
1169 static void sh_dmae_shutdown(struct platform_device *pdev)
1170 {
1171         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
1172         sh_dmae_ctl_stop(shdev);
1173 }
1174
1175 static struct platform_driver sh_dmae_driver = {
1176         .remove         = __exit_p(sh_dmae_remove),
1177         .shutdown       = sh_dmae_shutdown,
1178         .driver = {
1179                 .name   = "sh-dma-engine",
1180         },
1181 };
1182
1183 static int __init sh_dmae_init(void)
1184 {
1185         return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe);
1186 }
1187 module_init(sh_dmae_init);
1188
1189 static void __exit sh_dmae_exit(void)
1190 {
1191         platform_driver_unregister(&sh_dmae_driver);
1192 }
1193 module_exit(sh_dmae_exit);
1194
1195 MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>");
1196 MODULE_DESCRIPTION("Renesas SH DMA Engine driver");
1197 MODULE_LICENSE("GPL");