dmaengine: add private header file
[linux-2.6.git] / drivers / dma / shdma.c
1 /*
2  * Renesas SuperH DMA Engine support
3  *
4  * base is drivers/dma/flsdma.c
5  *
6  * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
7  * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
8  * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
9  *
10  * This is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * - DMA of SuperH does not have Hardware DMA chain mode.
16  * - MAX DMA size is 16MB.
17  *
18  */
19
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/slab.h>
23 #include <linux/interrupt.h>
24 #include <linux/dmaengine.h>
25 #include <linux/delay.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/sh_dma.h>
30 #include <linux/notifier.h>
31 #include <linux/kdebug.h>
32 #include <linux/spinlock.h>
33 #include <linux/rculist.h>
34
35 #include "dmaengine.h"
36 #include "shdma.h"
37
38 /* DMA descriptor control */
39 enum sh_dmae_desc_status {
40         DESC_IDLE,
41         DESC_PREPARED,
42         DESC_SUBMITTED,
43         DESC_COMPLETED, /* completed, have to call callback */
44         DESC_WAITING,   /* callback called, waiting for ack / re-submit */
45 };
46
47 #define NR_DESCS_PER_CHANNEL 32
48 /* Default MEMCPY transfer size = 2^2 = 4 bytes */
49 #define LOG2_DEFAULT_XFER_SIZE  2
50
51 /*
52  * Used for write-side mutual exclusion for the global device list,
53  * read-side synchronization by way of RCU, and per-controller data.
54  */
55 static DEFINE_SPINLOCK(sh_dmae_lock);
56 static LIST_HEAD(sh_dmae_devices);
57
58 /* A bitmask with bits enough for enum sh_dmae_slave_chan_id */
59 static unsigned long sh_dmae_slave_used[BITS_TO_LONGS(SH_DMA_SLAVE_NUMBER)];
60
61 static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all);
62
63 static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg)
64 {
65         __raw_writel(data, sh_dc->base + reg / sizeof(u32));
66 }
67
68 static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
69 {
70         return __raw_readl(sh_dc->base + reg / sizeof(u32));
71 }
72
73 static u16 dmaor_read(struct sh_dmae_device *shdev)
74 {
75         u32 __iomem *addr = shdev->chan_reg + DMAOR / sizeof(u32);
76
77         if (shdev->pdata->dmaor_is_32bit)
78                 return __raw_readl(addr);
79         else
80                 return __raw_readw(addr);
81 }
82
83 static void dmaor_write(struct sh_dmae_device *shdev, u16 data)
84 {
85         u32 __iomem *addr = shdev->chan_reg + DMAOR / sizeof(u32);
86
87         if (shdev->pdata->dmaor_is_32bit)
88                 __raw_writel(data, addr);
89         else
90                 __raw_writew(data, addr);
91 }
92
93 static void chcr_write(struct sh_dmae_chan *sh_dc, u32 data)
94 {
95         struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
96
97         __raw_writel(data, sh_dc->base + shdev->chcr_offset / sizeof(u32));
98 }
99
100 static u32 chcr_read(struct sh_dmae_chan *sh_dc)
101 {
102         struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
103
104         return __raw_readl(sh_dc->base + shdev->chcr_offset / sizeof(u32));
105 }
106
107 /*
108  * Reset DMA controller
109  *
110  * SH7780 has two DMAOR register
111  */
112 static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev)
113 {
114         unsigned short dmaor;
115         unsigned long flags;
116
117         spin_lock_irqsave(&sh_dmae_lock, flags);
118
119         dmaor = dmaor_read(shdev);
120         dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME));
121
122         spin_unlock_irqrestore(&sh_dmae_lock, flags);
123 }
124
125 static int sh_dmae_rst(struct sh_dmae_device *shdev)
126 {
127         unsigned short dmaor;
128         unsigned long flags;
129
130         spin_lock_irqsave(&sh_dmae_lock, flags);
131
132         dmaor = dmaor_read(shdev) & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME);
133
134         dmaor_write(shdev, dmaor | shdev->pdata->dmaor_init);
135
136         dmaor = dmaor_read(shdev);
137
138         spin_unlock_irqrestore(&sh_dmae_lock, flags);
139
140         if (dmaor & (DMAOR_AE | DMAOR_NMIF)) {
141                 dev_warn(shdev->common.dev, "Can't initialize DMAOR.\n");
142                 return -EIO;
143         }
144         return 0;
145 }
146
147 static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
148 {
149         u32 chcr = chcr_read(sh_chan);
150
151         if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE)
152                 return true; /* working */
153
154         return false; /* waiting */
155 }
156
157 static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr)
158 {
159         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
160         struct sh_dmae_pdata *pdata = shdev->pdata;
161         int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) |
162                 ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift);
163
164         if (cnt >= pdata->ts_shift_num)
165                 cnt = 0;
166
167         return pdata->ts_shift[cnt];
168 }
169
170 static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size)
171 {
172         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
173         struct sh_dmae_pdata *pdata = shdev->pdata;
174         int i;
175
176         for (i = 0; i < pdata->ts_shift_num; i++)
177                 if (pdata->ts_shift[i] == l2size)
178                         break;
179
180         if (i == pdata->ts_shift_num)
181                 i = 0;
182
183         return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) |
184                 ((i << pdata->ts_high_shift) & pdata->ts_high_mask);
185 }
186
187 static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
188 {
189         sh_dmae_writel(sh_chan, hw->sar, SAR);
190         sh_dmae_writel(sh_chan, hw->dar, DAR);
191         sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR);
192 }
193
194 static void dmae_start(struct sh_dmae_chan *sh_chan)
195 {
196         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
197         u32 chcr = chcr_read(sh_chan);
198
199         if (shdev->pdata->needs_tend_set)
200                 sh_dmae_writel(sh_chan, 0xFFFFFFFF, TEND);
201
202         chcr |= CHCR_DE | shdev->chcr_ie_bit;
203         chcr_write(sh_chan, chcr & ~CHCR_TE);
204 }
205
206 static void dmae_halt(struct sh_dmae_chan *sh_chan)
207 {
208         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
209         u32 chcr = chcr_read(sh_chan);
210
211         chcr &= ~(CHCR_DE | CHCR_TE | shdev->chcr_ie_bit);
212         chcr_write(sh_chan, chcr);
213 }
214
215 static void dmae_init(struct sh_dmae_chan *sh_chan)
216 {
217         /*
218          * Default configuration for dual address memory-memory transfer.
219          * 0x400 represents auto-request.
220          */
221         u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan,
222                                                    LOG2_DEFAULT_XFER_SIZE);
223         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
224         chcr_write(sh_chan, chcr);
225 }
226
227 static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
228 {
229         /* If DMA is active, cannot set CHCR. TODO: remove this superfluous check */
230         if (dmae_is_busy(sh_chan))
231                 return -EBUSY;
232
233         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val);
234         chcr_write(sh_chan, val);
235
236         return 0;
237 }
238
239 static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
240 {
241         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
242         struct sh_dmae_pdata *pdata = shdev->pdata;
243         const struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->id];
244         u16 __iomem *addr = shdev->dmars;
245         unsigned int shift = chan_pdata->dmars_bit;
246
247         if (dmae_is_busy(sh_chan))
248                 return -EBUSY;
249
250         if (pdata->no_dmars)
251                 return 0;
252
253         /* in the case of a missing DMARS resource use first memory window */
254         if (!addr)
255                 addr = (u16 __iomem *)shdev->chan_reg;
256         addr += chan_pdata->dmars / sizeof(u16);
257
258         __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift),
259                      addr);
260
261         return 0;
262 }
263
264 static dma_cookie_t sh_dmae_tx_submit(struct dma_async_tx_descriptor *tx)
265 {
266         struct sh_desc *desc = tx_to_sh_desc(tx), *chunk, *last = desc, *c;
267         struct sh_dmae_chan *sh_chan = to_sh_chan(tx->chan);
268         dma_async_tx_callback callback = tx->callback;
269         dma_cookie_t cookie;
270
271         spin_lock_bh(&sh_chan->desc_lock);
272
273         cookie = sh_chan->common.cookie;
274         cookie++;
275         if (cookie < 0)
276                 cookie = 1;
277
278         sh_chan->common.cookie = cookie;
279         tx->cookie = cookie;
280
281         /* Mark all chunks of this descriptor as submitted, move to the queue */
282         list_for_each_entry_safe(chunk, c, desc->node.prev, node) {
283                 /*
284                  * All chunks are on the global ld_free, so, we have to find
285                  * the end of the chain ourselves
286                  */
287                 if (chunk != desc && (chunk->mark == DESC_IDLE ||
288                                       chunk->async_tx.cookie > 0 ||
289                                       chunk->async_tx.cookie == -EBUSY ||
290                                       &chunk->node == &sh_chan->ld_free))
291                         break;
292                 chunk->mark = DESC_SUBMITTED;
293                 /* Callback goes to the last chunk */
294                 chunk->async_tx.callback = NULL;
295                 chunk->cookie = cookie;
296                 list_move_tail(&chunk->node, &sh_chan->ld_queue);
297                 last = chunk;
298         }
299
300         last->async_tx.callback = callback;
301         last->async_tx.callback_param = tx->callback_param;
302
303         dev_dbg(sh_chan->dev, "submit #%d@%p on %d: %x[%d] -> %x\n",
304                 tx->cookie, &last->async_tx, sh_chan->id,
305                 desc->hw.sar, desc->hw.tcr, desc->hw.dar);
306
307         spin_unlock_bh(&sh_chan->desc_lock);
308
309         return cookie;
310 }
311
312 /* Called with desc_lock held */
313 static struct sh_desc *sh_dmae_get_desc(struct sh_dmae_chan *sh_chan)
314 {
315         struct sh_desc *desc;
316
317         list_for_each_entry(desc, &sh_chan->ld_free, node)
318                 if (desc->mark != DESC_PREPARED) {
319                         BUG_ON(desc->mark != DESC_IDLE);
320                         list_del(&desc->node);
321                         return desc;
322                 }
323
324         return NULL;
325 }
326
327 static const struct sh_dmae_slave_config *sh_dmae_find_slave(
328         struct sh_dmae_chan *sh_chan, struct sh_dmae_slave *param)
329 {
330         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
331         struct sh_dmae_pdata *pdata = shdev->pdata;
332         int i;
333
334         if (param->slave_id >= SH_DMA_SLAVE_NUMBER)
335                 return NULL;
336
337         for (i = 0; i < pdata->slave_num; i++)
338                 if (pdata->slave[i].slave_id == param->slave_id)
339                         return pdata->slave + i;
340
341         return NULL;
342 }
343
344 static int sh_dmae_alloc_chan_resources(struct dma_chan *chan)
345 {
346         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
347         struct sh_desc *desc;
348         struct sh_dmae_slave *param = chan->private;
349         int ret;
350
351         pm_runtime_get_sync(sh_chan->dev);
352
353         /*
354          * This relies on the guarantee from dmaengine that alloc_chan_resources
355          * never runs concurrently with itself or free_chan_resources.
356          */
357         if (param) {
358                 const struct sh_dmae_slave_config *cfg;
359
360                 cfg = sh_dmae_find_slave(sh_chan, param);
361                 if (!cfg) {
362                         ret = -EINVAL;
363                         goto efindslave;
364                 }
365
366                 if (test_and_set_bit(param->slave_id, sh_dmae_slave_used)) {
367                         ret = -EBUSY;
368                         goto etestused;
369                 }
370
371                 param->config = cfg;
372
373                 dmae_set_dmars(sh_chan, cfg->mid_rid);
374                 dmae_set_chcr(sh_chan, cfg->chcr);
375         } else {
376                 dmae_init(sh_chan);
377         }
378
379         spin_lock_bh(&sh_chan->desc_lock);
380         while (sh_chan->descs_allocated < NR_DESCS_PER_CHANNEL) {
381                 spin_unlock_bh(&sh_chan->desc_lock);
382                 desc = kzalloc(sizeof(struct sh_desc), GFP_KERNEL);
383                 if (!desc) {
384                         spin_lock_bh(&sh_chan->desc_lock);
385                         break;
386                 }
387                 dma_async_tx_descriptor_init(&desc->async_tx,
388                                         &sh_chan->common);
389                 desc->async_tx.tx_submit = sh_dmae_tx_submit;
390                 desc->mark = DESC_IDLE;
391
392                 spin_lock_bh(&sh_chan->desc_lock);
393                 list_add(&desc->node, &sh_chan->ld_free);
394                 sh_chan->descs_allocated++;
395         }
396         spin_unlock_bh(&sh_chan->desc_lock);
397
398         if (!sh_chan->descs_allocated) {
399                 ret = -ENOMEM;
400                 goto edescalloc;
401         }
402
403         return sh_chan->descs_allocated;
404
405 edescalloc:
406         if (param)
407                 clear_bit(param->slave_id, sh_dmae_slave_used);
408 etestused:
409 efindslave:
410         pm_runtime_put(sh_chan->dev);
411         return ret;
412 }
413
414 /*
415  * sh_dma_free_chan_resources - Free all resources of the channel.
416  */
417 static void sh_dmae_free_chan_resources(struct dma_chan *chan)
418 {
419         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
420         struct sh_desc *desc, *_desc;
421         LIST_HEAD(list);
422         int descs = sh_chan->descs_allocated;
423
424         /* Protect against ISR */
425         spin_lock_irq(&sh_chan->desc_lock);
426         dmae_halt(sh_chan);
427         spin_unlock_irq(&sh_chan->desc_lock);
428
429         /* Now no new interrupts will occur */
430
431         /* Prepared and not submitted descriptors can still be on the queue */
432         if (!list_empty(&sh_chan->ld_queue))
433                 sh_dmae_chan_ld_cleanup(sh_chan, true);
434
435         if (chan->private) {
436                 /* The caller is holding dma_list_mutex */
437                 struct sh_dmae_slave *param = chan->private;
438                 clear_bit(param->slave_id, sh_dmae_slave_used);
439                 chan->private = NULL;
440         }
441
442         spin_lock_bh(&sh_chan->desc_lock);
443
444         list_splice_init(&sh_chan->ld_free, &list);
445         sh_chan->descs_allocated = 0;
446
447         spin_unlock_bh(&sh_chan->desc_lock);
448
449         if (descs > 0)
450                 pm_runtime_put(sh_chan->dev);
451
452         list_for_each_entry_safe(desc, _desc, &list, node)
453                 kfree(desc);
454 }
455
456 /**
457  * sh_dmae_add_desc - get, set up and return one transfer descriptor
458  * @sh_chan:    DMA channel
459  * @flags:      DMA transfer flags
460  * @dest:       destination DMA address, incremented when direction equals
461  *              DMA_FROM_DEVICE or DMA_BIDIRECTIONAL
462  * @src:        source DMA address, incremented when direction equals
463  *              DMA_TO_DEVICE or DMA_BIDIRECTIONAL
464  * @len:        DMA transfer length
465  * @first:      if NULL, set to the current descriptor and cookie set to -EBUSY
466  * @direction:  needed for slave DMA to decide which address to keep constant,
467  *              equals DMA_BIDIRECTIONAL for MEMCPY
468  * Returns 0 or an error
469  * Locks: called with desc_lock held
470  */
471 static struct sh_desc *sh_dmae_add_desc(struct sh_dmae_chan *sh_chan,
472         unsigned long flags, dma_addr_t *dest, dma_addr_t *src, size_t *len,
473         struct sh_desc **first, enum dma_data_direction direction)
474 {
475         struct sh_desc *new;
476         size_t copy_size;
477
478         if (!*len)
479                 return NULL;
480
481         /* Allocate the link descriptor from the free list */
482         new = sh_dmae_get_desc(sh_chan);
483         if (!new) {
484                 dev_err(sh_chan->dev, "No free link descriptor available\n");
485                 return NULL;
486         }
487
488         copy_size = min(*len, (size_t)SH_DMA_TCR_MAX + 1);
489
490         new->hw.sar = *src;
491         new->hw.dar = *dest;
492         new->hw.tcr = copy_size;
493
494         if (!*first) {
495                 /* First desc */
496                 new->async_tx.cookie = -EBUSY;
497                 *first = new;
498         } else {
499                 /* Other desc - invisible to the user */
500                 new->async_tx.cookie = -EINVAL;
501         }
502
503         dev_dbg(sh_chan->dev,
504                 "chaining (%u/%u)@%x -> %x with %p, cookie %d, shift %d\n",
505                 copy_size, *len, *src, *dest, &new->async_tx,
506                 new->async_tx.cookie, sh_chan->xmit_shift);
507
508         new->mark = DESC_PREPARED;
509         new->async_tx.flags = flags;
510         new->direction = direction;
511
512         *len -= copy_size;
513         if (direction == DMA_BIDIRECTIONAL || direction == DMA_TO_DEVICE)
514                 *src += copy_size;
515         if (direction == DMA_BIDIRECTIONAL || direction == DMA_FROM_DEVICE)
516                 *dest += copy_size;
517
518         return new;
519 }
520
521 /*
522  * sh_dmae_prep_sg - prepare transfer descriptors from an SG list
523  *
524  * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also
525  * converted to scatter-gather to guarantee consistent locking and a correct
526  * list manipulation. For slave DMA direction carries the usual meaning, and,
527  * logically, the SG list is RAM and the addr variable contains slave address,
528  * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_BIDIRECTIONAL
529  * and the SG list contains only one element and points at the source buffer.
530  */
531 static struct dma_async_tx_descriptor *sh_dmae_prep_sg(struct sh_dmae_chan *sh_chan,
532         struct scatterlist *sgl, unsigned int sg_len, dma_addr_t *addr,
533         enum dma_data_direction direction, unsigned long flags)
534 {
535         struct scatterlist *sg;
536         struct sh_desc *first = NULL, *new = NULL /* compiler... */;
537         LIST_HEAD(tx_list);
538         int chunks = 0;
539         int i;
540
541         if (!sg_len)
542                 return NULL;
543
544         for_each_sg(sgl, sg, sg_len, i)
545                 chunks += (sg_dma_len(sg) + SH_DMA_TCR_MAX) /
546                         (SH_DMA_TCR_MAX + 1);
547
548         /* Have to lock the whole loop to protect against concurrent release */
549         spin_lock_bh(&sh_chan->desc_lock);
550
551         /*
552          * Chaining:
553          * first descriptor is what user is dealing with in all API calls, its
554          *      cookie is at first set to -EBUSY, at tx-submit to a positive
555          *      number
556          * if more than one chunk is needed further chunks have cookie = -EINVAL
557          * the last chunk, if not equal to the first, has cookie = -ENOSPC
558          * all chunks are linked onto the tx_list head with their .node heads
559          *      only during this function, then they are immediately spliced
560          *      back onto the free list in form of a chain
561          */
562         for_each_sg(sgl, sg, sg_len, i) {
563                 dma_addr_t sg_addr = sg_dma_address(sg);
564                 size_t len = sg_dma_len(sg);
565
566                 if (!len)
567                         goto err_get_desc;
568
569                 do {
570                         dev_dbg(sh_chan->dev, "Add SG #%d@%p[%d], dma %llx\n",
571                                 i, sg, len, (unsigned long long)sg_addr);
572
573                         if (direction == DMA_FROM_DEVICE)
574                                 new = sh_dmae_add_desc(sh_chan, flags,
575                                                 &sg_addr, addr, &len, &first,
576                                                 direction);
577                         else
578                                 new = sh_dmae_add_desc(sh_chan, flags,
579                                                 addr, &sg_addr, &len, &first,
580                                                 direction);
581                         if (!new)
582                                 goto err_get_desc;
583
584                         new->chunks = chunks--;
585                         list_add_tail(&new->node, &tx_list);
586                 } while (len);
587         }
588
589         if (new != first)
590                 new->async_tx.cookie = -ENOSPC;
591
592         /* Put them back on the free list, so, they don't get lost */
593         list_splice_tail(&tx_list, &sh_chan->ld_free);
594
595         spin_unlock_bh(&sh_chan->desc_lock);
596
597         return &first->async_tx;
598
599 err_get_desc:
600         list_for_each_entry(new, &tx_list, node)
601                 new->mark = DESC_IDLE;
602         list_splice(&tx_list, &sh_chan->ld_free);
603
604         spin_unlock_bh(&sh_chan->desc_lock);
605
606         return NULL;
607 }
608
609 static struct dma_async_tx_descriptor *sh_dmae_prep_memcpy(
610         struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
611         size_t len, unsigned long flags)
612 {
613         struct sh_dmae_chan *sh_chan;
614         struct scatterlist sg;
615
616         if (!chan || !len)
617                 return NULL;
618
619         sh_chan = to_sh_chan(chan);
620
621         sg_init_table(&sg, 1);
622         sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_src)), len,
623                     offset_in_page(dma_src));
624         sg_dma_address(&sg) = dma_src;
625         sg_dma_len(&sg) = len;
626
627         return sh_dmae_prep_sg(sh_chan, &sg, 1, &dma_dest, DMA_BIDIRECTIONAL,
628                                flags);
629 }
630
631 static struct dma_async_tx_descriptor *sh_dmae_prep_slave_sg(
632         struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
633         enum dma_data_direction direction, unsigned long flags)
634 {
635         struct sh_dmae_slave *param;
636         struct sh_dmae_chan *sh_chan;
637         dma_addr_t slave_addr;
638
639         if (!chan)
640                 return NULL;
641
642         sh_chan = to_sh_chan(chan);
643         param = chan->private;
644
645         /* Someone calling slave DMA on a public channel? */
646         if (!param || !sg_len) {
647                 dev_warn(sh_chan->dev, "%s: bad parameter: %p, %d, %d\n",
648                          __func__, param, sg_len, param ? param->slave_id : -1);
649                 return NULL;
650         }
651
652         slave_addr = param->config->addr;
653
654         /*
655          * if (param != NULL), this is a successfully requested slave channel,
656          * therefore param->config != NULL too.
657          */
658         return sh_dmae_prep_sg(sh_chan, sgl, sg_len, &slave_addr,
659                                direction, flags);
660 }
661
662 static int sh_dmae_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
663                            unsigned long arg)
664 {
665         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
666
667         /* Only supports DMA_TERMINATE_ALL */
668         if (cmd != DMA_TERMINATE_ALL)
669                 return -ENXIO;
670
671         if (!chan)
672                 return -EINVAL;
673
674         spin_lock_bh(&sh_chan->desc_lock);
675         dmae_halt(sh_chan);
676
677         if (!list_empty(&sh_chan->ld_queue)) {
678                 /* Record partial transfer */
679                 struct sh_desc *desc = list_entry(sh_chan->ld_queue.next,
680                                                   struct sh_desc, node);
681                 desc->partial = (desc->hw.tcr - sh_dmae_readl(sh_chan, TCR)) <<
682                         sh_chan->xmit_shift;
683
684         }
685         spin_unlock_bh(&sh_chan->desc_lock);
686
687         sh_dmae_chan_ld_cleanup(sh_chan, true);
688
689         return 0;
690 }
691
692 static dma_async_tx_callback __ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
693 {
694         struct sh_desc *desc, *_desc;
695         /* Is the "exposed" head of a chain acked? */
696         bool head_acked = false;
697         dma_cookie_t cookie = 0;
698         dma_async_tx_callback callback = NULL;
699         void *param = NULL;
700
701         spin_lock_bh(&sh_chan->desc_lock);
702         list_for_each_entry_safe(desc, _desc, &sh_chan->ld_queue, node) {
703                 struct dma_async_tx_descriptor *tx = &desc->async_tx;
704
705                 BUG_ON(tx->cookie > 0 && tx->cookie != desc->cookie);
706                 BUG_ON(desc->mark != DESC_SUBMITTED &&
707                        desc->mark != DESC_COMPLETED &&
708                        desc->mark != DESC_WAITING);
709
710                 /*
711                  * queue is ordered, and we use this loop to (1) clean up all
712                  * completed descriptors, and to (2) update descriptor flags of
713                  * any chunks in a (partially) completed chain
714                  */
715                 if (!all && desc->mark == DESC_SUBMITTED &&
716                     desc->cookie != cookie)
717                         break;
718
719                 if (tx->cookie > 0)
720                         cookie = tx->cookie;
721
722                 if (desc->mark == DESC_COMPLETED && desc->chunks == 1) {
723                         if (sh_chan->common.completed_cookie != desc->cookie - 1)
724                                 dev_dbg(sh_chan->dev,
725                                         "Completing cookie %d, expected %d\n",
726                                         desc->cookie,
727                                         sh_chan->common.completed_cookie + 1);
728                         sh_chan->common.completed_cookie = desc->cookie;
729                 }
730
731                 /* Call callback on the last chunk */
732                 if (desc->mark == DESC_COMPLETED && tx->callback) {
733                         desc->mark = DESC_WAITING;
734                         callback = tx->callback;
735                         param = tx->callback_param;
736                         dev_dbg(sh_chan->dev, "descriptor #%d@%p on %d callback\n",
737                                 tx->cookie, tx, sh_chan->id);
738                         BUG_ON(desc->chunks != 1);
739                         break;
740                 }
741
742                 if (tx->cookie > 0 || tx->cookie == -EBUSY) {
743                         if (desc->mark == DESC_COMPLETED) {
744                                 BUG_ON(tx->cookie < 0);
745                                 desc->mark = DESC_WAITING;
746                         }
747                         head_acked = async_tx_test_ack(tx);
748                 } else {
749                         switch (desc->mark) {
750                         case DESC_COMPLETED:
751                                 desc->mark = DESC_WAITING;
752                                 /* Fall through */
753                         case DESC_WAITING:
754                                 if (head_acked)
755                                         async_tx_ack(&desc->async_tx);
756                         }
757                 }
758
759                 dev_dbg(sh_chan->dev, "descriptor %p #%d completed.\n",
760                         tx, tx->cookie);
761
762                 if (((desc->mark == DESC_COMPLETED ||
763                       desc->mark == DESC_WAITING) &&
764                      async_tx_test_ack(&desc->async_tx)) || all) {
765                         /* Remove from ld_queue list */
766                         desc->mark = DESC_IDLE;
767                         list_move(&desc->node, &sh_chan->ld_free);
768                 }
769         }
770
771         if (all && !callback)
772                 /*
773                  * Terminating and the loop completed normally: forgive
774                  * uncompleted cookies
775                  */
776                 sh_chan->common.completed_cookie = sh_chan->common.cookie;
777
778         spin_unlock_bh(&sh_chan->desc_lock);
779
780         if (callback)
781                 callback(param);
782
783         return callback;
784 }
785
786 /*
787  * sh_chan_ld_cleanup - Clean up link descriptors
788  *
789  * This function cleans up the ld_queue of DMA channel.
790  */
791 static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
792 {
793         while (__ld_cleanup(sh_chan, all))
794                 ;
795 }
796
797 static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan)
798 {
799         struct sh_desc *desc;
800
801         spin_lock_bh(&sh_chan->desc_lock);
802         /* DMA work check */
803         if (dmae_is_busy(sh_chan))
804                 goto sh_chan_xfer_ld_queue_end;
805
806         /* Find the first not transferred descriptor */
807         list_for_each_entry(desc, &sh_chan->ld_queue, node)
808                 if (desc->mark == DESC_SUBMITTED) {
809                         dev_dbg(sh_chan->dev, "Queue #%d to %d: %u@%x -> %x\n",
810                                 desc->async_tx.cookie, sh_chan->id,
811                                 desc->hw.tcr, desc->hw.sar, desc->hw.dar);
812                         /* Get the ld start address from ld_queue */
813                         dmae_set_reg(sh_chan, &desc->hw);
814                         dmae_start(sh_chan);
815                         break;
816                 }
817
818 sh_chan_xfer_ld_queue_end:
819         spin_unlock_bh(&sh_chan->desc_lock);
820 }
821
822 static void sh_dmae_memcpy_issue_pending(struct dma_chan *chan)
823 {
824         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
825         sh_chan_xfer_ld_queue(sh_chan);
826 }
827
828 static enum dma_status sh_dmae_tx_status(struct dma_chan *chan,
829                                         dma_cookie_t cookie,
830                                         struct dma_tx_state *txstate)
831 {
832         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
833         dma_cookie_t last_used;
834         dma_cookie_t last_complete;
835         enum dma_status status;
836
837         sh_dmae_chan_ld_cleanup(sh_chan, false);
838
839         /* First read completed cookie to avoid a skew */
840         last_complete = chan->completed_cookie;
841         rmb();
842         last_used = chan->cookie;
843         BUG_ON(last_complete < 0);
844         dma_set_tx_state(txstate, last_complete, last_used, 0);
845
846         spin_lock_bh(&sh_chan->desc_lock);
847
848         status = dma_async_is_complete(cookie, last_complete, last_used);
849
850         /*
851          * If we don't find cookie on the queue, it has been aborted and we have
852          * to report error
853          */
854         if (status != DMA_SUCCESS) {
855                 struct sh_desc *desc;
856                 status = DMA_ERROR;
857                 list_for_each_entry(desc, &sh_chan->ld_queue, node)
858                         if (desc->cookie == cookie) {
859                                 status = DMA_IN_PROGRESS;
860                                 break;
861                         }
862         }
863
864         spin_unlock_bh(&sh_chan->desc_lock);
865
866         return status;
867 }
868
869 static irqreturn_t sh_dmae_interrupt(int irq, void *data)
870 {
871         irqreturn_t ret = IRQ_NONE;
872         struct sh_dmae_chan *sh_chan = data;
873         u32 chcr;
874
875         spin_lock(&sh_chan->desc_lock);
876
877         chcr = chcr_read(sh_chan);
878
879         if (chcr & CHCR_TE) {
880                 /* DMA stop */
881                 dmae_halt(sh_chan);
882
883                 ret = IRQ_HANDLED;
884                 tasklet_schedule(&sh_chan->tasklet);
885         }
886
887         spin_unlock(&sh_chan->desc_lock);
888
889         return ret;
890 }
891
892 /* Called from error IRQ or NMI */
893 static bool sh_dmae_reset(struct sh_dmae_device *shdev)
894 {
895         unsigned int handled = 0;
896         int i;
897
898         /* halt the dma controller */
899         sh_dmae_ctl_stop(shdev);
900
901         /* We cannot detect, which channel caused the error, have to reset all */
902         for (i = 0; i < SH_DMAC_MAX_CHANNELS; i++) {
903                 struct sh_dmae_chan *sh_chan = shdev->chan[i];
904                 struct sh_desc *desc;
905                 LIST_HEAD(dl);
906
907                 if (!sh_chan)
908                         continue;
909
910                 spin_lock(&sh_chan->desc_lock);
911
912                 /* Stop the channel */
913                 dmae_halt(sh_chan);
914
915                 list_splice_init(&sh_chan->ld_queue, &dl);
916
917                 spin_unlock(&sh_chan->desc_lock);
918
919                 /* Complete all  */
920                 list_for_each_entry(desc, &dl, node) {
921                         struct dma_async_tx_descriptor *tx = &desc->async_tx;
922                         desc->mark = DESC_IDLE;
923                         if (tx->callback)
924                                 tx->callback(tx->callback_param);
925                 }
926
927                 spin_lock(&sh_chan->desc_lock);
928                 list_splice(&dl, &sh_chan->ld_free);
929                 spin_unlock(&sh_chan->desc_lock);
930
931                 handled++;
932         }
933
934         sh_dmae_rst(shdev);
935
936         return !!handled;
937 }
938
939 static irqreturn_t sh_dmae_err(int irq, void *data)
940 {
941         struct sh_dmae_device *shdev = data;
942
943         if (!(dmaor_read(shdev) & DMAOR_AE))
944                 return IRQ_NONE;
945
946         sh_dmae_reset(data);
947         return IRQ_HANDLED;
948 }
949
950 static void dmae_do_tasklet(unsigned long data)
951 {
952         struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data;
953         struct sh_desc *desc;
954         u32 sar_buf = sh_dmae_readl(sh_chan, SAR);
955         u32 dar_buf = sh_dmae_readl(sh_chan, DAR);
956
957         spin_lock(&sh_chan->desc_lock);
958         list_for_each_entry(desc, &sh_chan->ld_queue, node) {
959                 if (desc->mark == DESC_SUBMITTED &&
960                     ((desc->direction == DMA_FROM_DEVICE &&
961                       (desc->hw.dar + desc->hw.tcr) == dar_buf) ||
962                      (desc->hw.sar + desc->hw.tcr) == sar_buf)) {
963                         dev_dbg(sh_chan->dev, "done #%d@%p dst %u\n",
964                                 desc->async_tx.cookie, &desc->async_tx,
965                                 desc->hw.dar);
966                         desc->mark = DESC_COMPLETED;
967                         break;
968                 }
969         }
970         spin_unlock(&sh_chan->desc_lock);
971
972         /* Next desc */
973         sh_chan_xfer_ld_queue(sh_chan);
974         sh_dmae_chan_ld_cleanup(sh_chan, false);
975 }
976
977 static bool sh_dmae_nmi_notify(struct sh_dmae_device *shdev)
978 {
979         /* Fast path out if NMIF is not asserted for this controller */
980         if ((dmaor_read(shdev) & DMAOR_NMIF) == 0)
981                 return false;
982
983         return sh_dmae_reset(shdev);
984 }
985
986 static int sh_dmae_nmi_handler(struct notifier_block *self,
987                                unsigned long cmd, void *data)
988 {
989         struct sh_dmae_device *shdev;
990         int ret = NOTIFY_DONE;
991         bool triggered;
992
993         /*
994          * Only concern ourselves with NMI events.
995          *
996          * Normally we would check the die chain value, but as this needs
997          * to be architecture independent, check for NMI context instead.
998          */
999         if (!in_nmi())
1000                 return NOTIFY_DONE;
1001
1002         rcu_read_lock();
1003         list_for_each_entry_rcu(shdev, &sh_dmae_devices, node) {
1004                 /*
1005                  * Only stop if one of the controllers has NMIF asserted,
1006                  * we do not want to interfere with regular address error
1007                  * handling or NMI events that don't concern the DMACs.
1008                  */
1009                 triggered = sh_dmae_nmi_notify(shdev);
1010                 if (triggered == true)
1011                         ret = NOTIFY_OK;
1012         }
1013         rcu_read_unlock();
1014
1015         return ret;
1016 }
1017
1018 static struct notifier_block sh_dmae_nmi_notifier __read_mostly = {
1019         .notifier_call  = sh_dmae_nmi_handler,
1020
1021         /* Run before NMI debug handler and KGDB */
1022         .priority       = 1,
1023 };
1024
1025 static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id,
1026                                         int irq, unsigned long flags)
1027 {
1028         int err;
1029         const struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id];
1030         struct platform_device *pdev = to_platform_device(shdev->common.dev);
1031         struct sh_dmae_chan *new_sh_chan;
1032
1033         /* alloc channel */
1034         new_sh_chan = kzalloc(sizeof(struct sh_dmae_chan), GFP_KERNEL);
1035         if (!new_sh_chan) {
1036                 dev_err(shdev->common.dev,
1037                         "No free memory for allocating dma channels!\n");
1038                 return -ENOMEM;
1039         }
1040
1041         /* copy struct dma_device */
1042         new_sh_chan->common.device = &shdev->common;
1043
1044         new_sh_chan->dev = shdev->common.dev;
1045         new_sh_chan->id = id;
1046         new_sh_chan->irq = irq;
1047         new_sh_chan->base = shdev->chan_reg + chan_pdata->offset / sizeof(u32);
1048
1049         /* Init DMA tasklet */
1050         tasklet_init(&new_sh_chan->tasklet, dmae_do_tasklet,
1051                         (unsigned long)new_sh_chan);
1052
1053         spin_lock_init(&new_sh_chan->desc_lock);
1054
1055         /* Init descripter manage list */
1056         INIT_LIST_HEAD(&new_sh_chan->ld_queue);
1057         INIT_LIST_HEAD(&new_sh_chan->ld_free);
1058
1059         /* Add the channel to DMA device channel list */
1060         list_add_tail(&new_sh_chan->common.device_node,
1061                         &shdev->common.channels);
1062         shdev->common.chancnt++;
1063
1064         if (pdev->id >= 0)
1065                 snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
1066                          "sh-dmae%d.%d", pdev->id, new_sh_chan->id);
1067         else
1068                 snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
1069                          "sh-dma%d", new_sh_chan->id);
1070
1071         /* set up channel irq */
1072         err = request_irq(irq, &sh_dmae_interrupt, flags,
1073                           new_sh_chan->dev_id, new_sh_chan);
1074         if (err) {
1075                 dev_err(shdev->common.dev, "DMA channel %d request_irq error "
1076                         "with return %d\n", id, err);
1077                 goto err_no_irq;
1078         }
1079
1080         shdev->chan[id] = new_sh_chan;
1081         return 0;
1082
1083 err_no_irq:
1084         /* remove from dmaengine device node */
1085         list_del(&new_sh_chan->common.device_node);
1086         kfree(new_sh_chan);
1087         return err;
1088 }
1089
1090 static void sh_dmae_chan_remove(struct sh_dmae_device *shdev)
1091 {
1092         int i;
1093
1094         for (i = shdev->common.chancnt - 1 ; i >= 0 ; i--) {
1095                 if (shdev->chan[i]) {
1096                         struct sh_dmae_chan *sh_chan = shdev->chan[i];
1097
1098                         free_irq(sh_chan->irq, sh_chan);
1099
1100                         list_del(&sh_chan->common.device_node);
1101                         kfree(sh_chan);
1102                         shdev->chan[i] = NULL;
1103                 }
1104         }
1105         shdev->common.chancnt = 0;
1106 }
1107
1108 static int __init sh_dmae_probe(struct platform_device *pdev)
1109 {
1110         struct sh_dmae_pdata *pdata = pdev->dev.platform_data;
1111         unsigned long irqflags = IRQF_DISABLED,
1112                 chan_flag[SH_DMAC_MAX_CHANNELS] = {};
1113         int errirq, chan_irq[SH_DMAC_MAX_CHANNELS];
1114         int err, i, irq_cnt = 0, irqres = 0, irq_cap = 0;
1115         struct sh_dmae_device *shdev;
1116         struct resource *chan, *dmars, *errirq_res, *chanirq_res;
1117
1118         /* get platform data */
1119         if (!pdata || !pdata->channel_num)
1120                 return -ENODEV;
1121
1122         chan = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1123         /* DMARS area is optional */
1124         dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1125         /*
1126          * IRQ resources:
1127          * 1. there always must be at least one IRQ IO-resource. On SH4 it is
1128          *    the error IRQ, in which case it is the only IRQ in this resource:
1129          *    start == end. If it is the only IRQ resource, all channels also
1130          *    use the same IRQ.
1131          * 2. DMA channel IRQ resources can be specified one per resource or in
1132          *    ranges (start != end)
1133          * 3. iff all events (channels and, optionally, error) on this
1134          *    controller use the same IRQ, only one IRQ resource can be
1135          *    specified, otherwise there must be one IRQ per channel, even if
1136          *    some of them are equal
1137          * 4. if all IRQs on this controller are equal or if some specific IRQs
1138          *    specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be
1139          *    requested with the IRQF_SHARED flag
1140          */
1141         errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1142         if (!chan || !errirq_res)
1143                 return -ENODEV;
1144
1145         if (!request_mem_region(chan->start, resource_size(chan), pdev->name)) {
1146                 dev_err(&pdev->dev, "DMAC register region already claimed\n");
1147                 return -EBUSY;
1148         }
1149
1150         if (dmars && !request_mem_region(dmars->start, resource_size(dmars), pdev->name)) {
1151                 dev_err(&pdev->dev, "DMAC DMARS region already claimed\n");
1152                 err = -EBUSY;
1153                 goto ermrdmars;
1154         }
1155
1156         err = -ENOMEM;
1157         shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL);
1158         if (!shdev) {
1159                 dev_err(&pdev->dev, "Not enough memory\n");
1160                 goto ealloc;
1161         }
1162
1163         shdev->chan_reg = ioremap(chan->start, resource_size(chan));
1164         if (!shdev->chan_reg)
1165                 goto emapchan;
1166         if (dmars) {
1167                 shdev->dmars = ioremap(dmars->start, resource_size(dmars));
1168                 if (!shdev->dmars)
1169                         goto emapdmars;
1170         }
1171
1172         /* platform data */
1173         shdev->pdata = pdata;
1174
1175         if (pdata->chcr_offset)
1176                 shdev->chcr_offset = pdata->chcr_offset;
1177         else
1178                 shdev->chcr_offset = CHCR;
1179
1180         if (pdata->chcr_ie_bit)
1181                 shdev->chcr_ie_bit = pdata->chcr_ie_bit;
1182         else
1183                 shdev->chcr_ie_bit = CHCR_IE;
1184
1185         platform_set_drvdata(pdev, shdev);
1186
1187         pm_runtime_enable(&pdev->dev);
1188         pm_runtime_get_sync(&pdev->dev);
1189
1190         spin_lock_irq(&sh_dmae_lock);
1191         list_add_tail_rcu(&shdev->node, &sh_dmae_devices);
1192         spin_unlock_irq(&sh_dmae_lock);
1193
1194         /* reset dma controller - only needed as a test */
1195         err = sh_dmae_rst(shdev);
1196         if (err)
1197                 goto rst_err;
1198
1199         INIT_LIST_HEAD(&shdev->common.channels);
1200
1201         dma_cap_set(DMA_MEMCPY, shdev->common.cap_mask);
1202         if (pdata->slave && pdata->slave_num)
1203                 dma_cap_set(DMA_SLAVE, shdev->common.cap_mask);
1204
1205         shdev->common.device_alloc_chan_resources
1206                 = sh_dmae_alloc_chan_resources;
1207         shdev->common.device_free_chan_resources = sh_dmae_free_chan_resources;
1208         shdev->common.device_prep_dma_memcpy = sh_dmae_prep_memcpy;
1209         shdev->common.device_tx_status = sh_dmae_tx_status;
1210         shdev->common.device_issue_pending = sh_dmae_memcpy_issue_pending;
1211
1212         /* Compulsory for DMA_SLAVE fields */
1213         shdev->common.device_prep_slave_sg = sh_dmae_prep_slave_sg;
1214         shdev->common.device_control = sh_dmae_control;
1215
1216         shdev->common.dev = &pdev->dev;
1217         /* Default transfer size of 32 bytes requires 32-byte alignment */
1218         shdev->common.copy_align = LOG2_DEFAULT_XFER_SIZE;
1219
1220 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
1221         chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1222
1223         if (!chanirq_res)
1224                 chanirq_res = errirq_res;
1225         else
1226                 irqres++;
1227
1228         if (chanirq_res == errirq_res ||
1229             (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE)
1230                 irqflags = IRQF_SHARED;
1231
1232         errirq = errirq_res->start;
1233
1234         err = request_irq(errirq, sh_dmae_err, irqflags,
1235                           "DMAC Address Error", shdev);
1236         if (err) {
1237                 dev_err(&pdev->dev,
1238                         "DMA failed requesting irq #%d, error %d\n",
1239                         errirq, err);
1240                 goto eirq_err;
1241         }
1242
1243 #else
1244         chanirq_res = errirq_res;
1245 #endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */
1246
1247         if (chanirq_res->start == chanirq_res->end &&
1248             !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
1249                 /* Special case - all multiplexed */
1250                 for (; irq_cnt < pdata->channel_num; irq_cnt++) {
1251                         if (irq_cnt < SH_DMAC_MAX_CHANNELS) {
1252                                 chan_irq[irq_cnt] = chanirq_res->start;
1253                                 chan_flag[irq_cnt] = IRQF_SHARED;
1254                         } else {
1255                                 irq_cap = 1;
1256                                 break;
1257                         }
1258                 }
1259         } else {
1260                 do {
1261                         for (i = chanirq_res->start; i <= chanirq_res->end; i++) {
1262                                 if (irq_cnt >= SH_DMAC_MAX_CHANNELS) {
1263                                         irq_cap = 1;
1264                                         break;
1265                                 }
1266
1267                                 if ((errirq_res->flags & IORESOURCE_BITS) ==
1268                                     IORESOURCE_IRQ_SHAREABLE)
1269                                         chan_flag[irq_cnt] = IRQF_SHARED;
1270                                 else
1271                                         chan_flag[irq_cnt] = IRQF_DISABLED;
1272                                 dev_dbg(&pdev->dev,
1273                                         "Found IRQ %d for channel %d\n",
1274                                         i, irq_cnt);
1275                                 chan_irq[irq_cnt++] = i;
1276                         }
1277
1278                         if (irq_cnt >= SH_DMAC_MAX_CHANNELS)
1279                                 break;
1280
1281                         chanirq_res = platform_get_resource(pdev,
1282                                                 IORESOURCE_IRQ, ++irqres);
1283                 } while (irq_cnt < pdata->channel_num && chanirq_res);
1284         }
1285
1286         /* Create DMA Channel */
1287         for (i = 0; i < irq_cnt; i++) {
1288                 err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]);
1289                 if (err)
1290                         goto chan_probe_err;
1291         }
1292
1293         if (irq_cap)
1294                 dev_notice(&pdev->dev, "Attempting to register %d DMA "
1295                            "channels when a maximum of %d are supported.\n",
1296                            pdata->channel_num, SH_DMAC_MAX_CHANNELS);
1297
1298         pm_runtime_put(&pdev->dev);
1299
1300         dma_async_device_register(&shdev->common);
1301
1302         return err;
1303
1304 chan_probe_err:
1305         sh_dmae_chan_remove(shdev);
1306
1307 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
1308         free_irq(errirq, shdev);
1309 eirq_err:
1310 #endif
1311 rst_err:
1312         spin_lock_irq(&sh_dmae_lock);
1313         list_del_rcu(&shdev->node);
1314         spin_unlock_irq(&sh_dmae_lock);
1315
1316         pm_runtime_put(&pdev->dev);
1317         pm_runtime_disable(&pdev->dev);
1318
1319         if (dmars)
1320                 iounmap(shdev->dmars);
1321
1322         platform_set_drvdata(pdev, NULL);
1323 emapdmars:
1324         iounmap(shdev->chan_reg);
1325         synchronize_rcu();
1326 emapchan:
1327         kfree(shdev);
1328 ealloc:
1329         if (dmars)
1330                 release_mem_region(dmars->start, resource_size(dmars));
1331 ermrdmars:
1332         release_mem_region(chan->start, resource_size(chan));
1333
1334         return err;
1335 }
1336
1337 static int __exit sh_dmae_remove(struct platform_device *pdev)
1338 {
1339         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
1340         struct resource *res;
1341         int errirq = platform_get_irq(pdev, 0);
1342
1343         dma_async_device_unregister(&shdev->common);
1344
1345         if (errirq > 0)
1346                 free_irq(errirq, shdev);
1347
1348         spin_lock_irq(&sh_dmae_lock);
1349         list_del_rcu(&shdev->node);
1350         spin_unlock_irq(&sh_dmae_lock);
1351
1352         /* channel data remove */
1353         sh_dmae_chan_remove(shdev);
1354
1355         pm_runtime_disable(&pdev->dev);
1356
1357         if (shdev->dmars)
1358                 iounmap(shdev->dmars);
1359         iounmap(shdev->chan_reg);
1360
1361         platform_set_drvdata(pdev, NULL);
1362
1363         synchronize_rcu();
1364         kfree(shdev);
1365
1366         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1367         if (res)
1368                 release_mem_region(res->start, resource_size(res));
1369         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1370         if (res)
1371                 release_mem_region(res->start, resource_size(res));
1372
1373         return 0;
1374 }
1375
1376 static void sh_dmae_shutdown(struct platform_device *pdev)
1377 {
1378         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
1379         sh_dmae_ctl_stop(shdev);
1380 }
1381
1382 static int sh_dmae_runtime_suspend(struct device *dev)
1383 {
1384         return 0;
1385 }
1386
1387 static int sh_dmae_runtime_resume(struct device *dev)
1388 {
1389         struct sh_dmae_device *shdev = dev_get_drvdata(dev);
1390
1391         return sh_dmae_rst(shdev);
1392 }
1393
1394 #ifdef CONFIG_PM
1395 static int sh_dmae_suspend(struct device *dev)
1396 {
1397         struct sh_dmae_device *shdev = dev_get_drvdata(dev);
1398         int i;
1399
1400         for (i = 0; i < shdev->pdata->channel_num; i++) {
1401                 struct sh_dmae_chan *sh_chan = shdev->chan[i];
1402                 if (sh_chan->descs_allocated)
1403                         sh_chan->pm_error = pm_runtime_put_sync(dev);
1404         }
1405
1406         return 0;
1407 }
1408
1409 static int sh_dmae_resume(struct device *dev)
1410 {
1411         struct sh_dmae_device *shdev = dev_get_drvdata(dev);
1412         int i;
1413
1414         for (i = 0; i < shdev->pdata->channel_num; i++) {
1415                 struct sh_dmae_chan *sh_chan = shdev->chan[i];
1416                 struct sh_dmae_slave *param = sh_chan->common.private;
1417
1418                 if (!sh_chan->descs_allocated)
1419                         continue;
1420
1421                 if (!sh_chan->pm_error)
1422                         pm_runtime_get_sync(dev);
1423
1424                 if (param) {
1425                         const struct sh_dmae_slave_config *cfg = param->config;
1426                         dmae_set_dmars(sh_chan, cfg->mid_rid);
1427                         dmae_set_chcr(sh_chan, cfg->chcr);
1428                 } else {
1429                         dmae_init(sh_chan);
1430                 }
1431         }
1432
1433         return 0;
1434 }
1435 #else
1436 #define sh_dmae_suspend NULL
1437 #define sh_dmae_resume NULL
1438 #endif
1439
1440 const struct dev_pm_ops sh_dmae_pm = {
1441         .suspend                = sh_dmae_suspend,
1442         .resume                 = sh_dmae_resume,
1443         .runtime_suspend        = sh_dmae_runtime_suspend,
1444         .runtime_resume         = sh_dmae_runtime_resume,
1445 };
1446
1447 static struct platform_driver sh_dmae_driver = {
1448         .remove         = __exit_p(sh_dmae_remove),
1449         .shutdown       = sh_dmae_shutdown,
1450         .driver = {
1451                 .owner  = THIS_MODULE,
1452                 .name   = "sh-dma-engine",
1453                 .pm     = &sh_dmae_pm,
1454         },
1455 };
1456
1457 static int __init sh_dmae_init(void)
1458 {
1459         /* Wire up NMI handling */
1460         int err = register_die_notifier(&sh_dmae_nmi_notifier);
1461         if (err)
1462                 return err;
1463
1464         return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe);
1465 }
1466 module_init(sh_dmae_init);
1467
1468 static void __exit sh_dmae_exit(void)
1469 {
1470         platform_driver_unregister(&sh_dmae_driver);
1471
1472         unregister_die_notifier(&sh_dmae_nmi_notifier);
1473 }
1474 module_exit(sh_dmae_exit);
1475
1476 MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>");
1477 MODULE_DESCRIPTION("Renesas SH DMA Engine driver");
1478 MODULE_LICENSE("GPL");
1479 MODULE_ALIAS("platform:sh-dma-engine");