dmaengine: shdma: Enable on SH-Mobile ARM
[linux-2.6.git] / drivers / dma / shdma.c
1 /*
2  * Renesas SuperH DMA Engine support
3  *
4  * base is drivers/dma/flsdma.c
5  *
6  * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
7  * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
8  * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
9  *
10  * This is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * - DMA of SuperH does not have Hardware DMA chain mode.
16  * - MAX DMA size is 16MB.
17  *
18  */
19
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/interrupt.h>
23 #include <linux/dmaengine.h>
24 #include <linux/delay.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/sh_dma.h>
29
30 #include "shdma.h"
31
32 /* DMA descriptor control */
33 enum sh_dmae_desc_status {
34         DESC_IDLE,
35         DESC_PREPARED,
36         DESC_SUBMITTED,
37         DESC_COMPLETED, /* completed, have to call callback */
38         DESC_WAITING,   /* callback called, waiting for ack / re-submit */
39 };
40
41 #define NR_DESCS_PER_CHANNEL 32
42 /* Default MEMCPY transfer size = 2^2 = 4 bytes */
43 #define LOG2_DEFAULT_XFER_SIZE  2
44
45 /* A bitmask with bits enough for enum sh_dmae_slave_chan_id */
46 static unsigned long sh_dmae_slave_used[BITS_TO_LONGS(SH_DMA_SLAVE_NUMBER)];
47
48 static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all);
49
50 static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg)
51 {
52         __raw_writel(data, sh_dc->base + reg / sizeof(u32));
53 }
54
55 static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
56 {
57         return __raw_readl(sh_dc->base + reg / sizeof(u32));
58 }
59
60 static u16 dmaor_read(struct sh_dmae_device *shdev)
61 {
62         return __raw_readw(shdev->chan_reg + DMAOR / sizeof(u32));
63 }
64
65 static void dmaor_write(struct sh_dmae_device *shdev, u16 data)
66 {
67         __raw_writew(data, shdev->chan_reg + DMAOR / sizeof(u32));
68 }
69
70 /*
71  * Reset DMA controller
72  *
73  * SH7780 has two DMAOR register
74  */
75 static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev)
76 {
77         unsigned short dmaor = dmaor_read(shdev);
78
79         dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME));
80 }
81
82 static int sh_dmae_rst(struct sh_dmae_device *shdev)
83 {
84         unsigned short dmaor;
85
86         sh_dmae_ctl_stop(shdev);
87         dmaor = dmaor_read(shdev) | shdev->pdata->dmaor_init;
88
89         dmaor_write(shdev, dmaor);
90         if (dmaor_read(shdev) & (DMAOR_AE | DMAOR_NMIF)) {
91                 pr_warning("dma-sh: Can't initialize DMAOR.\n");
92                 return -EINVAL;
93         }
94         return 0;
95 }
96
97 static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
98 {
99         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
100
101         if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE)
102                 return true; /* working */
103
104         return false; /* waiting */
105 }
106
107 static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr)
108 {
109         struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
110                                                 struct sh_dmae_device, common);
111         struct sh_dmae_pdata *pdata = shdev->pdata;
112         int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) |
113                 ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift);
114
115         if (cnt >= pdata->ts_shift_num)
116                 cnt = 0;
117
118         return pdata->ts_shift[cnt];
119 }
120
121 static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size)
122 {
123         struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
124                                                 struct sh_dmae_device, common);
125         struct sh_dmae_pdata *pdata = shdev->pdata;
126         int i;
127
128         for (i = 0; i < pdata->ts_shift_num; i++)
129                 if (pdata->ts_shift[i] == l2size)
130                         break;
131
132         if (i == pdata->ts_shift_num)
133                 i = 0;
134
135         return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) |
136                 ((i << pdata->ts_high_shift) & pdata->ts_high_mask);
137 }
138
139 static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
140 {
141         sh_dmae_writel(sh_chan, hw->sar, SAR);
142         sh_dmae_writel(sh_chan, hw->dar, DAR);
143         sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR);
144 }
145
146 static void dmae_start(struct sh_dmae_chan *sh_chan)
147 {
148         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
149
150         chcr |= CHCR_DE | CHCR_IE;
151         sh_dmae_writel(sh_chan, chcr & ~CHCR_TE, CHCR);
152 }
153
154 static void dmae_halt(struct sh_dmae_chan *sh_chan)
155 {
156         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
157
158         chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
159         sh_dmae_writel(sh_chan, chcr, CHCR);
160 }
161
162 static void dmae_init(struct sh_dmae_chan *sh_chan)
163 {
164         /*
165          * Default configuration for dual address memory-memory transfer.
166          * 0x400 represents auto-request.
167          */
168         u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan,
169                                                    LOG2_DEFAULT_XFER_SIZE);
170         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
171         sh_dmae_writel(sh_chan, chcr, CHCR);
172 }
173
174 static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
175 {
176         /* When DMA was working, can not set data to CHCR */
177         if (dmae_is_busy(sh_chan))
178                 return -EBUSY;
179
180         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val);
181         sh_dmae_writel(sh_chan, val, CHCR);
182
183         return 0;
184 }
185
186 static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
187 {
188         struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
189                                                 struct sh_dmae_device, common);
190         struct sh_dmae_pdata *pdata = shdev->pdata;
191         struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->id];
192         u16 __iomem *addr = shdev->dmars + chan_pdata->dmars / sizeof(u16);
193         int shift = chan_pdata->dmars_bit;
194
195         if (dmae_is_busy(sh_chan))
196                 return -EBUSY;
197
198         __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift),
199                      addr);
200
201         return 0;
202 }
203
204 static dma_cookie_t sh_dmae_tx_submit(struct dma_async_tx_descriptor *tx)
205 {
206         struct sh_desc *desc = tx_to_sh_desc(tx), *chunk, *last = desc, *c;
207         struct sh_dmae_chan *sh_chan = to_sh_chan(tx->chan);
208         dma_async_tx_callback callback = tx->callback;
209         dma_cookie_t cookie;
210
211         spin_lock_bh(&sh_chan->desc_lock);
212
213         cookie = sh_chan->common.cookie;
214         cookie++;
215         if (cookie < 0)
216                 cookie = 1;
217
218         sh_chan->common.cookie = cookie;
219         tx->cookie = cookie;
220
221         /* Mark all chunks of this descriptor as submitted, move to the queue */
222         list_for_each_entry_safe(chunk, c, desc->node.prev, node) {
223                 /*
224                  * All chunks are on the global ld_free, so, we have to find
225                  * the end of the chain ourselves
226                  */
227                 if (chunk != desc && (chunk->mark == DESC_IDLE ||
228                                       chunk->async_tx.cookie > 0 ||
229                                       chunk->async_tx.cookie == -EBUSY ||
230                                       &chunk->node == &sh_chan->ld_free))
231                         break;
232                 chunk->mark = DESC_SUBMITTED;
233                 /* Callback goes to the last chunk */
234                 chunk->async_tx.callback = NULL;
235                 chunk->cookie = cookie;
236                 list_move_tail(&chunk->node, &sh_chan->ld_queue);
237                 last = chunk;
238         }
239
240         last->async_tx.callback = callback;
241         last->async_tx.callback_param = tx->callback_param;
242
243         dev_dbg(sh_chan->dev, "submit #%d@%p on %d: %x[%d] -> %x\n",
244                 tx->cookie, &last->async_tx, sh_chan->id,
245                 desc->hw.sar, desc->hw.tcr, desc->hw.dar);
246
247         spin_unlock_bh(&sh_chan->desc_lock);
248
249         return cookie;
250 }
251
252 /* Called with desc_lock held */
253 static struct sh_desc *sh_dmae_get_desc(struct sh_dmae_chan *sh_chan)
254 {
255         struct sh_desc *desc;
256
257         list_for_each_entry(desc, &sh_chan->ld_free, node)
258                 if (desc->mark != DESC_PREPARED) {
259                         BUG_ON(desc->mark != DESC_IDLE);
260                         list_del(&desc->node);
261                         return desc;
262                 }
263
264         return NULL;
265 }
266
267 static struct sh_dmae_slave_config *sh_dmae_find_slave(
268         struct sh_dmae_chan *sh_chan, struct sh_dmae_slave *param)
269 {
270         struct dma_device *dma_dev = sh_chan->common.device;
271         struct sh_dmae_device *shdev = container_of(dma_dev,
272                                         struct sh_dmae_device, common);
273         struct sh_dmae_pdata *pdata = shdev->pdata;
274         int i;
275
276         if (param->slave_id >= SH_DMA_SLAVE_NUMBER)
277                 return NULL;
278
279         for (i = 0; i < pdata->slave_num; i++)
280                 if (pdata->slave[i].slave_id == param->slave_id)
281                         return pdata->slave + i;
282
283         return NULL;
284 }
285
286 static int sh_dmae_alloc_chan_resources(struct dma_chan *chan)
287 {
288         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
289         struct sh_desc *desc;
290         struct sh_dmae_slave *param = chan->private;
291
292         pm_runtime_get_sync(sh_chan->dev);
293
294         /*
295          * This relies on the guarantee from dmaengine that alloc_chan_resources
296          * never runs concurrently with itself or free_chan_resources.
297          */
298         if (param) {
299                 struct sh_dmae_slave_config *cfg;
300
301                 cfg = sh_dmae_find_slave(sh_chan, param);
302                 if (!cfg)
303                         return -EINVAL;
304
305                 if (test_and_set_bit(param->slave_id, sh_dmae_slave_used))
306                         return -EBUSY;
307
308                 param->config = cfg;
309
310                 dmae_set_dmars(sh_chan, cfg->mid_rid);
311                 dmae_set_chcr(sh_chan, cfg->chcr);
312         } else if ((sh_dmae_readl(sh_chan, CHCR) & 0xf00) != 0x400) {
313                 dmae_init(sh_chan);
314         }
315
316         spin_lock_bh(&sh_chan->desc_lock);
317         while (sh_chan->descs_allocated < NR_DESCS_PER_CHANNEL) {
318                 spin_unlock_bh(&sh_chan->desc_lock);
319                 desc = kzalloc(sizeof(struct sh_desc), GFP_KERNEL);
320                 if (!desc) {
321                         spin_lock_bh(&sh_chan->desc_lock);
322                         break;
323                 }
324                 dma_async_tx_descriptor_init(&desc->async_tx,
325                                         &sh_chan->common);
326                 desc->async_tx.tx_submit = sh_dmae_tx_submit;
327                 desc->mark = DESC_IDLE;
328
329                 spin_lock_bh(&sh_chan->desc_lock);
330                 list_add(&desc->node, &sh_chan->ld_free);
331                 sh_chan->descs_allocated++;
332         }
333         spin_unlock_bh(&sh_chan->desc_lock);
334
335         if (!sh_chan->descs_allocated)
336                 pm_runtime_put(sh_chan->dev);
337
338         return sh_chan->descs_allocated;
339 }
340
341 /*
342  * sh_dma_free_chan_resources - Free all resources of the channel.
343  */
344 static void sh_dmae_free_chan_resources(struct dma_chan *chan)
345 {
346         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
347         struct sh_desc *desc, *_desc;
348         LIST_HEAD(list);
349         int descs = sh_chan->descs_allocated;
350
351         dmae_halt(sh_chan);
352
353         /* Prepared and not submitted descriptors can still be on the queue */
354         if (!list_empty(&sh_chan->ld_queue))
355                 sh_dmae_chan_ld_cleanup(sh_chan, true);
356
357         if (chan->private) {
358                 /* The caller is holding dma_list_mutex */
359                 struct sh_dmae_slave *param = chan->private;
360                 clear_bit(param->slave_id, sh_dmae_slave_used);
361         }
362
363         spin_lock_bh(&sh_chan->desc_lock);
364
365         list_splice_init(&sh_chan->ld_free, &list);
366         sh_chan->descs_allocated = 0;
367
368         spin_unlock_bh(&sh_chan->desc_lock);
369
370         if (descs > 0)
371                 pm_runtime_put(sh_chan->dev);
372
373         list_for_each_entry_safe(desc, _desc, &list, node)
374                 kfree(desc);
375 }
376
377 /**
378  * sh_dmae_add_desc - get, set up and return one transfer descriptor
379  * @sh_chan:    DMA channel
380  * @flags:      DMA transfer flags
381  * @dest:       destination DMA address, incremented when direction equals
382  *              DMA_FROM_DEVICE or DMA_BIDIRECTIONAL
383  * @src:        source DMA address, incremented when direction equals
384  *              DMA_TO_DEVICE or DMA_BIDIRECTIONAL
385  * @len:        DMA transfer length
386  * @first:      if NULL, set to the current descriptor and cookie set to -EBUSY
387  * @direction:  needed for slave DMA to decide which address to keep constant,
388  *              equals DMA_BIDIRECTIONAL for MEMCPY
389  * Returns 0 or an error
390  * Locks: called with desc_lock held
391  */
392 static struct sh_desc *sh_dmae_add_desc(struct sh_dmae_chan *sh_chan,
393         unsigned long flags, dma_addr_t *dest, dma_addr_t *src, size_t *len,
394         struct sh_desc **first, enum dma_data_direction direction)
395 {
396         struct sh_desc *new;
397         size_t copy_size;
398
399         if (!*len)
400                 return NULL;
401
402         /* Allocate the link descriptor from the free list */
403         new = sh_dmae_get_desc(sh_chan);
404         if (!new) {
405                 dev_err(sh_chan->dev, "No free link descriptor available\n");
406                 return NULL;
407         }
408
409         copy_size = min(*len, (size_t)SH_DMA_TCR_MAX + 1);
410
411         new->hw.sar = *src;
412         new->hw.dar = *dest;
413         new->hw.tcr = copy_size;
414
415         if (!*first) {
416                 /* First desc */
417                 new->async_tx.cookie = -EBUSY;
418                 *first = new;
419         } else {
420                 /* Other desc - invisible to the user */
421                 new->async_tx.cookie = -EINVAL;
422         }
423
424         dev_dbg(sh_chan->dev,
425                 "chaining (%u/%u)@%x -> %x with %p, cookie %d, shift %d\n",
426                 copy_size, *len, *src, *dest, &new->async_tx,
427                 new->async_tx.cookie, sh_chan->xmit_shift);
428
429         new->mark = DESC_PREPARED;
430         new->async_tx.flags = flags;
431         new->direction = direction;
432
433         *len -= copy_size;
434         if (direction == DMA_BIDIRECTIONAL || direction == DMA_TO_DEVICE)
435                 *src += copy_size;
436         if (direction == DMA_BIDIRECTIONAL || direction == DMA_FROM_DEVICE)
437                 *dest += copy_size;
438
439         return new;
440 }
441
442 /*
443  * sh_dmae_prep_sg - prepare transfer descriptors from an SG list
444  *
445  * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also
446  * converted to scatter-gather to guarantee consistent locking and a correct
447  * list manipulation. For slave DMA direction carries the usual meaning, and,
448  * logically, the SG list is RAM and the addr variable contains slave address,
449  * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_BIDIRECTIONAL
450  * and the SG list contains only one element and points at the source buffer.
451  */
452 static struct dma_async_tx_descriptor *sh_dmae_prep_sg(struct sh_dmae_chan *sh_chan,
453         struct scatterlist *sgl, unsigned int sg_len, dma_addr_t *addr,
454         enum dma_data_direction direction, unsigned long flags)
455 {
456         struct scatterlist *sg;
457         struct sh_desc *first = NULL, *new = NULL /* compiler... */;
458         LIST_HEAD(tx_list);
459         int chunks = 0;
460         int i;
461
462         if (!sg_len)
463                 return NULL;
464
465         for_each_sg(sgl, sg, sg_len, i)
466                 chunks += (sg_dma_len(sg) + SH_DMA_TCR_MAX) /
467                         (SH_DMA_TCR_MAX + 1);
468
469         /* Have to lock the whole loop to protect against concurrent release */
470         spin_lock_bh(&sh_chan->desc_lock);
471
472         /*
473          * Chaining:
474          * first descriptor is what user is dealing with in all API calls, its
475          *      cookie is at first set to -EBUSY, at tx-submit to a positive
476          *      number
477          * if more than one chunk is needed further chunks have cookie = -EINVAL
478          * the last chunk, if not equal to the first, has cookie = -ENOSPC
479          * all chunks are linked onto the tx_list head with their .node heads
480          *      only during this function, then they are immediately spliced
481          *      back onto the free list in form of a chain
482          */
483         for_each_sg(sgl, sg, sg_len, i) {
484                 dma_addr_t sg_addr = sg_dma_address(sg);
485                 size_t len = sg_dma_len(sg);
486
487                 if (!len)
488                         goto err_get_desc;
489
490                 do {
491                         dev_dbg(sh_chan->dev, "Add SG #%d@%p[%d], dma %llx\n",
492                                 i, sg, len, (unsigned long long)sg_addr);
493
494                         if (direction == DMA_FROM_DEVICE)
495                                 new = sh_dmae_add_desc(sh_chan, flags,
496                                                 &sg_addr, addr, &len, &first,
497                                                 direction);
498                         else
499                                 new = sh_dmae_add_desc(sh_chan, flags,
500                                                 addr, &sg_addr, &len, &first,
501                                                 direction);
502                         if (!new)
503                                 goto err_get_desc;
504
505                         new->chunks = chunks--;
506                         list_add_tail(&new->node, &tx_list);
507                 } while (len);
508         }
509
510         if (new != first)
511                 new->async_tx.cookie = -ENOSPC;
512
513         /* Put them back on the free list, so, they don't get lost */
514         list_splice_tail(&tx_list, &sh_chan->ld_free);
515
516         spin_unlock_bh(&sh_chan->desc_lock);
517
518         return &first->async_tx;
519
520 err_get_desc:
521         list_for_each_entry(new, &tx_list, node)
522                 new->mark = DESC_IDLE;
523         list_splice(&tx_list, &sh_chan->ld_free);
524
525         spin_unlock_bh(&sh_chan->desc_lock);
526
527         return NULL;
528 }
529
530 static struct dma_async_tx_descriptor *sh_dmae_prep_memcpy(
531         struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
532         size_t len, unsigned long flags)
533 {
534         struct sh_dmae_chan *sh_chan;
535         struct scatterlist sg;
536
537         if (!chan || !len)
538                 return NULL;
539
540         chan->private = NULL;
541
542         sh_chan = to_sh_chan(chan);
543
544         sg_init_table(&sg, 1);
545         sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_src)), len,
546                     offset_in_page(dma_src));
547         sg_dma_address(&sg) = dma_src;
548         sg_dma_len(&sg) = len;
549
550         return sh_dmae_prep_sg(sh_chan, &sg, 1, &dma_dest, DMA_BIDIRECTIONAL,
551                                flags);
552 }
553
554 static struct dma_async_tx_descriptor *sh_dmae_prep_slave_sg(
555         struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
556         enum dma_data_direction direction, unsigned long flags)
557 {
558         struct sh_dmae_slave *param;
559         struct sh_dmae_chan *sh_chan;
560
561         if (!chan)
562                 return NULL;
563
564         sh_chan = to_sh_chan(chan);
565         param = chan->private;
566
567         /* Someone calling slave DMA on a public channel? */
568         if (!param || !sg_len) {
569                 dev_warn(sh_chan->dev, "%s: bad parameter: %p, %d, %d\n",
570                          __func__, param, sg_len, param ? param->slave_id : -1);
571                 return NULL;
572         }
573
574         /*
575          * if (param != NULL), this is a successfully requested slave channel,
576          * therefore param->config != NULL too.
577          */
578         return sh_dmae_prep_sg(sh_chan, sgl, sg_len, &param->config->addr,
579                                direction, flags);
580 }
581
582 static void sh_dmae_terminate_all(struct dma_chan *chan)
583 {
584         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
585
586         if (!chan)
587                 return;
588
589         dmae_halt(sh_chan);
590
591         spin_lock_bh(&sh_chan->desc_lock);
592         if (!list_empty(&sh_chan->ld_queue)) {
593                 /* Record partial transfer */
594                 struct sh_desc *desc = list_entry(sh_chan->ld_queue.next,
595                                                   struct sh_desc, node);
596                 desc->partial = (desc->hw.tcr - sh_dmae_readl(sh_chan, TCR)) <<
597                         sh_chan->xmit_shift;
598
599         }
600         spin_unlock_bh(&sh_chan->desc_lock);
601
602         sh_dmae_chan_ld_cleanup(sh_chan, true);
603 }
604
605 static dma_async_tx_callback __ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
606 {
607         struct sh_desc *desc, *_desc;
608         /* Is the "exposed" head of a chain acked? */
609         bool head_acked = false;
610         dma_cookie_t cookie = 0;
611         dma_async_tx_callback callback = NULL;
612         void *param = NULL;
613
614         spin_lock_bh(&sh_chan->desc_lock);
615         list_for_each_entry_safe(desc, _desc, &sh_chan->ld_queue, node) {
616                 struct dma_async_tx_descriptor *tx = &desc->async_tx;
617
618                 BUG_ON(tx->cookie > 0 && tx->cookie != desc->cookie);
619                 BUG_ON(desc->mark != DESC_SUBMITTED &&
620                        desc->mark != DESC_COMPLETED &&
621                        desc->mark != DESC_WAITING);
622
623                 /*
624                  * queue is ordered, and we use this loop to (1) clean up all
625                  * completed descriptors, and to (2) update descriptor flags of
626                  * any chunks in a (partially) completed chain
627                  */
628                 if (!all && desc->mark == DESC_SUBMITTED &&
629                     desc->cookie != cookie)
630                         break;
631
632                 if (tx->cookie > 0)
633                         cookie = tx->cookie;
634
635                 if (desc->mark == DESC_COMPLETED && desc->chunks == 1) {
636                         if (sh_chan->completed_cookie != desc->cookie - 1)
637                                 dev_dbg(sh_chan->dev,
638                                         "Completing cookie %d, expected %d\n",
639                                         desc->cookie,
640                                         sh_chan->completed_cookie + 1);
641                         sh_chan->completed_cookie = desc->cookie;
642                 }
643
644                 /* Call callback on the last chunk */
645                 if (desc->mark == DESC_COMPLETED && tx->callback) {
646                         desc->mark = DESC_WAITING;
647                         callback = tx->callback;
648                         param = tx->callback_param;
649                         dev_dbg(sh_chan->dev, "descriptor #%d@%p on %d callback\n",
650                                 tx->cookie, tx, sh_chan->id);
651                         BUG_ON(desc->chunks != 1);
652                         break;
653                 }
654
655                 if (tx->cookie > 0 || tx->cookie == -EBUSY) {
656                         if (desc->mark == DESC_COMPLETED) {
657                                 BUG_ON(tx->cookie < 0);
658                                 desc->mark = DESC_WAITING;
659                         }
660                         head_acked = async_tx_test_ack(tx);
661                 } else {
662                         switch (desc->mark) {
663                         case DESC_COMPLETED:
664                                 desc->mark = DESC_WAITING;
665                                 /* Fall through */
666                         case DESC_WAITING:
667                                 if (head_acked)
668                                         async_tx_ack(&desc->async_tx);
669                         }
670                 }
671
672                 dev_dbg(sh_chan->dev, "descriptor %p #%d completed.\n",
673                         tx, tx->cookie);
674
675                 if (((desc->mark == DESC_COMPLETED ||
676                       desc->mark == DESC_WAITING) &&
677                      async_tx_test_ack(&desc->async_tx)) || all) {
678                         /* Remove from ld_queue list */
679                         desc->mark = DESC_IDLE;
680                         list_move(&desc->node, &sh_chan->ld_free);
681                 }
682         }
683         spin_unlock_bh(&sh_chan->desc_lock);
684
685         if (callback)
686                 callback(param);
687
688         return callback;
689 }
690
691 /*
692  * sh_chan_ld_cleanup - Clean up link descriptors
693  *
694  * This function cleans up the ld_queue of DMA channel.
695  */
696 static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
697 {
698         while (__ld_cleanup(sh_chan, all))
699                 ;
700 }
701
702 static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan)
703 {
704         struct sh_desc *desc;
705
706         spin_lock_bh(&sh_chan->desc_lock);
707         /* DMA work check */
708         if (dmae_is_busy(sh_chan)) {
709                 spin_unlock_bh(&sh_chan->desc_lock);
710                 return;
711         }
712
713         /* Find the first not transferred desciptor */
714         list_for_each_entry(desc, &sh_chan->ld_queue, node)
715                 if (desc->mark == DESC_SUBMITTED) {
716                         dev_dbg(sh_chan->dev, "Queue #%d to %d: %u@%x -> %x\n",
717                                 desc->async_tx.cookie, sh_chan->id,
718                                 desc->hw.tcr, desc->hw.sar, desc->hw.dar);
719                         /* Get the ld start address from ld_queue */
720                         dmae_set_reg(sh_chan, &desc->hw);
721                         dmae_start(sh_chan);
722                         break;
723                 }
724
725         spin_unlock_bh(&sh_chan->desc_lock);
726 }
727
728 static void sh_dmae_memcpy_issue_pending(struct dma_chan *chan)
729 {
730         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
731         sh_chan_xfer_ld_queue(sh_chan);
732 }
733
734 static enum dma_status sh_dmae_is_complete(struct dma_chan *chan,
735                                         dma_cookie_t cookie,
736                                         dma_cookie_t *done,
737                                         dma_cookie_t *used)
738 {
739         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
740         dma_cookie_t last_used;
741         dma_cookie_t last_complete;
742         enum dma_status status;
743
744         sh_dmae_chan_ld_cleanup(sh_chan, false);
745
746         last_used = chan->cookie;
747         last_complete = sh_chan->completed_cookie;
748         BUG_ON(last_complete < 0);
749
750         if (done)
751                 *done = last_complete;
752
753         if (used)
754                 *used = last_used;
755
756         spin_lock_bh(&sh_chan->desc_lock);
757
758         status = dma_async_is_complete(cookie, last_complete, last_used);
759
760         /*
761          * If we don't find cookie on the queue, it has been aborted and we have
762          * to report error
763          */
764         if (status != DMA_SUCCESS) {
765                 struct sh_desc *desc;
766                 status = DMA_ERROR;
767                 list_for_each_entry(desc, &sh_chan->ld_queue, node)
768                         if (desc->cookie == cookie) {
769                                 status = DMA_IN_PROGRESS;
770                                 break;
771                         }
772         }
773
774         spin_unlock_bh(&sh_chan->desc_lock);
775
776         return status;
777 }
778
779 static irqreturn_t sh_dmae_interrupt(int irq, void *data)
780 {
781         irqreturn_t ret = IRQ_NONE;
782         struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data;
783         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
784
785         if (chcr & CHCR_TE) {
786                 /* DMA stop */
787                 dmae_halt(sh_chan);
788
789                 ret = IRQ_HANDLED;
790                 tasklet_schedule(&sh_chan->tasklet);
791         }
792
793         return ret;
794 }
795
796 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
797 static irqreturn_t sh_dmae_err(int irq, void *data)
798 {
799         struct sh_dmae_device *shdev = (struct sh_dmae_device *)data;
800         int i;
801
802         /* halt the dma controller */
803         sh_dmae_ctl_stop(shdev);
804
805         /* We cannot detect, which channel caused the error, have to reset all */
806         for (i = 0; i < SH_DMAC_MAX_CHANNELS; i++) {
807                 struct sh_dmae_chan *sh_chan = shdev->chan[i];
808                 if (sh_chan) {
809                         struct sh_desc *desc;
810                         /* Stop the channel */
811                         dmae_halt(sh_chan);
812                         /* Complete all  */
813                         list_for_each_entry(desc, &sh_chan->ld_queue, node) {
814                                 struct dma_async_tx_descriptor *tx = &desc->async_tx;
815                                 desc->mark = DESC_IDLE;
816                                 if (tx->callback)
817                                         tx->callback(tx->callback_param);
818                         }
819                         list_splice_init(&sh_chan->ld_queue, &sh_chan->ld_free);
820                 }
821         }
822         sh_dmae_rst(shdev);
823
824         return IRQ_HANDLED;
825 }
826 #endif
827
828 static void dmae_do_tasklet(unsigned long data)
829 {
830         struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data;
831         struct sh_desc *desc;
832         u32 sar_buf = sh_dmae_readl(sh_chan, SAR);
833         u32 dar_buf = sh_dmae_readl(sh_chan, DAR);
834
835         spin_lock(&sh_chan->desc_lock);
836         list_for_each_entry(desc, &sh_chan->ld_queue, node) {
837                 if (desc->mark == DESC_SUBMITTED &&
838                     ((desc->direction == DMA_FROM_DEVICE &&
839                       (desc->hw.dar + desc->hw.tcr) == dar_buf) ||
840                      (desc->hw.sar + desc->hw.tcr) == sar_buf)) {
841                         dev_dbg(sh_chan->dev, "done #%d@%p dst %u\n",
842                                 desc->async_tx.cookie, &desc->async_tx,
843                                 desc->hw.dar);
844                         desc->mark = DESC_COMPLETED;
845                         break;
846                 }
847         }
848         spin_unlock(&sh_chan->desc_lock);
849
850         /* Next desc */
851         sh_chan_xfer_ld_queue(sh_chan);
852         sh_dmae_chan_ld_cleanup(sh_chan, false);
853 }
854
855 static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id,
856                                         int irq, unsigned long flags)
857 {
858         int err;
859         struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id];
860         struct platform_device *pdev = to_platform_device(shdev->common.dev);
861         struct sh_dmae_chan *new_sh_chan;
862
863         /* alloc channel */
864         new_sh_chan = kzalloc(sizeof(struct sh_dmae_chan), GFP_KERNEL);
865         if (!new_sh_chan) {
866                 dev_err(shdev->common.dev,
867                         "No free memory for allocating dma channels!\n");
868                 return -ENOMEM;
869         }
870
871         /* copy struct dma_device */
872         new_sh_chan->common.device = &shdev->common;
873
874         new_sh_chan->dev = shdev->common.dev;
875         new_sh_chan->id = id;
876         new_sh_chan->irq = irq;
877         new_sh_chan->base = shdev->chan_reg + chan_pdata->offset / sizeof(u32);
878
879         /* Init DMA tasklet */
880         tasklet_init(&new_sh_chan->tasklet, dmae_do_tasklet,
881                         (unsigned long)new_sh_chan);
882
883         /* Init the channel */
884         dmae_init(new_sh_chan);
885
886         spin_lock_init(&new_sh_chan->desc_lock);
887
888         /* Init descripter manage list */
889         INIT_LIST_HEAD(&new_sh_chan->ld_queue);
890         INIT_LIST_HEAD(&new_sh_chan->ld_free);
891
892         /* Add the channel to DMA device channel list */
893         list_add_tail(&new_sh_chan->common.device_node,
894                         &shdev->common.channels);
895         shdev->common.chancnt++;
896
897         if (pdev->id >= 0)
898                 snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
899                          "sh-dmae%d.%d", pdev->id, new_sh_chan->id);
900         else
901                 snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
902                          "sh-dma%d", new_sh_chan->id);
903
904         /* set up channel irq */
905         err = request_irq(irq, &sh_dmae_interrupt, flags,
906                           new_sh_chan->dev_id, new_sh_chan);
907         if (err) {
908                 dev_err(shdev->common.dev, "DMA channel %d request_irq error "
909                         "with return %d\n", id, err);
910                 goto err_no_irq;
911         }
912
913         shdev->chan[id] = new_sh_chan;
914         return 0;
915
916 err_no_irq:
917         /* remove from dmaengine device node */
918         list_del(&new_sh_chan->common.device_node);
919         kfree(new_sh_chan);
920         return err;
921 }
922
923 static void sh_dmae_chan_remove(struct sh_dmae_device *shdev)
924 {
925         int i;
926
927         for (i = shdev->common.chancnt - 1 ; i >= 0 ; i--) {
928                 if (shdev->chan[i]) {
929                         struct sh_dmae_chan *sh_chan = shdev->chan[i];
930
931                         free_irq(sh_chan->irq, sh_chan);
932
933                         list_del(&sh_chan->common.device_node);
934                         kfree(sh_chan);
935                         shdev->chan[i] = NULL;
936                 }
937         }
938         shdev->common.chancnt = 0;
939 }
940
941 static int __init sh_dmae_probe(struct platform_device *pdev)
942 {
943         struct sh_dmae_pdata *pdata = pdev->dev.platform_data;
944         unsigned long irqflags = IRQF_DISABLED,
945                 chan_flag[SH_DMAC_MAX_CHANNELS] = {};
946         int errirq, chan_irq[SH_DMAC_MAX_CHANNELS];
947         int err, i, irq_cnt = 0, irqres = 0;
948         struct sh_dmae_device *shdev;
949         struct resource *chan, *dmars, *errirq_res, *chanirq_res;
950
951         /* get platform data */
952         if (!pdata || !pdata->channel_num)
953                 return -ENODEV;
954
955         chan = platform_get_resource(pdev, IORESOURCE_MEM, 0);
956         /* DMARS area is optional, if absent, this controller cannot do slave DMA */
957         dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1);
958         /*
959          * IRQ resources:
960          * 1. there always must be at least one IRQ IO-resource. On SH4 it is
961          *    the error IRQ, in which case it is the only IRQ in this resource:
962          *    start == end. If it is the only IRQ resource, all channels also
963          *    use the same IRQ.
964          * 2. DMA channel IRQ resources can be specified one per resource or in
965          *    ranges (start != end)
966          * 3. iff all events (channels and, optionally, error) on this
967          *    controller use the same IRQ, only one IRQ resource can be
968          *    specified, otherwise there must be one IRQ per channel, even if
969          *    some of them are equal
970          * 4. if all IRQs on this controller are equal or if some specific IRQs
971          *    specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be
972          *    requested with the IRQF_SHARED flag
973          */
974         errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
975         if (!chan || !errirq_res)
976                 return -ENODEV;
977
978         if (!request_mem_region(chan->start, resource_size(chan), pdev->name)) {
979                 dev_err(&pdev->dev, "DMAC register region already claimed\n");
980                 return -EBUSY;
981         }
982
983         if (dmars && !request_mem_region(dmars->start, resource_size(dmars), pdev->name)) {
984                 dev_err(&pdev->dev, "DMAC DMARS region already claimed\n");
985                 err = -EBUSY;
986                 goto ermrdmars;
987         }
988
989         err = -ENOMEM;
990         shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL);
991         if (!shdev) {
992                 dev_err(&pdev->dev, "Not enough memory\n");
993                 goto ealloc;
994         }
995
996         shdev->chan_reg = ioremap(chan->start, resource_size(chan));
997         if (!shdev->chan_reg)
998                 goto emapchan;
999         if (dmars) {
1000                 shdev->dmars = ioremap(dmars->start, resource_size(dmars));
1001                 if (!shdev->dmars)
1002                         goto emapdmars;
1003         }
1004
1005         /* platform data */
1006         shdev->pdata = pdata;
1007
1008         pm_runtime_enable(&pdev->dev);
1009         pm_runtime_get_sync(&pdev->dev);
1010
1011         /* reset dma controller */
1012         err = sh_dmae_rst(shdev);
1013         if (err)
1014                 goto rst_err;
1015
1016         INIT_LIST_HEAD(&shdev->common.channels);
1017
1018         dma_cap_set(DMA_MEMCPY, shdev->common.cap_mask);
1019         if (dmars)
1020                 dma_cap_set(DMA_SLAVE, shdev->common.cap_mask);
1021
1022         shdev->common.device_alloc_chan_resources
1023                 = sh_dmae_alloc_chan_resources;
1024         shdev->common.device_free_chan_resources = sh_dmae_free_chan_resources;
1025         shdev->common.device_prep_dma_memcpy = sh_dmae_prep_memcpy;
1026         shdev->common.device_is_tx_complete = sh_dmae_is_complete;
1027         shdev->common.device_issue_pending = sh_dmae_memcpy_issue_pending;
1028
1029         /* Compulsory for DMA_SLAVE fields */
1030         shdev->common.device_prep_slave_sg = sh_dmae_prep_slave_sg;
1031         shdev->common.device_terminate_all = sh_dmae_terminate_all;
1032
1033         shdev->common.dev = &pdev->dev;
1034         /* Default transfer size of 32 bytes requires 32-byte alignment */
1035         shdev->common.copy_align = LOG2_DEFAULT_XFER_SIZE;
1036
1037 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
1038         chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1039
1040         if (!chanirq_res)
1041                 chanirq_res = errirq_res;
1042         else
1043                 irqres++;
1044
1045         if (chanirq_res == errirq_res ||
1046             (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE)
1047                 irqflags = IRQF_SHARED;
1048
1049         errirq = errirq_res->start;
1050
1051         err = request_irq(errirq, sh_dmae_err, irqflags,
1052                           "DMAC Address Error", shdev);
1053         if (err) {
1054                 dev_err(&pdev->dev,
1055                         "DMA failed requesting irq #%d, error %d\n",
1056                         errirq, err);
1057                 goto eirq_err;
1058         }
1059
1060 #else
1061         chanirq_res = errirq_res;
1062 #endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */
1063
1064         if (chanirq_res->start == chanirq_res->end &&
1065             !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
1066                 /* Special case - all multiplexed */
1067                 for (; irq_cnt < pdata->channel_num; irq_cnt++) {
1068                         chan_irq[irq_cnt] = chanirq_res->start;
1069                         chan_flag[irq_cnt] = IRQF_SHARED;
1070                 }
1071         } else {
1072                 do {
1073                         for (i = chanirq_res->start; i <= chanirq_res->end; i++) {
1074                                 if ((errirq_res->flags & IORESOURCE_BITS) ==
1075                                     IORESOURCE_IRQ_SHAREABLE)
1076                                         chan_flag[irq_cnt] = IRQF_SHARED;
1077                                 else
1078                                         chan_flag[irq_cnt] = IRQF_DISABLED;
1079                                 dev_dbg(&pdev->dev,
1080                                         "Found IRQ %d for channel %d\n",
1081                                         i, irq_cnt);
1082                                 chan_irq[irq_cnt++] = i;
1083                         }
1084                         chanirq_res = platform_get_resource(pdev,
1085                                                 IORESOURCE_IRQ, ++irqres);
1086                 } while (irq_cnt < pdata->channel_num && chanirq_res);
1087         }
1088
1089         if (irq_cnt < pdata->channel_num)
1090                 goto eirqres;
1091
1092         /* Create DMA Channel */
1093         for (i = 0; i < pdata->channel_num; i++) {
1094                 err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]);
1095                 if (err)
1096                         goto chan_probe_err;
1097         }
1098
1099         pm_runtime_put(&pdev->dev);
1100
1101         platform_set_drvdata(pdev, shdev);
1102         dma_async_device_register(&shdev->common);
1103
1104         return err;
1105
1106 chan_probe_err:
1107         sh_dmae_chan_remove(shdev);
1108 eirqres:
1109 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
1110         free_irq(errirq, shdev);
1111 eirq_err:
1112 #endif
1113 rst_err:
1114         pm_runtime_put(&pdev->dev);
1115         if (dmars)
1116                 iounmap(shdev->dmars);
1117 emapdmars:
1118         iounmap(shdev->chan_reg);
1119 emapchan:
1120         kfree(shdev);
1121 ealloc:
1122         if (dmars)
1123                 release_mem_region(dmars->start, resource_size(dmars));
1124 ermrdmars:
1125         release_mem_region(chan->start, resource_size(chan));
1126
1127         return err;
1128 }
1129
1130 static int __exit sh_dmae_remove(struct platform_device *pdev)
1131 {
1132         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
1133         struct resource *res;
1134         int errirq = platform_get_irq(pdev, 0);
1135
1136         dma_async_device_unregister(&shdev->common);
1137
1138         if (errirq > 0)
1139                 free_irq(errirq, shdev);
1140
1141         /* channel data remove */
1142         sh_dmae_chan_remove(shdev);
1143
1144         pm_runtime_disable(&pdev->dev);
1145
1146         if (shdev->dmars)
1147                 iounmap(shdev->dmars);
1148         iounmap(shdev->chan_reg);
1149
1150         kfree(shdev);
1151
1152         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1153         if (res)
1154                 release_mem_region(res->start, resource_size(res));
1155         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1156         if (res)
1157                 release_mem_region(res->start, resource_size(res));
1158
1159         return 0;
1160 }
1161
1162 static void sh_dmae_shutdown(struct platform_device *pdev)
1163 {
1164         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
1165         sh_dmae_ctl_stop(shdev);
1166 }
1167
1168 static struct platform_driver sh_dmae_driver = {
1169         .remove         = __exit_p(sh_dmae_remove),
1170         .shutdown       = sh_dmae_shutdown,
1171         .driver = {
1172                 .name   = "sh-dma-engine",
1173         },
1174 };
1175
1176 static int __init sh_dmae_init(void)
1177 {
1178         return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe);
1179 }
1180 module_init(sh_dmae_init);
1181
1182 static void __exit sh_dmae_exit(void)
1183 {
1184         platform_driver_unregister(&sh_dmae_driver);
1185 }
1186 module_exit(sh_dmae_exit);
1187
1188 MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>");
1189 MODULE_DESCRIPTION("Renesas SH DMA Engine driver");
1190 MODULE_LICENSE("GPL");