SH: fix error paths in DMA driver
[linux-2.6.git] / drivers / dma / shdma.c
1 /*
2  * Renesas SuperH DMA Engine support
3  *
4  * base is drivers/dma/flsdma.c
5  *
6  * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
7  * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
8  * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
9  *
10  * This is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * - DMA of SuperH does not have Hardware DMA chain mode.
16  * - MAX DMA size is 16MB.
17  *
18  */
19
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/slab.h>
23 #include <linux/interrupt.h>
24 #include <linux/dmaengine.h>
25 #include <linux/delay.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29
30 #include <asm/dmaengine.h>
31
32 #include "shdma.h"
33
34 /* DMA descriptor control */
35 enum sh_dmae_desc_status {
36         DESC_IDLE,
37         DESC_PREPARED,
38         DESC_SUBMITTED,
39         DESC_COMPLETED, /* completed, have to call callback */
40         DESC_WAITING,   /* callback called, waiting for ack / re-submit */
41 };
42
43 #define NR_DESCS_PER_CHANNEL 32
44 /* Default MEMCPY transfer size = 2^2 = 4 bytes */
45 #define LOG2_DEFAULT_XFER_SIZE  2
46
47 /* A bitmask with bits enough for enum sh_dmae_slave_chan_id */
48 static unsigned long sh_dmae_slave_used[BITS_TO_LONGS(SHDMA_SLAVE_NUMBER)];
49
50 static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all);
51
52 static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg)
53 {
54         __raw_writel(data, sh_dc->base + reg / sizeof(u32));
55 }
56
57 static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
58 {
59         return __raw_readl(sh_dc->base + reg / sizeof(u32));
60 }
61
62 static u16 dmaor_read(struct sh_dmae_device *shdev)
63 {
64         return __raw_readw(shdev->chan_reg + DMAOR / sizeof(u32));
65 }
66
67 static void dmaor_write(struct sh_dmae_device *shdev, u16 data)
68 {
69         __raw_writew(data, shdev->chan_reg + DMAOR / sizeof(u32));
70 }
71
72 /*
73  * Reset DMA controller
74  *
75  * SH7780 has two DMAOR register
76  */
77 static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev)
78 {
79         unsigned short dmaor = dmaor_read(shdev);
80
81         dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME));
82 }
83
84 static int sh_dmae_rst(struct sh_dmae_device *shdev)
85 {
86         unsigned short dmaor;
87
88         sh_dmae_ctl_stop(shdev);
89         dmaor = dmaor_read(shdev) | shdev->pdata->dmaor_init;
90
91         dmaor_write(shdev, dmaor);
92         if (dmaor_read(shdev) & (DMAOR_AE | DMAOR_NMIF)) {
93                 pr_warning("dma-sh: Can't initialize DMAOR.\n");
94                 return -EINVAL;
95         }
96         return 0;
97 }
98
99 static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
100 {
101         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
102
103         if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE)
104                 return true; /* working */
105
106         return false; /* waiting */
107 }
108
109 static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr)
110 {
111         struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
112                                                 struct sh_dmae_device, common);
113         struct sh_dmae_pdata *pdata = shdev->pdata;
114         int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) |
115                 ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift);
116
117         if (cnt >= pdata->ts_shift_num)
118                 cnt = 0;
119
120         return pdata->ts_shift[cnt];
121 }
122
123 static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size)
124 {
125         struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
126                                                 struct sh_dmae_device, common);
127         struct sh_dmae_pdata *pdata = shdev->pdata;
128         int i;
129
130         for (i = 0; i < pdata->ts_shift_num; i++)
131                 if (pdata->ts_shift[i] == l2size)
132                         break;
133
134         if (i == pdata->ts_shift_num)
135                 i = 0;
136
137         return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) |
138                 ((i << pdata->ts_high_shift) & pdata->ts_high_mask);
139 }
140
141 static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
142 {
143         sh_dmae_writel(sh_chan, hw->sar, SAR);
144         sh_dmae_writel(sh_chan, hw->dar, DAR);
145         sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR);
146 }
147
148 static void dmae_start(struct sh_dmae_chan *sh_chan)
149 {
150         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
151
152         chcr |= CHCR_DE | CHCR_IE;
153         sh_dmae_writel(sh_chan, chcr & ~CHCR_TE, CHCR);
154 }
155
156 static void dmae_halt(struct sh_dmae_chan *sh_chan)
157 {
158         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
159
160         chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
161         sh_dmae_writel(sh_chan, chcr, CHCR);
162 }
163
164 static void dmae_init(struct sh_dmae_chan *sh_chan)
165 {
166         /*
167          * Default configuration for dual address memory-memory transfer.
168          * 0x400 represents auto-request.
169          */
170         u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan,
171                                                    LOG2_DEFAULT_XFER_SIZE);
172         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
173         sh_dmae_writel(sh_chan, chcr, CHCR);
174 }
175
176 static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
177 {
178         /* When DMA was working, can not set data to CHCR */
179         if (dmae_is_busy(sh_chan))
180                 return -EBUSY;
181
182         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val);
183         sh_dmae_writel(sh_chan, val, CHCR);
184
185         return 0;
186 }
187
188 static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
189 {
190         struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
191                                                 struct sh_dmae_device, common);
192         struct sh_dmae_pdata *pdata = shdev->pdata;
193         struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->id];
194         u16 __iomem *addr = shdev->dmars + chan_pdata->dmars / sizeof(u16);
195         int shift = chan_pdata->dmars_bit;
196
197         if (dmae_is_busy(sh_chan))
198                 return -EBUSY;
199
200         __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift),
201                      addr);
202
203         return 0;
204 }
205
206 static dma_cookie_t sh_dmae_tx_submit(struct dma_async_tx_descriptor *tx)
207 {
208         struct sh_desc *desc = tx_to_sh_desc(tx), *chunk, *last = desc, *c;
209         struct sh_dmae_chan *sh_chan = to_sh_chan(tx->chan);
210         dma_async_tx_callback callback = tx->callback;
211         dma_cookie_t cookie;
212
213         spin_lock_bh(&sh_chan->desc_lock);
214
215         cookie = sh_chan->common.cookie;
216         cookie++;
217         if (cookie < 0)
218                 cookie = 1;
219
220         sh_chan->common.cookie = cookie;
221         tx->cookie = cookie;
222
223         /* Mark all chunks of this descriptor as submitted, move to the queue */
224         list_for_each_entry_safe(chunk, c, desc->node.prev, node) {
225                 /*
226                  * All chunks are on the global ld_free, so, we have to find
227                  * the end of the chain ourselves
228                  */
229                 if (chunk != desc && (chunk->mark == DESC_IDLE ||
230                                       chunk->async_tx.cookie > 0 ||
231                                       chunk->async_tx.cookie == -EBUSY ||
232                                       &chunk->node == &sh_chan->ld_free))
233                         break;
234                 chunk->mark = DESC_SUBMITTED;
235                 /* Callback goes to the last chunk */
236                 chunk->async_tx.callback = NULL;
237                 chunk->cookie = cookie;
238                 list_move_tail(&chunk->node, &sh_chan->ld_queue);
239                 last = chunk;
240         }
241
242         last->async_tx.callback = callback;
243         last->async_tx.callback_param = tx->callback_param;
244
245         dev_dbg(sh_chan->dev, "submit #%d@%p on %d: %x[%d] -> %x\n",
246                 tx->cookie, &last->async_tx, sh_chan->id,
247                 desc->hw.sar, desc->hw.tcr, desc->hw.dar);
248
249         spin_unlock_bh(&sh_chan->desc_lock);
250
251         return cookie;
252 }
253
254 /* Called with desc_lock held */
255 static struct sh_desc *sh_dmae_get_desc(struct sh_dmae_chan *sh_chan)
256 {
257         struct sh_desc *desc;
258
259         list_for_each_entry(desc, &sh_chan->ld_free, node)
260                 if (desc->mark != DESC_PREPARED) {
261                         BUG_ON(desc->mark != DESC_IDLE);
262                         list_del(&desc->node);
263                         return desc;
264                 }
265
266         return NULL;
267 }
268
269 static struct sh_dmae_slave_config *sh_dmae_find_slave(
270         struct sh_dmae_chan *sh_chan, enum sh_dmae_slave_chan_id slave_id)
271 {
272         struct dma_device *dma_dev = sh_chan->common.device;
273         struct sh_dmae_device *shdev = container_of(dma_dev,
274                                         struct sh_dmae_device, common);
275         struct sh_dmae_pdata *pdata = shdev->pdata;
276         int i;
277
278         if ((unsigned)slave_id >= SHDMA_SLAVE_NUMBER)
279                 return NULL;
280
281         for (i = 0; i < pdata->slave_num; i++)
282                 if (pdata->slave[i].slave_id == slave_id)
283                         return pdata->slave + i;
284
285         return NULL;
286 }
287
288 static int sh_dmae_alloc_chan_resources(struct dma_chan *chan)
289 {
290         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
291         struct sh_desc *desc;
292         struct sh_dmae_slave *param = chan->private;
293         int ret;
294
295         pm_runtime_get_sync(sh_chan->dev);
296
297         /*
298          * This relies on the guarantee from dmaengine that alloc_chan_resources
299          * never runs concurrently with itself or free_chan_resources.
300          */
301         if (param) {
302                 struct sh_dmae_slave_config *cfg;
303
304                 cfg = sh_dmae_find_slave(sh_chan, param->slave_id);
305                 if (!cfg) {
306                         ret = -EINVAL;
307                         goto efindslave;
308                 }
309
310                 if (test_and_set_bit(param->slave_id, sh_dmae_slave_used)) {
311                         ret = -EBUSY;
312                         goto etestused;
313                 }
314
315                 param->config = cfg;
316
317                 dmae_set_dmars(sh_chan, cfg->mid_rid);
318                 dmae_set_chcr(sh_chan, cfg->chcr);
319         } else if ((sh_dmae_readl(sh_chan, CHCR) & 0xf00) != 0x400) {
320                 dmae_init(sh_chan);
321         }
322
323         spin_lock_bh(&sh_chan->desc_lock);
324         while (sh_chan->descs_allocated < NR_DESCS_PER_CHANNEL) {
325                 spin_unlock_bh(&sh_chan->desc_lock);
326                 desc = kzalloc(sizeof(struct sh_desc), GFP_KERNEL);
327                 if (!desc) {
328                         spin_lock_bh(&sh_chan->desc_lock);
329                         break;
330                 }
331                 dma_async_tx_descriptor_init(&desc->async_tx,
332                                         &sh_chan->common);
333                 desc->async_tx.tx_submit = sh_dmae_tx_submit;
334                 desc->mark = DESC_IDLE;
335
336                 spin_lock_bh(&sh_chan->desc_lock);
337                 list_add(&desc->node, &sh_chan->ld_free);
338                 sh_chan->descs_allocated++;
339         }
340         spin_unlock_bh(&sh_chan->desc_lock);
341
342         if (!sh_chan->descs_allocated) {
343                 ret = -ENOMEM;
344                 goto edescalloc;
345         }
346
347         return sh_chan->descs_allocated;
348
349 edescalloc:
350         if (param)
351                 clear_bit(param->slave_id, sh_dmae_slave_used);
352 etestused:
353 efindslave:
354         pm_runtime_put(sh_chan->dev);
355         return ret;
356 }
357
358 /*
359  * sh_dma_free_chan_resources - Free all resources of the channel.
360  */
361 static void sh_dmae_free_chan_resources(struct dma_chan *chan)
362 {
363         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
364         struct sh_desc *desc, *_desc;
365         LIST_HEAD(list);
366         int descs = sh_chan->descs_allocated;
367
368         dmae_halt(sh_chan);
369
370         /* Prepared and not submitted descriptors can still be on the queue */
371         if (!list_empty(&sh_chan->ld_queue))
372                 sh_dmae_chan_ld_cleanup(sh_chan, true);
373
374         if (chan->private) {
375                 /* The caller is holding dma_list_mutex */
376                 struct sh_dmae_slave *param = chan->private;
377                 clear_bit(param->slave_id, sh_dmae_slave_used);
378         }
379
380         spin_lock_bh(&sh_chan->desc_lock);
381
382         list_splice_init(&sh_chan->ld_free, &list);
383         sh_chan->descs_allocated = 0;
384
385         spin_unlock_bh(&sh_chan->desc_lock);
386
387         if (descs > 0)
388                 pm_runtime_put(sh_chan->dev);
389
390         list_for_each_entry_safe(desc, _desc, &list, node)
391                 kfree(desc);
392 }
393
394 /**
395  * sh_dmae_add_desc - get, set up and return one transfer descriptor
396  * @sh_chan:    DMA channel
397  * @flags:      DMA transfer flags
398  * @dest:       destination DMA address, incremented when direction equals
399  *              DMA_FROM_DEVICE or DMA_BIDIRECTIONAL
400  * @src:        source DMA address, incremented when direction equals
401  *              DMA_TO_DEVICE or DMA_BIDIRECTIONAL
402  * @len:        DMA transfer length
403  * @first:      if NULL, set to the current descriptor and cookie set to -EBUSY
404  * @direction:  needed for slave DMA to decide which address to keep constant,
405  *              equals DMA_BIDIRECTIONAL for MEMCPY
406  * Returns 0 or an error
407  * Locks: called with desc_lock held
408  */
409 static struct sh_desc *sh_dmae_add_desc(struct sh_dmae_chan *sh_chan,
410         unsigned long flags, dma_addr_t *dest, dma_addr_t *src, size_t *len,
411         struct sh_desc **first, enum dma_data_direction direction)
412 {
413         struct sh_desc *new;
414         size_t copy_size;
415
416         if (!*len)
417                 return NULL;
418
419         /* Allocate the link descriptor from the free list */
420         new = sh_dmae_get_desc(sh_chan);
421         if (!new) {
422                 dev_err(sh_chan->dev, "No free link descriptor available\n");
423                 return NULL;
424         }
425
426         copy_size = min(*len, (size_t)SH_DMA_TCR_MAX + 1);
427
428         new->hw.sar = *src;
429         new->hw.dar = *dest;
430         new->hw.tcr = copy_size;
431
432         if (!*first) {
433                 /* First desc */
434                 new->async_tx.cookie = -EBUSY;
435                 *first = new;
436         } else {
437                 /* Other desc - invisible to the user */
438                 new->async_tx.cookie = -EINVAL;
439         }
440
441         dev_dbg(sh_chan->dev,
442                 "chaining (%u/%u)@%x -> %x with %p, cookie %d, shift %d\n",
443                 copy_size, *len, *src, *dest, &new->async_tx,
444                 new->async_tx.cookie, sh_chan->xmit_shift);
445
446         new->mark = DESC_PREPARED;
447         new->async_tx.flags = flags;
448         new->direction = direction;
449
450         *len -= copy_size;
451         if (direction == DMA_BIDIRECTIONAL || direction == DMA_TO_DEVICE)
452                 *src += copy_size;
453         if (direction == DMA_BIDIRECTIONAL || direction == DMA_FROM_DEVICE)
454                 *dest += copy_size;
455
456         return new;
457 }
458
459 /*
460  * sh_dmae_prep_sg - prepare transfer descriptors from an SG list
461  *
462  * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also
463  * converted to scatter-gather to guarantee consistent locking and a correct
464  * list manipulation. For slave DMA direction carries the usual meaning, and,
465  * logically, the SG list is RAM and the addr variable contains slave address,
466  * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_BIDIRECTIONAL
467  * and the SG list contains only one element and points at the source buffer.
468  */
469 static struct dma_async_tx_descriptor *sh_dmae_prep_sg(struct sh_dmae_chan *sh_chan,
470         struct scatterlist *sgl, unsigned int sg_len, dma_addr_t *addr,
471         enum dma_data_direction direction, unsigned long flags)
472 {
473         struct scatterlist *sg;
474         struct sh_desc *first = NULL, *new = NULL /* compiler... */;
475         LIST_HEAD(tx_list);
476         int chunks = 0;
477         int i;
478
479         if (!sg_len)
480                 return NULL;
481
482         for_each_sg(sgl, sg, sg_len, i)
483                 chunks += (sg_dma_len(sg) + SH_DMA_TCR_MAX) /
484                         (SH_DMA_TCR_MAX + 1);
485
486         /* Have to lock the whole loop to protect against concurrent release */
487         spin_lock_bh(&sh_chan->desc_lock);
488
489         /*
490          * Chaining:
491          * first descriptor is what user is dealing with in all API calls, its
492          *      cookie is at first set to -EBUSY, at tx-submit to a positive
493          *      number
494          * if more than one chunk is needed further chunks have cookie = -EINVAL
495          * the last chunk, if not equal to the first, has cookie = -ENOSPC
496          * all chunks are linked onto the tx_list head with their .node heads
497          *      only during this function, then they are immediately spliced
498          *      back onto the free list in form of a chain
499          */
500         for_each_sg(sgl, sg, sg_len, i) {
501                 dma_addr_t sg_addr = sg_dma_address(sg);
502                 size_t len = sg_dma_len(sg);
503
504                 if (!len)
505                         goto err_get_desc;
506
507                 do {
508                         dev_dbg(sh_chan->dev, "Add SG #%d@%p[%d], dma %llx\n",
509                                 i, sg, len, (unsigned long long)sg_addr);
510
511                         if (direction == DMA_FROM_DEVICE)
512                                 new = sh_dmae_add_desc(sh_chan, flags,
513                                                 &sg_addr, addr, &len, &first,
514                                                 direction);
515                         else
516                                 new = sh_dmae_add_desc(sh_chan, flags,
517                                                 addr, &sg_addr, &len, &first,
518                                                 direction);
519                         if (!new)
520                                 goto err_get_desc;
521
522                         new->chunks = chunks--;
523                         list_add_tail(&new->node, &tx_list);
524                 } while (len);
525         }
526
527         if (new != first)
528                 new->async_tx.cookie = -ENOSPC;
529
530         /* Put them back on the free list, so, they don't get lost */
531         list_splice_tail(&tx_list, &sh_chan->ld_free);
532
533         spin_unlock_bh(&sh_chan->desc_lock);
534
535         return &first->async_tx;
536
537 err_get_desc:
538         list_for_each_entry(new, &tx_list, node)
539                 new->mark = DESC_IDLE;
540         list_splice(&tx_list, &sh_chan->ld_free);
541
542         spin_unlock_bh(&sh_chan->desc_lock);
543
544         return NULL;
545 }
546
547 static struct dma_async_tx_descriptor *sh_dmae_prep_memcpy(
548         struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
549         size_t len, unsigned long flags)
550 {
551         struct sh_dmae_chan *sh_chan;
552         struct scatterlist sg;
553
554         if (!chan || !len)
555                 return NULL;
556
557         chan->private = NULL;
558
559         sh_chan = to_sh_chan(chan);
560
561         sg_init_table(&sg, 1);
562         sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_src)), len,
563                     offset_in_page(dma_src));
564         sg_dma_address(&sg) = dma_src;
565         sg_dma_len(&sg) = len;
566
567         return sh_dmae_prep_sg(sh_chan, &sg, 1, &dma_dest, DMA_BIDIRECTIONAL,
568                                flags);
569 }
570
571 static struct dma_async_tx_descriptor *sh_dmae_prep_slave_sg(
572         struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
573         enum dma_data_direction direction, unsigned long flags)
574 {
575         struct sh_dmae_slave *param;
576         struct sh_dmae_chan *sh_chan;
577
578         if (!chan)
579                 return NULL;
580
581         sh_chan = to_sh_chan(chan);
582         param = chan->private;
583
584         /* Someone calling slave DMA on a public channel? */
585         if (!param || !sg_len) {
586                 dev_warn(sh_chan->dev, "%s: bad parameter: %p, %d, %d\n",
587                          __func__, param, sg_len, param ? param->slave_id : -1);
588                 return NULL;
589         }
590
591         /*
592          * if (param != NULL), this is a successfully requested slave channel,
593          * therefore param->config != NULL too.
594          */
595         return sh_dmae_prep_sg(sh_chan, sgl, sg_len, &param->config->addr,
596                                direction, flags);
597 }
598
599 static void sh_dmae_terminate_all(struct dma_chan *chan)
600 {
601         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
602
603         if (!chan)
604                 return;
605
606         dmae_halt(sh_chan);
607
608         spin_lock_bh(&sh_chan->desc_lock);
609         if (!list_empty(&sh_chan->ld_queue)) {
610                 /* Record partial transfer */
611                 struct sh_desc *desc = list_entry(sh_chan->ld_queue.next,
612                                                   struct sh_desc, node);
613                 desc->partial = (desc->hw.tcr - sh_dmae_readl(sh_chan, TCR)) <<
614                         sh_chan->xmit_shift;
615
616         }
617         spin_unlock_bh(&sh_chan->desc_lock);
618
619         sh_dmae_chan_ld_cleanup(sh_chan, true);
620 }
621
622 static dma_async_tx_callback __ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
623 {
624         struct sh_desc *desc, *_desc;
625         /* Is the "exposed" head of a chain acked? */
626         bool head_acked = false;
627         dma_cookie_t cookie = 0;
628         dma_async_tx_callback callback = NULL;
629         void *param = NULL;
630
631         spin_lock_bh(&sh_chan->desc_lock);
632         list_for_each_entry_safe(desc, _desc, &sh_chan->ld_queue, node) {
633                 struct dma_async_tx_descriptor *tx = &desc->async_tx;
634
635                 BUG_ON(tx->cookie > 0 && tx->cookie != desc->cookie);
636                 BUG_ON(desc->mark != DESC_SUBMITTED &&
637                        desc->mark != DESC_COMPLETED &&
638                        desc->mark != DESC_WAITING);
639
640                 /*
641                  * queue is ordered, and we use this loop to (1) clean up all
642                  * completed descriptors, and to (2) update descriptor flags of
643                  * any chunks in a (partially) completed chain
644                  */
645                 if (!all && desc->mark == DESC_SUBMITTED &&
646                     desc->cookie != cookie)
647                         break;
648
649                 if (tx->cookie > 0)
650                         cookie = tx->cookie;
651
652                 if (desc->mark == DESC_COMPLETED && desc->chunks == 1) {
653                         if (sh_chan->completed_cookie != desc->cookie - 1)
654                                 dev_dbg(sh_chan->dev,
655                                         "Completing cookie %d, expected %d\n",
656                                         desc->cookie,
657                                         sh_chan->completed_cookie + 1);
658                         sh_chan->completed_cookie = desc->cookie;
659                 }
660
661                 /* Call callback on the last chunk */
662                 if (desc->mark == DESC_COMPLETED && tx->callback) {
663                         desc->mark = DESC_WAITING;
664                         callback = tx->callback;
665                         param = tx->callback_param;
666                         dev_dbg(sh_chan->dev, "descriptor #%d@%p on %d callback\n",
667                                 tx->cookie, tx, sh_chan->id);
668                         BUG_ON(desc->chunks != 1);
669                         break;
670                 }
671
672                 if (tx->cookie > 0 || tx->cookie == -EBUSY) {
673                         if (desc->mark == DESC_COMPLETED) {
674                                 BUG_ON(tx->cookie < 0);
675                                 desc->mark = DESC_WAITING;
676                         }
677                         head_acked = async_tx_test_ack(tx);
678                 } else {
679                         switch (desc->mark) {
680                         case DESC_COMPLETED:
681                                 desc->mark = DESC_WAITING;
682                                 /* Fall through */
683                         case DESC_WAITING:
684                                 if (head_acked)
685                                         async_tx_ack(&desc->async_tx);
686                         }
687                 }
688
689                 dev_dbg(sh_chan->dev, "descriptor %p #%d completed.\n",
690                         tx, tx->cookie);
691
692                 if (((desc->mark == DESC_COMPLETED ||
693                       desc->mark == DESC_WAITING) &&
694                      async_tx_test_ack(&desc->async_tx)) || all) {
695                         /* Remove from ld_queue list */
696                         desc->mark = DESC_IDLE;
697                         list_move(&desc->node, &sh_chan->ld_free);
698                 }
699         }
700         spin_unlock_bh(&sh_chan->desc_lock);
701
702         if (callback)
703                 callback(param);
704
705         return callback;
706 }
707
708 /*
709  * sh_chan_ld_cleanup - Clean up link descriptors
710  *
711  * This function cleans up the ld_queue of DMA channel.
712  */
713 static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
714 {
715         while (__ld_cleanup(sh_chan, all))
716                 ;
717 }
718
719 static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan)
720 {
721         struct sh_desc *desc;
722
723         spin_lock_bh(&sh_chan->desc_lock);
724         /* DMA work check */
725         if (dmae_is_busy(sh_chan)) {
726                 spin_unlock_bh(&sh_chan->desc_lock);
727                 return;
728         }
729
730         /* Find the first not transferred desciptor */
731         list_for_each_entry(desc, &sh_chan->ld_queue, node)
732                 if (desc->mark == DESC_SUBMITTED) {
733                         dev_dbg(sh_chan->dev, "Queue #%d to %d: %u@%x -> %x\n",
734                                 desc->async_tx.cookie, sh_chan->id,
735                                 desc->hw.tcr, desc->hw.sar, desc->hw.dar);
736                         /* Get the ld start address from ld_queue */
737                         dmae_set_reg(sh_chan, &desc->hw);
738                         dmae_start(sh_chan);
739                         break;
740                 }
741
742         spin_unlock_bh(&sh_chan->desc_lock);
743 }
744
745 static void sh_dmae_memcpy_issue_pending(struct dma_chan *chan)
746 {
747         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
748         sh_chan_xfer_ld_queue(sh_chan);
749 }
750
751 static enum dma_status sh_dmae_is_complete(struct dma_chan *chan,
752                                         dma_cookie_t cookie,
753                                         dma_cookie_t *done,
754                                         dma_cookie_t *used)
755 {
756         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
757         dma_cookie_t last_used;
758         dma_cookie_t last_complete;
759         enum dma_status status;
760
761         sh_dmae_chan_ld_cleanup(sh_chan, false);
762
763         last_used = chan->cookie;
764         last_complete = sh_chan->completed_cookie;
765         BUG_ON(last_complete < 0);
766
767         if (done)
768                 *done = last_complete;
769
770         if (used)
771                 *used = last_used;
772
773         spin_lock_bh(&sh_chan->desc_lock);
774
775         status = dma_async_is_complete(cookie, last_complete, last_used);
776
777         /*
778          * If we don't find cookie on the queue, it has been aborted and we have
779          * to report error
780          */
781         if (status != DMA_SUCCESS) {
782                 struct sh_desc *desc;
783                 status = DMA_ERROR;
784                 list_for_each_entry(desc, &sh_chan->ld_queue, node)
785                         if (desc->cookie == cookie) {
786                                 status = DMA_IN_PROGRESS;
787                                 break;
788                         }
789         }
790
791         spin_unlock_bh(&sh_chan->desc_lock);
792
793         return status;
794 }
795
796 static irqreturn_t sh_dmae_interrupt(int irq, void *data)
797 {
798         irqreturn_t ret = IRQ_NONE;
799         struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data;
800         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
801
802         if (chcr & CHCR_TE) {
803                 /* DMA stop */
804                 dmae_halt(sh_chan);
805
806                 ret = IRQ_HANDLED;
807                 tasklet_schedule(&sh_chan->tasklet);
808         }
809
810         return ret;
811 }
812
813 #if defined(CONFIG_CPU_SH4)
814 static irqreturn_t sh_dmae_err(int irq, void *data)
815 {
816         struct sh_dmae_device *shdev = (struct sh_dmae_device *)data;
817         int i;
818
819         /* halt the dma controller */
820         sh_dmae_ctl_stop(shdev);
821
822         /* We cannot detect, which channel caused the error, have to reset all */
823         for (i = 0; i < SH_DMAC_MAX_CHANNELS; i++) {
824                 struct sh_dmae_chan *sh_chan = shdev->chan[i];
825                 if (sh_chan) {
826                         struct sh_desc *desc;
827                         /* Stop the channel */
828                         dmae_halt(sh_chan);
829                         /* Complete all  */
830                         list_for_each_entry(desc, &sh_chan->ld_queue, node) {
831                                 struct dma_async_tx_descriptor *tx = &desc->async_tx;
832                                 desc->mark = DESC_IDLE;
833                                 if (tx->callback)
834                                         tx->callback(tx->callback_param);
835                         }
836                         list_splice_init(&sh_chan->ld_queue, &sh_chan->ld_free);
837                 }
838         }
839         sh_dmae_rst(shdev);
840
841         return IRQ_HANDLED;
842 }
843 #endif
844
845 static void dmae_do_tasklet(unsigned long data)
846 {
847         struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data;
848         struct sh_desc *desc;
849         u32 sar_buf = sh_dmae_readl(sh_chan, SAR);
850         u32 dar_buf = sh_dmae_readl(sh_chan, DAR);
851
852         spin_lock(&sh_chan->desc_lock);
853         list_for_each_entry(desc, &sh_chan->ld_queue, node) {
854                 if (desc->mark == DESC_SUBMITTED &&
855                     ((desc->direction == DMA_FROM_DEVICE &&
856                       (desc->hw.dar + desc->hw.tcr) == dar_buf) ||
857                      (desc->hw.sar + desc->hw.tcr) == sar_buf)) {
858                         dev_dbg(sh_chan->dev, "done #%d@%p dst %u\n",
859                                 desc->async_tx.cookie, &desc->async_tx,
860                                 desc->hw.dar);
861                         desc->mark = DESC_COMPLETED;
862                         break;
863                 }
864         }
865         spin_unlock(&sh_chan->desc_lock);
866
867         /* Next desc */
868         sh_chan_xfer_ld_queue(sh_chan);
869         sh_dmae_chan_ld_cleanup(sh_chan, false);
870 }
871
872 static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id,
873                                         int irq, unsigned long flags)
874 {
875         int err;
876         struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id];
877         struct platform_device *pdev = to_platform_device(shdev->common.dev);
878         struct sh_dmae_chan *new_sh_chan;
879
880         /* alloc channel */
881         new_sh_chan = kzalloc(sizeof(struct sh_dmae_chan), GFP_KERNEL);
882         if (!new_sh_chan) {
883                 dev_err(shdev->common.dev,
884                         "No free memory for allocating dma channels!\n");
885                 return -ENOMEM;
886         }
887
888         /* copy struct dma_device */
889         new_sh_chan->common.device = &shdev->common;
890
891         new_sh_chan->dev = shdev->common.dev;
892         new_sh_chan->id = id;
893         new_sh_chan->irq = irq;
894         new_sh_chan->base = shdev->chan_reg + chan_pdata->offset / sizeof(u32);
895
896         /* Init DMA tasklet */
897         tasklet_init(&new_sh_chan->tasklet, dmae_do_tasklet,
898                         (unsigned long)new_sh_chan);
899
900         /* Init the channel */
901         dmae_init(new_sh_chan);
902
903         spin_lock_init(&new_sh_chan->desc_lock);
904
905         /* Init descripter manage list */
906         INIT_LIST_HEAD(&new_sh_chan->ld_queue);
907         INIT_LIST_HEAD(&new_sh_chan->ld_free);
908
909         /* Add the channel to DMA device channel list */
910         list_add_tail(&new_sh_chan->common.device_node,
911                         &shdev->common.channels);
912         shdev->common.chancnt++;
913
914         if (pdev->id >= 0)
915                 snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
916                          "sh-dmae%d.%d", pdev->id, new_sh_chan->id);
917         else
918                 snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
919                          "sh-dma%d", new_sh_chan->id);
920
921         /* set up channel irq */
922         err = request_irq(irq, &sh_dmae_interrupt, flags,
923                           new_sh_chan->dev_id, new_sh_chan);
924         if (err) {
925                 dev_err(shdev->common.dev, "DMA channel %d request_irq error "
926                         "with return %d\n", id, err);
927                 goto err_no_irq;
928         }
929
930         shdev->chan[id] = new_sh_chan;
931         return 0;
932
933 err_no_irq:
934         /* remove from dmaengine device node */
935         list_del(&new_sh_chan->common.device_node);
936         kfree(new_sh_chan);
937         return err;
938 }
939
940 static void sh_dmae_chan_remove(struct sh_dmae_device *shdev)
941 {
942         int i;
943
944         for (i = shdev->common.chancnt - 1 ; i >= 0 ; i--) {
945                 if (shdev->chan[i]) {
946                         struct sh_dmae_chan *sh_chan = shdev->chan[i];
947
948                         free_irq(sh_chan->irq, sh_chan);
949
950                         list_del(&sh_chan->common.device_node);
951                         kfree(sh_chan);
952                         shdev->chan[i] = NULL;
953                 }
954         }
955         shdev->common.chancnt = 0;
956 }
957
958 static int __init sh_dmae_probe(struct platform_device *pdev)
959 {
960         struct sh_dmae_pdata *pdata = pdev->dev.platform_data;
961         unsigned long irqflags = IRQF_DISABLED,
962                 chan_flag[SH_DMAC_MAX_CHANNELS] = {};
963         int errirq, chan_irq[SH_DMAC_MAX_CHANNELS];
964         int err, i, irq_cnt = 0, irqres = 0;
965         struct sh_dmae_device *shdev;
966         struct resource *chan, *dmars, *errirq_res, *chanirq_res;
967
968         /* get platform data */
969         if (!pdata || !pdata->channel_num)
970                 return -ENODEV;
971
972         chan = platform_get_resource(pdev, IORESOURCE_MEM, 0);
973         /* DMARS area is optional, if absent, this controller cannot do slave DMA */
974         dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1);
975         /*
976          * IRQ resources:
977          * 1. there always must be at least one IRQ IO-resource. On SH4 it is
978          *    the error IRQ, in which case it is the only IRQ in this resource:
979          *    start == end. If it is the only IRQ resource, all channels also
980          *    use the same IRQ.
981          * 2. DMA channel IRQ resources can be specified one per resource or in
982          *    ranges (start != end)
983          * 3. iff all events (channels and, optionally, error) on this
984          *    controller use the same IRQ, only one IRQ resource can be
985          *    specified, otherwise there must be one IRQ per channel, even if
986          *    some of them are equal
987          * 4. if all IRQs on this controller are equal or if some specific IRQs
988          *    specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be
989          *    requested with the IRQF_SHARED flag
990          */
991         errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
992         if (!chan || !errirq_res)
993                 return -ENODEV;
994
995         if (!request_mem_region(chan->start, resource_size(chan), pdev->name)) {
996                 dev_err(&pdev->dev, "DMAC register region already claimed\n");
997                 return -EBUSY;
998         }
999
1000         if (dmars && !request_mem_region(dmars->start, resource_size(dmars), pdev->name)) {
1001                 dev_err(&pdev->dev, "DMAC DMARS region already claimed\n");
1002                 err = -EBUSY;
1003                 goto ermrdmars;
1004         }
1005
1006         err = -ENOMEM;
1007         shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL);
1008         if (!shdev) {
1009                 dev_err(&pdev->dev, "Not enough memory\n");
1010                 goto ealloc;
1011         }
1012
1013         shdev->chan_reg = ioremap(chan->start, resource_size(chan));
1014         if (!shdev->chan_reg)
1015                 goto emapchan;
1016         if (dmars) {
1017                 shdev->dmars = ioremap(dmars->start, resource_size(dmars));
1018                 if (!shdev->dmars)
1019                         goto emapdmars;
1020         }
1021
1022         /* platform data */
1023         shdev->pdata = pdata;
1024
1025         pm_runtime_enable(&pdev->dev);
1026         pm_runtime_get_sync(&pdev->dev);
1027
1028         /* reset dma controller */
1029         err = sh_dmae_rst(shdev);
1030         if (err)
1031                 goto rst_err;
1032
1033         INIT_LIST_HEAD(&shdev->common.channels);
1034
1035         dma_cap_set(DMA_MEMCPY, shdev->common.cap_mask);
1036         if (dmars)
1037                 dma_cap_set(DMA_SLAVE, shdev->common.cap_mask);
1038
1039         shdev->common.device_alloc_chan_resources
1040                 = sh_dmae_alloc_chan_resources;
1041         shdev->common.device_free_chan_resources = sh_dmae_free_chan_resources;
1042         shdev->common.device_prep_dma_memcpy = sh_dmae_prep_memcpy;
1043         shdev->common.device_is_tx_complete = sh_dmae_is_complete;
1044         shdev->common.device_issue_pending = sh_dmae_memcpy_issue_pending;
1045
1046         /* Compulsory for DMA_SLAVE fields */
1047         shdev->common.device_prep_slave_sg = sh_dmae_prep_slave_sg;
1048         shdev->common.device_terminate_all = sh_dmae_terminate_all;
1049
1050         shdev->common.dev = &pdev->dev;
1051         /* Default transfer size of 32 bytes requires 32-byte alignment */
1052         shdev->common.copy_align = LOG2_DEFAULT_XFER_SIZE;
1053
1054 #if defined(CONFIG_CPU_SH4)
1055         chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1056
1057         if (!chanirq_res)
1058                 chanirq_res = errirq_res;
1059         else
1060                 irqres++;
1061
1062         if (chanirq_res == errirq_res ||
1063             (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE)
1064                 irqflags = IRQF_SHARED;
1065
1066         errirq = errirq_res->start;
1067
1068         err = request_irq(errirq, sh_dmae_err, irqflags,
1069                           "DMAC Address Error", shdev);
1070         if (err) {
1071                 dev_err(&pdev->dev,
1072                         "DMA failed requesting irq #%d, error %d\n",
1073                         errirq, err);
1074                 goto eirq_err;
1075         }
1076
1077 #else
1078         chanirq_res = errirq_res;
1079 #endif /* CONFIG_CPU_SH4 */
1080
1081         if (chanirq_res->start == chanirq_res->end &&
1082             !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
1083                 /* Special case - all multiplexed */
1084                 for (; irq_cnt < pdata->channel_num; irq_cnt++) {
1085                         chan_irq[irq_cnt] = chanirq_res->start;
1086                         chan_flag[irq_cnt] = IRQF_SHARED;
1087                 }
1088         } else {
1089                 do {
1090                         for (i = chanirq_res->start; i <= chanirq_res->end; i++) {
1091                                 if ((errirq_res->flags & IORESOURCE_BITS) ==
1092                                     IORESOURCE_IRQ_SHAREABLE)
1093                                         chan_flag[irq_cnt] = IRQF_SHARED;
1094                                 else
1095                                         chan_flag[irq_cnt] = IRQF_DISABLED;
1096                                 dev_dbg(&pdev->dev,
1097                                         "Found IRQ %d for channel %d\n",
1098                                         i, irq_cnt);
1099                                 chan_irq[irq_cnt++] = i;
1100                         }
1101                         chanirq_res = platform_get_resource(pdev,
1102                                                 IORESOURCE_IRQ, ++irqres);
1103                 } while (irq_cnt < pdata->channel_num && chanirq_res);
1104         }
1105
1106         if (irq_cnt < pdata->channel_num)
1107                 goto eirqres;
1108
1109         /* Create DMA Channel */
1110         for (i = 0; i < pdata->channel_num; i++) {
1111                 err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]);
1112                 if (err)
1113                         goto chan_probe_err;
1114         }
1115
1116         pm_runtime_put(&pdev->dev);
1117
1118         platform_set_drvdata(pdev, shdev);
1119         dma_async_device_register(&shdev->common);
1120
1121         return err;
1122
1123 chan_probe_err:
1124         sh_dmae_chan_remove(shdev);
1125 eirqres:
1126 #if defined(CONFIG_CPU_SH4)
1127         free_irq(errirq, shdev);
1128 eirq_err:
1129 #endif
1130 rst_err:
1131         pm_runtime_put(&pdev->dev);
1132         if (dmars)
1133                 iounmap(shdev->dmars);
1134 emapdmars:
1135         iounmap(shdev->chan_reg);
1136 emapchan:
1137         kfree(shdev);
1138 ealloc:
1139         if (dmars)
1140                 release_mem_region(dmars->start, resource_size(dmars));
1141 ermrdmars:
1142         release_mem_region(chan->start, resource_size(chan));
1143
1144         return err;
1145 }
1146
1147 static int __exit sh_dmae_remove(struct platform_device *pdev)
1148 {
1149         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
1150         struct resource *res;
1151         int errirq = platform_get_irq(pdev, 0);
1152
1153         dma_async_device_unregister(&shdev->common);
1154
1155         if (errirq > 0)
1156                 free_irq(errirq, shdev);
1157
1158         /* channel data remove */
1159         sh_dmae_chan_remove(shdev);
1160
1161         pm_runtime_disable(&pdev->dev);
1162
1163         if (shdev->dmars)
1164                 iounmap(shdev->dmars);
1165         iounmap(shdev->chan_reg);
1166
1167         kfree(shdev);
1168
1169         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1170         if (res)
1171                 release_mem_region(res->start, resource_size(res));
1172         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1173         if (res)
1174                 release_mem_region(res->start, resource_size(res));
1175
1176         return 0;
1177 }
1178
1179 static void sh_dmae_shutdown(struct platform_device *pdev)
1180 {
1181         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
1182         sh_dmae_ctl_stop(shdev);
1183 }
1184
1185 static struct platform_driver sh_dmae_driver = {
1186         .remove         = __exit_p(sh_dmae_remove),
1187         .shutdown       = sh_dmae_shutdown,
1188         .driver = {
1189                 .name   = "sh-dma-engine",
1190         },
1191 };
1192
1193 static int __init sh_dmae_init(void)
1194 {
1195         return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe);
1196 }
1197 module_init(sh_dmae_init);
1198
1199 static void __exit sh_dmae_exit(void)
1200 {
1201         platform_driver_unregister(&sh_dmae_driver);
1202 }
1203 module_exit(sh_dmae_exit);
1204
1205 MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>");
1206 MODULE_DESCRIPTION("Renesas SH DMA Engine driver");
1207 MODULE_LICENSE("GPL");