39485c36fb7fef552bf1452c7ca9fc7902cbd646
[linux-2.6.git] / drivers / dma / shdma.c
1 /*
2  * Renesas SuperH DMA Engine support
3  *
4  * base is drivers/dma/flsdma.c
5  *
6  * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
7  * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
8  * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
9  *
10  * This is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * - DMA of SuperH does not have Hardware DMA chain mode.
16  * - MAX DMA size is 16MB.
17  *
18  */
19
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/slab.h>
23 #include <linux/interrupt.h>
24 #include <linux/dmaengine.h>
25 #include <linux/delay.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/sh_dma.h>
30 #include <linux/notifier.h>
31 #include <linux/kdebug.h>
32 #include <linux/spinlock.h>
33 #include <linux/rculist.h>
34
35 #include "dmaengine.h"
36 #include "shdma.h"
37
38 /* DMA descriptor control */
39 enum sh_dmae_desc_status {
40         DESC_IDLE,
41         DESC_PREPARED,
42         DESC_SUBMITTED,
43         DESC_COMPLETED, /* completed, have to call callback */
44         DESC_WAITING,   /* callback called, waiting for ack / re-submit */
45 };
46
47 #define NR_DESCS_PER_CHANNEL 32
48 /* Default MEMCPY transfer size = 2^2 = 4 bytes */
49 #define LOG2_DEFAULT_XFER_SIZE  2
50
51 /*
52  * Used for write-side mutual exclusion for the global device list,
53  * read-side synchronization by way of RCU, and per-controller data.
54  */
55 static DEFINE_SPINLOCK(sh_dmae_lock);
56 static LIST_HEAD(sh_dmae_devices);
57
58 /* A bitmask with bits enough for enum sh_dmae_slave_chan_id */
59 static unsigned long sh_dmae_slave_used[BITS_TO_LONGS(SH_DMA_SLAVE_NUMBER)];
60
61 static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all);
62
63 static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg)
64 {
65         __raw_writel(data, sh_dc->base + reg / sizeof(u32));
66 }
67
68 static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
69 {
70         return __raw_readl(sh_dc->base + reg / sizeof(u32));
71 }
72
73 static u16 dmaor_read(struct sh_dmae_device *shdev)
74 {
75         u32 __iomem *addr = shdev->chan_reg + DMAOR / sizeof(u32);
76
77         if (shdev->pdata->dmaor_is_32bit)
78                 return __raw_readl(addr);
79         else
80                 return __raw_readw(addr);
81 }
82
83 static void dmaor_write(struct sh_dmae_device *shdev, u16 data)
84 {
85         u32 __iomem *addr = shdev->chan_reg + DMAOR / sizeof(u32);
86
87         if (shdev->pdata->dmaor_is_32bit)
88                 __raw_writel(data, addr);
89         else
90                 __raw_writew(data, addr);
91 }
92
93 static void chcr_write(struct sh_dmae_chan *sh_dc, u32 data)
94 {
95         struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
96
97         __raw_writel(data, sh_dc->base + shdev->chcr_offset / sizeof(u32));
98 }
99
100 static u32 chcr_read(struct sh_dmae_chan *sh_dc)
101 {
102         struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
103
104         return __raw_readl(sh_dc->base + shdev->chcr_offset / sizeof(u32));
105 }
106
107 /*
108  * Reset DMA controller
109  *
110  * SH7780 has two DMAOR register
111  */
112 static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev)
113 {
114         unsigned short dmaor;
115         unsigned long flags;
116
117         spin_lock_irqsave(&sh_dmae_lock, flags);
118
119         dmaor = dmaor_read(shdev);
120         dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME));
121
122         spin_unlock_irqrestore(&sh_dmae_lock, flags);
123 }
124
125 static int sh_dmae_rst(struct sh_dmae_device *shdev)
126 {
127         unsigned short dmaor;
128         unsigned long flags;
129
130         spin_lock_irqsave(&sh_dmae_lock, flags);
131
132         dmaor = dmaor_read(shdev) & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME);
133
134         dmaor_write(shdev, dmaor | shdev->pdata->dmaor_init);
135
136         dmaor = dmaor_read(shdev);
137
138         spin_unlock_irqrestore(&sh_dmae_lock, flags);
139
140         if (dmaor & (DMAOR_AE | DMAOR_NMIF)) {
141                 dev_warn(shdev->common.dev, "Can't initialize DMAOR.\n");
142                 return -EIO;
143         }
144         return 0;
145 }
146
147 static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
148 {
149         u32 chcr = chcr_read(sh_chan);
150
151         if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE)
152                 return true; /* working */
153
154         return false; /* waiting */
155 }
156
157 static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr)
158 {
159         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
160         struct sh_dmae_pdata *pdata = shdev->pdata;
161         int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) |
162                 ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift);
163
164         if (cnt >= pdata->ts_shift_num)
165                 cnt = 0;
166
167         return pdata->ts_shift[cnt];
168 }
169
170 static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size)
171 {
172         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
173         struct sh_dmae_pdata *pdata = shdev->pdata;
174         int i;
175
176         for (i = 0; i < pdata->ts_shift_num; i++)
177                 if (pdata->ts_shift[i] == l2size)
178                         break;
179
180         if (i == pdata->ts_shift_num)
181                 i = 0;
182
183         return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) |
184                 ((i << pdata->ts_high_shift) & pdata->ts_high_mask);
185 }
186
187 static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
188 {
189         sh_dmae_writel(sh_chan, hw->sar, SAR);
190         sh_dmae_writel(sh_chan, hw->dar, DAR);
191         sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR);
192 }
193
194 static void dmae_start(struct sh_dmae_chan *sh_chan)
195 {
196         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
197         u32 chcr = chcr_read(sh_chan);
198
199         if (shdev->pdata->needs_tend_set)
200                 sh_dmae_writel(sh_chan, 0xFFFFFFFF, TEND);
201
202         chcr |= CHCR_DE | shdev->chcr_ie_bit;
203         chcr_write(sh_chan, chcr & ~CHCR_TE);
204 }
205
206 static void dmae_halt(struct sh_dmae_chan *sh_chan)
207 {
208         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
209         u32 chcr = chcr_read(sh_chan);
210
211         chcr &= ~(CHCR_DE | CHCR_TE | shdev->chcr_ie_bit);
212         chcr_write(sh_chan, chcr);
213 }
214
215 static void dmae_init(struct sh_dmae_chan *sh_chan)
216 {
217         /*
218          * Default configuration for dual address memory-memory transfer.
219          * 0x400 represents auto-request.
220          */
221         u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan,
222                                                    LOG2_DEFAULT_XFER_SIZE);
223         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
224         chcr_write(sh_chan, chcr);
225 }
226
227 static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
228 {
229         /* If DMA is active, cannot set CHCR. TODO: remove this superfluous check */
230         if (dmae_is_busy(sh_chan))
231                 return -EBUSY;
232
233         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val);
234         chcr_write(sh_chan, val);
235
236         return 0;
237 }
238
239 static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
240 {
241         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
242         struct sh_dmae_pdata *pdata = shdev->pdata;
243         const struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->id];
244         u16 __iomem *addr = shdev->dmars;
245         unsigned int shift = chan_pdata->dmars_bit;
246
247         if (dmae_is_busy(sh_chan))
248                 return -EBUSY;
249
250         if (pdata->no_dmars)
251                 return 0;
252
253         /* in the case of a missing DMARS resource use first memory window */
254         if (!addr)
255                 addr = (u16 __iomem *)shdev->chan_reg;
256         addr += chan_pdata->dmars / sizeof(u16);
257
258         __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift),
259                      addr);
260
261         return 0;
262 }
263
264 static dma_cookie_t sh_dmae_tx_submit(struct dma_async_tx_descriptor *tx)
265 {
266         struct sh_desc *desc = tx_to_sh_desc(tx), *chunk, *last = desc, *c;
267         struct sh_dmae_chan *sh_chan = to_sh_chan(tx->chan);
268         dma_async_tx_callback callback = tx->callback;
269         dma_cookie_t cookie;
270
271         spin_lock_bh(&sh_chan->desc_lock);
272
273         cookie = dma_cookie_assign(tx);
274
275         /* Mark all chunks of this descriptor as submitted, move to the queue */
276         list_for_each_entry_safe(chunk, c, desc->node.prev, node) {
277                 /*
278                  * All chunks are on the global ld_free, so, we have to find
279                  * the end of the chain ourselves
280                  */
281                 if (chunk != desc && (chunk->mark == DESC_IDLE ||
282                                       chunk->async_tx.cookie > 0 ||
283                                       chunk->async_tx.cookie == -EBUSY ||
284                                       &chunk->node == &sh_chan->ld_free))
285                         break;
286                 chunk->mark = DESC_SUBMITTED;
287                 /* Callback goes to the last chunk */
288                 chunk->async_tx.callback = NULL;
289                 chunk->cookie = cookie;
290                 list_move_tail(&chunk->node, &sh_chan->ld_queue);
291                 last = chunk;
292         }
293
294         last->async_tx.callback = callback;
295         last->async_tx.callback_param = tx->callback_param;
296
297         dev_dbg(sh_chan->dev, "submit #%d@%p on %d: %x[%d] -> %x\n",
298                 tx->cookie, &last->async_tx, sh_chan->id,
299                 desc->hw.sar, desc->hw.tcr, desc->hw.dar);
300
301         spin_unlock_bh(&sh_chan->desc_lock);
302
303         return cookie;
304 }
305
306 /* Called with desc_lock held */
307 static struct sh_desc *sh_dmae_get_desc(struct sh_dmae_chan *sh_chan)
308 {
309         struct sh_desc *desc;
310
311         list_for_each_entry(desc, &sh_chan->ld_free, node)
312                 if (desc->mark != DESC_PREPARED) {
313                         BUG_ON(desc->mark != DESC_IDLE);
314                         list_del(&desc->node);
315                         return desc;
316                 }
317
318         return NULL;
319 }
320
321 static const struct sh_dmae_slave_config *sh_dmae_find_slave(
322         struct sh_dmae_chan *sh_chan, struct sh_dmae_slave *param)
323 {
324         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
325         struct sh_dmae_pdata *pdata = shdev->pdata;
326         int i;
327
328         if (param->slave_id >= SH_DMA_SLAVE_NUMBER)
329                 return NULL;
330
331         for (i = 0; i < pdata->slave_num; i++)
332                 if (pdata->slave[i].slave_id == param->slave_id)
333                         return pdata->slave + i;
334
335         return NULL;
336 }
337
338 static int sh_dmae_alloc_chan_resources(struct dma_chan *chan)
339 {
340         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
341         struct sh_desc *desc;
342         struct sh_dmae_slave *param = chan->private;
343         int ret;
344
345         pm_runtime_get_sync(sh_chan->dev);
346
347         /*
348          * This relies on the guarantee from dmaengine that alloc_chan_resources
349          * never runs concurrently with itself or free_chan_resources.
350          */
351         if (param) {
352                 const struct sh_dmae_slave_config *cfg;
353
354                 cfg = sh_dmae_find_slave(sh_chan, param);
355                 if (!cfg) {
356                         ret = -EINVAL;
357                         goto efindslave;
358                 }
359
360                 if (test_and_set_bit(param->slave_id, sh_dmae_slave_used)) {
361                         ret = -EBUSY;
362                         goto etestused;
363                 }
364
365                 param->config = cfg;
366
367                 dmae_set_dmars(sh_chan, cfg->mid_rid);
368                 dmae_set_chcr(sh_chan, cfg->chcr);
369         } else {
370                 dmae_init(sh_chan);
371         }
372
373         spin_lock_bh(&sh_chan->desc_lock);
374         while (sh_chan->descs_allocated < NR_DESCS_PER_CHANNEL) {
375                 spin_unlock_bh(&sh_chan->desc_lock);
376                 desc = kzalloc(sizeof(struct sh_desc), GFP_KERNEL);
377                 if (!desc) {
378                         spin_lock_bh(&sh_chan->desc_lock);
379                         break;
380                 }
381                 dma_async_tx_descriptor_init(&desc->async_tx,
382                                         &sh_chan->common);
383                 desc->async_tx.tx_submit = sh_dmae_tx_submit;
384                 desc->mark = DESC_IDLE;
385
386                 spin_lock_bh(&sh_chan->desc_lock);
387                 list_add(&desc->node, &sh_chan->ld_free);
388                 sh_chan->descs_allocated++;
389         }
390         spin_unlock_bh(&sh_chan->desc_lock);
391
392         if (!sh_chan->descs_allocated) {
393                 ret = -ENOMEM;
394                 goto edescalloc;
395         }
396
397         return sh_chan->descs_allocated;
398
399 edescalloc:
400         if (param)
401                 clear_bit(param->slave_id, sh_dmae_slave_used);
402 etestused:
403 efindslave:
404         pm_runtime_put(sh_chan->dev);
405         return ret;
406 }
407
408 /*
409  * sh_dma_free_chan_resources - Free all resources of the channel.
410  */
411 static void sh_dmae_free_chan_resources(struct dma_chan *chan)
412 {
413         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
414         struct sh_desc *desc, *_desc;
415         LIST_HEAD(list);
416         int descs = sh_chan->descs_allocated;
417
418         /* Protect against ISR */
419         spin_lock_irq(&sh_chan->desc_lock);
420         dmae_halt(sh_chan);
421         spin_unlock_irq(&sh_chan->desc_lock);
422
423         /* Now no new interrupts will occur */
424
425         /* Prepared and not submitted descriptors can still be on the queue */
426         if (!list_empty(&sh_chan->ld_queue))
427                 sh_dmae_chan_ld_cleanup(sh_chan, true);
428
429         if (chan->private) {
430                 /* The caller is holding dma_list_mutex */
431                 struct sh_dmae_slave *param = chan->private;
432                 clear_bit(param->slave_id, sh_dmae_slave_used);
433                 chan->private = NULL;
434         }
435
436         spin_lock_bh(&sh_chan->desc_lock);
437
438         list_splice_init(&sh_chan->ld_free, &list);
439         sh_chan->descs_allocated = 0;
440
441         spin_unlock_bh(&sh_chan->desc_lock);
442
443         if (descs > 0)
444                 pm_runtime_put(sh_chan->dev);
445
446         list_for_each_entry_safe(desc, _desc, &list, node)
447                 kfree(desc);
448 }
449
450 /**
451  * sh_dmae_add_desc - get, set up and return one transfer descriptor
452  * @sh_chan:    DMA channel
453  * @flags:      DMA transfer flags
454  * @dest:       destination DMA address, incremented when direction equals
455  *              DMA_FROM_DEVICE or DMA_BIDIRECTIONAL
456  * @src:        source DMA address, incremented when direction equals
457  *              DMA_TO_DEVICE or DMA_BIDIRECTIONAL
458  * @len:        DMA transfer length
459  * @first:      if NULL, set to the current descriptor and cookie set to -EBUSY
460  * @direction:  needed for slave DMA to decide which address to keep constant,
461  *              equals DMA_BIDIRECTIONAL for MEMCPY
462  * Returns 0 or an error
463  * Locks: called with desc_lock held
464  */
465 static struct sh_desc *sh_dmae_add_desc(struct sh_dmae_chan *sh_chan,
466         unsigned long flags, dma_addr_t *dest, dma_addr_t *src, size_t *len,
467         struct sh_desc **first, enum dma_data_direction direction)
468 {
469         struct sh_desc *new;
470         size_t copy_size;
471
472         if (!*len)
473                 return NULL;
474
475         /* Allocate the link descriptor from the free list */
476         new = sh_dmae_get_desc(sh_chan);
477         if (!new) {
478                 dev_err(sh_chan->dev, "No free link descriptor available\n");
479                 return NULL;
480         }
481
482         copy_size = min(*len, (size_t)SH_DMA_TCR_MAX + 1);
483
484         new->hw.sar = *src;
485         new->hw.dar = *dest;
486         new->hw.tcr = copy_size;
487
488         if (!*first) {
489                 /* First desc */
490                 new->async_tx.cookie = -EBUSY;
491                 *first = new;
492         } else {
493                 /* Other desc - invisible to the user */
494                 new->async_tx.cookie = -EINVAL;
495         }
496
497         dev_dbg(sh_chan->dev,
498                 "chaining (%u/%u)@%x -> %x with %p, cookie %d, shift %d\n",
499                 copy_size, *len, *src, *dest, &new->async_tx,
500                 new->async_tx.cookie, sh_chan->xmit_shift);
501
502         new->mark = DESC_PREPARED;
503         new->async_tx.flags = flags;
504         new->direction = direction;
505
506         *len -= copy_size;
507         if (direction == DMA_BIDIRECTIONAL || direction == DMA_TO_DEVICE)
508                 *src += copy_size;
509         if (direction == DMA_BIDIRECTIONAL || direction == DMA_FROM_DEVICE)
510                 *dest += copy_size;
511
512         return new;
513 }
514
515 /*
516  * sh_dmae_prep_sg - prepare transfer descriptors from an SG list
517  *
518  * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also
519  * converted to scatter-gather to guarantee consistent locking and a correct
520  * list manipulation. For slave DMA direction carries the usual meaning, and,
521  * logically, the SG list is RAM and the addr variable contains slave address,
522  * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_BIDIRECTIONAL
523  * and the SG list contains only one element and points at the source buffer.
524  */
525 static struct dma_async_tx_descriptor *sh_dmae_prep_sg(struct sh_dmae_chan *sh_chan,
526         struct scatterlist *sgl, unsigned int sg_len, dma_addr_t *addr,
527         enum dma_data_direction direction, unsigned long flags)
528 {
529         struct scatterlist *sg;
530         struct sh_desc *first = NULL, *new = NULL /* compiler... */;
531         LIST_HEAD(tx_list);
532         int chunks = 0;
533         int i;
534
535         if (!sg_len)
536                 return NULL;
537
538         for_each_sg(sgl, sg, sg_len, i)
539                 chunks += (sg_dma_len(sg) + SH_DMA_TCR_MAX) /
540                         (SH_DMA_TCR_MAX + 1);
541
542         /* Have to lock the whole loop to protect against concurrent release */
543         spin_lock_bh(&sh_chan->desc_lock);
544
545         /*
546          * Chaining:
547          * first descriptor is what user is dealing with in all API calls, its
548          *      cookie is at first set to -EBUSY, at tx-submit to a positive
549          *      number
550          * if more than one chunk is needed further chunks have cookie = -EINVAL
551          * the last chunk, if not equal to the first, has cookie = -ENOSPC
552          * all chunks are linked onto the tx_list head with their .node heads
553          *      only during this function, then they are immediately spliced
554          *      back onto the free list in form of a chain
555          */
556         for_each_sg(sgl, sg, sg_len, i) {
557                 dma_addr_t sg_addr = sg_dma_address(sg);
558                 size_t len = sg_dma_len(sg);
559
560                 if (!len)
561                         goto err_get_desc;
562
563                 do {
564                         dev_dbg(sh_chan->dev, "Add SG #%d@%p[%d], dma %llx\n",
565                                 i, sg, len, (unsigned long long)sg_addr);
566
567                         if (direction == DMA_FROM_DEVICE)
568                                 new = sh_dmae_add_desc(sh_chan, flags,
569                                                 &sg_addr, addr, &len, &first,
570                                                 direction);
571                         else
572                                 new = sh_dmae_add_desc(sh_chan, flags,
573                                                 addr, &sg_addr, &len, &first,
574                                                 direction);
575                         if (!new)
576                                 goto err_get_desc;
577
578                         new->chunks = chunks--;
579                         list_add_tail(&new->node, &tx_list);
580                 } while (len);
581         }
582
583         if (new != first)
584                 new->async_tx.cookie = -ENOSPC;
585
586         /* Put them back on the free list, so, they don't get lost */
587         list_splice_tail(&tx_list, &sh_chan->ld_free);
588
589         spin_unlock_bh(&sh_chan->desc_lock);
590
591         return &first->async_tx;
592
593 err_get_desc:
594         list_for_each_entry(new, &tx_list, node)
595                 new->mark = DESC_IDLE;
596         list_splice(&tx_list, &sh_chan->ld_free);
597
598         spin_unlock_bh(&sh_chan->desc_lock);
599
600         return NULL;
601 }
602
603 static struct dma_async_tx_descriptor *sh_dmae_prep_memcpy(
604         struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
605         size_t len, unsigned long flags)
606 {
607         struct sh_dmae_chan *sh_chan;
608         struct scatterlist sg;
609
610         if (!chan || !len)
611                 return NULL;
612
613         sh_chan = to_sh_chan(chan);
614
615         sg_init_table(&sg, 1);
616         sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_src)), len,
617                     offset_in_page(dma_src));
618         sg_dma_address(&sg) = dma_src;
619         sg_dma_len(&sg) = len;
620
621         return sh_dmae_prep_sg(sh_chan, &sg, 1, &dma_dest, DMA_BIDIRECTIONAL,
622                                flags);
623 }
624
625 static struct dma_async_tx_descriptor *sh_dmae_prep_slave_sg(
626         struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
627         enum dma_transfer_direction direction, unsigned long flags,
628         void *context)
629 {
630         struct sh_dmae_slave *param;
631         struct sh_dmae_chan *sh_chan;
632         dma_addr_t slave_addr;
633
634         if (!chan)
635                 return NULL;
636
637         sh_chan = to_sh_chan(chan);
638         param = chan->private;
639
640         /* Someone calling slave DMA on a public channel? */
641         if (!param || !sg_len) {
642                 dev_warn(sh_chan->dev, "%s: bad parameter: %p, %d, %d\n",
643                          __func__, param, sg_len, param ? param->slave_id : -1);
644                 return NULL;
645         }
646
647         slave_addr = param->config->addr;
648
649         /*
650          * if (param != NULL), this is a successfully requested slave channel,
651          * therefore param->config != NULL too.
652          */
653         return sh_dmae_prep_sg(sh_chan, sgl, sg_len, &slave_addr,
654                                direction, flags);
655 }
656
657 static int sh_dmae_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
658                            unsigned long arg)
659 {
660         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
661
662         /* Only supports DMA_TERMINATE_ALL */
663         if (cmd != DMA_TERMINATE_ALL)
664                 return -ENXIO;
665
666         if (!chan)
667                 return -EINVAL;
668
669         spin_lock_bh(&sh_chan->desc_lock);
670         dmae_halt(sh_chan);
671
672         if (!list_empty(&sh_chan->ld_queue)) {
673                 /* Record partial transfer */
674                 struct sh_desc *desc = list_entry(sh_chan->ld_queue.next,
675                                                   struct sh_desc, node);
676                 desc->partial = (desc->hw.tcr - sh_dmae_readl(sh_chan, TCR)) <<
677                         sh_chan->xmit_shift;
678
679         }
680         spin_unlock_bh(&sh_chan->desc_lock);
681
682         sh_dmae_chan_ld_cleanup(sh_chan, true);
683
684         return 0;
685 }
686
687 static dma_async_tx_callback __ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
688 {
689         struct sh_desc *desc, *_desc;
690         /* Is the "exposed" head of a chain acked? */
691         bool head_acked = false;
692         dma_cookie_t cookie = 0;
693         dma_async_tx_callback callback = NULL;
694         void *param = NULL;
695
696         spin_lock_bh(&sh_chan->desc_lock);
697         list_for_each_entry_safe(desc, _desc, &sh_chan->ld_queue, node) {
698                 struct dma_async_tx_descriptor *tx = &desc->async_tx;
699
700                 BUG_ON(tx->cookie > 0 && tx->cookie != desc->cookie);
701                 BUG_ON(desc->mark != DESC_SUBMITTED &&
702                        desc->mark != DESC_COMPLETED &&
703                        desc->mark != DESC_WAITING);
704
705                 /*
706                  * queue is ordered, and we use this loop to (1) clean up all
707                  * completed descriptors, and to (2) update descriptor flags of
708                  * any chunks in a (partially) completed chain
709                  */
710                 if (!all && desc->mark == DESC_SUBMITTED &&
711                     desc->cookie != cookie)
712                         break;
713
714                 if (tx->cookie > 0)
715                         cookie = tx->cookie;
716
717                 if (desc->mark == DESC_COMPLETED && desc->chunks == 1) {
718                         if (sh_chan->common.completed_cookie != desc->cookie - 1)
719                                 dev_dbg(sh_chan->dev,
720                                         "Completing cookie %d, expected %d\n",
721                                         desc->cookie,
722                                         sh_chan->common.completed_cookie + 1);
723                         sh_chan->common.completed_cookie = desc->cookie;
724                 }
725
726                 /* Call callback on the last chunk */
727                 if (desc->mark == DESC_COMPLETED && tx->callback) {
728                         desc->mark = DESC_WAITING;
729                         callback = tx->callback;
730                         param = tx->callback_param;
731                         dev_dbg(sh_chan->dev, "descriptor #%d@%p on %d callback\n",
732                                 tx->cookie, tx, sh_chan->id);
733                         BUG_ON(desc->chunks != 1);
734                         break;
735                 }
736
737                 if (tx->cookie > 0 || tx->cookie == -EBUSY) {
738                         if (desc->mark == DESC_COMPLETED) {
739                                 BUG_ON(tx->cookie < 0);
740                                 desc->mark = DESC_WAITING;
741                         }
742                         head_acked = async_tx_test_ack(tx);
743                 } else {
744                         switch (desc->mark) {
745                         case DESC_COMPLETED:
746                                 desc->mark = DESC_WAITING;
747                                 /* Fall through */
748                         case DESC_WAITING:
749                                 if (head_acked)
750                                         async_tx_ack(&desc->async_tx);
751                         }
752                 }
753
754                 dev_dbg(sh_chan->dev, "descriptor %p #%d completed.\n",
755                         tx, tx->cookie);
756
757                 if (((desc->mark == DESC_COMPLETED ||
758                       desc->mark == DESC_WAITING) &&
759                      async_tx_test_ack(&desc->async_tx)) || all) {
760                         /* Remove from ld_queue list */
761                         desc->mark = DESC_IDLE;
762                         list_move(&desc->node, &sh_chan->ld_free);
763                 }
764         }
765
766         if (all && !callback)
767                 /*
768                  * Terminating and the loop completed normally: forgive
769                  * uncompleted cookies
770                  */
771                 sh_chan->common.completed_cookie = sh_chan->common.cookie;
772
773         spin_unlock_bh(&sh_chan->desc_lock);
774
775         if (callback)
776                 callback(param);
777
778         return callback;
779 }
780
781 /*
782  * sh_chan_ld_cleanup - Clean up link descriptors
783  *
784  * This function cleans up the ld_queue of DMA channel.
785  */
786 static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
787 {
788         while (__ld_cleanup(sh_chan, all))
789                 ;
790 }
791
792 static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan)
793 {
794         struct sh_desc *desc;
795
796         spin_lock_bh(&sh_chan->desc_lock);
797         /* DMA work check */
798         if (dmae_is_busy(sh_chan))
799                 goto sh_chan_xfer_ld_queue_end;
800
801         /* Find the first not transferred descriptor */
802         list_for_each_entry(desc, &sh_chan->ld_queue, node)
803                 if (desc->mark == DESC_SUBMITTED) {
804                         dev_dbg(sh_chan->dev, "Queue #%d to %d: %u@%x -> %x\n",
805                                 desc->async_tx.cookie, sh_chan->id,
806                                 desc->hw.tcr, desc->hw.sar, desc->hw.dar);
807                         /* Get the ld start address from ld_queue */
808                         dmae_set_reg(sh_chan, &desc->hw);
809                         dmae_start(sh_chan);
810                         break;
811                 }
812
813 sh_chan_xfer_ld_queue_end:
814         spin_unlock_bh(&sh_chan->desc_lock);
815 }
816
817 static void sh_dmae_memcpy_issue_pending(struct dma_chan *chan)
818 {
819         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
820         sh_chan_xfer_ld_queue(sh_chan);
821 }
822
823 static enum dma_status sh_dmae_tx_status(struct dma_chan *chan,
824                                         dma_cookie_t cookie,
825                                         struct dma_tx_state *txstate)
826 {
827         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
828         enum dma_status status;
829
830         sh_dmae_chan_ld_cleanup(sh_chan, false);
831
832         spin_lock_bh(&sh_chan->desc_lock);
833
834         status = dma_cookie_status(chan, cookie, txstate);
835
836         /*
837          * If we don't find cookie on the queue, it has been aborted and we have
838          * to report error
839          */
840         if (status != DMA_SUCCESS) {
841                 struct sh_desc *desc;
842                 status = DMA_ERROR;
843                 list_for_each_entry(desc, &sh_chan->ld_queue, node)
844                         if (desc->cookie == cookie) {
845                                 status = DMA_IN_PROGRESS;
846                                 break;
847                         }
848         }
849
850         spin_unlock_bh(&sh_chan->desc_lock);
851
852         return status;
853 }
854
855 static irqreturn_t sh_dmae_interrupt(int irq, void *data)
856 {
857         irqreturn_t ret = IRQ_NONE;
858         struct sh_dmae_chan *sh_chan = data;
859         u32 chcr;
860
861         spin_lock(&sh_chan->desc_lock);
862
863         chcr = chcr_read(sh_chan);
864
865         if (chcr & CHCR_TE) {
866                 /* DMA stop */
867                 dmae_halt(sh_chan);
868
869                 ret = IRQ_HANDLED;
870                 tasklet_schedule(&sh_chan->tasklet);
871         }
872
873         spin_unlock(&sh_chan->desc_lock);
874
875         return ret;
876 }
877
878 /* Called from error IRQ or NMI */
879 static bool sh_dmae_reset(struct sh_dmae_device *shdev)
880 {
881         unsigned int handled = 0;
882         int i;
883
884         /* halt the dma controller */
885         sh_dmae_ctl_stop(shdev);
886
887         /* We cannot detect, which channel caused the error, have to reset all */
888         for (i = 0; i < SH_DMAC_MAX_CHANNELS; i++) {
889                 struct sh_dmae_chan *sh_chan = shdev->chan[i];
890                 struct sh_desc *desc;
891                 LIST_HEAD(dl);
892
893                 if (!sh_chan)
894                         continue;
895
896                 spin_lock(&sh_chan->desc_lock);
897
898                 /* Stop the channel */
899                 dmae_halt(sh_chan);
900
901                 list_splice_init(&sh_chan->ld_queue, &dl);
902
903                 spin_unlock(&sh_chan->desc_lock);
904
905                 /* Complete all  */
906                 list_for_each_entry(desc, &dl, node) {
907                         struct dma_async_tx_descriptor *tx = &desc->async_tx;
908                         desc->mark = DESC_IDLE;
909                         if (tx->callback)
910                                 tx->callback(tx->callback_param);
911                 }
912
913                 spin_lock(&sh_chan->desc_lock);
914                 list_splice(&dl, &sh_chan->ld_free);
915                 spin_unlock(&sh_chan->desc_lock);
916
917                 handled++;
918         }
919
920         sh_dmae_rst(shdev);
921
922         return !!handled;
923 }
924
925 static irqreturn_t sh_dmae_err(int irq, void *data)
926 {
927         struct sh_dmae_device *shdev = data;
928
929         if (!(dmaor_read(shdev) & DMAOR_AE))
930                 return IRQ_NONE;
931
932         sh_dmae_reset(data);
933         return IRQ_HANDLED;
934 }
935
936 static void dmae_do_tasklet(unsigned long data)
937 {
938         struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data;
939         struct sh_desc *desc;
940         u32 sar_buf = sh_dmae_readl(sh_chan, SAR);
941         u32 dar_buf = sh_dmae_readl(sh_chan, DAR);
942
943         spin_lock(&sh_chan->desc_lock);
944         list_for_each_entry(desc, &sh_chan->ld_queue, node) {
945                 if (desc->mark == DESC_SUBMITTED &&
946                     ((desc->direction == DMA_FROM_DEVICE &&
947                       (desc->hw.dar + desc->hw.tcr) == dar_buf) ||
948                      (desc->hw.sar + desc->hw.tcr) == sar_buf)) {
949                         dev_dbg(sh_chan->dev, "done #%d@%p dst %u\n",
950                                 desc->async_tx.cookie, &desc->async_tx,
951                                 desc->hw.dar);
952                         desc->mark = DESC_COMPLETED;
953                         break;
954                 }
955         }
956         spin_unlock(&sh_chan->desc_lock);
957
958         /* Next desc */
959         sh_chan_xfer_ld_queue(sh_chan);
960         sh_dmae_chan_ld_cleanup(sh_chan, false);
961 }
962
963 static bool sh_dmae_nmi_notify(struct sh_dmae_device *shdev)
964 {
965         /* Fast path out if NMIF is not asserted for this controller */
966         if ((dmaor_read(shdev) & DMAOR_NMIF) == 0)
967                 return false;
968
969         return sh_dmae_reset(shdev);
970 }
971
972 static int sh_dmae_nmi_handler(struct notifier_block *self,
973                                unsigned long cmd, void *data)
974 {
975         struct sh_dmae_device *shdev;
976         int ret = NOTIFY_DONE;
977         bool triggered;
978
979         /*
980          * Only concern ourselves with NMI events.
981          *
982          * Normally we would check the die chain value, but as this needs
983          * to be architecture independent, check for NMI context instead.
984          */
985         if (!in_nmi())
986                 return NOTIFY_DONE;
987
988         rcu_read_lock();
989         list_for_each_entry_rcu(shdev, &sh_dmae_devices, node) {
990                 /*
991                  * Only stop if one of the controllers has NMIF asserted,
992                  * we do not want to interfere with regular address error
993                  * handling or NMI events that don't concern the DMACs.
994                  */
995                 triggered = sh_dmae_nmi_notify(shdev);
996                 if (triggered == true)
997                         ret = NOTIFY_OK;
998         }
999         rcu_read_unlock();
1000
1001         return ret;
1002 }
1003
1004 static struct notifier_block sh_dmae_nmi_notifier __read_mostly = {
1005         .notifier_call  = sh_dmae_nmi_handler,
1006
1007         /* Run before NMI debug handler and KGDB */
1008         .priority       = 1,
1009 };
1010
1011 static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id,
1012                                         int irq, unsigned long flags)
1013 {
1014         int err;
1015         const struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id];
1016         struct platform_device *pdev = to_platform_device(shdev->common.dev);
1017         struct sh_dmae_chan *new_sh_chan;
1018
1019         /* alloc channel */
1020         new_sh_chan = kzalloc(sizeof(struct sh_dmae_chan), GFP_KERNEL);
1021         if (!new_sh_chan) {
1022                 dev_err(shdev->common.dev,
1023                         "No free memory for allocating dma channels!\n");
1024                 return -ENOMEM;
1025         }
1026
1027         /* copy struct dma_device */
1028         new_sh_chan->common.device = &shdev->common;
1029
1030         new_sh_chan->dev = shdev->common.dev;
1031         new_sh_chan->id = id;
1032         new_sh_chan->irq = irq;
1033         new_sh_chan->base = shdev->chan_reg + chan_pdata->offset / sizeof(u32);
1034
1035         /* Init DMA tasklet */
1036         tasklet_init(&new_sh_chan->tasklet, dmae_do_tasklet,
1037                         (unsigned long)new_sh_chan);
1038
1039         spin_lock_init(&new_sh_chan->desc_lock);
1040
1041         /* Init descripter manage list */
1042         INIT_LIST_HEAD(&new_sh_chan->ld_queue);
1043         INIT_LIST_HEAD(&new_sh_chan->ld_free);
1044
1045         /* Add the channel to DMA device channel list */
1046         list_add_tail(&new_sh_chan->common.device_node,
1047                         &shdev->common.channels);
1048         shdev->common.chancnt++;
1049
1050         if (pdev->id >= 0)
1051                 snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
1052                          "sh-dmae%d.%d", pdev->id, new_sh_chan->id);
1053         else
1054                 snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
1055                          "sh-dma%d", new_sh_chan->id);
1056
1057         /* set up channel irq */
1058         err = request_irq(irq, &sh_dmae_interrupt, flags,
1059                           new_sh_chan->dev_id, new_sh_chan);
1060         if (err) {
1061                 dev_err(shdev->common.dev, "DMA channel %d request_irq error "
1062                         "with return %d\n", id, err);
1063                 goto err_no_irq;
1064         }
1065
1066         shdev->chan[id] = new_sh_chan;
1067         return 0;
1068
1069 err_no_irq:
1070         /* remove from dmaengine device node */
1071         list_del(&new_sh_chan->common.device_node);
1072         kfree(new_sh_chan);
1073         return err;
1074 }
1075
1076 static void sh_dmae_chan_remove(struct sh_dmae_device *shdev)
1077 {
1078         int i;
1079
1080         for (i = shdev->common.chancnt - 1 ; i >= 0 ; i--) {
1081                 if (shdev->chan[i]) {
1082                         struct sh_dmae_chan *sh_chan = shdev->chan[i];
1083
1084                         free_irq(sh_chan->irq, sh_chan);
1085
1086                         list_del(&sh_chan->common.device_node);
1087                         kfree(sh_chan);
1088                         shdev->chan[i] = NULL;
1089                 }
1090         }
1091         shdev->common.chancnt = 0;
1092 }
1093
1094 static int __init sh_dmae_probe(struct platform_device *pdev)
1095 {
1096         struct sh_dmae_pdata *pdata = pdev->dev.platform_data;
1097         unsigned long irqflags = IRQF_DISABLED,
1098                 chan_flag[SH_DMAC_MAX_CHANNELS] = {};
1099         int errirq, chan_irq[SH_DMAC_MAX_CHANNELS];
1100         int err, i, irq_cnt = 0, irqres = 0, irq_cap = 0;
1101         struct sh_dmae_device *shdev;
1102         struct resource *chan, *dmars, *errirq_res, *chanirq_res;
1103
1104         /* get platform data */
1105         if (!pdata || !pdata->channel_num)
1106                 return -ENODEV;
1107
1108         chan = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1109         /* DMARS area is optional */
1110         dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1111         /*
1112          * IRQ resources:
1113          * 1. there always must be at least one IRQ IO-resource. On SH4 it is
1114          *    the error IRQ, in which case it is the only IRQ in this resource:
1115          *    start == end. If it is the only IRQ resource, all channels also
1116          *    use the same IRQ.
1117          * 2. DMA channel IRQ resources can be specified one per resource or in
1118          *    ranges (start != end)
1119          * 3. iff all events (channels and, optionally, error) on this
1120          *    controller use the same IRQ, only one IRQ resource can be
1121          *    specified, otherwise there must be one IRQ per channel, even if
1122          *    some of them are equal
1123          * 4. if all IRQs on this controller are equal or if some specific IRQs
1124          *    specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be
1125          *    requested with the IRQF_SHARED flag
1126          */
1127         errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1128         if (!chan || !errirq_res)
1129                 return -ENODEV;
1130
1131         if (!request_mem_region(chan->start, resource_size(chan), pdev->name)) {
1132                 dev_err(&pdev->dev, "DMAC register region already claimed\n");
1133                 return -EBUSY;
1134         }
1135
1136         if (dmars && !request_mem_region(dmars->start, resource_size(dmars), pdev->name)) {
1137                 dev_err(&pdev->dev, "DMAC DMARS region already claimed\n");
1138                 err = -EBUSY;
1139                 goto ermrdmars;
1140         }
1141
1142         err = -ENOMEM;
1143         shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL);
1144         if (!shdev) {
1145                 dev_err(&pdev->dev, "Not enough memory\n");
1146                 goto ealloc;
1147         }
1148
1149         shdev->chan_reg = ioremap(chan->start, resource_size(chan));
1150         if (!shdev->chan_reg)
1151                 goto emapchan;
1152         if (dmars) {
1153                 shdev->dmars = ioremap(dmars->start, resource_size(dmars));
1154                 if (!shdev->dmars)
1155                         goto emapdmars;
1156         }
1157
1158         /* platform data */
1159         shdev->pdata = pdata;
1160
1161         if (pdata->chcr_offset)
1162                 shdev->chcr_offset = pdata->chcr_offset;
1163         else
1164                 shdev->chcr_offset = CHCR;
1165
1166         if (pdata->chcr_ie_bit)
1167                 shdev->chcr_ie_bit = pdata->chcr_ie_bit;
1168         else
1169                 shdev->chcr_ie_bit = CHCR_IE;
1170
1171         platform_set_drvdata(pdev, shdev);
1172
1173         pm_runtime_enable(&pdev->dev);
1174         pm_runtime_get_sync(&pdev->dev);
1175
1176         spin_lock_irq(&sh_dmae_lock);
1177         list_add_tail_rcu(&shdev->node, &sh_dmae_devices);
1178         spin_unlock_irq(&sh_dmae_lock);
1179
1180         /* reset dma controller - only needed as a test */
1181         err = sh_dmae_rst(shdev);
1182         if (err)
1183                 goto rst_err;
1184
1185         INIT_LIST_HEAD(&shdev->common.channels);
1186
1187         dma_cap_set(DMA_MEMCPY, shdev->common.cap_mask);
1188         if (pdata->slave && pdata->slave_num)
1189                 dma_cap_set(DMA_SLAVE, shdev->common.cap_mask);
1190
1191         shdev->common.device_alloc_chan_resources
1192                 = sh_dmae_alloc_chan_resources;
1193         shdev->common.device_free_chan_resources = sh_dmae_free_chan_resources;
1194         shdev->common.device_prep_dma_memcpy = sh_dmae_prep_memcpy;
1195         shdev->common.device_tx_status = sh_dmae_tx_status;
1196         shdev->common.device_issue_pending = sh_dmae_memcpy_issue_pending;
1197
1198         /* Compulsory for DMA_SLAVE fields */
1199         shdev->common.device_prep_slave_sg = sh_dmae_prep_slave_sg;
1200         shdev->common.device_control = sh_dmae_control;
1201
1202         shdev->common.dev = &pdev->dev;
1203         /* Default transfer size of 32 bytes requires 32-byte alignment */
1204         shdev->common.copy_align = LOG2_DEFAULT_XFER_SIZE;
1205
1206 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
1207         chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1208
1209         if (!chanirq_res)
1210                 chanirq_res = errirq_res;
1211         else
1212                 irqres++;
1213
1214         if (chanirq_res == errirq_res ||
1215             (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE)
1216                 irqflags = IRQF_SHARED;
1217
1218         errirq = errirq_res->start;
1219
1220         err = request_irq(errirq, sh_dmae_err, irqflags,
1221                           "DMAC Address Error", shdev);
1222         if (err) {
1223                 dev_err(&pdev->dev,
1224                         "DMA failed requesting irq #%d, error %d\n",
1225                         errirq, err);
1226                 goto eirq_err;
1227         }
1228
1229 #else
1230         chanirq_res = errirq_res;
1231 #endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */
1232
1233         if (chanirq_res->start == chanirq_res->end &&
1234             !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
1235                 /* Special case - all multiplexed */
1236                 for (; irq_cnt < pdata->channel_num; irq_cnt++) {
1237                         if (irq_cnt < SH_DMAC_MAX_CHANNELS) {
1238                                 chan_irq[irq_cnt] = chanirq_res->start;
1239                                 chan_flag[irq_cnt] = IRQF_SHARED;
1240                         } else {
1241                                 irq_cap = 1;
1242                                 break;
1243                         }
1244                 }
1245         } else {
1246                 do {
1247                         for (i = chanirq_res->start; i <= chanirq_res->end; i++) {
1248                                 if (irq_cnt >= SH_DMAC_MAX_CHANNELS) {
1249                                         irq_cap = 1;
1250                                         break;
1251                                 }
1252
1253                                 if ((errirq_res->flags & IORESOURCE_BITS) ==
1254                                     IORESOURCE_IRQ_SHAREABLE)
1255                                         chan_flag[irq_cnt] = IRQF_SHARED;
1256                                 else
1257                                         chan_flag[irq_cnt] = IRQF_DISABLED;
1258                                 dev_dbg(&pdev->dev,
1259                                         "Found IRQ %d for channel %d\n",
1260                                         i, irq_cnt);
1261                                 chan_irq[irq_cnt++] = i;
1262                         }
1263
1264                         if (irq_cnt >= SH_DMAC_MAX_CHANNELS)
1265                                 break;
1266
1267                         chanirq_res = platform_get_resource(pdev,
1268                                                 IORESOURCE_IRQ, ++irqres);
1269                 } while (irq_cnt < pdata->channel_num && chanirq_res);
1270         }
1271
1272         /* Create DMA Channel */
1273         for (i = 0; i < irq_cnt; i++) {
1274                 err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]);
1275                 if (err)
1276                         goto chan_probe_err;
1277         }
1278
1279         if (irq_cap)
1280                 dev_notice(&pdev->dev, "Attempting to register %d DMA "
1281                            "channels when a maximum of %d are supported.\n",
1282                            pdata->channel_num, SH_DMAC_MAX_CHANNELS);
1283
1284         pm_runtime_put(&pdev->dev);
1285
1286         dma_async_device_register(&shdev->common);
1287
1288         return err;
1289
1290 chan_probe_err:
1291         sh_dmae_chan_remove(shdev);
1292
1293 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
1294         free_irq(errirq, shdev);
1295 eirq_err:
1296 #endif
1297 rst_err:
1298         spin_lock_irq(&sh_dmae_lock);
1299         list_del_rcu(&shdev->node);
1300         spin_unlock_irq(&sh_dmae_lock);
1301
1302         pm_runtime_put(&pdev->dev);
1303         pm_runtime_disable(&pdev->dev);
1304
1305         if (dmars)
1306                 iounmap(shdev->dmars);
1307
1308         platform_set_drvdata(pdev, NULL);
1309 emapdmars:
1310         iounmap(shdev->chan_reg);
1311         synchronize_rcu();
1312 emapchan:
1313         kfree(shdev);
1314 ealloc:
1315         if (dmars)
1316                 release_mem_region(dmars->start, resource_size(dmars));
1317 ermrdmars:
1318         release_mem_region(chan->start, resource_size(chan));
1319
1320         return err;
1321 }
1322
1323 static int __exit sh_dmae_remove(struct platform_device *pdev)
1324 {
1325         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
1326         struct resource *res;
1327         int errirq = platform_get_irq(pdev, 0);
1328
1329         dma_async_device_unregister(&shdev->common);
1330
1331         if (errirq > 0)
1332                 free_irq(errirq, shdev);
1333
1334         spin_lock_irq(&sh_dmae_lock);
1335         list_del_rcu(&shdev->node);
1336         spin_unlock_irq(&sh_dmae_lock);
1337
1338         /* channel data remove */
1339         sh_dmae_chan_remove(shdev);
1340
1341         pm_runtime_disable(&pdev->dev);
1342
1343         if (shdev->dmars)
1344                 iounmap(shdev->dmars);
1345         iounmap(shdev->chan_reg);
1346
1347         platform_set_drvdata(pdev, NULL);
1348
1349         synchronize_rcu();
1350         kfree(shdev);
1351
1352         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1353         if (res)
1354                 release_mem_region(res->start, resource_size(res));
1355         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1356         if (res)
1357                 release_mem_region(res->start, resource_size(res));
1358
1359         return 0;
1360 }
1361
1362 static void sh_dmae_shutdown(struct platform_device *pdev)
1363 {
1364         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
1365         sh_dmae_ctl_stop(shdev);
1366 }
1367
1368 static int sh_dmae_runtime_suspend(struct device *dev)
1369 {
1370         return 0;
1371 }
1372
1373 static int sh_dmae_runtime_resume(struct device *dev)
1374 {
1375         struct sh_dmae_device *shdev = dev_get_drvdata(dev);
1376
1377         return sh_dmae_rst(shdev);
1378 }
1379
1380 #ifdef CONFIG_PM
1381 static int sh_dmae_suspend(struct device *dev)
1382 {
1383         struct sh_dmae_device *shdev = dev_get_drvdata(dev);
1384         int i;
1385
1386         for (i = 0; i < shdev->pdata->channel_num; i++) {
1387                 struct sh_dmae_chan *sh_chan = shdev->chan[i];
1388                 if (sh_chan->descs_allocated)
1389                         sh_chan->pm_error = pm_runtime_put_sync(dev);
1390         }
1391
1392         return 0;
1393 }
1394
1395 static int sh_dmae_resume(struct device *dev)
1396 {
1397         struct sh_dmae_device *shdev = dev_get_drvdata(dev);
1398         int i;
1399
1400         for (i = 0; i < shdev->pdata->channel_num; i++) {
1401                 struct sh_dmae_chan *sh_chan = shdev->chan[i];
1402                 struct sh_dmae_slave *param = sh_chan->common.private;
1403
1404                 if (!sh_chan->descs_allocated)
1405                         continue;
1406
1407                 if (!sh_chan->pm_error)
1408                         pm_runtime_get_sync(dev);
1409
1410                 if (param) {
1411                         const struct sh_dmae_slave_config *cfg = param->config;
1412                         dmae_set_dmars(sh_chan, cfg->mid_rid);
1413                         dmae_set_chcr(sh_chan, cfg->chcr);
1414                 } else {
1415                         dmae_init(sh_chan);
1416                 }
1417         }
1418
1419         return 0;
1420 }
1421 #else
1422 #define sh_dmae_suspend NULL
1423 #define sh_dmae_resume NULL
1424 #endif
1425
1426 const struct dev_pm_ops sh_dmae_pm = {
1427         .suspend                = sh_dmae_suspend,
1428         .resume                 = sh_dmae_resume,
1429         .runtime_suspend        = sh_dmae_runtime_suspend,
1430         .runtime_resume         = sh_dmae_runtime_resume,
1431 };
1432
1433 static struct platform_driver sh_dmae_driver = {
1434         .remove         = __exit_p(sh_dmae_remove),
1435         .shutdown       = sh_dmae_shutdown,
1436         .driver = {
1437                 .owner  = THIS_MODULE,
1438                 .name   = "sh-dma-engine",
1439                 .pm     = &sh_dmae_pm,
1440         },
1441 };
1442
1443 static int __init sh_dmae_init(void)
1444 {
1445         /* Wire up NMI handling */
1446         int err = register_die_notifier(&sh_dmae_nmi_notifier);
1447         if (err)
1448                 return err;
1449
1450         return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe);
1451 }
1452 module_init(sh_dmae_init);
1453
1454 static void __exit sh_dmae_exit(void)
1455 {
1456         platform_driver_unregister(&sh_dmae_driver);
1457
1458         unregister_die_notifier(&sh_dmae_nmi_notifier);
1459 }
1460 module_exit(sh_dmae_exit);
1461
1462 MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>");
1463 MODULE_DESCRIPTION("Renesas SH DMA Engine driver");
1464 MODULE_LICENSE("GPL");
1465 MODULE_ALIAS("platform:sh-dma-engine");