pch_dma: Fix DMA setting issue
[linux-2.6.git] / drivers / dma / pch_dma.c
1 /*
2  * Topcliff PCH DMA controller driver
3  * Copyright (c) 2010 Intel Corporation
4  * Copyright (C) 2011 OKI SEMICONDUCTOR CO., LTD.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18  */
19
20 #include <linux/dmaengine.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/init.h>
23 #include <linux/pci.h>
24 #include <linux/interrupt.h>
25 #include <linux/module.h>
26 #include <linux/pch_dma.h>
27
28 #define DRV_NAME "pch-dma"
29
30 #define DMA_CTL0_DISABLE                0x0
31 #define DMA_CTL0_SG                     0x1
32 #define DMA_CTL0_ONESHOT                0x2
33 #define DMA_CTL0_MODE_MASK_BITS         0x3
34 #define DMA_CTL0_DIR_SHIFT_BITS         2
35 #define DMA_CTL0_BITS_PER_CH            4
36
37 #define DMA_CTL2_START_SHIFT_BITS       8
38 #define DMA_CTL2_IRQ_ENABLE_MASK        ((1UL << DMA_CTL2_START_SHIFT_BITS) - 1)
39
40 #define DMA_STATUS_IDLE                 0x0
41 #define DMA_STATUS_DESC_READ            0x1
42 #define DMA_STATUS_WAIT                 0x2
43 #define DMA_STATUS_ACCESS               0x3
44 #define DMA_STATUS_BITS_PER_CH          2
45 #define DMA_STATUS_MASK_BITS            0x3
46 #define DMA_STATUS_SHIFT_BITS           16
47 #define DMA_STATUS_IRQ(x)               (0x1 << (x))
48 #define DMA_STATUS_ERR(x)               (0x1 << ((x) + 8))
49
50 #define DMA_DESC_WIDTH_SHIFT_BITS       12
51 #define DMA_DESC_WIDTH_1_BYTE           (0x3 << DMA_DESC_WIDTH_SHIFT_BITS)
52 #define DMA_DESC_WIDTH_2_BYTES          (0x2 << DMA_DESC_WIDTH_SHIFT_BITS)
53 #define DMA_DESC_WIDTH_4_BYTES          (0x0 << DMA_DESC_WIDTH_SHIFT_BITS)
54 #define DMA_DESC_MAX_COUNT_1_BYTE       0x3FF
55 #define DMA_DESC_MAX_COUNT_2_BYTES      0x3FF
56 #define DMA_DESC_MAX_COUNT_4_BYTES      0x7FF
57 #define DMA_DESC_END_WITHOUT_IRQ        0x0
58 #define DMA_DESC_END_WITH_IRQ           0x1
59 #define DMA_DESC_FOLLOW_WITHOUT_IRQ     0x2
60 #define DMA_DESC_FOLLOW_WITH_IRQ        0x3
61
62 #define MAX_CHAN_NR                     8
63
64 static unsigned int init_nr_desc_per_channel = 64;
65 module_param(init_nr_desc_per_channel, uint, 0644);
66 MODULE_PARM_DESC(init_nr_desc_per_channel,
67                  "initial descriptors per channel (default: 64)");
68
69 struct pch_dma_desc_regs {
70         u32     dev_addr;
71         u32     mem_addr;
72         u32     size;
73         u32     next;
74 };
75
76 struct pch_dma_regs {
77         u32     dma_ctl0;
78         u32     dma_ctl1;
79         u32     dma_ctl2;
80         u32     reserved1;
81         u32     dma_sts0;
82         u32     dma_sts1;
83         u32     reserved2;
84         u32     reserved3;
85         struct pch_dma_desc_regs desc[MAX_CHAN_NR];
86 };
87
88 struct pch_dma_desc {
89         struct pch_dma_desc_regs regs;
90         struct dma_async_tx_descriptor txd;
91         struct list_head        desc_node;
92         struct list_head        tx_list;
93 };
94
95 struct pch_dma_chan {
96         struct dma_chan         chan;
97         void __iomem *membase;
98         enum dma_data_direction dir;
99         struct tasklet_struct   tasklet;
100         unsigned long           err_status;
101
102         spinlock_t              lock;
103
104         dma_cookie_t            completed_cookie;
105         struct list_head        active_list;
106         struct list_head        queue;
107         struct list_head        free_list;
108         unsigned int            descs_allocated;
109 };
110
111 #define PDC_DEV_ADDR    0x00
112 #define PDC_MEM_ADDR    0x04
113 #define PDC_SIZE        0x08
114 #define PDC_NEXT        0x0C
115
116 #define channel_readl(pdc, name) \
117         readl((pdc)->membase + PDC_##name)
118 #define channel_writel(pdc, name, val) \
119         writel((val), (pdc)->membase + PDC_##name)
120
121 struct pch_dma {
122         struct dma_device       dma;
123         void __iomem *membase;
124         struct pci_pool         *pool;
125         struct pch_dma_regs     regs;
126         struct pch_dma_desc_regs ch_regs[MAX_CHAN_NR];
127         struct pch_dma_chan     channels[MAX_CHAN_NR];
128 };
129
130 #define PCH_DMA_CTL0    0x00
131 #define PCH_DMA_CTL1    0x04
132 #define PCH_DMA_CTL2    0x08
133 #define PCH_DMA_STS0    0x10
134 #define PCH_DMA_STS1    0x14
135
136 #define dma_readl(pd, name) \
137         readl((pd)->membase + PCH_DMA_##name)
138 #define dma_writel(pd, name, val) \
139         writel((val), (pd)->membase + PCH_DMA_##name)
140
141 static inline
142 struct pch_dma_desc *to_pd_desc(struct dma_async_tx_descriptor *txd)
143 {
144         return container_of(txd, struct pch_dma_desc, txd);
145 }
146
147 static inline struct pch_dma_chan *to_pd_chan(struct dma_chan *chan)
148 {
149         return container_of(chan, struct pch_dma_chan, chan);
150 }
151
152 static inline struct pch_dma *to_pd(struct dma_device *ddev)
153 {
154         return container_of(ddev, struct pch_dma, dma);
155 }
156
157 static inline struct device *chan2dev(struct dma_chan *chan)
158 {
159         return &chan->dev->device;
160 }
161
162 static inline struct device *chan2parent(struct dma_chan *chan)
163 {
164         return chan->dev->device.parent;
165 }
166
167 static inline
168 struct pch_dma_desc *pdc_first_active(struct pch_dma_chan *pd_chan)
169 {
170         return list_first_entry(&pd_chan->active_list,
171                                 struct pch_dma_desc, desc_node);
172 }
173
174 static inline
175 struct pch_dma_desc *pdc_first_queued(struct pch_dma_chan *pd_chan)
176 {
177         return list_first_entry(&pd_chan->queue,
178                                 struct pch_dma_desc, desc_node);
179 }
180
181 static void pdc_enable_irq(struct dma_chan *chan, int enable)
182 {
183         struct pch_dma *pd = to_pd(chan->device);
184         u32 val;
185
186         val = dma_readl(pd, CTL2);
187
188         if (enable)
189                 val |= 0x1 << chan->chan_id;
190         else
191                 val &= ~(0x1 << chan->chan_id);
192
193         dma_writel(pd, CTL2, val);
194
195         dev_dbg(chan2dev(chan), "pdc_enable_irq: chan %d -> %x\n",
196                 chan->chan_id, val);
197 }
198
199 static void pdc_set_dir(struct dma_chan *chan)
200 {
201         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
202         struct pch_dma *pd = to_pd(chan->device);
203         u32 val;
204
205         val = dma_readl(pd, CTL0);
206
207         if (pd_chan->dir == DMA_TO_DEVICE)
208                 val |= 0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id +
209                                DMA_CTL0_DIR_SHIFT_BITS);
210         else
211                 val &= ~(0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id +
212                                  DMA_CTL0_DIR_SHIFT_BITS));
213
214         dma_writel(pd, CTL0, val);
215
216         dev_dbg(chan2dev(chan), "pdc_set_dir: chan %d -> %x\n",
217                 chan->chan_id, val);
218 }
219
220 static void pdc_set_mode(struct dma_chan *chan, u32 mode)
221 {
222         struct pch_dma *pd = to_pd(chan->device);
223         u32 val;
224
225         val = dma_readl(pd, CTL0);
226
227         val &= ~(DMA_CTL0_MODE_MASK_BITS <<
228                 (DMA_CTL0_BITS_PER_CH * chan->chan_id));
229         val |= mode << (DMA_CTL0_BITS_PER_CH * chan->chan_id);
230
231         dma_writel(pd, CTL0, val);
232
233         dev_dbg(chan2dev(chan), "pdc_set_mode: chan %d -> %x\n",
234                 chan->chan_id, val);
235 }
236
237 static u32 pdc_get_status(struct pch_dma_chan *pd_chan)
238 {
239         struct pch_dma *pd = to_pd(pd_chan->chan.device);
240         u32 val;
241
242         val = dma_readl(pd, STS0);
243         return DMA_STATUS_MASK_BITS & (val >> (DMA_STATUS_SHIFT_BITS +
244                         DMA_STATUS_BITS_PER_CH * pd_chan->chan.chan_id));
245 }
246
247 static bool pdc_is_idle(struct pch_dma_chan *pd_chan)
248 {
249         if (pdc_get_status(pd_chan) == DMA_STATUS_IDLE)
250                 return true;
251         else
252                 return false;
253 }
254
255 static void pdc_dostart(struct pch_dma_chan *pd_chan, struct pch_dma_desc* desc)
256 {
257         if (!pdc_is_idle(pd_chan)) {
258                 dev_err(chan2dev(&pd_chan->chan),
259                         "BUG: Attempt to start non-idle channel\n");
260                 return;
261         }
262
263         dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> dev_addr: %x\n",
264                 pd_chan->chan.chan_id, desc->regs.dev_addr);
265         dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> mem_addr: %x\n",
266                 pd_chan->chan.chan_id, desc->regs.mem_addr);
267         dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> size: %x\n",
268                 pd_chan->chan.chan_id, desc->regs.size);
269         dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> next: %x\n",
270                 pd_chan->chan.chan_id, desc->regs.next);
271
272         if (list_empty(&desc->tx_list)) {
273                 channel_writel(pd_chan, DEV_ADDR, desc->regs.dev_addr);
274                 channel_writel(pd_chan, MEM_ADDR, desc->regs.mem_addr);
275                 channel_writel(pd_chan, SIZE, desc->regs.size);
276                 channel_writel(pd_chan, NEXT, desc->regs.next);
277                 pdc_set_mode(&pd_chan->chan, DMA_CTL0_ONESHOT);
278         } else {
279                 channel_writel(pd_chan, NEXT, desc->txd.phys);
280                 pdc_set_mode(&pd_chan->chan, DMA_CTL0_SG);
281         }
282 }
283
284 static void pdc_chain_complete(struct pch_dma_chan *pd_chan,
285                                struct pch_dma_desc *desc)
286 {
287         struct dma_async_tx_descriptor *txd = &desc->txd;
288         dma_async_tx_callback callback = txd->callback;
289         void *param = txd->callback_param;
290
291         list_splice_init(&desc->tx_list, &pd_chan->free_list);
292         list_move(&desc->desc_node, &pd_chan->free_list);
293
294         if (callback)
295                 callback(param);
296 }
297
298 static void pdc_complete_all(struct pch_dma_chan *pd_chan)
299 {
300         struct pch_dma_desc *desc, *_d;
301         LIST_HEAD(list);
302
303         BUG_ON(!pdc_is_idle(pd_chan));
304
305         if (!list_empty(&pd_chan->queue))
306                 pdc_dostart(pd_chan, pdc_first_queued(pd_chan));
307
308         list_splice_init(&pd_chan->active_list, &list);
309         list_splice_init(&pd_chan->queue, &pd_chan->active_list);
310
311         list_for_each_entry_safe(desc, _d, &list, desc_node)
312                 pdc_chain_complete(pd_chan, desc);
313 }
314
315 static void pdc_handle_error(struct pch_dma_chan *pd_chan)
316 {
317         struct pch_dma_desc *bad_desc;
318
319         bad_desc = pdc_first_active(pd_chan);
320         list_del(&bad_desc->desc_node);
321
322         list_splice_init(&pd_chan->queue, pd_chan->active_list.prev);
323
324         if (!list_empty(&pd_chan->active_list))
325                 pdc_dostart(pd_chan, pdc_first_active(pd_chan));
326
327         dev_crit(chan2dev(&pd_chan->chan), "Bad descriptor submitted\n");
328         dev_crit(chan2dev(&pd_chan->chan), "descriptor cookie: %d\n",
329                  bad_desc->txd.cookie);
330
331         pdc_chain_complete(pd_chan, bad_desc);
332 }
333
334 static void pdc_advance_work(struct pch_dma_chan *pd_chan)
335 {
336         if (list_empty(&pd_chan->active_list) ||
337                 list_is_singular(&pd_chan->active_list)) {
338                 pdc_complete_all(pd_chan);
339         } else {
340                 pdc_chain_complete(pd_chan, pdc_first_active(pd_chan));
341                 pdc_dostart(pd_chan, pdc_first_active(pd_chan));
342         }
343 }
344
345 static dma_cookie_t pdc_assign_cookie(struct pch_dma_chan *pd_chan,
346                                       struct pch_dma_desc *desc)
347 {
348         dma_cookie_t cookie = pd_chan->chan.cookie;
349
350         if (++cookie < 0)
351                 cookie = 1;
352
353         pd_chan->chan.cookie = cookie;
354         desc->txd.cookie = cookie;
355
356         return cookie;
357 }
358
359 static dma_cookie_t pd_tx_submit(struct dma_async_tx_descriptor *txd)
360 {
361         struct pch_dma_desc *desc = to_pd_desc(txd);
362         struct pch_dma_chan *pd_chan = to_pd_chan(txd->chan);
363         dma_cookie_t cookie;
364
365         spin_lock(&pd_chan->lock);
366         cookie = pdc_assign_cookie(pd_chan, desc);
367
368         if (list_empty(&pd_chan->active_list)) {
369                 list_add_tail(&desc->desc_node, &pd_chan->active_list);
370                 pdc_dostart(pd_chan, desc);
371         } else {
372                 list_add_tail(&desc->desc_node, &pd_chan->queue);
373         }
374
375         spin_unlock(&pd_chan->lock);
376         return 0;
377 }
378
379 static struct pch_dma_desc *pdc_alloc_desc(struct dma_chan *chan, gfp_t flags)
380 {
381         struct pch_dma_desc *desc = NULL;
382         struct pch_dma *pd = to_pd(chan->device);
383         dma_addr_t addr;
384
385         desc = pci_pool_alloc(pd->pool, flags, &addr);
386         if (desc) {
387                 memset(desc, 0, sizeof(struct pch_dma_desc));
388                 INIT_LIST_HEAD(&desc->tx_list);
389                 dma_async_tx_descriptor_init(&desc->txd, chan);
390                 desc->txd.tx_submit = pd_tx_submit;
391                 desc->txd.flags = DMA_CTRL_ACK;
392                 desc->txd.phys = addr;
393         }
394
395         return desc;
396 }
397
398 static struct pch_dma_desc *pdc_desc_get(struct pch_dma_chan *pd_chan)
399 {
400         struct pch_dma_desc *desc, *_d;
401         struct pch_dma_desc *ret = NULL;
402         int i = 0;
403
404         spin_lock(&pd_chan->lock);
405         list_for_each_entry_safe(desc, _d, &pd_chan->free_list, desc_node) {
406                 i++;
407                 if (async_tx_test_ack(&desc->txd)) {
408                         list_del(&desc->desc_node);
409                         ret = desc;
410                         break;
411                 }
412                 dev_dbg(chan2dev(&pd_chan->chan), "desc %p not ACKed\n", desc);
413         }
414         spin_unlock(&pd_chan->lock);
415         dev_dbg(chan2dev(&pd_chan->chan), "scanned %d descriptors\n", i);
416
417         if (!ret) {
418                 ret = pdc_alloc_desc(&pd_chan->chan, GFP_NOIO);
419                 if (ret) {
420                         spin_lock(&pd_chan->lock);
421                         pd_chan->descs_allocated++;
422                         spin_unlock(&pd_chan->lock);
423                 } else {
424                         dev_err(chan2dev(&pd_chan->chan),
425                                 "failed to alloc desc\n");
426                 }
427         }
428
429         return ret;
430 }
431
432 static void pdc_desc_put(struct pch_dma_chan *pd_chan,
433                          struct pch_dma_desc *desc)
434 {
435         if (desc) {
436                 spin_lock(&pd_chan->lock);
437                 list_splice_init(&desc->tx_list, &pd_chan->free_list);
438                 list_add(&desc->desc_node, &pd_chan->free_list);
439                 spin_unlock(&pd_chan->lock);
440         }
441 }
442
443 static int pd_alloc_chan_resources(struct dma_chan *chan)
444 {
445         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
446         struct pch_dma_desc *desc;
447         LIST_HEAD(tmp_list);
448         int i;
449
450         if (!pdc_is_idle(pd_chan)) {
451                 dev_dbg(chan2dev(chan), "DMA channel not idle ?\n");
452                 return -EIO;
453         }
454
455         if (!list_empty(&pd_chan->free_list))
456                 return pd_chan->descs_allocated;
457
458         for (i = 0; i < init_nr_desc_per_channel; i++) {
459                 desc = pdc_alloc_desc(chan, GFP_KERNEL);
460
461                 if (!desc) {
462                         dev_warn(chan2dev(chan),
463                                 "Only allocated %d initial descriptors\n", i);
464                         break;
465                 }
466
467                 list_add_tail(&desc->desc_node, &tmp_list);
468         }
469
470         spin_lock_bh(&pd_chan->lock);
471         list_splice(&tmp_list, &pd_chan->free_list);
472         pd_chan->descs_allocated = i;
473         pd_chan->completed_cookie = chan->cookie = 1;
474         spin_unlock_bh(&pd_chan->lock);
475
476         pdc_enable_irq(chan, 1);
477
478         return pd_chan->descs_allocated;
479 }
480
481 static void pd_free_chan_resources(struct dma_chan *chan)
482 {
483         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
484         struct pch_dma *pd = to_pd(chan->device);
485         struct pch_dma_desc *desc, *_d;
486         LIST_HEAD(tmp_list);
487
488         BUG_ON(!pdc_is_idle(pd_chan));
489         BUG_ON(!list_empty(&pd_chan->active_list));
490         BUG_ON(!list_empty(&pd_chan->queue));
491
492         spin_lock_bh(&pd_chan->lock);
493         list_splice_init(&pd_chan->free_list, &tmp_list);
494         pd_chan->descs_allocated = 0;
495         spin_unlock_bh(&pd_chan->lock);
496
497         list_for_each_entry_safe(desc, _d, &tmp_list, desc_node)
498                 pci_pool_free(pd->pool, desc, desc->txd.phys);
499
500         pdc_enable_irq(chan, 0);
501 }
502
503 static enum dma_status pd_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
504                                     struct dma_tx_state *txstate)
505 {
506         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
507         dma_cookie_t last_used;
508         dma_cookie_t last_completed;
509         int ret;
510
511         spin_lock_bh(&pd_chan->lock);
512         last_completed = pd_chan->completed_cookie;
513         last_used = chan->cookie;
514         spin_unlock_bh(&pd_chan->lock);
515
516         ret = dma_async_is_complete(cookie, last_completed, last_used);
517
518         dma_set_tx_state(txstate, last_completed, last_used, 0);
519
520         return ret;
521 }
522
523 static void pd_issue_pending(struct dma_chan *chan)
524 {
525         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
526
527         if (pdc_is_idle(pd_chan)) {
528                 spin_lock(&pd_chan->lock);
529                 pdc_advance_work(pd_chan);
530                 spin_unlock(&pd_chan->lock);
531         }
532 }
533
534 static struct dma_async_tx_descriptor *pd_prep_slave_sg(struct dma_chan *chan,
535                         struct scatterlist *sgl, unsigned int sg_len,
536                         enum dma_data_direction direction, unsigned long flags)
537 {
538         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
539         struct pch_dma_slave *pd_slave = chan->private;
540         struct pch_dma_desc *first = NULL;
541         struct pch_dma_desc *prev = NULL;
542         struct pch_dma_desc *desc = NULL;
543         struct scatterlist *sg;
544         dma_addr_t reg;
545         int i;
546
547         if (unlikely(!sg_len)) {
548                 dev_info(chan2dev(chan), "prep_slave_sg: length is zero!\n");
549                 return NULL;
550         }
551
552         if (direction == DMA_FROM_DEVICE)
553                 reg = pd_slave->rx_reg;
554         else if (direction == DMA_TO_DEVICE)
555                 reg = pd_slave->tx_reg;
556         else
557                 return NULL;
558
559         pd_chan->dir = direction;
560         pdc_set_dir(chan);
561
562         for_each_sg(sgl, sg, sg_len, i) {
563                 desc = pdc_desc_get(pd_chan);
564
565                 if (!desc)
566                         goto err_desc_get;
567
568                 desc->regs.dev_addr = reg;
569                 desc->regs.mem_addr = sg_phys(sg);
570                 desc->regs.size = sg_dma_len(sg);
571                 desc->regs.next = DMA_DESC_FOLLOW_WITHOUT_IRQ;
572
573                 switch (pd_slave->width) {
574                 case PCH_DMA_WIDTH_1_BYTE:
575                         if (desc->regs.size > DMA_DESC_MAX_COUNT_1_BYTE)
576                                 goto err_desc_get;
577                         desc->regs.size |= DMA_DESC_WIDTH_1_BYTE;
578                         break;
579                 case PCH_DMA_WIDTH_2_BYTES:
580                         if (desc->regs.size > DMA_DESC_MAX_COUNT_2_BYTES)
581                                 goto err_desc_get;
582                         desc->regs.size |= DMA_DESC_WIDTH_2_BYTES;
583                         break;
584                 case PCH_DMA_WIDTH_4_BYTES:
585                         if (desc->regs.size > DMA_DESC_MAX_COUNT_4_BYTES)
586                                 goto err_desc_get;
587                         desc->regs.size |= DMA_DESC_WIDTH_4_BYTES;
588                         break;
589                 default:
590                         goto err_desc_get;
591                 }
592
593                 if (!first) {
594                         first = desc;
595                 } else {
596                         prev->regs.next |= desc->txd.phys;
597                         list_add_tail(&desc->desc_node, &first->tx_list);
598                 }
599
600                 prev = desc;
601         }
602
603         if (flags & DMA_PREP_INTERRUPT)
604                 desc->regs.next = DMA_DESC_END_WITH_IRQ;
605         else
606                 desc->regs.next = DMA_DESC_END_WITHOUT_IRQ;
607
608         first->txd.cookie = -EBUSY;
609         desc->txd.flags = flags;
610
611         return &first->txd;
612
613 err_desc_get:
614         dev_err(chan2dev(chan), "failed to get desc or wrong parameters\n");
615         pdc_desc_put(pd_chan, first);
616         return NULL;
617 }
618
619 static int pd_device_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
620                              unsigned long arg)
621 {
622         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
623         struct pch_dma_desc *desc, *_d;
624         LIST_HEAD(list);
625
626         if (cmd != DMA_TERMINATE_ALL)
627                 return -ENXIO;
628
629         spin_lock_bh(&pd_chan->lock);
630
631         pdc_set_mode(&pd_chan->chan, DMA_CTL0_DISABLE);
632
633         list_splice_init(&pd_chan->active_list, &list);
634         list_splice_init(&pd_chan->queue, &list);
635
636         list_for_each_entry_safe(desc, _d, &list, desc_node)
637                 pdc_chain_complete(pd_chan, desc);
638
639         spin_unlock_bh(&pd_chan->lock);
640
641         return 0;
642 }
643
644 static void pdc_tasklet(unsigned long data)
645 {
646         struct pch_dma_chan *pd_chan = (struct pch_dma_chan *)data;
647         unsigned long flags;
648
649         if (!pdc_is_idle(pd_chan)) {
650                 dev_err(chan2dev(&pd_chan->chan),
651                         "BUG: handle non-idle channel in tasklet\n");
652                 return;
653         }
654
655         spin_lock_irqsave(&pd_chan->lock, flags);
656         if (test_and_clear_bit(0, &pd_chan->err_status))
657                 pdc_handle_error(pd_chan);
658         else
659                 pdc_advance_work(pd_chan);
660         spin_unlock_irqrestore(&pd_chan->lock, flags);
661 }
662
663 static irqreturn_t pd_irq(int irq, void *devid)
664 {
665         struct pch_dma *pd = (struct pch_dma *)devid;
666         struct pch_dma_chan *pd_chan;
667         u32 sts0;
668         int i;
669         int ret = IRQ_NONE;
670
671         sts0 = dma_readl(pd, STS0);
672
673         dev_dbg(pd->dma.dev, "pd_irq sts0: %x\n", sts0);
674
675         for (i = 0; i < pd->dma.chancnt; i++) {
676                 pd_chan = &pd->channels[i];
677
678                 if (sts0 & DMA_STATUS_IRQ(i)) {
679                         if (sts0 & DMA_STATUS_ERR(i))
680                                 set_bit(0, &pd_chan->err_status);
681
682                         tasklet_schedule(&pd_chan->tasklet);
683                         ret = IRQ_HANDLED;
684                 }
685
686         }
687
688         /* clear interrupt bits in status register */
689         dma_writel(pd, STS0, sts0);
690
691         return ret;
692 }
693
694 #ifdef  CONFIG_PM
695 static void pch_dma_save_regs(struct pch_dma *pd)
696 {
697         struct pch_dma_chan *pd_chan;
698         struct dma_chan *chan, *_c;
699         int i = 0;
700
701         pd->regs.dma_ctl0 = dma_readl(pd, CTL0);
702         pd->regs.dma_ctl1 = dma_readl(pd, CTL1);
703         pd->regs.dma_ctl2 = dma_readl(pd, CTL2);
704
705         list_for_each_entry_safe(chan, _c, &pd->dma.channels, device_node) {
706                 pd_chan = to_pd_chan(chan);
707
708                 pd->ch_regs[i].dev_addr = channel_readl(pd_chan, DEV_ADDR);
709                 pd->ch_regs[i].mem_addr = channel_readl(pd_chan, MEM_ADDR);
710                 pd->ch_regs[i].size = channel_readl(pd_chan, SIZE);
711                 pd->ch_regs[i].next = channel_readl(pd_chan, NEXT);
712
713                 i++;
714         }
715 }
716
717 static void pch_dma_restore_regs(struct pch_dma *pd)
718 {
719         struct pch_dma_chan *pd_chan;
720         struct dma_chan *chan, *_c;
721         int i = 0;
722
723         dma_writel(pd, CTL0, pd->regs.dma_ctl0);
724         dma_writel(pd, CTL1, pd->regs.dma_ctl1);
725         dma_writel(pd, CTL2, pd->regs.dma_ctl2);
726
727         list_for_each_entry_safe(chan, _c, &pd->dma.channels, device_node) {
728                 pd_chan = to_pd_chan(chan);
729
730                 channel_writel(pd_chan, DEV_ADDR, pd->ch_regs[i].dev_addr);
731                 channel_writel(pd_chan, MEM_ADDR, pd->ch_regs[i].mem_addr);
732                 channel_writel(pd_chan, SIZE, pd->ch_regs[i].size);
733                 channel_writel(pd_chan, NEXT, pd->ch_regs[i].next);
734
735                 i++;
736         }
737 }
738
739 static int pch_dma_suspend(struct pci_dev *pdev, pm_message_t state)
740 {
741         struct pch_dma *pd = pci_get_drvdata(pdev);
742
743         if (pd)
744                 pch_dma_save_regs(pd);
745
746         pci_save_state(pdev);
747         pci_disable_device(pdev);
748         pci_set_power_state(pdev, pci_choose_state(pdev, state));
749
750         return 0;
751 }
752
753 static int pch_dma_resume(struct pci_dev *pdev)
754 {
755         struct pch_dma *pd = pci_get_drvdata(pdev);
756         int err;
757
758         pci_set_power_state(pdev, PCI_D0);
759         pci_restore_state(pdev);
760
761         err = pci_enable_device(pdev);
762         if (err) {
763                 dev_dbg(&pdev->dev, "failed to enable device\n");
764                 return err;
765         }
766
767         if (pd)
768                 pch_dma_restore_regs(pd);
769
770         return 0;
771 }
772 #endif
773
774 static int __devinit pch_dma_probe(struct pci_dev *pdev,
775                                    const struct pci_device_id *id)
776 {
777         struct pch_dma *pd;
778         struct pch_dma_regs *regs;
779         unsigned int nr_channels;
780         int err;
781         int i;
782
783         nr_channels = id->driver_data;
784         pd = kzalloc(sizeof(struct pch_dma)+
785                 sizeof(struct pch_dma_chan) * nr_channels, GFP_KERNEL);
786         if (!pd)
787                 return -ENOMEM;
788
789         pci_set_drvdata(pdev, pd);
790
791         err = pci_enable_device(pdev);
792         if (err) {
793                 dev_err(&pdev->dev, "Cannot enable PCI device\n");
794                 goto err_free_mem;
795         }
796
797         if (!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
798                 dev_err(&pdev->dev, "Cannot find proper base address\n");
799                 goto err_disable_pdev;
800         }
801
802         err = pci_request_regions(pdev, DRV_NAME);
803         if (err) {
804                 dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
805                 goto err_disable_pdev;
806         }
807
808         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
809         if (err) {
810                 dev_err(&pdev->dev, "Cannot set proper DMA config\n");
811                 goto err_free_res;
812         }
813
814         regs = pd->membase = pci_iomap(pdev, 1, 0);
815         if (!pd->membase) {
816                 dev_err(&pdev->dev, "Cannot map MMIO registers\n");
817                 err = -ENOMEM;
818                 goto err_free_res;
819         }
820
821         pci_set_master(pdev);
822
823         err = request_irq(pdev->irq, pd_irq, IRQF_SHARED, DRV_NAME, pd);
824         if (err) {
825                 dev_err(&pdev->dev, "Failed to request IRQ\n");
826                 goto err_iounmap;
827         }
828
829         pd->pool = pci_pool_create("pch_dma_desc_pool", pdev,
830                                    sizeof(struct pch_dma_desc), 4, 0);
831         if (!pd->pool) {
832                 dev_err(&pdev->dev, "Failed to alloc DMA descriptors\n");
833                 err = -ENOMEM;
834                 goto err_free_irq;
835         }
836
837         pd->dma.dev = &pdev->dev;
838         pd->dma.chancnt = nr_channels;
839
840         INIT_LIST_HEAD(&pd->dma.channels);
841
842         for (i = 0; i < nr_channels; i++) {
843                 struct pch_dma_chan *pd_chan = &pd->channels[i];
844
845                 pd_chan->chan.device = &pd->dma;
846                 pd_chan->chan.cookie = 1;
847                 pd_chan->chan.chan_id = i;
848
849                 pd_chan->membase = &regs->desc[i];
850
851                 spin_lock_init(&pd_chan->lock);
852
853                 INIT_LIST_HEAD(&pd_chan->active_list);
854                 INIT_LIST_HEAD(&pd_chan->queue);
855                 INIT_LIST_HEAD(&pd_chan->free_list);
856
857                 tasklet_init(&pd_chan->tasklet, pdc_tasklet,
858                              (unsigned long)pd_chan);
859                 list_add_tail(&pd_chan->chan.device_node, &pd->dma.channels);
860         }
861
862         dma_cap_zero(pd->dma.cap_mask);
863         dma_cap_set(DMA_PRIVATE, pd->dma.cap_mask);
864         dma_cap_set(DMA_SLAVE, pd->dma.cap_mask);
865
866         pd->dma.device_alloc_chan_resources = pd_alloc_chan_resources;
867         pd->dma.device_free_chan_resources = pd_free_chan_resources;
868         pd->dma.device_tx_status = pd_tx_status;
869         pd->dma.device_issue_pending = pd_issue_pending;
870         pd->dma.device_prep_slave_sg = pd_prep_slave_sg;
871         pd->dma.device_control = pd_device_control;
872
873         err = dma_async_device_register(&pd->dma);
874         if (err) {
875                 dev_err(&pdev->dev, "Failed to register DMA device\n");
876                 goto err_free_pool;
877         }
878
879         return 0;
880
881 err_free_pool:
882         pci_pool_destroy(pd->pool);
883 err_free_irq:
884         free_irq(pdev->irq, pd);
885 err_iounmap:
886         pci_iounmap(pdev, pd->membase);
887 err_free_res:
888         pci_release_regions(pdev);
889 err_disable_pdev:
890         pci_disable_device(pdev);
891 err_free_mem:
892         return err;
893 }
894
895 static void __devexit pch_dma_remove(struct pci_dev *pdev)
896 {
897         struct pch_dma *pd = pci_get_drvdata(pdev);
898         struct pch_dma_chan *pd_chan;
899         struct dma_chan *chan, *_c;
900
901         if (pd) {
902                 dma_async_device_unregister(&pd->dma);
903
904                 list_for_each_entry_safe(chan, _c, &pd->dma.channels,
905                                          device_node) {
906                         pd_chan = to_pd_chan(chan);
907
908                         tasklet_disable(&pd_chan->tasklet);
909                         tasklet_kill(&pd_chan->tasklet);
910                 }
911
912                 pci_pool_destroy(pd->pool);
913                 free_irq(pdev->irq, pd);
914                 pci_iounmap(pdev, pd->membase);
915                 pci_release_regions(pdev);
916                 pci_disable_device(pdev);
917                 kfree(pd);
918         }
919 }
920
921 /* PCI Device ID of DMA device */
922 #define PCI_VENDOR_ID_ROHM             0x10DB
923 #define PCI_DEVICE_ID_EG20T_PCH_DMA_8CH        0x8810
924 #define PCI_DEVICE_ID_EG20T_PCH_DMA_4CH        0x8815
925 #define PCI_DEVICE_ID_ML7213_DMA1_8CH   0x8026
926 #define PCI_DEVICE_ID_ML7213_DMA2_8CH   0x802B
927 #define PCI_DEVICE_ID_ML7213_DMA3_4CH   0x8034
928
929 static const struct pci_device_id pch_dma_id_table[] = {
930         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_EG20T_PCH_DMA_8CH), 8 },
931         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_EG20T_PCH_DMA_4CH), 4 },
932         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA1_8CH), 8}, /* UART Video */
933         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA2_8CH), 8}, /* PCMIF SPI */
934         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA3_4CH), 4}, /* FPGA */
935         { 0, },
936 };
937
938 static struct pci_driver pch_dma_driver = {
939         .name           = DRV_NAME,
940         .id_table       = pch_dma_id_table,
941         .probe          = pch_dma_probe,
942         .remove         = __devexit_p(pch_dma_remove),
943 #ifdef CONFIG_PM
944         .suspend        = pch_dma_suspend,
945         .resume         = pch_dma_resume,
946 #endif
947 };
948
949 static int __init pch_dma_init(void)
950 {
951         return pci_register_driver(&pch_dma_driver);
952 }
953
954 static void __exit pch_dma_exit(void)
955 {
956         pci_unregister_driver(&pch_dma_driver);
957 }
958
959 module_init(pch_dma_init);
960 module_exit(pch_dma_exit);
961
962 MODULE_DESCRIPTION("Intel EG20T PCH / OKI SEMICONDUCTOR ML7213 IOH "
963                    "DMA controller driver");
964 MODULE_AUTHOR("Yong Wang <yong.y.wang@intel.com>");
965 MODULE_LICENSE("GPL v2");