dmaengine: move last completed cookie into generic dma_chan structure
[linux-2.6.git] / drivers / dma / pch_dma.c
1 /*
2  * Topcliff PCH DMA controller driver
3  * Copyright (c) 2010 Intel Corporation
4  * Copyright (C) 2011 OKI SEMICONDUCTOR CO., LTD.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18  */
19
20 #include <linux/dmaengine.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/init.h>
23 #include <linux/pci.h>
24 #include <linux/interrupt.h>
25 #include <linux/module.h>
26 #include <linux/pch_dma.h>
27
28 #define DRV_NAME "pch-dma"
29
30 #define DMA_CTL0_DISABLE                0x0
31 #define DMA_CTL0_SG                     0x1
32 #define DMA_CTL0_ONESHOT                0x2
33 #define DMA_CTL0_MODE_MASK_BITS         0x3
34 #define DMA_CTL0_DIR_SHIFT_BITS         2
35 #define DMA_CTL0_BITS_PER_CH            4
36
37 #define DMA_CTL2_START_SHIFT_BITS       8
38 #define DMA_CTL2_IRQ_ENABLE_MASK        ((1UL << DMA_CTL2_START_SHIFT_BITS) - 1)
39
40 #define DMA_STATUS_IDLE                 0x0
41 #define DMA_STATUS_DESC_READ            0x1
42 #define DMA_STATUS_WAIT                 0x2
43 #define DMA_STATUS_ACCESS               0x3
44 #define DMA_STATUS_BITS_PER_CH          2
45 #define DMA_STATUS_MASK_BITS            0x3
46 #define DMA_STATUS_SHIFT_BITS           16
47 #define DMA_STATUS_IRQ(x)               (0x1 << (x))
48 #define DMA_STATUS0_ERR(x)              (0x1 << ((x) + 8))
49 #define DMA_STATUS2_ERR(x)              (0x1 << (x))
50
51 #define DMA_DESC_WIDTH_SHIFT_BITS       12
52 #define DMA_DESC_WIDTH_1_BYTE           (0x3 << DMA_DESC_WIDTH_SHIFT_BITS)
53 #define DMA_DESC_WIDTH_2_BYTES          (0x2 << DMA_DESC_WIDTH_SHIFT_BITS)
54 #define DMA_DESC_WIDTH_4_BYTES          (0x0 << DMA_DESC_WIDTH_SHIFT_BITS)
55 #define DMA_DESC_MAX_COUNT_1_BYTE       0x3FF
56 #define DMA_DESC_MAX_COUNT_2_BYTES      0x3FF
57 #define DMA_DESC_MAX_COUNT_4_BYTES      0x7FF
58 #define DMA_DESC_END_WITHOUT_IRQ        0x0
59 #define DMA_DESC_END_WITH_IRQ           0x1
60 #define DMA_DESC_FOLLOW_WITHOUT_IRQ     0x2
61 #define DMA_DESC_FOLLOW_WITH_IRQ        0x3
62
63 #define MAX_CHAN_NR                     8
64
65 #define DMA_MASK_CTL0_MODE      0x33333333
66 #define DMA_MASK_CTL2_MODE      0x00003333
67
68 static unsigned int init_nr_desc_per_channel = 64;
69 module_param(init_nr_desc_per_channel, uint, 0644);
70 MODULE_PARM_DESC(init_nr_desc_per_channel,
71                  "initial descriptors per channel (default: 64)");
72
73 struct pch_dma_desc_regs {
74         u32     dev_addr;
75         u32     mem_addr;
76         u32     size;
77         u32     next;
78 };
79
80 struct pch_dma_regs {
81         u32     dma_ctl0;
82         u32     dma_ctl1;
83         u32     dma_ctl2;
84         u32     dma_ctl3;
85         u32     dma_sts0;
86         u32     dma_sts1;
87         u32     dma_sts2;
88         u32     reserved3;
89         struct pch_dma_desc_regs desc[MAX_CHAN_NR];
90 };
91
92 struct pch_dma_desc {
93         struct pch_dma_desc_regs regs;
94         struct dma_async_tx_descriptor txd;
95         struct list_head        desc_node;
96         struct list_head        tx_list;
97 };
98
99 struct pch_dma_chan {
100         struct dma_chan         chan;
101         void __iomem *membase;
102         enum dma_data_direction dir;
103         struct tasklet_struct   tasklet;
104         unsigned long           err_status;
105
106         spinlock_t              lock;
107
108         struct list_head        active_list;
109         struct list_head        queue;
110         struct list_head        free_list;
111         unsigned int            descs_allocated;
112 };
113
114 #define PDC_DEV_ADDR    0x00
115 #define PDC_MEM_ADDR    0x04
116 #define PDC_SIZE        0x08
117 #define PDC_NEXT        0x0C
118
119 #define channel_readl(pdc, name) \
120         readl((pdc)->membase + PDC_##name)
121 #define channel_writel(pdc, name, val) \
122         writel((val), (pdc)->membase + PDC_##name)
123
124 struct pch_dma {
125         struct dma_device       dma;
126         void __iomem *membase;
127         struct pci_pool         *pool;
128         struct pch_dma_regs     regs;
129         struct pch_dma_desc_regs ch_regs[MAX_CHAN_NR];
130         struct pch_dma_chan     channels[MAX_CHAN_NR];
131 };
132
133 #define PCH_DMA_CTL0    0x00
134 #define PCH_DMA_CTL1    0x04
135 #define PCH_DMA_CTL2    0x08
136 #define PCH_DMA_CTL3    0x0C
137 #define PCH_DMA_STS0    0x10
138 #define PCH_DMA_STS1    0x14
139 #define PCH_DMA_STS2    0x18
140
141 #define dma_readl(pd, name) \
142         readl((pd)->membase + PCH_DMA_##name)
143 #define dma_writel(pd, name, val) \
144         writel((val), (pd)->membase + PCH_DMA_##name)
145
146 static inline
147 struct pch_dma_desc *to_pd_desc(struct dma_async_tx_descriptor *txd)
148 {
149         return container_of(txd, struct pch_dma_desc, txd);
150 }
151
152 static inline struct pch_dma_chan *to_pd_chan(struct dma_chan *chan)
153 {
154         return container_of(chan, struct pch_dma_chan, chan);
155 }
156
157 static inline struct pch_dma *to_pd(struct dma_device *ddev)
158 {
159         return container_of(ddev, struct pch_dma, dma);
160 }
161
162 static inline struct device *chan2dev(struct dma_chan *chan)
163 {
164         return &chan->dev->device;
165 }
166
167 static inline struct device *chan2parent(struct dma_chan *chan)
168 {
169         return chan->dev->device.parent;
170 }
171
172 static inline
173 struct pch_dma_desc *pdc_first_active(struct pch_dma_chan *pd_chan)
174 {
175         return list_first_entry(&pd_chan->active_list,
176                                 struct pch_dma_desc, desc_node);
177 }
178
179 static inline
180 struct pch_dma_desc *pdc_first_queued(struct pch_dma_chan *pd_chan)
181 {
182         return list_first_entry(&pd_chan->queue,
183                                 struct pch_dma_desc, desc_node);
184 }
185
186 static void pdc_enable_irq(struct dma_chan *chan, int enable)
187 {
188         struct pch_dma *pd = to_pd(chan->device);
189         u32 val;
190         int pos;
191
192         if (chan->chan_id < 8)
193                 pos = chan->chan_id;
194         else
195                 pos = chan->chan_id + 8;
196
197         val = dma_readl(pd, CTL2);
198
199         if (enable)
200                 val |= 0x1 << pos;
201         else
202                 val &= ~(0x1 << pos);
203
204         dma_writel(pd, CTL2, val);
205
206         dev_dbg(chan2dev(chan), "pdc_enable_irq: chan %d -> %x\n",
207                 chan->chan_id, val);
208 }
209
210 static void pdc_set_dir(struct dma_chan *chan)
211 {
212         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
213         struct pch_dma *pd = to_pd(chan->device);
214         u32 val;
215         u32 mask_mode;
216         u32 mask_ctl;
217
218         if (chan->chan_id < 8) {
219                 val = dma_readl(pd, CTL0);
220
221                 mask_mode = DMA_CTL0_MODE_MASK_BITS <<
222                                         (DMA_CTL0_BITS_PER_CH * chan->chan_id);
223                 mask_ctl = DMA_MASK_CTL0_MODE & ~(DMA_CTL0_MODE_MASK_BITS <<
224                                        (DMA_CTL0_BITS_PER_CH * chan->chan_id));
225                 val &= mask_mode;
226                 if (pd_chan->dir == DMA_TO_DEVICE)
227                         val |= 0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id +
228                                        DMA_CTL0_DIR_SHIFT_BITS);
229                 else
230                         val &= ~(0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id +
231                                          DMA_CTL0_DIR_SHIFT_BITS));
232
233                 val |= mask_ctl;
234                 dma_writel(pd, CTL0, val);
235         } else {
236                 int ch = chan->chan_id - 8; /* ch8-->0 ch9-->1 ... ch11->3 */
237                 val = dma_readl(pd, CTL3);
238
239                 mask_mode = DMA_CTL0_MODE_MASK_BITS <<
240                                                 (DMA_CTL0_BITS_PER_CH * ch);
241                 mask_ctl = DMA_MASK_CTL2_MODE & ~(DMA_CTL0_MODE_MASK_BITS <<
242                                                  (DMA_CTL0_BITS_PER_CH * ch));
243                 val &= mask_mode;
244                 if (pd_chan->dir == DMA_TO_DEVICE)
245                         val |= 0x1 << (DMA_CTL0_BITS_PER_CH * ch +
246                                        DMA_CTL0_DIR_SHIFT_BITS);
247                 else
248                         val &= ~(0x1 << (DMA_CTL0_BITS_PER_CH * ch +
249                                          DMA_CTL0_DIR_SHIFT_BITS));
250                 val |= mask_ctl;
251                 dma_writel(pd, CTL3, val);
252         }
253
254         dev_dbg(chan2dev(chan), "pdc_set_dir: chan %d -> %x\n",
255                 chan->chan_id, val);
256 }
257
258 static void pdc_set_mode(struct dma_chan *chan, u32 mode)
259 {
260         struct pch_dma *pd = to_pd(chan->device);
261         u32 val;
262         u32 mask_ctl;
263         u32 mask_dir;
264
265         if (chan->chan_id < 8) {
266                 mask_ctl = DMA_MASK_CTL0_MODE & ~(DMA_CTL0_MODE_MASK_BITS <<
267                            (DMA_CTL0_BITS_PER_CH * chan->chan_id));
268                 mask_dir = 1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id +\
269                                  DMA_CTL0_DIR_SHIFT_BITS);
270                 val = dma_readl(pd, CTL0);
271                 val &= mask_dir;
272                 val |= mode << (DMA_CTL0_BITS_PER_CH * chan->chan_id);
273                 val |= mask_ctl;
274                 dma_writel(pd, CTL0, val);
275         } else {
276                 int ch = chan->chan_id - 8; /* ch8-->0 ch9-->1 ... ch11->3 */
277                 mask_ctl = DMA_MASK_CTL2_MODE & ~(DMA_CTL0_MODE_MASK_BITS <<
278                                                  (DMA_CTL0_BITS_PER_CH * ch));
279                 mask_dir = 1 << (DMA_CTL0_BITS_PER_CH * ch +\
280                                  DMA_CTL0_DIR_SHIFT_BITS);
281                 val = dma_readl(pd, CTL3);
282                 val &= mask_dir;
283                 val |= mode << (DMA_CTL0_BITS_PER_CH * ch);
284                 val |= mask_ctl;
285                 dma_writel(pd, CTL3, val);
286         }
287
288         dev_dbg(chan2dev(chan), "pdc_set_mode: chan %d -> %x\n",
289                 chan->chan_id, val);
290 }
291
292 static u32 pdc_get_status0(struct pch_dma_chan *pd_chan)
293 {
294         struct pch_dma *pd = to_pd(pd_chan->chan.device);
295         u32 val;
296
297         val = dma_readl(pd, STS0);
298         return DMA_STATUS_MASK_BITS & (val >> (DMA_STATUS_SHIFT_BITS +
299                         DMA_STATUS_BITS_PER_CH * pd_chan->chan.chan_id));
300 }
301
302 static u32 pdc_get_status2(struct pch_dma_chan *pd_chan)
303 {
304         struct pch_dma *pd = to_pd(pd_chan->chan.device);
305         u32 val;
306
307         val = dma_readl(pd, STS2);
308         return DMA_STATUS_MASK_BITS & (val >> (DMA_STATUS_SHIFT_BITS +
309                         DMA_STATUS_BITS_PER_CH * (pd_chan->chan.chan_id - 8)));
310 }
311
312 static bool pdc_is_idle(struct pch_dma_chan *pd_chan)
313 {
314         u32 sts;
315
316         if (pd_chan->chan.chan_id < 8)
317                 sts = pdc_get_status0(pd_chan);
318         else
319                 sts = pdc_get_status2(pd_chan);
320
321
322         if (sts == DMA_STATUS_IDLE)
323                 return true;
324         else
325                 return false;
326 }
327
328 static void pdc_dostart(struct pch_dma_chan *pd_chan, struct pch_dma_desc* desc)
329 {
330         if (!pdc_is_idle(pd_chan)) {
331                 dev_err(chan2dev(&pd_chan->chan),
332                         "BUG: Attempt to start non-idle channel\n");
333                 return;
334         }
335
336         dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> dev_addr: %x\n",
337                 pd_chan->chan.chan_id, desc->regs.dev_addr);
338         dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> mem_addr: %x\n",
339                 pd_chan->chan.chan_id, desc->regs.mem_addr);
340         dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> size: %x\n",
341                 pd_chan->chan.chan_id, desc->regs.size);
342         dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> next: %x\n",
343                 pd_chan->chan.chan_id, desc->regs.next);
344
345         if (list_empty(&desc->tx_list)) {
346                 channel_writel(pd_chan, DEV_ADDR, desc->regs.dev_addr);
347                 channel_writel(pd_chan, MEM_ADDR, desc->regs.mem_addr);
348                 channel_writel(pd_chan, SIZE, desc->regs.size);
349                 channel_writel(pd_chan, NEXT, desc->regs.next);
350                 pdc_set_mode(&pd_chan->chan, DMA_CTL0_ONESHOT);
351         } else {
352                 channel_writel(pd_chan, NEXT, desc->txd.phys);
353                 pdc_set_mode(&pd_chan->chan, DMA_CTL0_SG);
354         }
355 }
356
357 static void pdc_chain_complete(struct pch_dma_chan *pd_chan,
358                                struct pch_dma_desc *desc)
359 {
360         struct dma_async_tx_descriptor *txd = &desc->txd;
361         dma_async_tx_callback callback = txd->callback;
362         void *param = txd->callback_param;
363
364         list_splice_init(&desc->tx_list, &pd_chan->free_list);
365         list_move(&desc->desc_node, &pd_chan->free_list);
366
367         if (callback)
368                 callback(param);
369 }
370
371 static void pdc_complete_all(struct pch_dma_chan *pd_chan)
372 {
373         struct pch_dma_desc *desc, *_d;
374         LIST_HEAD(list);
375
376         BUG_ON(!pdc_is_idle(pd_chan));
377
378         if (!list_empty(&pd_chan->queue))
379                 pdc_dostart(pd_chan, pdc_first_queued(pd_chan));
380
381         list_splice_init(&pd_chan->active_list, &list);
382         list_splice_init(&pd_chan->queue, &pd_chan->active_list);
383
384         list_for_each_entry_safe(desc, _d, &list, desc_node)
385                 pdc_chain_complete(pd_chan, desc);
386 }
387
388 static void pdc_handle_error(struct pch_dma_chan *pd_chan)
389 {
390         struct pch_dma_desc *bad_desc;
391
392         bad_desc = pdc_first_active(pd_chan);
393         list_del(&bad_desc->desc_node);
394
395         list_splice_init(&pd_chan->queue, pd_chan->active_list.prev);
396
397         if (!list_empty(&pd_chan->active_list))
398                 pdc_dostart(pd_chan, pdc_first_active(pd_chan));
399
400         dev_crit(chan2dev(&pd_chan->chan), "Bad descriptor submitted\n");
401         dev_crit(chan2dev(&pd_chan->chan), "descriptor cookie: %d\n",
402                  bad_desc->txd.cookie);
403
404         pdc_chain_complete(pd_chan, bad_desc);
405 }
406
407 static void pdc_advance_work(struct pch_dma_chan *pd_chan)
408 {
409         if (list_empty(&pd_chan->active_list) ||
410                 list_is_singular(&pd_chan->active_list)) {
411                 pdc_complete_all(pd_chan);
412         } else {
413                 pdc_chain_complete(pd_chan, pdc_first_active(pd_chan));
414                 pdc_dostart(pd_chan, pdc_first_active(pd_chan));
415         }
416 }
417
418 static dma_cookie_t pdc_assign_cookie(struct pch_dma_chan *pd_chan,
419                                       struct pch_dma_desc *desc)
420 {
421         dma_cookie_t cookie = pd_chan->chan.cookie;
422
423         if (++cookie < 0)
424                 cookie = 1;
425
426         pd_chan->chan.cookie = cookie;
427         desc->txd.cookie = cookie;
428
429         return cookie;
430 }
431
432 static dma_cookie_t pd_tx_submit(struct dma_async_tx_descriptor *txd)
433 {
434         struct pch_dma_desc *desc = to_pd_desc(txd);
435         struct pch_dma_chan *pd_chan = to_pd_chan(txd->chan);
436         dma_cookie_t cookie;
437
438         spin_lock(&pd_chan->lock);
439         cookie = pdc_assign_cookie(pd_chan, desc);
440
441         if (list_empty(&pd_chan->active_list)) {
442                 list_add_tail(&desc->desc_node, &pd_chan->active_list);
443                 pdc_dostart(pd_chan, desc);
444         } else {
445                 list_add_tail(&desc->desc_node, &pd_chan->queue);
446         }
447
448         spin_unlock(&pd_chan->lock);
449         return 0;
450 }
451
452 static struct pch_dma_desc *pdc_alloc_desc(struct dma_chan *chan, gfp_t flags)
453 {
454         struct pch_dma_desc *desc = NULL;
455         struct pch_dma *pd = to_pd(chan->device);
456         dma_addr_t addr;
457
458         desc = pci_pool_alloc(pd->pool, flags, &addr);
459         if (desc) {
460                 memset(desc, 0, sizeof(struct pch_dma_desc));
461                 INIT_LIST_HEAD(&desc->tx_list);
462                 dma_async_tx_descriptor_init(&desc->txd, chan);
463                 desc->txd.tx_submit = pd_tx_submit;
464                 desc->txd.flags = DMA_CTRL_ACK;
465                 desc->txd.phys = addr;
466         }
467
468         return desc;
469 }
470
471 static struct pch_dma_desc *pdc_desc_get(struct pch_dma_chan *pd_chan)
472 {
473         struct pch_dma_desc *desc, *_d;
474         struct pch_dma_desc *ret = NULL;
475         int i = 0;
476
477         spin_lock(&pd_chan->lock);
478         list_for_each_entry_safe(desc, _d, &pd_chan->free_list, desc_node) {
479                 i++;
480                 if (async_tx_test_ack(&desc->txd)) {
481                         list_del(&desc->desc_node);
482                         ret = desc;
483                         break;
484                 }
485                 dev_dbg(chan2dev(&pd_chan->chan), "desc %p not ACKed\n", desc);
486         }
487         spin_unlock(&pd_chan->lock);
488         dev_dbg(chan2dev(&pd_chan->chan), "scanned %d descriptors\n", i);
489
490         if (!ret) {
491                 ret = pdc_alloc_desc(&pd_chan->chan, GFP_NOIO);
492                 if (ret) {
493                         spin_lock(&pd_chan->lock);
494                         pd_chan->descs_allocated++;
495                         spin_unlock(&pd_chan->lock);
496                 } else {
497                         dev_err(chan2dev(&pd_chan->chan),
498                                 "failed to alloc desc\n");
499                 }
500         }
501
502         return ret;
503 }
504
505 static void pdc_desc_put(struct pch_dma_chan *pd_chan,
506                          struct pch_dma_desc *desc)
507 {
508         if (desc) {
509                 spin_lock(&pd_chan->lock);
510                 list_splice_init(&desc->tx_list, &pd_chan->free_list);
511                 list_add(&desc->desc_node, &pd_chan->free_list);
512                 spin_unlock(&pd_chan->lock);
513         }
514 }
515
516 static int pd_alloc_chan_resources(struct dma_chan *chan)
517 {
518         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
519         struct pch_dma_desc *desc;
520         LIST_HEAD(tmp_list);
521         int i;
522
523         if (!pdc_is_idle(pd_chan)) {
524                 dev_dbg(chan2dev(chan), "DMA channel not idle ?\n");
525                 return -EIO;
526         }
527
528         if (!list_empty(&pd_chan->free_list))
529                 return pd_chan->descs_allocated;
530
531         for (i = 0; i < init_nr_desc_per_channel; i++) {
532                 desc = pdc_alloc_desc(chan, GFP_KERNEL);
533
534                 if (!desc) {
535                         dev_warn(chan2dev(chan),
536                                 "Only allocated %d initial descriptors\n", i);
537                         break;
538                 }
539
540                 list_add_tail(&desc->desc_node, &tmp_list);
541         }
542
543         spin_lock_irq(&pd_chan->lock);
544         list_splice(&tmp_list, &pd_chan->free_list);
545         pd_chan->descs_allocated = i;
546         chan->completed_cookie = chan->cookie = 1;
547         spin_unlock_irq(&pd_chan->lock);
548
549         pdc_enable_irq(chan, 1);
550
551         return pd_chan->descs_allocated;
552 }
553
554 static void pd_free_chan_resources(struct dma_chan *chan)
555 {
556         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
557         struct pch_dma *pd = to_pd(chan->device);
558         struct pch_dma_desc *desc, *_d;
559         LIST_HEAD(tmp_list);
560
561         BUG_ON(!pdc_is_idle(pd_chan));
562         BUG_ON(!list_empty(&pd_chan->active_list));
563         BUG_ON(!list_empty(&pd_chan->queue));
564
565         spin_lock_irq(&pd_chan->lock);
566         list_splice_init(&pd_chan->free_list, &tmp_list);
567         pd_chan->descs_allocated = 0;
568         spin_unlock_irq(&pd_chan->lock);
569
570         list_for_each_entry_safe(desc, _d, &tmp_list, desc_node)
571                 pci_pool_free(pd->pool, desc, desc->txd.phys);
572
573         pdc_enable_irq(chan, 0);
574 }
575
576 static enum dma_status pd_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
577                                     struct dma_tx_state *txstate)
578 {
579         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
580         dma_cookie_t last_used;
581         dma_cookie_t last_completed;
582         int ret;
583
584         spin_lock_irq(&pd_chan->lock);
585         last_completed = chan->completed_cookie;
586         last_used = chan->cookie;
587         spin_unlock_irq(&pd_chan->lock);
588
589         ret = dma_async_is_complete(cookie, last_completed, last_used);
590
591         dma_set_tx_state(txstate, last_completed, last_used, 0);
592
593         return ret;
594 }
595
596 static void pd_issue_pending(struct dma_chan *chan)
597 {
598         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
599
600         if (pdc_is_idle(pd_chan)) {
601                 spin_lock(&pd_chan->lock);
602                 pdc_advance_work(pd_chan);
603                 spin_unlock(&pd_chan->lock);
604         }
605 }
606
607 static struct dma_async_tx_descriptor *pd_prep_slave_sg(struct dma_chan *chan,
608                         struct scatterlist *sgl, unsigned int sg_len,
609                         enum dma_data_direction direction, unsigned long flags)
610 {
611         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
612         struct pch_dma_slave *pd_slave = chan->private;
613         struct pch_dma_desc *first = NULL;
614         struct pch_dma_desc *prev = NULL;
615         struct pch_dma_desc *desc = NULL;
616         struct scatterlist *sg;
617         dma_addr_t reg;
618         int i;
619
620         if (unlikely(!sg_len)) {
621                 dev_info(chan2dev(chan), "prep_slave_sg: length is zero!\n");
622                 return NULL;
623         }
624
625         if (direction == DMA_FROM_DEVICE)
626                 reg = pd_slave->rx_reg;
627         else if (direction == DMA_TO_DEVICE)
628                 reg = pd_slave->tx_reg;
629         else
630                 return NULL;
631
632         pd_chan->dir = direction;
633         pdc_set_dir(chan);
634
635         for_each_sg(sgl, sg, sg_len, i) {
636                 desc = pdc_desc_get(pd_chan);
637
638                 if (!desc)
639                         goto err_desc_get;
640
641                 desc->regs.dev_addr = reg;
642                 desc->regs.mem_addr = sg_phys(sg);
643                 desc->regs.size = sg_dma_len(sg);
644                 desc->regs.next = DMA_DESC_FOLLOW_WITHOUT_IRQ;
645
646                 switch (pd_slave->width) {
647                 case PCH_DMA_WIDTH_1_BYTE:
648                         if (desc->regs.size > DMA_DESC_MAX_COUNT_1_BYTE)
649                                 goto err_desc_get;
650                         desc->regs.size |= DMA_DESC_WIDTH_1_BYTE;
651                         break;
652                 case PCH_DMA_WIDTH_2_BYTES:
653                         if (desc->regs.size > DMA_DESC_MAX_COUNT_2_BYTES)
654                                 goto err_desc_get;
655                         desc->regs.size |= DMA_DESC_WIDTH_2_BYTES;
656                         break;
657                 case PCH_DMA_WIDTH_4_BYTES:
658                         if (desc->regs.size > DMA_DESC_MAX_COUNT_4_BYTES)
659                                 goto err_desc_get;
660                         desc->regs.size |= DMA_DESC_WIDTH_4_BYTES;
661                         break;
662                 default:
663                         goto err_desc_get;
664                 }
665
666                 if (!first) {
667                         first = desc;
668                 } else {
669                         prev->regs.next |= desc->txd.phys;
670                         list_add_tail(&desc->desc_node, &first->tx_list);
671                 }
672
673                 prev = desc;
674         }
675
676         if (flags & DMA_PREP_INTERRUPT)
677                 desc->regs.next = DMA_DESC_END_WITH_IRQ;
678         else
679                 desc->regs.next = DMA_DESC_END_WITHOUT_IRQ;
680
681         first->txd.cookie = -EBUSY;
682         desc->txd.flags = flags;
683
684         return &first->txd;
685
686 err_desc_get:
687         dev_err(chan2dev(chan), "failed to get desc or wrong parameters\n");
688         pdc_desc_put(pd_chan, first);
689         return NULL;
690 }
691
692 static int pd_device_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
693                              unsigned long arg)
694 {
695         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
696         struct pch_dma_desc *desc, *_d;
697         LIST_HEAD(list);
698
699         if (cmd != DMA_TERMINATE_ALL)
700                 return -ENXIO;
701
702         spin_lock_irq(&pd_chan->lock);
703
704         pdc_set_mode(&pd_chan->chan, DMA_CTL0_DISABLE);
705
706         list_splice_init(&pd_chan->active_list, &list);
707         list_splice_init(&pd_chan->queue, &list);
708
709         list_for_each_entry_safe(desc, _d, &list, desc_node)
710                 pdc_chain_complete(pd_chan, desc);
711
712         spin_unlock_irq(&pd_chan->lock);
713
714         return 0;
715 }
716
717 static void pdc_tasklet(unsigned long data)
718 {
719         struct pch_dma_chan *pd_chan = (struct pch_dma_chan *)data;
720         unsigned long flags;
721
722         if (!pdc_is_idle(pd_chan)) {
723                 dev_err(chan2dev(&pd_chan->chan),
724                         "BUG: handle non-idle channel in tasklet\n");
725                 return;
726         }
727
728         spin_lock_irqsave(&pd_chan->lock, flags);
729         if (test_and_clear_bit(0, &pd_chan->err_status))
730                 pdc_handle_error(pd_chan);
731         else
732                 pdc_advance_work(pd_chan);
733         spin_unlock_irqrestore(&pd_chan->lock, flags);
734 }
735
736 static irqreturn_t pd_irq(int irq, void *devid)
737 {
738         struct pch_dma *pd = (struct pch_dma *)devid;
739         struct pch_dma_chan *pd_chan;
740         u32 sts0;
741         u32 sts2;
742         int i;
743         int ret0 = IRQ_NONE;
744         int ret2 = IRQ_NONE;
745
746         sts0 = dma_readl(pd, STS0);
747         sts2 = dma_readl(pd, STS2);
748
749         dev_dbg(pd->dma.dev, "pd_irq sts0: %x\n", sts0);
750
751         for (i = 0; i < pd->dma.chancnt; i++) {
752                 pd_chan = &pd->channels[i];
753
754                 if (i < 8) {
755                         if (sts0 & DMA_STATUS_IRQ(i)) {
756                                 if (sts0 & DMA_STATUS0_ERR(i))
757                                         set_bit(0, &pd_chan->err_status);
758
759                                 tasklet_schedule(&pd_chan->tasklet);
760                                 ret0 = IRQ_HANDLED;
761                         }
762                 } else {
763                         if (sts2 & DMA_STATUS_IRQ(i - 8)) {
764                                 if (sts2 & DMA_STATUS2_ERR(i))
765                                         set_bit(0, &pd_chan->err_status);
766
767                                 tasklet_schedule(&pd_chan->tasklet);
768                                 ret2 = IRQ_HANDLED;
769                         }
770                 }
771         }
772
773         /* clear interrupt bits in status register */
774         if (ret0)
775                 dma_writel(pd, STS0, sts0);
776         if (ret2)
777                 dma_writel(pd, STS2, sts2);
778
779         return ret0 | ret2;
780 }
781
782 #ifdef  CONFIG_PM
783 static void pch_dma_save_regs(struct pch_dma *pd)
784 {
785         struct pch_dma_chan *pd_chan;
786         struct dma_chan *chan, *_c;
787         int i = 0;
788
789         pd->regs.dma_ctl0 = dma_readl(pd, CTL0);
790         pd->regs.dma_ctl1 = dma_readl(pd, CTL1);
791         pd->regs.dma_ctl2 = dma_readl(pd, CTL2);
792         pd->regs.dma_ctl3 = dma_readl(pd, CTL3);
793
794         list_for_each_entry_safe(chan, _c, &pd->dma.channels, device_node) {
795                 pd_chan = to_pd_chan(chan);
796
797                 pd->ch_regs[i].dev_addr = channel_readl(pd_chan, DEV_ADDR);
798                 pd->ch_regs[i].mem_addr = channel_readl(pd_chan, MEM_ADDR);
799                 pd->ch_regs[i].size = channel_readl(pd_chan, SIZE);
800                 pd->ch_regs[i].next = channel_readl(pd_chan, NEXT);
801
802                 i++;
803         }
804 }
805
806 static void pch_dma_restore_regs(struct pch_dma *pd)
807 {
808         struct pch_dma_chan *pd_chan;
809         struct dma_chan *chan, *_c;
810         int i = 0;
811
812         dma_writel(pd, CTL0, pd->regs.dma_ctl0);
813         dma_writel(pd, CTL1, pd->regs.dma_ctl1);
814         dma_writel(pd, CTL2, pd->regs.dma_ctl2);
815         dma_writel(pd, CTL3, pd->regs.dma_ctl3);
816
817         list_for_each_entry_safe(chan, _c, &pd->dma.channels, device_node) {
818                 pd_chan = to_pd_chan(chan);
819
820                 channel_writel(pd_chan, DEV_ADDR, pd->ch_regs[i].dev_addr);
821                 channel_writel(pd_chan, MEM_ADDR, pd->ch_regs[i].mem_addr);
822                 channel_writel(pd_chan, SIZE, pd->ch_regs[i].size);
823                 channel_writel(pd_chan, NEXT, pd->ch_regs[i].next);
824
825                 i++;
826         }
827 }
828
829 static int pch_dma_suspend(struct pci_dev *pdev, pm_message_t state)
830 {
831         struct pch_dma *pd = pci_get_drvdata(pdev);
832
833         if (pd)
834                 pch_dma_save_regs(pd);
835
836         pci_save_state(pdev);
837         pci_disable_device(pdev);
838         pci_set_power_state(pdev, pci_choose_state(pdev, state));
839
840         return 0;
841 }
842
843 static int pch_dma_resume(struct pci_dev *pdev)
844 {
845         struct pch_dma *pd = pci_get_drvdata(pdev);
846         int err;
847
848         pci_set_power_state(pdev, PCI_D0);
849         pci_restore_state(pdev);
850
851         err = pci_enable_device(pdev);
852         if (err) {
853                 dev_dbg(&pdev->dev, "failed to enable device\n");
854                 return err;
855         }
856
857         if (pd)
858                 pch_dma_restore_regs(pd);
859
860         return 0;
861 }
862 #endif
863
864 static int __devinit pch_dma_probe(struct pci_dev *pdev,
865                                    const struct pci_device_id *id)
866 {
867         struct pch_dma *pd;
868         struct pch_dma_regs *regs;
869         unsigned int nr_channels;
870         int err;
871         int i;
872
873         nr_channels = id->driver_data;
874         pd = kzalloc(sizeof(struct pch_dma)+
875                 sizeof(struct pch_dma_chan) * nr_channels, GFP_KERNEL);
876         if (!pd)
877                 return -ENOMEM;
878
879         pci_set_drvdata(pdev, pd);
880
881         err = pci_enable_device(pdev);
882         if (err) {
883                 dev_err(&pdev->dev, "Cannot enable PCI device\n");
884                 goto err_free_mem;
885         }
886
887         if (!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
888                 dev_err(&pdev->dev, "Cannot find proper base address\n");
889                 goto err_disable_pdev;
890         }
891
892         err = pci_request_regions(pdev, DRV_NAME);
893         if (err) {
894                 dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
895                 goto err_disable_pdev;
896         }
897
898         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
899         if (err) {
900                 dev_err(&pdev->dev, "Cannot set proper DMA config\n");
901                 goto err_free_res;
902         }
903
904         regs = pd->membase = pci_iomap(pdev, 1, 0);
905         if (!pd->membase) {
906                 dev_err(&pdev->dev, "Cannot map MMIO registers\n");
907                 err = -ENOMEM;
908                 goto err_free_res;
909         }
910
911         pci_set_master(pdev);
912
913         err = request_irq(pdev->irq, pd_irq, IRQF_SHARED, DRV_NAME, pd);
914         if (err) {
915                 dev_err(&pdev->dev, "Failed to request IRQ\n");
916                 goto err_iounmap;
917         }
918
919         pd->pool = pci_pool_create("pch_dma_desc_pool", pdev,
920                                    sizeof(struct pch_dma_desc), 4, 0);
921         if (!pd->pool) {
922                 dev_err(&pdev->dev, "Failed to alloc DMA descriptors\n");
923                 err = -ENOMEM;
924                 goto err_free_irq;
925         }
926
927         pd->dma.dev = &pdev->dev;
928         pd->dma.chancnt = nr_channels;
929
930         INIT_LIST_HEAD(&pd->dma.channels);
931
932         for (i = 0; i < nr_channels; i++) {
933                 struct pch_dma_chan *pd_chan = &pd->channels[i];
934
935                 pd_chan->chan.device = &pd->dma;
936                 pd_chan->chan.cookie = 1;
937                 pd_chan->chan.chan_id = i;
938
939                 pd_chan->membase = &regs->desc[i];
940
941                 spin_lock_init(&pd_chan->lock);
942
943                 INIT_LIST_HEAD(&pd_chan->active_list);
944                 INIT_LIST_HEAD(&pd_chan->queue);
945                 INIT_LIST_HEAD(&pd_chan->free_list);
946
947                 tasklet_init(&pd_chan->tasklet, pdc_tasklet,
948                              (unsigned long)pd_chan);
949                 list_add_tail(&pd_chan->chan.device_node, &pd->dma.channels);
950         }
951
952         dma_cap_zero(pd->dma.cap_mask);
953         dma_cap_set(DMA_PRIVATE, pd->dma.cap_mask);
954         dma_cap_set(DMA_SLAVE, pd->dma.cap_mask);
955
956         pd->dma.device_alloc_chan_resources = pd_alloc_chan_resources;
957         pd->dma.device_free_chan_resources = pd_free_chan_resources;
958         pd->dma.device_tx_status = pd_tx_status;
959         pd->dma.device_issue_pending = pd_issue_pending;
960         pd->dma.device_prep_slave_sg = pd_prep_slave_sg;
961         pd->dma.device_control = pd_device_control;
962
963         err = dma_async_device_register(&pd->dma);
964         if (err) {
965                 dev_err(&pdev->dev, "Failed to register DMA device\n");
966                 goto err_free_pool;
967         }
968
969         return 0;
970
971 err_free_pool:
972         pci_pool_destroy(pd->pool);
973 err_free_irq:
974         free_irq(pdev->irq, pd);
975 err_iounmap:
976         pci_iounmap(pdev, pd->membase);
977 err_free_res:
978         pci_release_regions(pdev);
979 err_disable_pdev:
980         pci_disable_device(pdev);
981 err_free_mem:
982         return err;
983 }
984
985 static void __devexit pch_dma_remove(struct pci_dev *pdev)
986 {
987         struct pch_dma *pd = pci_get_drvdata(pdev);
988         struct pch_dma_chan *pd_chan;
989         struct dma_chan *chan, *_c;
990
991         if (pd) {
992                 dma_async_device_unregister(&pd->dma);
993
994                 list_for_each_entry_safe(chan, _c, &pd->dma.channels,
995                                          device_node) {
996                         pd_chan = to_pd_chan(chan);
997
998                         tasklet_disable(&pd_chan->tasklet);
999                         tasklet_kill(&pd_chan->tasklet);
1000                 }
1001
1002                 pci_pool_destroy(pd->pool);
1003                 free_irq(pdev->irq, pd);
1004                 pci_iounmap(pdev, pd->membase);
1005                 pci_release_regions(pdev);
1006                 pci_disable_device(pdev);
1007                 kfree(pd);
1008         }
1009 }
1010
1011 /* PCI Device ID of DMA device */
1012 #define PCI_VENDOR_ID_ROHM             0x10DB
1013 #define PCI_DEVICE_ID_EG20T_PCH_DMA_8CH        0x8810
1014 #define PCI_DEVICE_ID_EG20T_PCH_DMA_4CH        0x8815
1015 #define PCI_DEVICE_ID_ML7213_DMA1_8CH   0x8026
1016 #define PCI_DEVICE_ID_ML7213_DMA2_8CH   0x802B
1017 #define PCI_DEVICE_ID_ML7213_DMA3_4CH   0x8034
1018 #define PCI_DEVICE_ID_ML7213_DMA4_12CH  0x8032
1019 #define PCI_DEVICE_ID_ML7223_DMA1_4CH   0x800B
1020 #define PCI_DEVICE_ID_ML7223_DMA2_4CH   0x800E
1021 #define PCI_DEVICE_ID_ML7223_DMA3_4CH   0x8017
1022 #define PCI_DEVICE_ID_ML7223_DMA4_4CH   0x803B
1023
1024 DEFINE_PCI_DEVICE_TABLE(pch_dma_id_table) = {
1025         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_EG20T_PCH_DMA_8CH), 8 },
1026         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_EG20T_PCH_DMA_4CH), 4 },
1027         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA1_8CH), 8}, /* UART Video */
1028         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA2_8CH), 8}, /* PCMIF SPI */
1029         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA3_4CH), 4}, /* FPGA */
1030         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA4_12CH), 12}, /* I2S */
1031         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA1_4CH), 4}, /* UART */
1032         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA2_4CH), 4}, /* Video SPI */
1033         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA3_4CH), 4}, /* Security */
1034         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA4_4CH), 4}, /* FPGA */
1035         { 0, },
1036 };
1037
1038 static struct pci_driver pch_dma_driver = {
1039         .name           = DRV_NAME,
1040         .id_table       = pch_dma_id_table,
1041         .probe          = pch_dma_probe,
1042         .remove         = __devexit_p(pch_dma_remove),
1043 #ifdef CONFIG_PM
1044         .suspend        = pch_dma_suspend,
1045         .resume         = pch_dma_resume,
1046 #endif
1047 };
1048
1049 static int __init pch_dma_init(void)
1050 {
1051         return pci_register_driver(&pch_dma_driver);
1052 }
1053
1054 static void __exit pch_dma_exit(void)
1055 {
1056         pci_unregister_driver(&pch_dma_driver);
1057 }
1058
1059 module_init(pch_dma_init);
1060 module_exit(pch_dma_exit);
1061
1062 MODULE_DESCRIPTION("Intel EG20T PCH / OKI SEMICONDUCTOR ML7213 IOH "
1063                    "DMA controller driver");
1064 MODULE_AUTHOR("Yong Wang <yong.y.wang@intel.com>");
1065 MODULE_LICENSE("GPL v2");