drivers/dma/pch_dma.c

   1 /*
   2  * Topcliff PCH DMA controller driver
   3  * Copyright (c) 2010 Intel Corporation
   4  * Copyright (C) 2011 OKI SEMICONDUCTOR CO., LTD.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  */
  19
  20 #include <linux/dmaengine.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/init.h>
  23 #include <linux/pci.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/module.h>
  26 #include <linux/pch_dma.h>
  27
  28 #define DRV_NAME "pch-dma"
  29
  30 #define DMA_CTL0_DISABLE                0x0
  31 #define DMA_CTL0_SG                     0x1
  32 #define DMA_CTL0_ONESHOT                0x2
  33 #define DMA_CTL0_MODE_MASK_BITS         0x3
  34 #define DMA_CTL0_DIR_SHIFT_BITS         2
  35 #define DMA_CTL0_BITS_PER_CH            4
  36
  37 #define DMA_CTL2_START_SHIFT_BITS       8
  38 #define DMA_CTL2_IRQ_ENABLE_MASK        ((1UL << DMA_CTL2_START_SHIFT_BITS) - 1)
  39
  40 #define DMA_STATUS_IDLE                 0x0
  41 #define DMA_STATUS_DESC_READ            0x1
  42 #define DMA_STATUS_WAIT                 0x2
  43 #define DMA_STATUS_ACCESS               0x3
  44 #define DMA_STATUS_BITS_PER_CH          2
  45 #define DMA_STATUS_MASK_BITS            0x3
  46 #define DMA_STATUS_SHIFT_BITS           16
  47 #define DMA_STATUS_IRQ(x)               (0x1 << (x))
  48 #define DMA_STATUS_ERR(x)               (0x1 << ((x) + 8))
  49
  50 #define DMA_DESC_WIDTH_SHIFT_BITS       12
  51 #define DMA_DESC_WIDTH_1_BYTE           (0x3 << DMA_DESC_WIDTH_SHIFT_BITS)
  52 #define DMA_DESC_WIDTH_2_BYTES          (0x2 << DMA_DESC_WIDTH_SHIFT_BITS)
  53 #define DMA_DESC_WIDTH_4_BYTES          (0x0 << DMA_DESC_WIDTH_SHIFT_BITS)
  54 #define DMA_DESC_MAX_COUNT_1_BYTE       0x3FF
  55 #define DMA_DESC_MAX_COUNT_2_BYTES      0x3FF
  56 #define DMA_DESC_MAX_COUNT_4_BYTES      0x7FF
  57 #define DMA_DESC_END_WITHOUT_IRQ        0x0
  58 #define DMA_DESC_END_WITH_IRQ           0x1
  59 #define DMA_DESC_FOLLOW_WITHOUT_IRQ     0x2
  60 #define DMA_DESC_FOLLOW_WITH_IRQ        0x3
  61
  62 #define MAX_CHAN_NR                     8
  63
  64 static unsigned int init_nr_desc_per_channel = 64;
  65 module_param(init_nr_desc_per_channel, uint, 0644);
  66 MODULE_PARM_DESC(init_nr_desc_per_channel,
  67                  "initial descriptors per channel (default: 64)");
  68
  69 struct pch_dma_desc_regs {
  70         u32     dev_addr;
  71         u32     mem_addr;
  72         u32     size;
  73         u32     next;
  74 };
  75
  76 struct pch_dma_regs {
  77         u32     dma_ctl0;
  78         u32     dma_ctl1;
  79         u32     dma_ctl2;
  80         u32     reserved1;
  81         u32     dma_sts0;
  82         u32     dma_sts1;
  83         u32     reserved2;
  84         u32     reserved3;
  85         struct pch_dma_desc_regs desc[MAX_CHAN_NR];
  86 };
  87
  88 struct pch_dma_desc {
  89         struct pch_dma_desc_regs regs;
  90         struct dma_async_tx_descriptor txd;
  91         struct list_head        desc_node;
  92         struct list_head        tx_list;
  93 };
  94
  95 struct pch_dma_chan {
  96         struct dma_chan         chan;
  97         void __iomem *membase;
  98         enum dma_data_direction dir;
  99         struct tasklet_struct   tasklet;
 100         unsigned long           err_status;
 101
 102         spinlock_t              lock;
 103
 104         dma_cookie_t            completed_cookie;
 105         struct list_head        active_list;
 106         struct list_head        queue;
 107         struct list_head        free_list;
 108         unsigned int            descs_allocated;
 109 };
 110
 111 #define PDC_DEV_ADDR    0x00
 112 #define PDC_MEM_ADDR    0x04
 113 #define PDC_SIZE        0x08
 114 #define PDC_NEXT        0x0C
 115
 116 #define channel_readl(pdc, name) \
 117         readl((pdc)->membase + PDC_##name)
 118 #define channel_writel(pdc, name, val) \
 119         writel((val), (pdc)->membase + PDC_##name)
 120
 121 struct pch_dma {
 122         struct dma_device       dma;
 123         void __iomem *membase;
 124         struct pci_pool         *pool;
 125         struct pch_dma_regs     regs;
 126         struct pch_dma_desc_regs ch_regs[MAX_CHAN_NR];
 127         struct pch_dma_chan     channels[MAX_CHAN_NR];
 128 };
 129
 130 #define PCH_DMA_CTL0    0x00
 131 #define PCH_DMA_CTL1    0x04
 132 #define PCH_DMA_CTL2    0x08
 133 #define PCH_DMA_STS0    0x10
 134 #define PCH_DMA_STS1    0x14
 135
 136 #define dma_readl(pd, name) \
 137         readl((pd)->membase + PCH_DMA_##name)
 138 #define dma_writel(pd, name, val) \
 139         writel((val), (pd)->membase + PCH_DMA_##name)
 140
 141 static inline
 142 struct pch_dma_desc *to_pd_desc(struct dma_async_tx_descriptor *txd)
 143 {
 144         return container_of(txd, struct pch_dma_desc, txd);
 145 }
 146
 147 static inline struct pch_dma_chan *to_pd_chan(struct dma_chan *chan)
 148 {
 149         return container_of(chan, struct pch_dma_chan, chan);
 150 }
 151
 152 static inline struct pch_dma *to_pd(struct dma_device *ddev)
 153 {
 154         return container_of(ddev, struct pch_dma, dma);
 155 }
 156
 157 static inline struct device *chan2dev(struct dma_chan *chan)
 158 {
 159         return &chan->dev->device;
 160 }
 161
 162 static inline struct device *chan2parent(struct dma_chan *chan)
 163 {
 164         return chan->dev->device.parent;
 165 }
 166
 167 static inline
 168 struct pch_dma_desc *pdc_first_active(struct pch_dma_chan *pd_chan)
 169 {
 170         return list_first_entry(&pd_chan->active_list,
 171                                 struct pch_dma_desc, desc_node);
 172 }
 173
 174 static inline
 175 struct pch_dma_desc *pdc_first_queued(struct pch_dma_chan *pd_chan)
 176 {
 177         return list_first_entry(&pd_chan->queue,
 178                                 struct pch_dma_desc, desc_node);
 179 }
 180
 181 static void pdc_enable_irq(struct dma_chan *chan, int enable)
 182 {
 183         struct pch_dma *pd = to_pd(chan->device);
 184         u32 val;
 185
 186         val = dma_readl(pd, CTL2);
 187
 188         if (enable)
 189                 val |= 0x1 << chan->chan_id;
 190         else
 191                 val &= ~(0x1 << chan->chan_id);
 192
 193         dma_writel(pd, CTL2, val);
 194
 195         dev_dbg(chan2dev(chan), "pdc_enable_irq: chan %d -> %x\n",
 196                 chan->chan_id, val);
 197 }
 198
 199 static void pdc_set_dir(struct dma_chan *chan)
 200 {
 201         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
 202         struct pch_dma *pd = to_pd(chan->device);
 203         u32 val;
 204
 205         val = dma_readl(pd, CTL0);
 206
 207         if (pd_chan->dir == DMA_TO_DEVICE)
 208                 val |= 0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id +
 209                                DMA_CTL0_DIR_SHIFT_BITS);
 210         else
 211                 val &= ~(0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id +
 212                                  DMA_CTL0_DIR_SHIFT_BITS));
 213
 214         dma_writel(pd, CTL0, val);
 215
 216         dev_dbg(chan2dev(chan), "pdc_set_dir: chan %d -> %x\n",
 217                 chan->chan_id, val);
 218 }
 219
 220 static void pdc_set_mode(struct dma_chan *chan, u32 mode)
 221 {
 222         struct pch_dma *pd = to_pd(chan->device);
 223         u32 val;
 224
 225         val = dma_readl(pd, CTL0);
 226
 227         val &= ~(DMA_CTL0_MODE_MASK_BITS <<
 228                 (DMA_CTL0_BITS_PER_CH * chan->chan_id));
 229         val |= mode << (DMA_CTL0_BITS_PER_CH * chan->chan_id);
 230
 231         dma_writel(pd, CTL0, val);
 232
 233         dev_dbg(chan2dev(chan), "pdc_set_mode: chan %d -> %x\n",
 234                 chan->chan_id, val);
 235 }
 236
 237 static u32 pdc_get_status(struct pch_dma_chan *pd_chan)
 238 {
 239         struct pch_dma *pd = to_pd(pd_chan->chan.device);
 240         u32 val;
 241
 242         val = dma_readl(pd, STS0);
 243         return DMA_STATUS_MASK_BITS & (val >> (DMA_STATUS_SHIFT_BITS +
 244                         DMA_STATUS_BITS_PER_CH * pd_chan->chan.chan_id));
 245 }
 246
 247 static bool pdc_is_idle(struct pch_dma_chan *pd_chan)
 248 {
 249         if (pdc_get_status(pd_chan) == DMA_STATUS_IDLE)
 250                 return true;
 251         else
 252                 return false;
 253 }
 254
 255 static void pdc_dostart(struct pch_dma_chan *pd_chan, struct pch_dma_desc* desc)
 256 {
 257         struct pch_dma *pd = to_pd(pd_chan->chan.device);
 258         u32 val;
 259
 260         if (!pdc_is_idle(pd_chan)) {
 261                 dev_err(chan2dev(&pd_chan->chan),
 262                         "BUG: Attempt to start non-idle channel\n");
 263                 return;
 264         }
 265
 266         dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> dev_addr: %x\n",
 267                 pd_chan->chan.chan_id, desc->regs.dev_addr);
 268         dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> mem_addr: %x\n",
 269                 pd_chan->chan.chan_id, desc->regs.mem_addr);
 270         dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> size: %x\n",
 271                 pd_chan->chan.chan_id, desc->regs.size);
 272         dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> next: %x\n",
 273                 pd_chan->chan.chan_id, desc->regs.next);
 274
 275         if (list_empty(&desc->tx_list)) {
 276                 channel_writel(pd_chan, DEV_ADDR, desc->regs.dev_addr);
 277                 channel_writel(pd_chan, MEM_ADDR, desc->regs.mem_addr);
 278                 channel_writel(pd_chan, SIZE, desc->regs.size);
 279                 channel_writel(pd_chan, NEXT, desc->regs.next);
 280                 pdc_set_mode(&pd_chan->chan, DMA_CTL0_ONESHOT);
 281         } else {
 282                 channel_writel(pd_chan, NEXT, desc->txd.phys);
 283                 pdc_set_mode(&pd_chan->chan, DMA_CTL0_SG);
 284         }
 285
 286         val = dma_readl(pd, CTL2);
 287         val |= 1 << (DMA_CTL2_START_SHIFT_BITS + pd_chan->chan.chan_id);
 288         dma_writel(pd, CTL2, val);
 289 }
 290
 291 static void pdc_chain_complete(struct pch_dma_chan *pd_chan,
 292                                struct pch_dma_desc *desc)
 293 {
 294         struct dma_async_tx_descriptor *txd = &desc->txd;
 295         dma_async_tx_callback callback = txd->callback;
 296         void *param = txd->callback_param;
 297
 298         list_splice_init(&desc->tx_list, &pd_chan->free_list);
 299         list_move(&desc->desc_node, &pd_chan->free_list);
 300
 301         if (callback)
 302                 callback(param);
 303 }
 304
 305 static void pdc_complete_all(struct pch_dma_chan *pd_chan)
 306 {
 307         struct pch_dma_desc *desc, *_d;
 308         LIST_HEAD(list);
 309
 310         BUG_ON(!pdc_is_idle(pd_chan));
 311
 312         if (!list_empty(&pd_chan->queue))
 313                 pdc_dostart(pd_chan, pdc_first_queued(pd_chan));
 314
 315         list_splice_init(&pd_chan->active_list, &list);
 316         list_splice_init(&pd_chan->queue, &pd_chan->active_list);
 317
 318         list_for_each_entry_safe(desc, _d, &list, desc_node)
 319                 pdc_chain_complete(pd_chan, desc);
 320 }
 321
 322 static void pdc_handle_error(struct pch_dma_chan *pd_chan)
 323 {
 324         struct pch_dma_desc *bad_desc;
 325
 326         bad_desc = pdc_first_active(pd_chan);
 327         list_del(&bad_desc->desc_node);
 328
 329         list_splice_init(&pd_chan->queue, pd_chan->active_list.prev);
 330
 331         if (!list_empty(&pd_chan->active_list))
 332                 pdc_dostart(pd_chan, pdc_first_active(pd_chan));
 333
 334         dev_crit(chan2dev(&pd_chan->chan), "Bad descriptor submitted\n");
 335         dev_crit(chan2dev(&pd_chan->chan), "descriptor cookie: %d\n",
 336                  bad_desc->txd.cookie);
 337
 338         pdc_chain_complete(pd_chan, bad_desc);
 339 }
 340
 341 static void pdc_advance_work(struct pch_dma_chan *pd_chan)
 342 {
 343         if (list_empty(&pd_chan->active_list) ||
 344                 list_is_singular(&pd_chan->active_list)) {
 345                 pdc_complete_all(pd_chan);
 346         } else {
 347                 pdc_chain_complete(pd_chan, pdc_first_active(pd_chan));
 348                 pdc_dostart(pd_chan, pdc_first_active(pd_chan));
 349         }
 350 }
 351
 352 static dma_cookie_t pdc_assign_cookie(struct pch_dma_chan *pd_chan,
 353                                       struct pch_dma_desc *desc)
 354 {
 355         dma_cookie_t cookie = pd_chan->chan.cookie;
 356
 357         if (++cookie < 0)
 358                 cookie = 1;
 359
 360         pd_chan->chan.cookie = cookie;
 361         desc->txd.cookie = cookie;
 362
 363         return cookie;
 364 }
 365
 366 static dma_cookie_t pd_tx_submit(struct dma_async_tx_descriptor *txd)
 367 {
 368         struct pch_dma_desc *desc = to_pd_desc(txd);
 369         struct pch_dma_chan *pd_chan = to_pd_chan(txd->chan);
 370         dma_cookie_t cookie;
 371
 372         spin_lock(&pd_chan->lock);
 373         cookie = pdc_assign_cookie(pd_chan, desc);
 374
 375         if (list_empty(&pd_chan->active_list)) {
 376                 list_add_tail(&desc->desc_node, &pd_chan->active_list);
 377                 pdc_dostart(pd_chan, desc);
 378         } else {
 379                 list_add_tail(&desc->desc_node, &pd_chan->queue);
 380         }
 381
 382         spin_unlock(&pd_chan->lock);
 383         return 0;
 384 }
 385
 386 static struct pch_dma_desc *pdc_alloc_desc(struct dma_chan *chan, gfp_t flags)
 387 {
 388         struct pch_dma_desc *desc = NULL;
 389         struct pch_dma *pd = to_pd(chan->device);
 390         dma_addr_t addr;
 391
 392         desc = pci_pool_alloc(pd->pool, flags, &addr);
 393         if (desc) {
 394                 memset(desc, 0, sizeof(struct pch_dma_desc));
 395                 INIT_LIST_HEAD(&desc->tx_list);
 396                 dma_async_tx_descriptor_init(&desc->txd, chan);
 397                 desc->txd.tx_submit = pd_tx_submit;
 398                 desc->txd.flags = DMA_CTRL_ACK;
 399                 desc->txd.phys = addr;
 400         }
 401
 402         return desc;
 403 }
 404
 405 static struct pch_dma_desc *pdc_desc_get(struct pch_dma_chan *pd_chan)
 406 {
 407         struct pch_dma_desc *desc, *_d;
 408         struct pch_dma_desc *ret = NULL;
 409         int i = 0;
 410
 411         spin_lock(&pd_chan->lock);
 412         list_for_each_entry_safe(desc, _d, &pd_chan->free_list, desc_node) {
 413                 i++;
 414                 if (async_tx_test_ack(&desc->txd)) {
 415                         list_del(&desc->desc_node);
 416                         ret = desc;
 417                         break;
 418                 }
 419                 dev_dbg(chan2dev(&pd_chan->chan), "desc %p not ACKed\n", desc);
 420         }
 421         spin_unlock(&pd_chan->lock);
 422         dev_dbg(chan2dev(&pd_chan->chan), "scanned %d descriptors\n", i);
 423
 424         if (!ret) {
 425                 ret = pdc_alloc_desc(&pd_chan->chan, GFP_NOIO);
 426                 if (ret) {
 427                         spin_lock(&pd_chan->lock);
 428                         pd_chan->descs_allocated++;
 429                         spin_unlock(&pd_chan->lock);
 430                 } else {
 431                         dev_err(chan2dev(&pd_chan->chan),
 432                                 "failed to alloc desc\n");
 433                 }
 434         }
 435
 436         return ret;
 437 }
 438
 439 static void pdc_desc_put(struct pch_dma_chan *pd_chan,
 440                          struct pch_dma_desc *desc)
 441 {
 442         if (desc) {
 443                 spin_lock(&pd_chan->lock);
 444                 list_splice_init(&desc->tx_list, &pd_chan->free_list);
 445                 list_add(&desc->desc_node, &pd_chan->free_list);
 446                 spin_unlock(&pd_chan->lock);
 447         }
 448 }
 449
 450 static int pd_alloc_chan_resources(struct dma_chan *chan)
 451 {
 452         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
 453         struct pch_dma_desc *desc;
 454         LIST_HEAD(tmp_list);
 455         int i;
 456
 457         if (!pdc_is_idle(pd_chan)) {
 458                 dev_dbg(chan2dev(chan), "DMA channel not idle ?\n");
 459                 return -EIO;
 460         }
 461
 462         if (!list_empty(&pd_chan->free_list))
 463                 return pd_chan->descs_allocated;
 464
 465         for (i = 0; i < init_nr_desc_per_channel; i++) {
 466                 desc = pdc_alloc_desc(chan, GFP_KERNEL);
 467
 468                 if (!desc) {
 469                         dev_warn(chan2dev(chan),
 470                                 "Only allocated %d initial descriptors\n", i);
 471                         break;
 472                 }
 473
 474                 list_add_tail(&desc->desc_node, &tmp_list);
 475         }
 476
 477         spin_lock_bh(&pd_chan->lock);
 478         list_splice(&tmp_list, &pd_chan->free_list);
 479         pd_chan->descs_allocated = i;
 480         pd_chan->completed_cookie = chan->cookie = 1;
 481         spin_unlock_bh(&pd_chan->lock);
 482
 483         pdc_enable_irq(chan, 1);
 484
 485         return pd_chan->descs_allocated;
 486 }
 487
 488 static void pd_free_chan_resources(struct dma_chan *chan)
 489 {
 490         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
 491         struct pch_dma *pd = to_pd(chan->device);
 492         struct pch_dma_desc *desc, *_d;
 493         LIST_HEAD(tmp_list);
 494
 495         BUG_ON(!pdc_is_idle(pd_chan));
 496         BUG_ON(!list_empty(&pd_chan->active_list));
 497         BUG_ON(!list_empty(&pd_chan->queue));
 498
 499         spin_lock_bh(&pd_chan->lock);
 500         list_splice_init(&pd_chan->free_list, &tmp_list);
 501         pd_chan->descs_allocated = 0;
 502         spin_unlock_bh(&pd_chan->lock);
 503
 504         list_for_each_entry_safe(desc, _d, &tmp_list, desc_node)
 505                 pci_pool_free(pd->pool, desc, desc->txd.phys);
 506
 507         pdc_enable_irq(chan, 0);
 508 }
 509
 510 static enum dma_status pd_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 511                                     struct dma_tx_state *txstate)
 512 {
 513         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
 514         dma_cookie_t last_used;
 515         dma_cookie_t last_completed;
 516         int ret;
 517
 518         spin_lock_bh(&pd_chan->lock);
 519         last_completed = pd_chan->completed_cookie;
 520         last_used = chan->cookie;
 521         spin_unlock_bh(&pd_chan->lock);
 522
 523         ret = dma_async_is_complete(cookie, last_completed, last_used);
 524
 525         dma_set_tx_state(txstate, last_completed, last_used, 0);
 526
 527         return ret;
 528 }
 529
 530 static void pd_issue_pending(struct dma_chan *chan)
 531 {
 532         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
 533
 534         if (pdc_is_idle(pd_chan)) {
 535                 spin_lock(&pd_chan->lock);
 536                 pdc_advance_work(pd_chan);
 537                 spin_unlock(&pd_chan->lock);
 538         }
 539 }
 540
 541 static struct dma_async_tx_descriptor *pd_prep_slave_sg(struct dma_chan *chan,
 542                         struct scatterlist *sgl, unsigned int sg_len,
 543                         enum dma_data_direction direction, unsigned long flags)
 544 {
 545         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
 546         struct pch_dma_slave *pd_slave = chan->private;
 547         struct pch_dma_desc *first = NULL;
 548         struct pch_dma_desc *prev = NULL;
 549         struct pch_dma_desc *desc = NULL;
 550         struct scatterlist *sg;
 551         dma_addr_t reg;
 552         int i;
 553
 554         if (unlikely(!sg_len)) {
 555                 dev_info(chan2dev(chan), "prep_slave_sg: length is zero!\n");
 556                 return NULL;
 557         }
 558
 559         if (direction == DMA_FROM_DEVICE)
 560                 reg = pd_slave->rx_reg;
 561         else if (direction == DMA_TO_DEVICE)
 562                 reg = pd_slave->tx_reg;
 563         else
 564                 return NULL;
 565
 566         pd_chan->dir = direction;
 567         pdc_set_dir(chan);
 568
 569         for_each_sg(sgl, sg, sg_len, i) {
 570                 desc = pdc_desc_get(pd_chan);
 571
 572                 if (!desc)
 573                         goto err_desc_get;
 574
 575                 desc->regs.dev_addr = reg;
 576                 desc->regs.mem_addr = sg_phys(sg);
 577                 desc->regs.size = sg_dma_len(sg);
 578                 desc->regs.next = DMA_DESC_FOLLOW_WITHOUT_IRQ;
 579
 580                 switch (pd_slave->width) {
 581                 case PCH_DMA_WIDTH_1_BYTE:
 582                         if (desc->regs.size > DMA_DESC_MAX_COUNT_1_BYTE)
 583                                 goto err_desc_get;
 584                         desc->regs.size |= DMA_DESC_WIDTH_1_BYTE;
 585                         break;
 586                 case PCH_DMA_WIDTH_2_BYTES:
 587                         if (desc->regs.size > DMA_DESC_MAX_COUNT_2_BYTES)
 588                                 goto err_desc_get;
 589                         desc->regs.size |= DMA_DESC_WIDTH_2_BYTES;
 590                         break;
 591                 case PCH_DMA_WIDTH_4_BYTES:
 592                         if (desc->regs.size > DMA_DESC_MAX_COUNT_4_BYTES)
 593                                 goto err_desc_get;
 594                         desc->regs.size |= DMA_DESC_WIDTH_4_BYTES;
 595                         break;
 596                 default:
 597                         goto err_desc_get;
 598                 }
 599
 600                 if (!first) {
 601                         first = desc;
 602                 } else {
 603                         prev->regs.next |= desc->txd.phys;
 604                         list_add_tail(&desc->desc_node, &first->tx_list);
 605                 }
 606
 607                 prev = desc;
 608         }
 609
 610         if (flags & DMA_PREP_INTERRUPT)
 611                 desc->regs.next = DMA_DESC_END_WITH_IRQ;
 612         else
 613                 desc->regs.next = DMA_DESC_END_WITHOUT_IRQ;
 614
 615         first->txd.cookie = -EBUSY;
 616         desc->txd.flags = flags;
 617
 618         return &first->txd;
 619
 620 err_desc_get:
 621         dev_err(chan2dev(chan), "failed to get desc or wrong parameters\n");
 622         pdc_desc_put(pd_chan, first);
 623         return NULL;
 624 }
 625
 626 static int pd_device_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 627                              unsigned long arg)
 628 {
 629         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
 630         struct pch_dma_desc *desc, *_d;
 631         LIST_HEAD(list);
 632
 633         if (cmd != DMA_TERMINATE_ALL)
 634                 return -ENXIO;
 635
 636         spin_lock_bh(&pd_chan->lock);
 637
 638         pdc_set_mode(&pd_chan->chan, DMA_CTL0_DISABLE);
 639
 640         list_splice_init(&pd_chan->active_list, &list);
 641         list_splice_init(&pd_chan->queue, &list);
 642
 643         list_for_each_entry_safe(desc, _d, &list, desc_node)
 644                 pdc_chain_complete(pd_chan, desc);
 645
 646         spin_unlock_bh(&pd_chan->lock);
 647
 648         return 0;
 649 }
 650
 651 static void pdc_tasklet(unsigned long data)
 652 {
 653         struct pch_dma_chan *pd_chan = (struct pch_dma_chan *)data;
 654         unsigned long flags;
 655
 656         if (!pdc_is_idle(pd_chan)) {
 657                 dev_err(chan2dev(&pd_chan->chan),
 658                         "BUG: handle non-idle channel in tasklet\n");
 659                 return;
 660         }
 661
 662         spin_lock_irqsave(&pd_chan->lock, flags);
 663         if (test_and_clear_bit(0, &pd_chan->err_status))
 664                 pdc_handle_error(pd_chan);
 665         else
 666                 pdc_advance_work(pd_chan);
 667         spin_unlock_irqrestore(&pd_chan->lock, flags);
 668 }
 669
 670 static irqreturn_t pd_irq(int irq, void *devid)
 671 {
 672         struct pch_dma *pd = (struct pch_dma *)devid;
 673         struct pch_dma_chan *pd_chan;
 674         u32 sts0;
 675         int i;
 676         int ret = IRQ_NONE;
 677
 678         sts0 = dma_readl(pd, STS0);
 679
 680         dev_dbg(pd->dma.dev, "pd_irq sts0: %x\n", sts0);
 681
 682         for (i = 0; i < pd->dma.chancnt; i++) {
 683                 pd_chan = &pd->channels[i];
 684
 685                 if (sts0 & DMA_STATUS_IRQ(i)) {
 686                         if (sts0 & DMA_STATUS_ERR(i))
 687                                 set_bit(0, &pd_chan->err_status);
 688
 689                         tasklet_schedule(&pd_chan->tasklet);
 690                         ret = IRQ_HANDLED;
 691                 }
 692
 693         }
 694
 695         /* clear interrupt bits in status register */
 696         dma_writel(pd, STS0, sts0);
 697
 698         return ret;
 699 }
 700
 701 #ifdef  CONFIG_PM
 702 static void pch_dma_save_regs(struct pch_dma *pd)
 703 {
 704         struct pch_dma_chan *pd_chan;
 705         struct dma_chan *chan, *_c;
 706         int i = 0;
 707
 708         pd->regs.dma_ctl0 = dma_readl(pd, CTL0);
 709         pd->regs.dma_ctl1 = dma_readl(pd, CTL1);
 710         pd->regs.dma_ctl2 = dma_readl(pd, CTL2);
 711
 712         list_for_each_entry_safe(chan, _c, &pd->dma.channels, device_node) {
 713                 pd_chan = to_pd_chan(chan);
 714
 715                 pd->ch_regs[i].dev_addr = channel_readl(pd_chan, DEV_ADDR);
 716                 pd->ch_regs[i].mem_addr = channel_readl(pd_chan, MEM_ADDR);
 717                 pd->ch_regs[i].size = channel_readl(pd_chan, SIZE);
 718                 pd->ch_regs[i].next = channel_readl(pd_chan, NEXT);
 719
 720                 i++;
 721         }
 722 }
 723
 724 static void pch_dma_restore_regs(struct pch_dma *pd)
 725 {
 726         struct pch_dma_chan *pd_chan;
 727         struct dma_chan *chan, *_c;
 728         int i = 0;
 729
 730         dma_writel(pd, CTL0, pd->regs.dma_ctl0);
 731         dma_writel(pd, CTL1, pd->regs.dma_ctl1);
 732         dma_writel(pd, CTL2, pd->regs.dma_ctl2);
 733
 734         list_for_each_entry_safe(chan, _c, &pd->dma.channels, device_node) {
 735                 pd_chan = to_pd_chan(chan);
 736
 737                 channel_writel(pd_chan, DEV_ADDR, pd->ch_regs[i].dev_addr);
 738                 channel_writel(pd_chan, MEM_ADDR, pd->ch_regs[i].mem_addr);
 739                 channel_writel(pd_chan, SIZE, pd->ch_regs[i].size);
 740                 channel_writel(pd_chan, NEXT, pd->ch_regs[i].next);
 741
 742                 i++;
 743         }
 744 }
 745
 746 static int pch_dma_suspend(struct pci_dev *pdev, pm_message_t state)
 747 {
 748         struct pch_dma *pd = pci_get_drvdata(pdev);
 749
 750         if (pd)
 751                 pch_dma_save_regs(pd);
 752
 753         pci_save_state(pdev);
 754         pci_disable_device(pdev);
 755         pci_set_power_state(pdev, pci_choose_state(pdev, state));
 756
 757         return 0;
 758 }
 759
 760 static int pch_dma_resume(struct pci_dev *pdev)
 761 {
 762         struct pch_dma *pd = pci_get_drvdata(pdev);
 763         int err;
 764
 765         pci_set_power_state(pdev, PCI_D0);
 766         pci_restore_state(pdev);
 767
 768         err = pci_enable_device(pdev);
 769         if (err) {
 770                 dev_dbg(&pdev->dev, "failed to enable device\n");
 771                 return err;
 772         }
 773
 774         if (pd)
 775                 pch_dma_restore_regs(pd);
 776
 777         return 0;
 778 }
 779 #endif
 780
 781 static int __devinit pch_dma_probe(struct pci_dev *pdev,
 782                                    const struct pci_device_id *id)
 783 {
 784         struct pch_dma *pd;
 785         struct pch_dma_regs *regs;
 786         unsigned int nr_channels;
 787         int err;
 788         int i;
 789
 790         nr_channels = id->driver_data;
 791         pd = kzalloc(sizeof(struct pch_dma)+
 792                 sizeof(struct pch_dma_chan) * nr_channels, GFP_KERNEL);
 793         if (!pd)
 794                 return -ENOMEM;
 795
 796         pci_set_drvdata(pdev, pd);
 797
 798         err = pci_enable_device(pdev);
 799         if (err) {
 800                 dev_err(&pdev->dev, "Cannot enable PCI device\n");
 801                 goto err_free_mem;
 802         }
 803
 804         if (!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
 805                 dev_err(&pdev->dev, "Cannot find proper base address\n");
 806                 goto err_disable_pdev;
 807         }
 808
 809         err = pci_request_regions(pdev, DRV_NAME);
 810         if (err) {
 811                 dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
 812                 goto err_disable_pdev;
 813         }
 814
 815         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 816         if (err) {
 817                 dev_err(&pdev->dev, "Cannot set proper DMA config\n");
 818                 goto err_free_res;
 819         }
 820
 821         regs = pd->membase = pci_iomap(pdev, 1, 0);
 822         if (!pd->membase) {
 823                 dev_err(&pdev->dev, "Cannot map MMIO registers\n");
 824                 err = -ENOMEM;
 825                 goto err_free_res;
 826         }
 827
 828         pci_set_master(pdev);
 829
 830         err = request_irq(pdev->irq, pd_irq, IRQF_SHARED, DRV_NAME, pd);
 831         if (err) {
 832                 dev_err(&pdev->dev, "Failed to request IRQ\n");
 833                 goto err_iounmap;
 834         }
 835
 836         pd->pool = pci_pool_create("pch_dma_desc_pool", pdev,
 837                                    sizeof(struct pch_dma_desc), 4, 0);
 838         if (!pd->pool) {
 839                 dev_err(&pdev->dev, "Failed to alloc DMA descriptors\n");
 840                 err = -ENOMEM;
 841                 goto err_free_irq;
 842         }
 843
 844         pd->dma.dev = &pdev->dev;
 845         pd->dma.chancnt = nr_channels;
 846
 847         INIT_LIST_HEAD(&pd->dma.channels);
 848
 849         for (i = 0; i < nr_channels; i++) {
 850                 struct pch_dma_chan *pd_chan = &pd->channels[i];
 851
 852                 pd_chan->chan.device = &pd->dma;
 853                 pd_chan->chan.cookie = 1;
 854                 pd_chan->chan.chan_id = i;
 855
 856                 pd_chan->membase = &regs->desc[i];
 857
 858                 spin_lock_init(&pd_chan->lock);
 859
 860                 INIT_LIST_HEAD(&pd_chan->active_list);
 861                 INIT_LIST_HEAD(&pd_chan->queue);
 862                 INIT_LIST_HEAD(&pd_chan->free_list);
 863
 864                 tasklet_init(&pd_chan->tasklet, pdc_tasklet,
 865                              (unsigned long)pd_chan);
 866                 list_add_tail(&pd_chan->chan.device_node, &pd->dma.channels);
 867         }
 868
 869         dma_cap_zero(pd->dma.cap_mask);
 870         dma_cap_set(DMA_PRIVATE, pd->dma.cap_mask);
 871         dma_cap_set(DMA_SLAVE, pd->dma.cap_mask);
 872
 873         pd->dma.device_alloc_chan_resources = pd_alloc_chan_resources;
 874         pd->dma.device_free_chan_resources = pd_free_chan_resources;
 875         pd->dma.device_tx_status = pd_tx_status;
 876         pd->dma.device_issue_pending = pd_issue_pending;
 877         pd->dma.device_prep_slave_sg = pd_prep_slave_sg;
 878         pd->dma.device_control = pd_device_control;
 879
 880         err = dma_async_device_register(&pd->dma);
 881         if (err) {
 882                 dev_err(&pdev->dev, "Failed to register DMA device\n");
 883                 goto err_free_pool;
 884         }
 885
 886         return 0;
 887
 888 err_free_pool:
 889         pci_pool_destroy(pd->pool);
 890 err_free_irq:
 891         free_irq(pdev->irq, pd);
 892 err_iounmap:
 893         pci_iounmap(pdev, pd->membase);
 894 err_free_res:
 895         pci_release_regions(pdev);
 896 err_disable_pdev:
 897         pci_disable_device(pdev);
 898 err_free_mem:
 899         return err;
 900 }
 901
 902 static void __devexit pch_dma_remove(struct pci_dev *pdev)
 903 {
 904         struct pch_dma *pd = pci_get_drvdata(pdev);
 905         struct pch_dma_chan *pd_chan;
 906         struct dma_chan *chan, *_c;
 907
 908         if (pd) {
 909                 dma_async_device_unregister(&pd->dma);
 910
 911                 list_for_each_entry_safe(chan, _c, &pd->dma.channels,
 912                                          device_node) {
 913                         pd_chan = to_pd_chan(chan);
 914
 915                         tasklet_disable(&pd_chan->tasklet);
 916                         tasklet_kill(&pd_chan->tasklet);
 917                 }
 918
 919                 pci_pool_destroy(pd->pool);
 920                 free_irq(pdev->irq, pd);
 921                 pci_iounmap(pdev, pd->membase);
 922                 pci_release_regions(pdev);
 923                 pci_disable_device(pdev);
 924                 kfree(pd);
 925         }
 926 }
 927
 928 /* PCI Device ID of DMA device */
 929 #define PCI_VENDOR_ID_ROHM             0x10DB
 930 #define PCI_DEVICE_ID_EG20T_PCH_DMA_8CH        0x8810
 931 #define PCI_DEVICE_ID_EG20T_PCH_DMA_4CH        0x8815
 932 #define PCI_DEVICE_ID_ML7213_DMA1_8CH   0x8026
 933 #define PCI_DEVICE_ID_ML7213_DMA2_8CH   0x802B
 934 #define PCI_DEVICE_ID_ML7213_DMA3_4CH   0x8034
 935
 936 static const struct pci_device_id pch_dma_id_table[] = {
 937         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_EG20T_PCH_DMA_8CH), 8 },
 938         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_EG20T_PCH_DMA_4CH), 4 },
 939         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA1_8CH), 8}, /* UART Video */
 940         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA2_8CH), 8}, /* PCMIF SPI */
 941         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA3_4CH), 4}, /* FPGA */
 942         { 0, },
 943 };
 944
 945 static struct pci_driver pch_dma_driver = {
 946         .name           = DRV_NAME,
 947         .id_table       = pch_dma_id_table,
 948         .probe          = pch_dma_probe,
 949         .remove         = __devexit_p(pch_dma_remove),
 950 #ifdef CONFIG_PM
 951         .suspend        = pch_dma_suspend,
 952         .resume         = pch_dma_resume,
 953 #endif
 954 };
 955
 956 static int __init pch_dma_init(void)
 957 {
 958         return pci_register_driver(&pch_dma_driver);
 959 }
 960
 961 static void __exit pch_dma_exit(void)
 962 {
 963         pci_unregister_driver(&pch_dma_driver);
 964 }
 965
 966 module_init(pch_dma_init);
 967 module_exit(pch_dma_exit);
 968
 969 MODULE_DESCRIPTION("Intel EG20T PCH / OKI SEMICONDUCTOR ML7213 IOH "
 970                    "DMA controller driver");
 971 MODULE_AUTHOR("Yong Wang <yong.y.wang@intel.com>");
 972 MODULE_LICENSE("GPL v2");