dmaengine: Add dma_client parameter to device_alloc_chan_resources
[linux-2.6.git] / drivers / dma / mv_xor.c
1 /*
2  * offload engine driver for the Marvell XOR engine
3  * Copyright (C) 2007, 2008, Marvell International Ltd.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17  */
18
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/async_tx.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/platform_device.h>
27 #include <linux/memory.h>
28 #include <asm/plat-orion/mv_xor.h>
29 #include "mv_xor.h"
30
31 static void mv_xor_issue_pending(struct dma_chan *chan);
32
33 #define to_mv_xor_chan(chan)            \
34         container_of(chan, struct mv_xor_chan, common)
35
36 #define to_mv_xor_device(dev)           \
37         container_of(dev, struct mv_xor_device, common)
38
39 #define to_mv_xor_slot(tx)              \
40         container_of(tx, struct mv_xor_desc_slot, async_tx)
41
42 static void mv_desc_init(struct mv_xor_desc_slot *desc, unsigned long flags)
43 {
44         struct mv_xor_desc *hw_desc = desc->hw_desc;
45
46         hw_desc->status = (1 << 31);
47         hw_desc->phy_next_desc = 0;
48         hw_desc->desc_command = (1 << 31);
49 }
50
51 static u32 mv_desc_get_dest_addr(struct mv_xor_desc_slot *desc)
52 {
53         struct mv_xor_desc *hw_desc = desc->hw_desc;
54         return hw_desc->phy_dest_addr;
55 }
56
57 static u32 mv_desc_get_src_addr(struct mv_xor_desc_slot *desc,
58                                 int src_idx)
59 {
60         struct mv_xor_desc *hw_desc = desc->hw_desc;
61         return hw_desc->phy_src_addr[src_idx];
62 }
63
64
65 static void mv_desc_set_byte_count(struct mv_xor_desc_slot *desc,
66                                    u32 byte_count)
67 {
68         struct mv_xor_desc *hw_desc = desc->hw_desc;
69         hw_desc->byte_count = byte_count;
70 }
71
72 static void mv_desc_set_next_desc(struct mv_xor_desc_slot *desc,
73                                   u32 next_desc_addr)
74 {
75         struct mv_xor_desc *hw_desc = desc->hw_desc;
76         BUG_ON(hw_desc->phy_next_desc);
77         hw_desc->phy_next_desc = next_desc_addr;
78 }
79
80 static void mv_desc_clear_next_desc(struct mv_xor_desc_slot *desc)
81 {
82         struct mv_xor_desc *hw_desc = desc->hw_desc;
83         hw_desc->phy_next_desc = 0;
84 }
85
86 static void mv_desc_set_block_fill_val(struct mv_xor_desc_slot *desc, u32 val)
87 {
88         desc->value = val;
89 }
90
91 static void mv_desc_set_dest_addr(struct mv_xor_desc_slot *desc,
92                                   dma_addr_t addr)
93 {
94         struct mv_xor_desc *hw_desc = desc->hw_desc;
95         hw_desc->phy_dest_addr = addr;
96 }
97
98 static int mv_chan_memset_slot_count(size_t len)
99 {
100         return 1;
101 }
102
103 #define mv_chan_memcpy_slot_count(c) mv_chan_memset_slot_count(c)
104
105 static void mv_desc_set_src_addr(struct mv_xor_desc_slot *desc,
106                                  int index, dma_addr_t addr)
107 {
108         struct mv_xor_desc *hw_desc = desc->hw_desc;
109         hw_desc->phy_src_addr[index] = addr;
110         if (desc->type == DMA_XOR)
111                 hw_desc->desc_command |= (1 << index);
112 }
113
114 static u32 mv_chan_get_current_desc(struct mv_xor_chan *chan)
115 {
116         return __raw_readl(XOR_CURR_DESC(chan));
117 }
118
119 static void mv_chan_set_next_descriptor(struct mv_xor_chan *chan,
120                                         u32 next_desc_addr)
121 {
122         __raw_writel(next_desc_addr, XOR_NEXT_DESC(chan));
123 }
124
125 static void mv_chan_set_dest_pointer(struct mv_xor_chan *chan, u32 desc_addr)
126 {
127         __raw_writel(desc_addr, XOR_DEST_POINTER(chan));
128 }
129
130 static void mv_chan_set_block_size(struct mv_xor_chan *chan, u32 block_size)
131 {
132         __raw_writel(block_size, XOR_BLOCK_SIZE(chan));
133 }
134
135 static void mv_chan_set_value(struct mv_xor_chan *chan, u32 value)
136 {
137         __raw_writel(value, XOR_INIT_VALUE_LOW(chan));
138         __raw_writel(value, XOR_INIT_VALUE_HIGH(chan));
139 }
140
141 static void mv_chan_unmask_interrupts(struct mv_xor_chan *chan)
142 {
143         u32 val = __raw_readl(XOR_INTR_MASK(chan));
144         val |= XOR_INTR_MASK_VALUE << (chan->idx * 16);
145         __raw_writel(val, XOR_INTR_MASK(chan));
146 }
147
148 static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan)
149 {
150         u32 intr_cause = __raw_readl(XOR_INTR_CAUSE(chan));
151         intr_cause = (intr_cause >> (chan->idx * 16)) & 0xFFFF;
152         return intr_cause;
153 }
154
155 static int mv_is_err_intr(u32 intr_cause)
156 {
157         if (intr_cause & ((1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<9)))
158                 return 1;
159
160         return 0;
161 }
162
163 static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan)
164 {
165         u32 val = (1 << (1 + (chan->idx * 16)));
166         dev_dbg(chan->device->common.dev, "%s, val 0x%08x\n", __func__, val);
167         __raw_writel(val, XOR_INTR_CAUSE(chan));
168 }
169
170 static void mv_xor_device_clear_err_status(struct mv_xor_chan *chan)
171 {
172         u32 val = 0xFFFF0000 >> (chan->idx * 16);
173         __raw_writel(val, XOR_INTR_CAUSE(chan));
174 }
175
176 static int mv_can_chain(struct mv_xor_desc_slot *desc)
177 {
178         struct mv_xor_desc_slot *chain_old_tail = list_entry(
179                 desc->chain_node.prev, struct mv_xor_desc_slot, chain_node);
180
181         if (chain_old_tail->type != desc->type)
182                 return 0;
183         if (desc->type == DMA_MEMSET)
184                 return 0;
185
186         return 1;
187 }
188
189 static void mv_set_mode(struct mv_xor_chan *chan,
190                                enum dma_transaction_type type)
191 {
192         u32 op_mode;
193         u32 config = __raw_readl(XOR_CONFIG(chan));
194
195         switch (type) {
196         case DMA_XOR:
197                 op_mode = XOR_OPERATION_MODE_XOR;
198                 break;
199         case DMA_MEMCPY:
200                 op_mode = XOR_OPERATION_MODE_MEMCPY;
201                 break;
202         case DMA_MEMSET:
203                 op_mode = XOR_OPERATION_MODE_MEMSET;
204                 break;
205         default:
206                 dev_printk(KERN_ERR, chan->device->common.dev,
207                            "error: unsupported operation %d.\n",
208                            type);
209                 BUG();
210                 return;
211         }
212
213         config &= ~0x7;
214         config |= op_mode;
215         __raw_writel(config, XOR_CONFIG(chan));
216         chan->current_type = type;
217 }
218
219 static void mv_chan_activate(struct mv_xor_chan *chan)
220 {
221         u32 activation;
222
223         dev_dbg(chan->device->common.dev, " activate chan.\n");
224         activation = __raw_readl(XOR_ACTIVATION(chan));
225         activation |= 0x1;
226         __raw_writel(activation, XOR_ACTIVATION(chan));
227 }
228
229 static char mv_chan_is_busy(struct mv_xor_chan *chan)
230 {
231         u32 state = __raw_readl(XOR_ACTIVATION(chan));
232
233         state = (state >> 4) & 0x3;
234
235         return (state == 1) ? 1 : 0;
236 }
237
238 static int mv_chan_xor_slot_count(size_t len, int src_cnt)
239 {
240         return 1;
241 }
242
243 /**
244  * mv_xor_free_slots - flags descriptor slots for reuse
245  * @slot: Slot to free
246  * Caller must hold &mv_chan->lock while calling this function
247  */
248 static void mv_xor_free_slots(struct mv_xor_chan *mv_chan,
249                               struct mv_xor_desc_slot *slot)
250 {
251         dev_dbg(mv_chan->device->common.dev, "%s %d slot %p\n",
252                 __func__, __LINE__, slot);
253
254         slot->slots_per_op = 0;
255
256 }
257
258 /*
259  * mv_xor_start_new_chain - program the engine to operate on new chain headed by
260  * sw_desc
261  * Caller must hold &mv_chan->lock while calling this function
262  */
263 static void mv_xor_start_new_chain(struct mv_xor_chan *mv_chan,
264                                    struct mv_xor_desc_slot *sw_desc)
265 {
266         dev_dbg(mv_chan->device->common.dev, "%s %d: sw_desc %p\n",
267                 __func__, __LINE__, sw_desc);
268         if (sw_desc->type != mv_chan->current_type)
269                 mv_set_mode(mv_chan, sw_desc->type);
270
271         if (sw_desc->type == DMA_MEMSET) {
272                 /* for memset requests we need to program the engine, no
273                  * descriptors used.
274                  */
275                 struct mv_xor_desc *hw_desc = sw_desc->hw_desc;
276                 mv_chan_set_dest_pointer(mv_chan, hw_desc->phy_dest_addr);
277                 mv_chan_set_block_size(mv_chan, sw_desc->unmap_len);
278                 mv_chan_set_value(mv_chan, sw_desc->value);
279         } else {
280                 /* set the hardware chain */
281                 mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys);
282         }
283         mv_chan->pending += sw_desc->slot_cnt;
284         mv_xor_issue_pending(&mv_chan->common);
285 }
286
287 static dma_cookie_t
288 mv_xor_run_tx_complete_actions(struct mv_xor_desc_slot *desc,
289         struct mv_xor_chan *mv_chan, dma_cookie_t cookie)
290 {
291         BUG_ON(desc->async_tx.cookie < 0);
292
293         if (desc->async_tx.cookie > 0) {
294                 cookie = desc->async_tx.cookie;
295
296                 /* call the callback (must not sleep or submit new
297                  * operations to this channel)
298                  */
299                 if (desc->async_tx.callback)
300                         desc->async_tx.callback(
301                                 desc->async_tx.callback_param);
302
303                 /* unmap dma addresses
304                  * (unmap_single vs unmap_page?)
305                  */
306                 if (desc->group_head && desc->unmap_len) {
307                         struct mv_xor_desc_slot *unmap = desc->group_head;
308                         struct device *dev =
309                                 &mv_chan->device->pdev->dev;
310                         u32 len = unmap->unmap_len;
311                         u32 src_cnt = unmap->unmap_src_cnt;
312                         dma_addr_t addr = mv_desc_get_dest_addr(unmap);
313
314                         dma_unmap_page(dev, addr, len, DMA_FROM_DEVICE);
315                         while (src_cnt--) {
316                                 addr = mv_desc_get_src_addr(unmap, src_cnt);
317                                 dma_unmap_page(dev, addr, len, DMA_TO_DEVICE);
318                         }
319                         desc->group_head = NULL;
320                 }
321         }
322
323         /* run dependent operations */
324         async_tx_run_dependencies(&desc->async_tx);
325
326         return cookie;
327 }
328
329 static int
330 mv_xor_clean_completed_slots(struct mv_xor_chan *mv_chan)
331 {
332         struct mv_xor_desc_slot *iter, *_iter;
333
334         dev_dbg(mv_chan->device->common.dev, "%s %d\n", __func__, __LINE__);
335         list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
336                                  completed_node) {
337
338                 if (async_tx_test_ack(&iter->async_tx)) {
339                         list_del(&iter->completed_node);
340                         mv_xor_free_slots(mv_chan, iter);
341                 }
342         }
343         return 0;
344 }
345
346 static int
347 mv_xor_clean_slot(struct mv_xor_desc_slot *desc,
348         struct mv_xor_chan *mv_chan)
349 {
350         dev_dbg(mv_chan->device->common.dev, "%s %d: desc %p flags %d\n",
351                 __func__, __LINE__, desc, desc->async_tx.flags);
352         list_del(&desc->chain_node);
353         /* the client is allowed to attach dependent operations
354          * until 'ack' is set
355          */
356         if (!async_tx_test_ack(&desc->async_tx)) {
357                 /* move this slot to the completed_slots */
358                 list_add_tail(&desc->completed_node, &mv_chan->completed_slots);
359                 return 0;
360         }
361
362         mv_xor_free_slots(mv_chan, desc);
363         return 0;
364 }
365
366 static void __mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan)
367 {
368         struct mv_xor_desc_slot *iter, *_iter;
369         dma_cookie_t cookie = 0;
370         int busy = mv_chan_is_busy(mv_chan);
371         u32 current_desc = mv_chan_get_current_desc(mv_chan);
372         int seen_current = 0;
373
374         dev_dbg(mv_chan->device->common.dev, "%s %d\n", __func__, __LINE__);
375         dev_dbg(mv_chan->device->common.dev, "current_desc %x\n", current_desc);
376         mv_xor_clean_completed_slots(mv_chan);
377
378         /* free completed slots from the chain starting with
379          * the oldest descriptor
380          */
381
382         list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
383                                         chain_node) {
384                 prefetch(_iter);
385                 prefetch(&_iter->async_tx);
386
387                 /* do not advance past the current descriptor loaded into the
388                  * hardware channel, subsequent descriptors are either in
389                  * process or have not been submitted
390                  */
391                 if (seen_current)
392                         break;
393
394                 /* stop the search if we reach the current descriptor and the
395                  * channel is busy
396                  */
397                 if (iter->async_tx.phys == current_desc) {
398                         seen_current = 1;
399                         if (busy)
400                                 break;
401                 }
402
403                 cookie = mv_xor_run_tx_complete_actions(iter, mv_chan, cookie);
404
405                 if (mv_xor_clean_slot(iter, mv_chan))
406                         break;
407         }
408
409         if ((busy == 0) && !list_empty(&mv_chan->chain)) {
410                 struct mv_xor_desc_slot *chain_head;
411                 chain_head = list_entry(mv_chan->chain.next,
412                                         struct mv_xor_desc_slot,
413                                         chain_node);
414
415                 mv_xor_start_new_chain(mv_chan, chain_head);
416         }
417
418         if (cookie > 0)
419                 mv_chan->completed_cookie = cookie;
420 }
421
422 static void
423 mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan)
424 {
425         spin_lock_bh(&mv_chan->lock);
426         __mv_xor_slot_cleanup(mv_chan);
427         spin_unlock_bh(&mv_chan->lock);
428 }
429
430 static void mv_xor_tasklet(unsigned long data)
431 {
432         struct mv_xor_chan *chan = (struct mv_xor_chan *) data;
433         __mv_xor_slot_cleanup(chan);
434 }
435
436 static struct mv_xor_desc_slot *
437 mv_xor_alloc_slots(struct mv_xor_chan *mv_chan, int num_slots,
438                     int slots_per_op)
439 {
440         struct mv_xor_desc_slot *iter, *_iter, *alloc_start = NULL;
441         LIST_HEAD(chain);
442         int slots_found, retry = 0;
443
444         /* start search from the last allocated descrtiptor
445          * if a contiguous allocation can not be found start searching
446          * from the beginning of the list
447          */
448 retry:
449         slots_found = 0;
450         if (retry == 0)
451                 iter = mv_chan->last_used;
452         else
453                 iter = list_entry(&mv_chan->all_slots,
454                         struct mv_xor_desc_slot,
455                         slot_node);
456
457         list_for_each_entry_safe_continue(
458                 iter, _iter, &mv_chan->all_slots, slot_node) {
459                 prefetch(_iter);
460                 prefetch(&_iter->async_tx);
461                 if (iter->slots_per_op) {
462                         /* give up after finding the first busy slot
463                          * on the second pass through the list
464                          */
465                         if (retry)
466                                 break;
467
468                         slots_found = 0;
469                         continue;
470                 }
471
472                 /* start the allocation if the slot is correctly aligned */
473                 if (!slots_found++)
474                         alloc_start = iter;
475
476                 if (slots_found == num_slots) {
477                         struct mv_xor_desc_slot *alloc_tail = NULL;
478                         struct mv_xor_desc_slot *last_used = NULL;
479                         iter = alloc_start;
480                         while (num_slots) {
481                                 int i;
482
483                                 /* pre-ack all but the last descriptor */
484                                 async_tx_ack(&iter->async_tx);
485
486                                 list_add_tail(&iter->chain_node, &chain);
487                                 alloc_tail = iter;
488                                 iter->async_tx.cookie = 0;
489                                 iter->slot_cnt = num_slots;
490                                 iter->xor_check_result = NULL;
491                                 for (i = 0; i < slots_per_op; i++) {
492                                         iter->slots_per_op = slots_per_op - i;
493                                         last_used = iter;
494                                         iter = list_entry(iter->slot_node.next,
495                                                 struct mv_xor_desc_slot,
496                                                 slot_node);
497                                 }
498                                 num_slots -= slots_per_op;
499                         }
500                         alloc_tail->group_head = alloc_start;
501                         alloc_tail->async_tx.cookie = -EBUSY;
502                         list_splice(&chain, &alloc_tail->async_tx.tx_list);
503                         mv_chan->last_used = last_used;
504                         mv_desc_clear_next_desc(alloc_start);
505                         mv_desc_clear_next_desc(alloc_tail);
506                         return alloc_tail;
507                 }
508         }
509         if (!retry++)
510                 goto retry;
511
512         /* try to free some slots if the allocation fails */
513         tasklet_schedule(&mv_chan->irq_tasklet);
514
515         return NULL;
516 }
517
518 static dma_cookie_t
519 mv_desc_assign_cookie(struct mv_xor_chan *mv_chan,
520                       struct mv_xor_desc_slot *desc)
521 {
522         dma_cookie_t cookie = mv_chan->common.cookie;
523
524         if (++cookie < 0)
525                 cookie = 1;
526         mv_chan->common.cookie = desc->async_tx.cookie = cookie;
527         return cookie;
528 }
529
530 /************************ DMA engine API functions ****************************/
531 static dma_cookie_t
532 mv_xor_tx_submit(struct dma_async_tx_descriptor *tx)
533 {
534         struct mv_xor_desc_slot *sw_desc = to_mv_xor_slot(tx);
535         struct mv_xor_chan *mv_chan = to_mv_xor_chan(tx->chan);
536         struct mv_xor_desc_slot *grp_start, *old_chain_tail;
537         dma_cookie_t cookie;
538         int new_hw_chain = 1;
539
540         dev_dbg(mv_chan->device->common.dev,
541                 "%s sw_desc %p: async_tx %p\n",
542                 __func__, sw_desc, &sw_desc->async_tx);
543
544         grp_start = sw_desc->group_head;
545
546         spin_lock_bh(&mv_chan->lock);
547         cookie = mv_desc_assign_cookie(mv_chan, sw_desc);
548
549         if (list_empty(&mv_chan->chain))
550                 list_splice_init(&sw_desc->async_tx.tx_list, &mv_chan->chain);
551         else {
552                 new_hw_chain = 0;
553
554                 old_chain_tail = list_entry(mv_chan->chain.prev,
555                                             struct mv_xor_desc_slot,
556                                             chain_node);
557                 list_splice_init(&grp_start->async_tx.tx_list,
558                                  &old_chain_tail->chain_node);
559
560                 if (!mv_can_chain(grp_start))
561                         goto submit_done;
562
563                 dev_dbg(mv_chan->device->common.dev, "Append to last desc %x\n",
564                         old_chain_tail->async_tx.phys);
565
566                 /* fix up the hardware chain */
567                 mv_desc_set_next_desc(old_chain_tail, grp_start->async_tx.phys);
568
569                 /* if the channel is not busy */
570                 if (!mv_chan_is_busy(mv_chan)) {
571                         u32 current_desc = mv_chan_get_current_desc(mv_chan);
572                         /*
573                          * and the curren desc is the end of the chain before
574                          * the append, then we need to start the channel
575                          */
576                         if (current_desc == old_chain_tail->async_tx.phys)
577                                 new_hw_chain = 1;
578                 }
579         }
580
581         if (new_hw_chain)
582                 mv_xor_start_new_chain(mv_chan, grp_start);
583
584 submit_done:
585         spin_unlock_bh(&mv_chan->lock);
586
587         return cookie;
588 }
589
590 /* returns the number of allocated descriptors */
591 static int mv_xor_alloc_chan_resources(struct dma_chan *chan,
592                                        struct dma_client *client)
593 {
594         char *hw_desc;
595         int idx;
596         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
597         struct mv_xor_desc_slot *slot = NULL;
598         struct mv_xor_platform_data *plat_data =
599                 mv_chan->device->pdev->dev.platform_data;
600         int num_descs_in_pool = plat_data->pool_size/MV_XOR_SLOT_SIZE;
601
602         /* Allocate descriptor slots */
603         idx = mv_chan->slots_allocated;
604         while (idx < num_descs_in_pool) {
605                 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
606                 if (!slot) {
607                         printk(KERN_INFO "MV XOR Channel only initialized"
608                                 " %d descriptor slots", idx);
609                         break;
610                 }
611                 hw_desc = (char *) mv_chan->device->dma_desc_pool_virt;
612                 slot->hw_desc = (void *) &hw_desc[idx * MV_XOR_SLOT_SIZE];
613
614                 dma_async_tx_descriptor_init(&slot->async_tx, chan);
615                 slot->async_tx.tx_submit = mv_xor_tx_submit;
616                 INIT_LIST_HEAD(&slot->chain_node);
617                 INIT_LIST_HEAD(&slot->slot_node);
618                 INIT_LIST_HEAD(&slot->async_tx.tx_list);
619                 hw_desc = (char *) mv_chan->device->dma_desc_pool;
620                 slot->async_tx.phys =
621                         (dma_addr_t) &hw_desc[idx * MV_XOR_SLOT_SIZE];
622                 slot->idx = idx++;
623
624                 spin_lock_bh(&mv_chan->lock);
625                 mv_chan->slots_allocated = idx;
626                 list_add_tail(&slot->slot_node, &mv_chan->all_slots);
627                 spin_unlock_bh(&mv_chan->lock);
628         }
629
630         if (mv_chan->slots_allocated && !mv_chan->last_used)
631                 mv_chan->last_used = list_entry(mv_chan->all_slots.next,
632                                         struct mv_xor_desc_slot,
633                                         slot_node);
634
635         dev_dbg(mv_chan->device->common.dev,
636                 "allocated %d descriptor slots last_used: %p\n",
637                 mv_chan->slots_allocated, mv_chan->last_used);
638
639         return mv_chan->slots_allocated ? : -ENOMEM;
640 }
641
642 static struct dma_async_tx_descriptor *
643 mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
644                 size_t len, unsigned long flags)
645 {
646         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
647         struct mv_xor_desc_slot *sw_desc, *grp_start;
648         int slot_cnt;
649
650         dev_dbg(mv_chan->device->common.dev,
651                 "%s dest: %x src %x len: %u flags: %ld\n",
652                 __func__, dest, src, len, flags);
653         if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
654                 return NULL;
655
656         BUG_ON(unlikely(len > MV_XOR_MAX_BYTE_COUNT));
657
658         spin_lock_bh(&mv_chan->lock);
659         slot_cnt = mv_chan_memcpy_slot_count(len);
660         sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1);
661         if (sw_desc) {
662                 sw_desc->type = DMA_MEMCPY;
663                 sw_desc->async_tx.flags = flags;
664                 grp_start = sw_desc->group_head;
665                 mv_desc_init(grp_start, flags);
666                 mv_desc_set_byte_count(grp_start, len);
667                 mv_desc_set_dest_addr(sw_desc->group_head, dest);
668                 mv_desc_set_src_addr(grp_start, 0, src);
669                 sw_desc->unmap_src_cnt = 1;
670                 sw_desc->unmap_len = len;
671         }
672         spin_unlock_bh(&mv_chan->lock);
673
674         dev_dbg(mv_chan->device->common.dev,
675                 "%s sw_desc %p async_tx %p\n",
676                 __func__, sw_desc, sw_desc ? &sw_desc->async_tx : 0);
677
678         return sw_desc ? &sw_desc->async_tx : NULL;
679 }
680
681 static struct dma_async_tx_descriptor *
682 mv_xor_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value,
683                        size_t len, unsigned long flags)
684 {
685         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
686         struct mv_xor_desc_slot *sw_desc, *grp_start;
687         int slot_cnt;
688
689         dev_dbg(mv_chan->device->common.dev,
690                 "%s dest: %x len: %u flags: %ld\n",
691                 __func__, dest, len, flags);
692         if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
693                 return NULL;
694
695         BUG_ON(unlikely(len > MV_XOR_MAX_BYTE_COUNT));
696
697         spin_lock_bh(&mv_chan->lock);
698         slot_cnt = mv_chan_memset_slot_count(len);
699         sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1);
700         if (sw_desc) {
701                 sw_desc->type = DMA_MEMSET;
702                 sw_desc->async_tx.flags = flags;
703                 grp_start = sw_desc->group_head;
704                 mv_desc_init(grp_start, flags);
705                 mv_desc_set_byte_count(grp_start, len);
706                 mv_desc_set_dest_addr(sw_desc->group_head, dest);
707                 mv_desc_set_block_fill_val(grp_start, value);
708                 sw_desc->unmap_src_cnt = 1;
709                 sw_desc->unmap_len = len;
710         }
711         spin_unlock_bh(&mv_chan->lock);
712         dev_dbg(mv_chan->device->common.dev,
713                 "%s sw_desc %p async_tx %p \n",
714                 __func__, sw_desc, &sw_desc->async_tx);
715         return sw_desc ? &sw_desc->async_tx : NULL;
716 }
717
718 static struct dma_async_tx_descriptor *
719 mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
720                     unsigned int src_cnt, size_t len, unsigned long flags)
721 {
722         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
723         struct mv_xor_desc_slot *sw_desc, *grp_start;
724         int slot_cnt;
725
726         if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
727                 return NULL;
728
729         BUG_ON(unlikely(len > MV_XOR_MAX_BYTE_COUNT));
730
731         dev_dbg(mv_chan->device->common.dev,
732                 "%s src_cnt: %d len: dest %x %u flags: %ld\n",
733                 __func__, src_cnt, len, dest, flags);
734
735         spin_lock_bh(&mv_chan->lock);
736         slot_cnt = mv_chan_xor_slot_count(len, src_cnt);
737         sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1);
738         if (sw_desc) {
739                 sw_desc->type = DMA_XOR;
740                 sw_desc->async_tx.flags = flags;
741                 grp_start = sw_desc->group_head;
742                 mv_desc_init(grp_start, flags);
743                 /* the byte count field is the same as in memcpy desc*/
744                 mv_desc_set_byte_count(grp_start, len);
745                 mv_desc_set_dest_addr(sw_desc->group_head, dest);
746                 sw_desc->unmap_src_cnt = src_cnt;
747                 sw_desc->unmap_len = len;
748                 while (src_cnt--)
749                         mv_desc_set_src_addr(grp_start, src_cnt, src[src_cnt]);
750         }
751         spin_unlock_bh(&mv_chan->lock);
752         dev_dbg(mv_chan->device->common.dev,
753                 "%s sw_desc %p async_tx %p \n",
754                 __func__, sw_desc, &sw_desc->async_tx);
755         return sw_desc ? &sw_desc->async_tx : NULL;
756 }
757
758 static void mv_xor_free_chan_resources(struct dma_chan *chan)
759 {
760         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
761         struct mv_xor_desc_slot *iter, *_iter;
762         int in_use_descs = 0;
763
764         mv_xor_slot_cleanup(mv_chan);
765
766         spin_lock_bh(&mv_chan->lock);
767         list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
768                                         chain_node) {
769                 in_use_descs++;
770                 list_del(&iter->chain_node);
771         }
772         list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
773                                  completed_node) {
774                 in_use_descs++;
775                 list_del(&iter->completed_node);
776         }
777         list_for_each_entry_safe_reverse(
778                 iter, _iter, &mv_chan->all_slots, slot_node) {
779                 list_del(&iter->slot_node);
780                 kfree(iter);
781                 mv_chan->slots_allocated--;
782         }
783         mv_chan->last_used = NULL;
784
785         dev_dbg(mv_chan->device->common.dev, "%s slots_allocated %d\n",
786                 __func__, mv_chan->slots_allocated);
787         spin_unlock_bh(&mv_chan->lock);
788
789         if (in_use_descs)
790                 dev_err(mv_chan->device->common.dev,
791                         "freeing %d in use descriptors!\n", in_use_descs);
792 }
793
794 /**
795  * mv_xor_is_complete - poll the status of an XOR transaction
796  * @chan: XOR channel handle
797  * @cookie: XOR transaction identifier
798  */
799 static enum dma_status mv_xor_is_complete(struct dma_chan *chan,
800                                           dma_cookie_t cookie,
801                                           dma_cookie_t *done,
802                                           dma_cookie_t *used)
803 {
804         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
805         dma_cookie_t last_used;
806         dma_cookie_t last_complete;
807         enum dma_status ret;
808
809         last_used = chan->cookie;
810         last_complete = mv_chan->completed_cookie;
811         mv_chan->is_complete_cookie = cookie;
812         if (done)
813                 *done = last_complete;
814         if (used)
815                 *used = last_used;
816
817         ret = dma_async_is_complete(cookie, last_complete, last_used);
818         if (ret == DMA_SUCCESS) {
819                 mv_xor_clean_completed_slots(mv_chan);
820                 return ret;
821         }
822         mv_xor_slot_cleanup(mv_chan);
823
824         last_used = chan->cookie;
825         last_complete = mv_chan->completed_cookie;
826
827         if (done)
828                 *done = last_complete;
829         if (used)
830                 *used = last_used;
831
832         return dma_async_is_complete(cookie, last_complete, last_used);
833 }
834
835 static void mv_dump_xor_regs(struct mv_xor_chan *chan)
836 {
837         u32 val;
838
839         val = __raw_readl(XOR_CONFIG(chan));
840         dev_printk(KERN_ERR, chan->device->common.dev,
841                    "config       0x%08x.\n", val);
842
843         val = __raw_readl(XOR_ACTIVATION(chan));
844         dev_printk(KERN_ERR, chan->device->common.dev,
845                    "activation   0x%08x.\n", val);
846
847         val = __raw_readl(XOR_INTR_CAUSE(chan));
848         dev_printk(KERN_ERR, chan->device->common.dev,
849                    "intr cause   0x%08x.\n", val);
850
851         val = __raw_readl(XOR_INTR_MASK(chan));
852         dev_printk(KERN_ERR, chan->device->common.dev,
853                    "intr mask    0x%08x.\n", val);
854
855         val = __raw_readl(XOR_ERROR_CAUSE(chan));
856         dev_printk(KERN_ERR, chan->device->common.dev,
857                    "error cause  0x%08x.\n", val);
858
859         val = __raw_readl(XOR_ERROR_ADDR(chan));
860         dev_printk(KERN_ERR, chan->device->common.dev,
861                    "error addr   0x%08x.\n", val);
862 }
863
864 static void mv_xor_err_interrupt_handler(struct mv_xor_chan *chan,
865                                          u32 intr_cause)
866 {
867         if (intr_cause & (1 << 4)) {
868              dev_dbg(chan->device->common.dev,
869                      "ignore this error\n");
870              return;
871         }
872
873         dev_printk(KERN_ERR, chan->device->common.dev,
874                    "error on chan %d. intr cause 0x%08x.\n",
875                    chan->idx, intr_cause);
876
877         mv_dump_xor_regs(chan);
878         BUG();
879 }
880
881 static irqreturn_t mv_xor_interrupt_handler(int irq, void *data)
882 {
883         struct mv_xor_chan *chan = data;
884         u32 intr_cause = mv_chan_get_intr_cause(chan);
885
886         dev_dbg(chan->device->common.dev, "intr cause %x\n", intr_cause);
887
888         if (mv_is_err_intr(intr_cause))
889                 mv_xor_err_interrupt_handler(chan, intr_cause);
890
891         tasklet_schedule(&chan->irq_tasklet);
892
893         mv_xor_device_clear_eoc_cause(chan);
894
895         return IRQ_HANDLED;
896 }
897
898 static void mv_xor_issue_pending(struct dma_chan *chan)
899 {
900         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
901
902         if (mv_chan->pending >= MV_XOR_THRESHOLD) {
903                 mv_chan->pending = 0;
904                 mv_chan_activate(mv_chan);
905         }
906 }
907
908 /*
909  * Perform a transaction to verify the HW works.
910  */
911 #define MV_XOR_TEST_SIZE 2000
912
913 static int __devinit mv_xor_memcpy_self_test(struct mv_xor_device *device)
914 {
915         int i;
916         void *src, *dest;
917         dma_addr_t src_dma, dest_dma;
918         struct dma_chan *dma_chan;
919         dma_cookie_t cookie;
920         struct dma_async_tx_descriptor *tx;
921         int err = 0;
922         struct mv_xor_chan *mv_chan;
923
924         src = kmalloc(sizeof(u8) * MV_XOR_TEST_SIZE, GFP_KERNEL);
925         if (!src)
926                 return -ENOMEM;
927
928         dest = kzalloc(sizeof(u8) * MV_XOR_TEST_SIZE, GFP_KERNEL);
929         if (!dest) {
930                 kfree(src);
931                 return -ENOMEM;
932         }
933
934         /* Fill in src buffer */
935         for (i = 0; i < MV_XOR_TEST_SIZE; i++)
936                 ((u8 *) src)[i] = (u8)i;
937
938         /* Start copy, using first DMA channel */
939         dma_chan = container_of(device->common.channels.next,
940                                 struct dma_chan,
941                                 device_node);
942         if (mv_xor_alloc_chan_resources(dma_chan, NULL) < 1) {
943                 err = -ENODEV;
944                 goto out;
945         }
946
947         dest_dma = dma_map_single(dma_chan->device->dev, dest,
948                                   MV_XOR_TEST_SIZE, DMA_FROM_DEVICE);
949
950         src_dma = dma_map_single(dma_chan->device->dev, src,
951                                  MV_XOR_TEST_SIZE, DMA_TO_DEVICE);
952
953         tx = mv_xor_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
954                                     MV_XOR_TEST_SIZE, 0);
955         cookie = mv_xor_tx_submit(tx);
956         mv_xor_issue_pending(dma_chan);
957         async_tx_ack(tx);
958         msleep(1);
959
960         if (mv_xor_is_complete(dma_chan, cookie, NULL, NULL) !=
961             DMA_SUCCESS) {
962                 dev_printk(KERN_ERR, dma_chan->device->dev,
963                            "Self-test copy timed out, disabling\n");
964                 err = -ENODEV;
965                 goto free_resources;
966         }
967
968         mv_chan = to_mv_xor_chan(dma_chan);
969         dma_sync_single_for_cpu(&mv_chan->device->pdev->dev, dest_dma,
970                                 MV_XOR_TEST_SIZE, DMA_FROM_DEVICE);
971         if (memcmp(src, dest, MV_XOR_TEST_SIZE)) {
972                 dev_printk(KERN_ERR, dma_chan->device->dev,
973                            "Self-test copy failed compare, disabling\n");
974                 err = -ENODEV;
975                 goto free_resources;
976         }
977
978 free_resources:
979         mv_xor_free_chan_resources(dma_chan);
980 out:
981         kfree(src);
982         kfree(dest);
983         return err;
984 }
985
986 #define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */
987 static int __devinit
988 mv_xor_xor_self_test(struct mv_xor_device *device)
989 {
990         int i, src_idx;
991         struct page *dest;
992         struct page *xor_srcs[MV_XOR_NUM_SRC_TEST];
993         dma_addr_t dma_srcs[MV_XOR_NUM_SRC_TEST];
994         dma_addr_t dest_dma;
995         struct dma_async_tx_descriptor *tx;
996         struct dma_chan *dma_chan;
997         dma_cookie_t cookie;
998         u8 cmp_byte = 0;
999         u32 cmp_word;
1000         int err = 0;
1001         struct mv_xor_chan *mv_chan;
1002
1003         for (src_idx = 0; src_idx < MV_XOR_NUM_SRC_TEST; src_idx++) {
1004                 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
1005                 if (!xor_srcs[src_idx])
1006                         while (src_idx--) {
1007                                 __free_page(xor_srcs[src_idx]);
1008                                 return -ENOMEM;
1009                         }
1010         }
1011
1012         dest = alloc_page(GFP_KERNEL);
1013         if (!dest)
1014                 while (src_idx--) {
1015                         __free_page(xor_srcs[src_idx]);
1016                         return -ENOMEM;
1017                 }
1018
1019         /* Fill in src buffers */
1020         for (src_idx = 0; src_idx < MV_XOR_NUM_SRC_TEST; src_idx++) {
1021                 u8 *ptr = page_address(xor_srcs[src_idx]);
1022                 for (i = 0; i < PAGE_SIZE; i++)
1023                         ptr[i] = (1 << src_idx);
1024         }
1025
1026         for (src_idx = 0; src_idx < MV_XOR_NUM_SRC_TEST; src_idx++)
1027                 cmp_byte ^= (u8) (1 << src_idx);
1028
1029         cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
1030                 (cmp_byte << 8) | cmp_byte;
1031
1032         memset(page_address(dest), 0, PAGE_SIZE);
1033
1034         dma_chan = container_of(device->common.channels.next,
1035                                 struct dma_chan,
1036                                 device_node);
1037         if (mv_xor_alloc_chan_resources(dma_chan, NULL) < 1) {
1038                 err = -ENODEV;
1039                 goto out;
1040         }
1041
1042         /* test xor */
1043         dest_dma = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE,
1044                                 DMA_FROM_DEVICE);
1045
1046         for (i = 0; i < MV_XOR_NUM_SRC_TEST; i++)
1047                 dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
1048                                            0, PAGE_SIZE, DMA_TO_DEVICE);
1049
1050         tx = mv_xor_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
1051                                  MV_XOR_NUM_SRC_TEST, PAGE_SIZE, 0);
1052
1053         cookie = mv_xor_tx_submit(tx);
1054         mv_xor_issue_pending(dma_chan);
1055         async_tx_ack(tx);
1056         msleep(8);
1057
1058         if (mv_xor_is_complete(dma_chan, cookie, NULL, NULL) !=
1059             DMA_SUCCESS) {
1060                 dev_printk(KERN_ERR, dma_chan->device->dev,
1061                            "Self-test xor timed out, disabling\n");
1062                 err = -ENODEV;
1063                 goto free_resources;
1064         }
1065
1066         mv_chan = to_mv_xor_chan(dma_chan);
1067         dma_sync_single_for_cpu(&mv_chan->device->pdev->dev, dest_dma,
1068                                 PAGE_SIZE, DMA_FROM_DEVICE);
1069         for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
1070                 u32 *ptr = page_address(dest);
1071                 if (ptr[i] != cmp_word) {
1072                         dev_printk(KERN_ERR, dma_chan->device->dev,
1073                                    "Self-test xor failed compare, disabling."
1074                                    " index %d, data %x, expected %x\n", i,
1075                                    ptr[i], cmp_word);
1076                         err = -ENODEV;
1077                         goto free_resources;
1078                 }
1079         }
1080
1081 free_resources:
1082         mv_xor_free_chan_resources(dma_chan);
1083 out:
1084         src_idx = MV_XOR_NUM_SRC_TEST;
1085         while (src_idx--)
1086                 __free_page(xor_srcs[src_idx]);
1087         __free_page(dest);
1088         return err;
1089 }
1090
1091 static int __devexit mv_xor_remove(struct platform_device *dev)
1092 {
1093         struct mv_xor_device *device = platform_get_drvdata(dev);
1094         struct dma_chan *chan, *_chan;
1095         struct mv_xor_chan *mv_chan;
1096         struct mv_xor_platform_data *plat_data = dev->dev.platform_data;
1097
1098         dma_async_device_unregister(&device->common);
1099
1100         dma_free_coherent(&dev->dev, plat_data->pool_size,
1101                         device->dma_desc_pool_virt, device->dma_desc_pool);
1102
1103         list_for_each_entry_safe(chan, _chan, &device->common.channels,
1104                                 device_node) {
1105                 mv_chan = to_mv_xor_chan(chan);
1106                 list_del(&chan->device_node);
1107         }
1108
1109         return 0;
1110 }
1111
1112 static int __devinit mv_xor_probe(struct platform_device *pdev)
1113 {
1114         int ret = 0;
1115         int irq;
1116         struct mv_xor_device *adev;
1117         struct mv_xor_chan *mv_chan;
1118         struct dma_device *dma_dev;
1119         struct mv_xor_platform_data *plat_data = pdev->dev.platform_data;
1120
1121
1122         adev = devm_kzalloc(&pdev->dev, sizeof(*adev), GFP_KERNEL);
1123         if (!adev)
1124                 return -ENOMEM;
1125
1126         dma_dev = &adev->common;
1127
1128         /* allocate coherent memory for hardware descriptors
1129          * note: writecombine gives slightly better performance, but
1130          * requires that we explicitly flush the writes
1131          */
1132         adev->dma_desc_pool_virt = dma_alloc_writecombine(&pdev->dev,
1133                                                           plat_data->pool_size,
1134                                                           &adev->dma_desc_pool,
1135                                                           GFP_KERNEL);
1136         if (!adev->dma_desc_pool_virt)
1137                 return -ENOMEM;
1138
1139         adev->id = plat_data->hw_id;
1140
1141         /* discover transaction capabilites from the platform data */
1142         dma_dev->cap_mask = plat_data->cap_mask;
1143         adev->pdev = pdev;
1144         platform_set_drvdata(pdev, adev);
1145
1146         adev->shared = platform_get_drvdata(plat_data->shared);
1147
1148         INIT_LIST_HEAD(&dma_dev->channels);
1149
1150         /* set base routines */
1151         dma_dev->device_alloc_chan_resources = mv_xor_alloc_chan_resources;
1152         dma_dev->device_free_chan_resources = mv_xor_free_chan_resources;
1153         dma_dev->device_is_tx_complete = mv_xor_is_complete;
1154         dma_dev->device_issue_pending = mv_xor_issue_pending;
1155         dma_dev->dev = &pdev->dev;
1156
1157         /* set prep routines based on capability */
1158         if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1159                 dma_dev->device_prep_dma_memcpy = mv_xor_prep_dma_memcpy;
1160         if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask))
1161                 dma_dev->device_prep_dma_memset = mv_xor_prep_dma_memset;
1162         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1163                 dma_dev->max_xor = 8;                  ;
1164                 dma_dev->device_prep_dma_xor = mv_xor_prep_dma_xor;
1165         }
1166
1167         mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL);
1168         if (!mv_chan) {
1169                 ret = -ENOMEM;
1170                 goto err_free_dma;
1171         }
1172         mv_chan->device = adev;
1173         mv_chan->idx = plat_data->hw_id;
1174         mv_chan->mmr_base = adev->shared->xor_base;
1175
1176         if (!mv_chan->mmr_base) {
1177                 ret = -ENOMEM;
1178                 goto err_free_dma;
1179         }
1180         tasklet_init(&mv_chan->irq_tasklet, mv_xor_tasklet, (unsigned long)
1181                      mv_chan);
1182
1183         /* clear errors before enabling interrupts */
1184         mv_xor_device_clear_err_status(mv_chan);
1185
1186         irq = platform_get_irq(pdev, 0);
1187         if (irq < 0) {
1188                 ret = irq;
1189                 goto err_free_dma;
1190         }
1191         ret = devm_request_irq(&pdev->dev, irq,
1192                                mv_xor_interrupt_handler,
1193                                0, dev_name(&pdev->dev), mv_chan);
1194         if (ret)
1195                 goto err_free_dma;
1196
1197         mv_chan_unmask_interrupts(mv_chan);
1198
1199         mv_set_mode(mv_chan, DMA_MEMCPY);
1200
1201         spin_lock_init(&mv_chan->lock);
1202         INIT_LIST_HEAD(&mv_chan->chain);
1203         INIT_LIST_HEAD(&mv_chan->completed_slots);
1204         INIT_LIST_HEAD(&mv_chan->all_slots);
1205         INIT_RCU_HEAD(&mv_chan->common.rcu);
1206         mv_chan->common.device = dma_dev;
1207
1208         list_add_tail(&mv_chan->common.device_node, &dma_dev->channels);
1209
1210         if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1211                 ret = mv_xor_memcpy_self_test(adev);
1212                 dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
1213                 if (ret)
1214                         goto err_free_dma;
1215         }
1216
1217         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1218                 ret = mv_xor_xor_self_test(adev);
1219                 dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
1220                 if (ret)
1221                         goto err_free_dma;
1222         }
1223
1224         dev_printk(KERN_INFO, &pdev->dev, "Marvell XOR: "
1225           "( %s%s%s%s)\n",
1226           dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1227           dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)  ? "fill " : "",
1228           dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
1229           dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
1230
1231         dma_async_device_register(dma_dev);
1232         goto out;
1233
1234  err_free_dma:
1235         dma_free_coherent(&adev->pdev->dev, plat_data->pool_size,
1236                         adev->dma_desc_pool_virt, adev->dma_desc_pool);
1237  out:
1238         return ret;
1239 }
1240
1241 static void
1242 mv_xor_conf_mbus_windows(struct mv_xor_shared_private *msp,
1243                          struct mbus_dram_target_info *dram)
1244 {
1245         void __iomem *base = msp->xor_base;
1246         u32 win_enable = 0;
1247         int i;
1248
1249         for (i = 0; i < 8; i++) {
1250                 writel(0, base + WINDOW_BASE(i));
1251                 writel(0, base + WINDOW_SIZE(i));
1252                 if (i < 4)
1253                         writel(0, base + WINDOW_REMAP_HIGH(i));
1254         }
1255
1256         for (i = 0; i < dram->num_cs; i++) {
1257                 struct mbus_dram_window *cs = dram->cs + i;
1258
1259                 writel((cs->base & 0xffff0000) |
1260                        (cs->mbus_attr << 8) |
1261                        dram->mbus_dram_target_id, base + WINDOW_BASE(i));
1262                 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
1263
1264                 win_enable |= (1 << i);
1265                 win_enable |= 3 << (16 + (2 * i));
1266         }
1267
1268         writel(win_enable, base + WINDOW_BAR_ENABLE(0));
1269         writel(win_enable, base + WINDOW_BAR_ENABLE(1));
1270 }
1271
1272 static struct platform_driver mv_xor_driver = {
1273         .probe          = mv_xor_probe,
1274         .remove         = mv_xor_remove,
1275         .driver         = {
1276                 .owner  = THIS_MODULE,
1277                 .name   = MV_XOR_NAME,
1278         },
1279 };
1280
1281 static int mv_xor_shared_probe(struct platform_device *pdev)
1282 {
1283         struct mv_xor_platform_shared_data *msd = pdev->dev.platform_data;
1284         struct mv_xor_shared_private *msp;
1285         struct resource *res;
1286
1287         dev_printk(KERN_NOTICE, &pdev->dev, "Marvell shared XOR driver\n");
1288
1289         msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
1290         if (!msp)
1291                 return -ENOMEM;
1292
1293         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1294         if (!res)
1295                 return -ENODEV;
1296
1297         msp->xor_base = devm_ioremap(&pdev->dev, res->start,
1298                                      res->end - res->start + 1);
1299         if (!msp->xor_base)
1300                 return -EBUSY;
1301
1302         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1303         if (!res)
1304                 return -ENODEV;
1305
1306         msp->xor_high_base = devm_ioremap(&pdev->dev, res->start,
1307                                           res->end - res->start + 1);
1308         if (!msp->xor_high_base)
1309                 return -EBUSY;
1310
1311         platform_set_drvdata(pdev, msp);
1312
1313         /*
1314          * (Re-)program MBUS remapping windows if we are asked to.
1315          */
1316         if (msd != NULL && msd->dram != NULL)
1317                 mv_xor_conf_mbus_windows(msp, msd->dram);
1318
1319         return 0;
1320 }
1321
1322 static int mv_xor_shared_remove(struct platform_device *pdev)
1323 {
1324         return 0;
1325 }
1326
1327 static struct platform_driver mv_xor_shared_driver = {
1328         .probe          = mv_xor_shared_probe,
1329         .remove         = mv_xor_shared_remove,
1330         .driver         = {
1331                 .owner  = THIS_MODULE,
1332                 .name   = MV_XOR_SHARED_NAME,
1333         },
1334 };
1335
1336
1337 static int __init mv_xor_init(void)
1338 {
1339         int rc;
1340
1341         rc = platform_driver_register(&mv_xor_shared_driver);
1342         if (!rc) {
1343                 rc = platform_driver_register(&mv_xor_driver);
1344                 if (rc)
1345                         platform_driver_unregister(&mv_xor_shared_driver);
1346         }
1347         return rc;
1348 }
1349 module_init(mv_xor_init);
1350
1351 /* it's currently unsafe to unload this module */
1352 #if 0
1353 static void __exit mv_xor_exit(void)
1354 {
1355         platform_driver_unregister(&mv_xor_driver);
1356         platform_driver_unregister(&mv_xor_shared_driver);
1357         return;
1358 }
1359
1360 module_exit(mv_xor_exit);
1361 #endif
1362
1363 MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>");
1364 MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine");
1365 MODULE_LICENSE("GPL");