5a0f4fe2ee6e46f5e56a1d3de22c7034fcb2f07a
[linux-2.6.git] / drivers / dma / iop-adma.c
1 /*
2  * offload engine driver for the Intel Xscale series of i/o processors
3  * Copyright © 2006, Intel Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17  *
18  */
19
20 /*
21  * This driver supports the asynchrounous DMA copy and RAID engines available
22  * on the Intel Xscale(R) family of I/O Processors (IOP 32x, 33x, 134x)
23  */
24
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/delay.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/spinlock.h>
30 #include <linux/interrupt.h>
31 #include <linux/platform_device.h>
32 #include <linux/memory.h>
33 #include <linux/ioport.h>
34
35 #include <mach/adma.h>
36
37 #define to_iop_adma_chan(chan) container_of(chan, struct iop_adma_chan, common)
38 #define to_iop_adma_device(dev) \
39         container_of(dev, struct iop_adma_device, common)
40 #define tx_to_iop_adma_slot(tx) \
41         container_of(tx, struct iop_adma_desc_slot, async_tx)
42
43 /**
44  * iop_adma_free_slots - flags descriptor slots for reuse
45  * @slot: Slot to free
46  * Caller must hold &iop_chan->lock while calling this function
47  */
48 static void iop_adma_free_slots(struct iop_adma_desc_slot *slot)
49 {
50         int stride = slot->slots_per_op;
51
52         while (stride--) {
53                 slot->slots_per_op = 0;
54                 slot = list_entry(slot->slot_node.next,
55                                 struct iop_adma_desc_slot,
56                                 slot_node);
57         }
58 }
59
60 static void
61 iop_desc_unmap(struct iop_adma_chan *iop_chan, struct iop_adma_desc_slot *desc)
62 {
63         struct dma_async_tx_descriptor *tx = &desc->async_tx;
64         struct iop_adma_desc_slot *unmap = desc->group_head;
65         struct device *dev = &iop_chan->device->pdev->dev;
66         u32 len = unmap->unmap_len;
67         enum dma_ctrl_flags flags = tx->flags;
68         u32 src_cnt;
69         dma_addr_t addr;
70         dma_addr_t dest;
71
72         src_cnt = unmap->unmap_src_cnt;
73         dest = iop_desc_get_dest_addr(unmap, iop_chan);
74         if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
75                 enum dma_data_direction dir;
76
77                 if (src_cnt > 1) /* is xor? */
78                         dir = DMA_BIDIRECTIONAL;
79                 else
80                         dir = DMA_FROM_DEVICE;
81
82                 dma_unmap_page(dev, dest, len, dir);
83         }
84
85         if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
86                 while (src_cnt--) {
87                         addr = iop_desc_get_src_addr(unmap, iop_chan, src_cnt);
88                         if (addr == dest)
89                                 continue;
90                         dma_unmap_page(dev, addr, len, DMA_TO_DEVICE);
91                 }
92         }
93         desc->group_head = NULL;
94 }
95
96 static void
97 iop_desc_unmap_pq(struct iop_adma_chan *iop_chan, struct iop_adma_desc_slot *desc)
98 {
99         struct dma_async_tx_descriptor *tx = &desc->async_tx;
100         struct iop_adma_desc_slot *unmap = desc->group_head;
101         struct device *dev = &iop_chan->device->pdev->dev;
102         u32 len = unmap->unmap_len;
103         enum dma_ctrl_flags flags = tx->flags;
104         u32 src_cnt = unmap->unmap_src_cnt;
105         dma_addr_t pdest = iop_desc_get_dest_addr(unmap, iop_chan);
106         dma_addr_t qdest = iop_desc_get_qdest_addr(unmap, iop_chan);
107         int i;
108
109         if (tx->flags & DMA_PREP_CONTINUE)
110                 src_cnt -= 3;
111
112         if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP) && !desc->pq_check_result) {
113                 dma_unmap_page(dev, pdest, len, DMA_BIDIRECTIONAL);
114                 dma_unmap_page(dev, qdest, len, DMA_BIDIRECTIONAL);
115         }
116
117         if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
118                 dma_addr_t addr;
119
120                 for (i = 0; i < src_cnt; i++) {
121                         addr = iop_desc_get_src_addr(unmap, iop_chan, i);
122                         dma_unmap_page(dev, addr, len, DMA_TO_DEVICE);
123                 }
124                 if (desc->pq_check_result) {
125                         dma_unmap_page(dev, pdest, len, DMA_TO_DEVICE);
126                         dma_unmap_page(dev, qdest, len, DMA_TO_DEVICE);
127                 }
128         }
129
130         desc->group_head = NULL;
131 }
132
133
134 static dma_cookie_t
135 iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc,
136         struct iop_adma_chan *iop_chan, dma_cookie_t cookie)
137 {
138         struct dma_async_tx_descriptor *tx = &desc->async_tx;
139
140         BUG_ON(tx->cookie < 0);
141         if (tx->cookie > 0) {
142                 cookie = tx->cookie;
143                 tx->cookie = 0;
144
145                 /* call the callback (must not sleep or submit new
146                  * operations to this channel)
147                  */
148                 if (tx->callback)
149                         tx->callback(tx->callback_param);
150
151                 /* unmap dma addresses
152                  * (unmap_single vs unmap_page?)
153                  */
154                 if (desc->group_head && desc->unmap_len) {
155                         if (iop_desc_is_pq(desc))
156                                 iop_desc_unmap_pq(iop_chan, desc);
157                         else
158                                 iop_desc_unmap(iop_chan, desc);
159                 }
160         }
161
162         /* run dependent operations */
163         dma_run_dependencies(tx);
164
165         return cookie;
166 }
167
168 static int
169 iop_adma_clean_slot(struct iop_adma_desc_slot *desc,
170         struct iop_adma_chan *iop_chan)
171 {
172         /* the client is allowed to attach dependent operations
173          * until 'ack' is set
174          */
175         if (!async_tx_test_ack(&desc->async_tx))
176                 return 0;
177
178         /* leave the last descriptor in the chain
179          * so we can append to it
180          */
181         if (desc->chain_node.next == &iop_chan->chain)
182                 return 1;
183
184         dev_dbg(iop_chan->device->common.dev,
185                 "\tfree slot: %d slots_per_op: %d\n",
186                 desc->idx, desc->slots_per_op);
187
188         list_del(&desc->chain_node);
189         iop_adma_free_slots(desc);
190
191         return 0;
192 }
193
194 static void __iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
195 {
196         struct iop_adma_desc_slot *iter, *_iter, *grp_start = NULL;
197         dma_cookie_t cookie = 0;
198         u32 current_desc = iop_chan_get_current_descriptor(iop_chan);
199         int busy = iop_chan_is_busy(iop_chan);
200         int seen_current = 0, slot_cnt = 0, slots_per_op = 0;
201
202         dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
203         /* free completed slots from the chain starting with
204          * the oldest descriptor
205          */
206         list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
207                                         chain_node) {
208                 pr_debug("\tcookie: %d slot: %d busy: %d "
209                         "this_desc: %#x next_desc: %#x ack: %d\n",
210                         iter->async_tx.cookie, iter->idx, busy,
211                         iter->async_tx.phys, iop_desc_get_next_desc(iter),
212                         async_tx_test_ack(&iter->async_tx));
213                 prefetch(_iter);
214                 prefetch(&_iter->async_tx);
215
216                 /* do not advance past the current descriptor loaded into the
217                  * hardware channel, subsequent descriptors are either in
218                  * process or have not been submitted
219                  */
220                 if (seen_current)
221                         break;
222
223                 /* stop the search if we reach the current descriptor and the
224                  * channel is busy, or if it appears that the current descriptor
225                  * needs to be re-read (i.e. has been appended to)
226                  */
227                 if (iter->async_tx.phys == current_desc) {
228                         BUG_ON(seen_current++);
229                         if (busy || iop_desc_get_next_desc(iter))
230                                 break;
231                 }
232
233                 /* detect the start of a group transaction */
234                 if (!slot_cnt && !slots_per_op) {
235                         slot_cnt = iter->slot_cnt;
236                         slots_per_op = iter->slots_per_op;
237                         if (slot_cnt <= slots_per_op) {
238                                 slot_cnt = 0;
239                                 slots_per_op = 0;
240                         }
241                 }
242
243                 if (slot_cnt) {
244                         pr_debug("\tgroup++\n");
245                         if (!grp_start)
246                                 grp_start = iter;
247                         slot_cnt -= slots_per_op;
248                 }
249
250                 /* all the members of a group are complete */
251                 if (slots_per_op != 0 && slot_cnt == 0) {
252                         struct iop_adma_desc_slot *grp_iter, *_grp_iter;
253                         int end_of_chain = 0;
254                         pr_debug("\tgroup end\n");
255
256                         /* collect the total results */
257                         if (grp_start->xor_check_result) {
258                                 u32 zero_sum_result = 0;
259                                 slot_cnt = grp_start->slot_cnt;
260                                 grp_iter = grp_start;
261
262                                 list_for_each_entry_from(grp_iter,
263                                         &iop_chan->chain, chain_node) {
264                                         zero_sum_result |=
265                                             iop_desc_get_zero_result(grp_iter);
266                                             pr_debug("\titer%d result: %d\n",
267                                             grp_iter->idx, zero_sum_result);
268                                         slot_cnt -= slots_per_op;
269                                         if (slot_cnt == 0)
270                                                 break;
271                                 }
272                                 pr_debug("\tgrp_start->xor_check_result: %p\n",
273                                         grp_start->xor_check_result);
274                                 *grp_start->xor_check_result = zero_sum_result;
275                         }
276
277                         /* clean up the group */
278                         slot_cnt = grp_start->slot_cnt;
279                         grp_iter = grp_start;
280                         list_for_each_entry_safe_from(grp_iter, _grp_iter,
281                                 &iop_chan->chain, chain_node) {
282                                 cookie = iop_adma_run_tx_complete_actions(
283                                         grp_iter, iop_chan, cookie);
284
285                                 slot_cnt -= slots_per_op;
286                                 end_of_chain = iop_adma_clean_slot(grp_iter,
287                                         iop_chan);
288
289                                 if (slot_cnt == 0 || end_of_chain)
290                                         break;
291                         }
292
293                         /* the group should be complete at this point */
294                         BUG_ON(slot_cnt);
295
296                         slots_per_op = 0;
297                         grp_start = NULL;
298                         if (end_of_chain)
299                                 break;
300                         else
301                                 continue;
302                 } else if (slots_per_op) /* wait for group completion */
303                         continue;
304
305                 /* write back zero sum results (single descriptor case) */
306                 if (iter->xor_check_result && iter->async_tx.cookie)
307                         *iter->xor_check_result =
308                                 iop_desc_get_zero_result(iter);
309
310                 cookie = iop_adma_run_tx_complete_actions(
311                                         iter, iop_chan, cookie);
312
313                 if (iop_adma_clean_slot(iter, iop_chan))
314                         break;
315         }
316
317         if (cookie > 0) {
318                 iop_chan->completed_cookie = cookie;
319                 pr_debug("\tcompleted cookie %d\n", cookie);
320         }
321 }
322
323 static void
324 iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
325 {
326         spin_lock_bh(&iop_chan->lock);
327         __iop_adma_slot_cleanup(iop_chan);
328         spin_unlock_bh(&iop_chan->lock);
329 }
330
331 static void iop_adma_tasklet(unsigned long data)
332 {
333         struct iop_adma_chan *iop_chan = (struct iop_adma_chan *) data;
334
335         /* lockdep will flag depedency submissions as potentially
336          * recursive locking, this is not the case as a dependency
337          * submission will never recurse a channels submit routine.
338          * There are checks in async_tx.c to prevent this.
339          */
340         spin_lock_nested(&iop_chan->lock, SINGLE_DEPTH_NESTING);
341         __iop_adma_slot_cleanup(iop_chan);
342         spin_unlock(&iop_chan->lock);
343 }
344
345 static struct iop_adma_desc_slot *
346 iop_adma_alloc_slots(struct iop_adma_chan *iop_chan, int num_slots,
347                         int slots_per_op)
348 {
349         struct iop_adma_desc_slot *iter, *_iter, *alloc_start = NULL;
350         LIST_HEAD(chain);
351         int slots_found, retry = 0;
352
353         /* start search from the last allocated descrtiptor
354          * if a contiguous allocation can not be found start searching
355          * from the beginning of the list
356          */
357 retry:
358         slots_found = 0;
359         if (retry == 0)
360                 iter = iop_chan->last_used;
361         else
362                 iter = list_entry(&iop_chan->all_slots,
363                         struct iop_adma_desc_slot,
364                         slot_node);
365
366         list_for_each_entry_safe_continue(
367                 iter, _iter, &iop_chan->all_slots, slot_node) {
368                 prefetch(_iter);
369                 prefetch(&_iter->async_tx);
370                 if (iter->slots_per_op) {
371                         /* give up after finding the first busy slot
372                          * on the second pass through the list
373                          */
374                         if (retry)
375                                 break;
376
377                         slots_found = 0;
378                         continue;
379                 }
380
381                 /* start the allocation if the slot is correctly aligned */
382                 if (!slots_found++) {
383                         if (iop_desc_is_aligned(iter, slots_per_op))
384                                 alloc_start = iter;
385                         else {
386                                 slots_found = 0;
387                                 continue;
388                         }
389                 }
390
391                 if (slots_found == num_slots) {
392                         struct iop_adma_desc_slot *alloc_tail = NULL;
393                         struct iop_adma_desc_slot *last_used = NULL;
394                         iter = alloc_start;
395                         while (num_slots) {
396                                 int i;
397                                 dev_dbg(iop_chan->device->common.dev,
398                                         "allocated slot: %d "
399                                         "(desc %p phys: %#x) slots_per_op %d\n",
400                                         iter->idx, iter->hw_desc,
401                                         iter->async_tx.phys, slots_per_op);
402
403                                 /* pre-ack all but the last descriptor */
404                                 if (num_slots != slots_per_op)
405                                         async_tx_ack(&iter->async_tx);
406
407                                 list_add_tail(&iter->chain_node, &chain);
408                                 alloc_tail = iter;
409                                 iter->async_tx.cookie = 0;
410                                 iter->slot_cnt = num_slots;
411                                 iter->xor_check_result = NULL;
412                                 for (i = 0; i < slots_per_op; i++) {
413                                         iter->slots_per_op = slots_per_op - i;
414                                         last_used = iter;
415                                         iter = list_entry(iter->slot_node.next,
416                                                 struct iop_adma_desc_slot,
417                                                 slot_node);
418                                 }
419                                 num_slots -= slots_per_op;
420                         }
421                         alloc_tail->group_head = alloc_start;
422                         alloc_tail->async_tx.cookie = -EBUSY;
423                         list_splice(&chain, &alloc_tail->async_tx.tx_list);
424                         iop_chan->last_used = last_used;
425                         iop_desc_clear_next_desc(alloc_start);
426                         iop_desc_clear_next_desc(alloc_tail);
427                         return alloc_tail;
428                 }
429         }
430         if (!retry++)
431                 goto retry;
432
433         /* perform direct reclaim if the allocation fails */
434         __iop_adma_slot_cleanup(iop_chan);
435
436         return NULL;
437 }
438
439 static dma_cookie_t
440 iop_desc_assign_cookie(struct iop_adma_chan *iop_chan,
441         struct iop_adma_desc_slot *desc)
442 {
443         dma_cookie_t cookie = iop_chan->common.cookie;
444         cookie++;
445         if (cookie < 0)
446                 cookie = 1;
447         iop_chan->common.cookie = desc->async_tx.cookie = cookie;
448         return cookie;
449 }
450
451 static void iop_adma_check_threshold(struct iop_adma_chan *iop_chan)
452 {
453         dev_dbg(iop_chan->device->common.dev, "pending: %d\n",
454                 iop_chan->pending);
455
456         if (iop_chan->pending >= IOP_ADMA_THRESHOLD) {
457                 iop_chan->pending = 0;
458                 iop_chan_append(iop_chan);
459         }
460 }
461
462 static dma_cookie_t
463 iop_adma_tx_submit(struct dma_async_tx_descriptor *tx)
464 {
465         struct iop_adma_desc_slot *sw_desc = tx_to_iop_adma_slot(tx);
466         struct iop_adma_chan *iop_chan = to_iop_adma_chan(tx->chan);
467         struct iop_adma_desc_slot *grp_start, *old_chain_tail;
468         int slot_cnt;
469         int slots_per_op;
470         dma_cookie_t cookie;
471         dma_addr_t next_dma;
472
473         grp_start = sw_desc->group_head;
474         slot_cnt = grp_start->slot_cnt;
475         slots_per_op = grp_start->slots_per_op;
476
477         spin_lock_bh(&iop_chan->lock);
478         cookie = iop_desc_assign_cookie(iop_chan, sw_desc);
479
480         old_chain_tail = list_entry(iop_chan->chain.prev,
481                 struct iop_adma_desc_slot, chain_node);
482         list_splice_init(&sw_desc->async_tx.tx_list,
483                          &old_chain_tail->chain_node);
484
485         /* fix up the hardware chain */
486         next_dma = grp_start->async_tx.phys;
487         iop_desc_set_next_desc(old_chain_tail, next_dma);
488         BUG_ON(iop_desc_get_next_desc(old_chain_tail) != next_dma); /* flush */
489
490         /* check for pre-chained descriptors */
491         iop_paranoia(iop_desc_get_next_desc(sw_desc));
492
493         /* increment the pending count by the number of slots
494          * memcpy operations have a 1:1 (slot:operation) relation
495          * other operations are heavier and will pop the threshold
496          * more often.
497          */
498         iop_chan->pending += slot_cnt;
499         iop_adma_check_threshold(iop_chan);
500         spin_unlock_bh(&iop_chan->lock);
501
502         dev_dbg(iop_chan->device->common.dev, "%s cookie: %d slot: %d\n",
503                 __func__, sw_desc->async_tx.cookie, sw_desc->idx);
504
505         return cookie;
506 }
507
508 static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan);
509 static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan);
510
511 /**
512  * iop_adma_alloc_chan_resources -  returns the number of allocated descriptors
513  * @chan - allocate descriptor resources for this channel
514  * @client - current client requesting the channel be ready for requests
515  *
516  * Note: We keep the slots for 1 operation on iop_chan->chain at all times.  To
517  * avoid deadlock, via async_xor, num_descs_in_pool must at a minimum be
518  * greater than 2x the number slots needed to satisfy a device->max_xor
519  * request.
520  * */
521 static int iop_adma_alloc_chan_resources(struct dma_chan *chan)
522 {
523         char *hw_desc;
524         int idx;
525         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
526         struct iop_adma_desc_slot *slot = NULL;
527         int init = iop_chan->slots_allocated ? 0 : 1;
528         struct iop_adma_platform_data *plat_data =
529                 iop_chan->device->pdev->dev.platform_data;
530         int num_descs_in_pool = plat_data->pool_size/IOP_ADMA_SLOT_SIZE;
531
532         /* Allocate descriptor slots */
533         do {
534                 idx = iop_chan->slots_allocated;
535                 if (idx == num_descs_in_pool)
536                         break;
537
538                 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
539                 if (!slot) {
540                         printk(KERN_INFO "IOP ADMA Channel only initialized"
541                                 " %d descriptor slots", idx);
542                         break;
543                 }
544                 hw_desc = (char *) iop_chan->device->dma_desc_pool_virt;
545                 slot->hw_desc = (void *) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
546
547                 dma_async_tx_descriptor_init(&slot->async_tx, chan);
548                 slot->async_tx.tx_submit = iop_adma_tx_submit;
549                 INIT_LIST_HEAD(&slot->chain_node);
550                 INIT_LIST_HEAD(&slot->slot_node);
551                 hw_desc = (char *) iop_chan->device->dma_desc_pool;
552                 slot->async_tx.phys =
553                         (dma_addr_t) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
554                 slot->idx = idx;
555
556                 spin_lock_bh(&iop_chan->lock);
557                 iop_chan->slots_allocated++;
558                 list_add_tail(&slot->slot_node, &iop_chan->all_slots);
559                 spin_unlock_bh(&iop_chan->lock);
560         } while (iop_chan->slots_allocated < num_descs_in_pool);
561
562         if (idx && !iop_chan->last_used)
563                 iop_chan->last_used = list_entry(iop_chan->all_slots.next,
564                                         struct iop_adma_desc_slot,
565                                         slot_node);
566
567         dev_dbg(iop_chan->device->common.dev,
568                 "allocated %d descriptor slots last_used: %p\n",
569                 iop_chan->slots_allocated, iop_chan->last_used);
570
571         /* initialize the channel and the chain with a null operation */
572         if (init) {
573                 if (dma_has_cap(DMA_MEMCPY,
574                         iop_chan->device->common.cap_mask))
575                         iop_chan_start_null_memcpy(iop_chan);
576                 else if (dma_has_cap(DMA_XOR,
577                         iop_chan->device->common.cap_mask))
578                         iop_chan_start_null_xor(iop_chan);
579                 else
580                         BUG();
581         }
582
583         return (idx > 0) ? idx : -ENOMEM;
584 }
585
586 static struct dma_async_tx_descriptor *
587 iop_adma_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags)
588 {
589         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
590         struct iop_adma_desc_slot *sw_desc, *grp_start;
591         int slot_cnt, slots_per_op;
592
593         dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
594
595         spin_lock_bh(&iop_chan->lock);
596         slot_cnt = iop_chan_interrupt_slot_count(&slots_per_op, iop_chan);
597         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
598         if (sw_desc) {
599                 grp_start = sw_desc->group_head;
600                 iop_desc_init_interrupt(grp_start, iop_chan);
601                 grp_start->unmap_len = 0;
602                 sw_desc->async_tx.flags = flags;
603         }
604         spin_unlock_bh(&iop_chan->lock);
605
606         return sw_desc ? &sw_desc->async_tx : NULL;
607 }
608
609 static struct dma_async_tx_descriptor *
610 iop_adma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest,
611                          dma_addr_t dma_src, size_t len, unsigned long flags)
612 {
613         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
614         struct iop_adma_desc_slot *sw_desc, *grp_start;
615         int slot_cnt, slots_per_op;
616
617         if (unlikely(!len))
618                 return NULL;
619         BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT));
620
621         dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
622                 __func__, len);
623
624         spin_lock_bh(&iop_chan->lock);
625         slot_cnt = iop_chan_memcpy_slot_count(len, &slots_per_op);
626         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
627         if (sw_desc) {
628                 grp_start = sw_desc->group_head;
629                 iop_desc_init_memcpy(grp_start, flags);
630                 iop_desc_set_byte_count(grp_start, iop_chan, len);
631                 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
632                 iop_desc_set_memcpy_src_addr(grp_start, dma_src);
633                 sw_desc->unmap_src_cnt = 1;
634                 sw_desc->unmap_len = len;
635                 sw_desc->async_tx.flags = flags;
636         }
637         spin_unlock_bh(&iop_chan->lock);
638
639         return sw_desc ? &sw_desc->async_tx : NULL;
640 }
641
642 static struct dma_async_tx_descriptor *
643 iop_adma_prep_dma_memset(struct dma_chan *chan, dma_addr_t dma_dest,
644                          int value, size_t len, unsigned long flags)
645 {
646         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
647         struct iop_adma_desc_slot *sw_desc, *grp_start;
648         int slot_cnt, slots_per_op;
649
650         if (unlikely(!len))
651                 return NULL;
652         BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT));
653
654         dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
655                 __func__, len);
656
657         spin_lock_bh(&iop_chan->lock);
658         slot_cnt = iop_chan_memset_slot_count(len, &slots_per_op);
659         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
660         if (sw_desc) {
661                 grp_start = sw_desc->group_head;
662                 iop_desc_init_memset(grp_start, flags);
663                 iop_desc_set_byte_count(grp_start, iop_chan, len);
664                 iop_desc_set_block_fill_val(grp_start, value);
665                 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
666                 sw_desc->unmap_src_cnt = 1;
667                 sw_desc->unmap_len = len;
668                 sw_desc->async_tx.flags = flags;
669         }
670         spin_unlock_bh(&iop_chan->lock);
671
672         return sw_desc ? &sw_desc->async_tx : NULL;
673 }
674
675 static struct dma_async_tx_descriptor *
676 iop_adma_prep_dma_xor(struct dma_chan *chan, dma_addr_t dma_dest,
677                       dma_addr_t *dma_src, unsigned int src_cnt, size_t len,
678                       unsigned long flags)
679 {
680         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
681         struct iop_adma_desc_slot *sw_desc, *grp_start;
682         int slot_cnt, slots_per_op;
683
684         if (unlikely(!len))
685                 return NULL;
686         BUG_ON(unlikely(len > IOP_ADMA_XOR_MAX_BYTE_COUNT));
687
688         dev_dbg(iop_chan->device->common.dev,
689                 "%s src_cnt: %d len: %u flags: %lx\n",
690                 __func__, src_cnt, len, flags);
691
692         spin_lock_bh(&iop_chan->lock);
693         slot_cnt = iop_chan_xor_slot_count(len, src_cnt, &slots_per_op);
694         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
695         if (sw_desc) {
696                 grp_start = sw_desc->group_head;
697                 iop_desc_init_xor(grp_start, src_cnt, flags);
698                 iop_desc_set_byte_count(grp_start, iop_chan, len);
699                 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
700                 sw_desc->unmap_src_cnt = src_cnt;
701                 sw_desc->unmap_len = len;
702                 sw_desc->async_tx.flags = flags;
703                 while (src_cnt--)
704                         iop_desc_set_xor_src_addr(grp_start, src_cnt,
705                                                   dma_src[src_cnt]);
706         }
707         spin_unlock_bh(&iop_chan->lock);
708
709         return sw_desc ? &sw_desc->async_tx : NULL;
710 }
711
712 static struct dma_async_tx_descriptor *
713 iop_adma_prep_dma_xor_val(struct dma_chan *chan, dma_addr_t *dma_src,
714                           unsigned int src_cnt, size_t len, u32 *result,
715                           unsigned long flags)
716 {
717         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
718         struct iop_adma_desc_slot *sw_desc, *grp_start;
719         int slot_cnt, slots_per_op;
720
721         if (unlikely(!len))
722                 return NULL;
723
724         dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u\n",
725                 __func__, src_cnt, len);
726
727         spin_lock_bh(&iop_chan->lock);
728         slot_cnt = iop_chan_zero_sum_slot_count(len, src_cnt, &slots_per_op);
729         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
730         if (sw_desc) {
731                 grp_start = sw_desc->group_head;
732                 iop_desc_init_zero_sum(grp_start, src_cnt, flags);
733                 iop_desc_set_zero_sum_byte_count(grp_start, len);
734                 grp_start->xor_check_result = result;
735                 pr_debug("\t%s: grp_start->xor_check_result: %p\n",
736                         __func__, grp_start->xor_check_result);
737                 sw_desc->unmap_src_cnt = src_cnt;
738                 sw_desc->unmap_len = len;
739                 sw_desc->async_tx.flags = flags;
740                 while (src_cnt--)
741                         iop_desc_set_zero_sum_src_addr(grp_start, src_cnt,
742                                                        dma_src[src_cnt]);
743         }
744         spin_unlock_bh(&iop_chan->lock);
745
746         return sw_desc ? &sw_desc->async_tx : NULL;
747 }
748
749 static struct dma_async_tx_descriptor *
750 iop_adma_prep_dma_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
751                      unsigned int src_cnt, const unsigned char *scf, size_t len,
752                      unsigned long flags)
753 {
754         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
755         struct iop_adma_desc_slot *sw_desc, *g;
756         int slot_cnt, slots_per_op;
757         int continue_srcs;
758
759         if (unlikely(!len))
760                 return NULL;
761         BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT);
762
763         dev_dbg(iop_chan->device->common.dev,
764                 "%s src_cnt: %d len: %u flags: %lx\n",
765                 __func__, src_cnt, len, flags);
766
767         if (dmaf_p_disabled_continue(flags))
768                 continue_srcs = 1+src_cnt;
769         else if (dmaf_continue(flags))
770                 continue_srcs = 3+src_cnt;
771         else
772                 continue_srcs = 0+src_cnt;
773
774         spin_lock_bh(&iop_chan->lock);
775         slot_cnt = iop_chan_pq_slot_count(len, continue_srcs, &slots_per_op);
776         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
777         if (sw_desc) {
778                 int i;
779
780                 g = sw_desc->group_head;
781                 iop_desc_set_byte_count(g, iop_chan, len);
782
783                 /* even if P is disabled its destination address (bits
784                  * [3:0]) must match Q.  It is ok if P points to an
785                  * invalid address, it won't be written.
786                  */
787                 if (flags & DMA_PREP_PQ_DISABLE_P)
788                         dst[0] = dst[1] & 0x7;
789
790                 iop_desc_set_pq_addr(g, dst);
791                 sw_desc->unmap_src_cnt = src_cnt;
792                 sw_desc->unmap_len = len;
793                 sw_desc->async_tx.flags = flags;
794                 for (i = 0; i < src_cnt; i++)
795                         iop_desc_set_pq_src_addr(g, i, src[i], scf[i]);
796
797                 /* if we are continuing a previous operation factor in
798                  * the old p and q values, see the comment for dma_maxpq
799                  * in include/linux/dmaengine.h
800                  */
801                 if (dmaf_p_disabled_continue(flags))
802                         iop_desc_set_pq_src_addr(g, i++, dst[1], 1);
803                 else if (dmaf_continue(flags)) {
804                         iop_desc_set_pq_src_addr(g, i++, dst[0], 0);
805                         iop_desc_set_pq_src_addr(g, i++, dst[1], 1);
806                         iop_desc_set_pq_src_addr(g, i++, dst[1], 0);
807                 }
808                 iop_desc_init_pq(g, i, flags);
809         }
810         spin_unlock_bh(&iop_chan->lock);
811
812         return sw_desc ? &sw_desc->async_tx : NULL;
813 }
814
815 static struct dma_async_tx_descriptor *
816 iop_adma_prep_dma_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
817                          unsigned int src_cnt, const unsigned char *scf,
818                          size_t len, enum sum_check_flags *pqres,
819                          unsigned long flags)
820 {
821         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
822         struct iop_adma_desc_slot *sw_desc, *g;
823         int slot_cnt, slots_per_op;
824
825         if (unlikely(!len))
826                 return NULL;
827         BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT);
828
829         dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u\n",
830                 __func__, src_cnt, len);
831
832         spin_lock_bh(&iop_chan->lock);
833         slot_cnt = iop_chan_pq_zero_sum_slot_count(len, src_cnt + 2, &slots_per_op);
834         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
835         if (sw_desc) {
836                 /* for validate operations p and q are tagged onto the
837                  * end of the source list
838                  */
839                 int pq_idx = src_cnt;
840
841                 g = sw_desc->group_head;
842                 iop_desc_init_pq_zero_sum(g, src_cnt+2, flags);
843                 iop_desc_set_pq_zero_sum_byte_count(g, len);
844                 g->pq_check_result = pqres;
845                 pr_debug("\t%s: g->pq_check_result: %p\n",
846                         __func__, g->pq_check_result);
847                 sw_desc->unmap_src_cnt = src_cnt+2;
848                 sw_desc->unmap_len = len;
849                 sw_desc->async_tx.flags = flags;
850                 while (src_cnt--)
851                         iop_desc_set_pq_zero_sum_src_addr(g, src_cnt,
852                                                           src[src_cnt],
853                                                           scf[src_cnt]);
854                 iop_desc_set_pq_zero_sum_addr(g, pq_idx, src);
855         }
856         spin_unlock_bh(&iop_chan->lock);
857
858         return sw_desc ? &sw_desc->async_tx : NULL;
859 }
860
861 static void iop_adma_free_chan_resources(struct dma_chan *chan)
862 {
863         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
864         struct iop_adma_desc_slot *iter, *_iter;
865         int in_use_descs = 0;
866
867         iop_adma_slot_cleanup(iop_chan);
868
869         spin_lock_bh(&iop_chan->lock);
870         list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
871                                         chain_node) {
872                 in_use_descs++;
873                 list_del(&iter->chain_node);
874         }
875         list_for_each_entry_safe_reverse(
876                 iter, _iter, &iop_chan->all_slots, slot_node) {
877                 list_del(&iter->slot_node);
878                 kfree(iter);
879                 iop_chan->slots_allocated--;
880         }
881         iop_chan->last_used = NULL;
882
883         dev_dbg(iop_chan->device->common.dev, "%s slots_allocated %d\n",
884                 __func__, iop_chan->slots_allocated);
885         spin_unlock_bh(&iop_chan->lock);
886
887         /* one is ok since we left it on there on purpose */
888         if (in_use_descs > 1)
889                 printk(KERN_ERR "IOP: Freeing %d in use descriptors!\n",
890                         in_use_descs - 1);
891 }
892
893 /**
894  * iop_adma_is_complete - poll the status of an ADMA transaction
895  * @chan: ADMA channel handle
896  * @cookie: ADMA transaction identifier
897  */
898 static enum dma_status iop_adma_is_complete(struct dma_chan *chan,
899                                         dma_cookie_t cookie,
900                                         dma_cookie_t *done,
901                                         dma_cookie_t *used)
902 {
903         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
904         dma_cookie_t last_used;
905         dma_cookie_t last_complete;
906         enum dma_status ret;
907
908         last_used = chan->cookie;
909         last_complete = iop_chan->completed_cookie;
910
911         if (done)
912                 *done = last_complete;
913         if (used)
914                 *used = last_used;
915
916         ret = dma_async_is_complete(cookie, last_complete, last_used);
917         if (ret == DMA_SUCCESS)
918                 return ret;
919
920         iop_adma_slot_cleanup(iop_chan);
921
922         last_used = chan->cookie;
923         last_complete = iop_chan->completed_cookie;
924
925         if (done)
926                 *done = last_complete;
927         if (used)
928                 *used = last_used;
929
930         return dma_async_is_complete(cookie, last_complete, last_used);
931 }
932
933 static irqreturn_t iop_adma_eot_handler(int irq, void *data)
934 {
935         struct iop_adma_chan *chan = data;
936
937         dev_dbg(chan->device->common.dev, "%s\n", __func__);
938
939         tasklet_schedule(&chan->irq_tasklet);
940
941         iop_adma_device_clear_eot_status(chan);
942
943         return IRQ_HANDLED;
944 }
945
946 static irqreturn_t iop_adma_eoc_handler(int irq, void *data)
947 {
948         struct iop_adma_chan *chan = data;
949
950         dev_dbg(chan->device->common.dev, "%s\n", __func__);
951
952         tasklet_schedule(&chan->irq_tasklet);
953
954         iop_adma_device_clear_eoc_status(chan);
955
956         return IRQ_HANDLED;
957 }
958
959 static irqreturn_t iop_adma_err_handler(int irq, void *data)
960 {
961         struct iop_adma_chan *chan = data;
962         unsigned long status = iop_chan_get_status(chan);
963
964         dev_printk(KERN_ERR, chan->device->common.dev,
965                 "error ( %s%s%s%s%s%s%s)\n",
966                 iop_is_err_int_parity(status, chan) ? "int_parity " : "",
967                 iop_is_err_mcu_abort(status, chan) ? "mcu_abort " : "",
968                 iop_is_err_int_tabort(status, chan) ? "int_tabort " : "",
969                 iop_is_err_int_mabort(status, chan) ? "int_mabort " : "",
970                 iop_is_err_pci_tabort(status, chan) ? "pci_tabort " : "",
971                 iop_is_err_pci_mabort(status, chan) ? "pci_mabort " : "",
972                 iop_is_err_split_tx(status, chan) ? "split_tx " : "");
973
974         iop_adma_device_clear_err_status(chan);
975
976         BUG();
977
978         return IRQ_HANDLED;
979 }
980
981 static void iop_adma_issue_pending(struct dma_chan *chan)
982 {
983         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
984
985         if (iop_chan->pending) {
986                 iop_chan->pending = 0;
987                 iop_chan_append(iop_chan);
988         }
989 }
990
991 /*
992  * Perform a transaction to verify the HW works.
993  */
994 #define IOP_ADMA_TEST_SIZE 2000
995
996 static int __devinit iop_adma_memcpy_self_test(struct iop_adma_device *device)
997 {
998         int i;
999         void *src, *dest;
1000         dma_addr_t src_dma, dest_dma;
1001         struct dma_chan *dma_chan;
1002         dma_cookie_t cookie;
1003         struct dma_async_tx_descriptor *tx;
1004         int err = 0;
1005         struct iop_adma_chan *iop_chan;
1006
1007         dev_dbg(device->common.dev, "%s\n", __func__);
1008
1009         src = kmalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL);
1010         if (!src)
1011                 return -ENOMEM;
1012         dest = kzalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL);
1013         if (!dest) {
1014                 kfree(src);
1015                 return -ENOMEM;
1016         }
1017
1018         /* Fill in src buffer */
1019         for (i = 0; i < IOP_ADMA_TEST_SIZE; i++)
1020                 ((u8 *) src)[i] = (u8)i;
1021
1022         /* Start copy, using first DMA channel */
1023         dma_chan = container_of(device->common.channels.next,
1024                                 struct dma_chan,
1025                                 device_node);
1026         if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
1027                 err = -ENODEV;
1028                 goto out;
1029         }
1030
1031         dest_dma = dma_map_single(dma_chan->device->dev, dest,
1032                                 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
1033         src_dma = dma_map_single(dma_chan->device->dev, src,
1034                                 IOP_ADMA_TEST_SIZE, DMA_TO_DEVICE);
1035         tx = iop_adma_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
1036                                       IOP_ADMA_TEST_SIZE,
1037                                       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1038
1039         cookie = iop_adma_tx_submit(tx);
1040         iop_adma_issue_pending(dma_chan);
1041         msleep(1);
1042
1043         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
1044                         DMA_SUCCESS) {
1045                 dev_printk(KERN_ERR, dma_chan->device->dev,
1046                         "Self-test copy timed out, disabling\n");
1047                 err = -ENODEV;
1048                 goto free_resources;
1049         }
1050
1051         iop_chan = to_iop_adma_chan(dma_chan);
1052         dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
1053                 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
1054         if (memcmp(src, dest, IOP_ADMA_TEST_SIZE)) {
1055                 dev_printk(KERN_ERR, dma_chan->device->dev,
1056                         "Self-test copy failed compare, disabling\n");
1057                 err = -ENODEV;
1058                 goto free_resources;
1059         }
1060
1061 free_resources:
1062         iop_adma_free_chan_resources(dma_chan);
1063 out:
1064         kfree(src);
1065         kfree(dest);
1066         return err;
1067 }
1068
1069 #define IOP_ADMA_NUM_SRC_TEST 4 /* must be <= 15 */
1070 static int __devinit
1071 iop_adma_xor_val_self_test(struct iop_adma_device *device)
1072 {
1073         int i, src_idx;
1074         struct page *dest;
1075         struct page *xor_srcs[IOP_ADMA_NUM_SRC_TEST];
1076         struct page *zero_sum_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
1077         dma_addr_t dma_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
1078         dma_addr_t dma_addr, dest_dma;
1079         struct dma_async_tx_descriptor *tx;
1080         struct dma_chan *dma_chan;
1081         dma_cookie_t cookie;
1082         u8 cmp_byte = 0;
1083         u32 cmp_word;
1084         u32 zero_sum_result;
1085         int err = 0;
1086         struct iop_adma_chan *iop_chan;
1087
1088         dev_dbg(device->common.dev, "%s\n", __func__);
1089
1090         for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
1091                 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
1092                 if (!xor_srcs[src_idx]) {
1093                         while (src_idx--)
1094                                 __free_page(xor_srcs[src_idx]);
1095                         return -ENOMEM;
1096                 }
1097         }
1098
1099         dest = alloc_page(GFP_KERNEL);
1100         if (!dest) {
1101                 while (src_idx--)
1102                         __free_page(xor_srcs[src_idx]);
1103                 return -ENOMEM;
1104         }
1105
1106         /* Fill in src buffers */
1107         for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
1108                 u8 *ptr = page_address(xor_srcs[src_idx]);
1109                 for (i = 0; i < PAGE_SIZE; i++)
1110                         ptr[i] = (1 << src_idx);
1111         }
1112
1113         for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++)
1114                 cmp_byte ^= (u8) (1 << src_idx);
1115
1116         cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
1117                         (cmp_byte << 8) | cmp_byte;
1118
1119         memset(page_address(dest), 0, PAGE_SIZE);
1120
1121         dma_chan = container_of(device->common.channels.next,
1122                                 struct dma_chan,
1123                                 device_node);
1124         if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
1125                 err = -ENODEV;
1126                 goto out;
1127         }
1128
1129         /* test xor */
1130         dest_dma = dma_map_page(dma_chan->device->dev, dest, 0,
1131                                 PAGE_SIZE, DMA_FROM_DEVICE);
1132         for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
1133                 dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
1134                                            0, PAGE_SIZE, DMA_TO_DEVICE);
1135         tx = iop_adma_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
1136                                    IOP_ADMA_NUM_SRC_TEST, PAGE_SIZE,
1137                                    DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1138
1139         cookie = iop_adma_tx_submit(tx);
1140         iop_adma_issue_pending(dma_chan);
1141         msleep(8);
1142
1143         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
1144                 DMA_SUCCESS) {
1145                 dev_printk(KERN_ERR, dma_chan->device->dev,
1146                         "Self-test xor timed out, disabling\n");
1147                 err = -ENODEV;
1148                 goto free_resources;
1149         }
1150
1151         iop_chan = to_iop_adma_chan(dma_chan);
1152         dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
1153                 PAGE_SIZE, DMA_FROM_DEVICE);
1154         for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
1155                 u32 *ptr = page_address(dest);
1156                 if (ptr[i] != cmp_word) {
1157                         dev_printk(KERN_ERR, dma_chan->device->dev,
1158                                 "Self-test xor failed compare, disabling\n");
1159                         err = -ENODEV;
1160                         goto free_resources;
1161                 }
1162         }
1163         dma_sync_single_for_device(&iop_chan->device->pdev->dev, dest_dma,
1164                 PAGE_SIZE, DMA_TO_DEVICE);
1165
1166         /* skip zero sum if the capability is not present */
1167         if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask))
1168                 goto free_resources;
1169
1170         /* zero sum the sources with the destintation page */
1171         for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
1172                 zero_sum_srcs[i] = xor_srcs[i];
1173         zero_sum_srcs[i] = dest;
1174
1175         zero_sum_result = 1;
1176
1177         for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
1178                 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
1179                                            zero_sum_srcs[i], 0, PAGE_SIZE,
1180                                            DMA_TO_DEVICE);
1181         tx = iop_adma_prep_dma_xor_val(dma_chan, dma_srcs,
1182                                        IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1183                                        &zero_sum_result,
1184                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1185
1186         cookie = iop_adma_tx_submit(tx);
1187         iop_adma_issue_pending(dma_chan);
1188         msleep(8);
1189
1190         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1191                 dev_printk(KERN_ERR, dma_chan->device->dev,
1192                         "Self-test zero sum timed out, disabling\n");
1193                 err = -ENODEV;
1194                 goto free_resources;
1195         }
1196
1197         if (zero_sum_result != 0) {
1198                 dev_printk(KERN_ERR, dma_chan->device->dev,
1199                         "Self-test zero sum failed compare, disabling\n");
1200                 err = -ENODEV;
1201                 goto free_resources;
1202         }
1203
1204         /* test memset */
1205         dma_addr = dma_map_page(dma_chan->device->dev, dest, 0,
1206                         PAGE_SIZE, DMA_FROM_DEVICE);
1207         tx = iop_adma_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE,
1208                                       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1209
1210         cookie = iop_adma_tx_submit(tx);
1211         iop_adma_issue_pending(dma_chan);
1212         msleep(8);
1213
1214         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1215                 dev_printk(KERN_ERR, dma_chan->device->dev,
1216                         "Self-test memset timed out, disabling\n");
1217                 err = -ENODEV;
1218                 goto free_resources;
1219         }
1220
1221         for (i = 0; i < PAGE_SIZE/sizeof(u32); i++) {
1222                 u32 *ptr = page_address(dest);
1223                 if (ptr[i]) {
1224                         dev_printk(KERN_ERR, dma_chan->device->dev,
1225                                 "Self-test memset failed compare, disabling\n");
1226                         err = -ENODEV;
1227                         goto free_resources;
1228                 }
1229         }
1230
1231         /* test for non-zero parity sum */
1232         zero_sum_result = 0;
1233         for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
1234                 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
1235                                            zero_sum_srcs[i], 0, PAGE_SIZE,
1236                                            DMA_TO_DEVICE);
1237         tx = iop_adma_prep_dma_xor_val(dma_chan, dma_srcs,
1238                                        IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1239                                        &zero_sum_result,
1240                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1241
1242         cookie = iop_adma_tx_submit(tx);
1243         iop_adma_issue_pending(dma_chan);
1244         msleep(8);
1245
1246         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1247                 dev_printk(KERN_ERR, dma_chan->device->dev,
1248                         "Self-test non-zero sum timed out, disabling\n");
1249                 err = -ENODEV;
1250                 goto free_resources;
1251         }
1252
1253         if (zero_sum_result != 1) {
1254                 dev_printk(KERN_ERR, dma_chan->device->dev,
1255                         "Self-test non-zero sum failed compare, disabling\n");
1256                 err = -ENODEV;
1257                 goto free_resources;
1258         }
1259
1260 free_resources:
1261         iop_adma_free_chan_resources(dma_chan);
1262 out:
1263         src_idx = IOP_ADMA_NUM_SRC_TEST;
1264         while (src_idx--)
1265                 __free_page(xor_srcs[src_idx]);
1266         __free_page(dest);
1267         return err;
1268 }
1269
1270 static int __devexit iop_adma_remove(struct platform_device *dev)
1271 {
1272         struct iop_adma_device *device = platform_get_drvdata(dev);
1273         struct dma_chan *chan, *_chan;
1274         struct iop_adma_chan *iop_chan;
1275         struct iop_adma_platform_data *plat_data = dev->dev.platform_data;
1276
1277         dma_async_device_unregister(&device->common);
1278
1279         dma_free_coherent(&dev->dev, plat_data->pool_size,
1280                         device->dma_desc_pool_virt, device->dma_desc_pool);
1281
1282         list_for_each_entry_safe(chan, _chan, &device->common.channels,
1283                                 device_node) {
1284                 iop_chan = to_iop_adma_chan(chan);
1285                 list_del(&chan->device_node);
1286                 kfree(iop_chan);
1287         }
1288         kfree(device);
1289
1290         return 0;
1291 }
1292
1293 static int __devinit iop_adma_probe(struct platform_device *pdev)
1294 {
1295         struct resource *res;
1296         int ret = 0, i;
1297         struct iop_adma_device *adev;
1298         struct iop_adma_chan *iop_chan;
1299         struct dma_device *dma_dev;
1300         struct iop_adma_platform_data *plat_data = pdev->dev.platform_data;
1301
1302         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1303         if (!res)
1304                 return -ENODEV;
1305
1306         if (!devm_request_mem_region(&pdev->dev, res->start,
1307                                 res->end - res->start, pdev->name))
1308                 return -EBUSY;
1309
1310         adev = kzalloc(sizeof(*adev), GFP_KERNEL);
1311         if (!adev)
1312                 return -ENOMEM;
1313         dma_dev = &adev->common;
1314
1315         /* allocate coherent memory for hardware descriptors
1316          * note: writecombine gives slightly better performance, but
1317          * requires that we explicitly flush the writes
1318          */
1319         if ((adev->dma_desc_pool_virt = dma_alloc_writecombine(&pdev->dev,
1320                                         plat_data->pool_size,
1321                                         &adev->dma_desc_pool,
1322                                         GFP_KERNEL)) == NULL) {
1323                 ret = -ENOMEM;
1324                 goto err_free_adev;
1325         }
1326
1327         dev_dbg(&pdev->dev, "%s: allocted descriptor pool virt %p phys %p\n",
1328                 __func__, adev->dma_desc_pool_virt,
1329                 (void *) adev->dma_desc_pool);
1330
1331         adev->id = plat_data->hw_id;
1332
1333         /* discover transaction capabilites from the platform data */
1334         dma_dev->cap_mask = plat_data->cap_mask;
1335
1336         adev->pdev = pdev;
1337         platform_set_drvdata(pdev, adev);
1338
1339         INIT_LIST_HEAD(&dma_dev->channels);
1340
1341         /* set base routines */
1342         dma_dev->device_alloc_chan_resources = iop_adma_alloc_chan_resources;
1343         dma_dev->device_free_chan_resources = iop_adma_free_chan_resources;
1344         dma_dev->device_is_tx_complete = iop_adma_is_complete;
1345         dma_dev->device_issue_pending = iop_adma_issue_pending;
1346         dma_dev->dev = &pdev->dev;
1347
1348         /* set prep routines based on capability */
1349         if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1350                 dma_dev->device_prep_dma_memcpy = iop_adma_prep_dma_memcpy;
1351         if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask))
1352                 dma_dev->device_prep_dma_memset = iop_adma_prep_dma_memset;
1353         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1354                 dma_dev->max_xor = iop_adma_get_max_xor();
1355                 dma_dev->device_prep_dma_xor = iop_adma_prep_dma_xor;
1356         }
1357         if (dma_has_cap(DMA_XOR_VAL, dma_dev->cap_mask))
1358                 dma_dev->device_prep_dma_xor_val =
1359                         iop_adma_prep_dma_xor_val;
1360         if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
1361                 dma_set_maxpq(dma_dev, iop_adma_get_max_pq(), 0);
1362                 dma_dev->device_prep_dma_pq = iop_adma_prep_dma_pq;
1363         }
1364         if (dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask))
1365                 dma_dev->device_prep_dma_pq_val =
1366                         iop_adma_prep_dma_pq_val;
1367         if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask))
1368                 dma_dev->device_prep_dma_interrupt =
1369                         iop_adma_prep_dma_interrupt;
1370
1371         iop_chan = kzalloc(sizeof(*iop_chan), GFP_KERNEL);
1372         if (!iop_chan) {
1373                 ret = -ENOMEM;
1374                 goto err_free_dma;
1375         }
1376         iop_chan->device = adev;
1377
1378         iop_chan->mmr_base = devm_ioremap(&pdev->dev, res->start,
1379                                         res->end - res->start);
1380         if (!iop_chan->mmr_base) {
1381                 ret = -ENOMEM;
1382                 goto err_free_iop_chan;
1383         }
1384         tasklet_init(&iop_chan->irq_tasklet, iop_adma_tasklet, (unsigned long)
1385                 iop_chan);
1386
1387         /* clear errors before enabling interrupts */
1388         iop_adma_device_clear_err_status(iop_chan);
1389
1390         for (i = 0; i < 3; i++) {
1391                 irq_handler_t handler[] = { iop_adma_eot_handler,
1392                                         iop_adma_eoc_handler,
1393                                         iop_adma_err_handler };
1394                 int irq = platform_get_irq(pdev, i);
1395                 if (irq < 0) {
1396                         ret = -ENXIO;
1397                         goto err_free_iop_chan;
1398                 } else {
1399                         ret = devm_request_irq(&pdev->dev, irq,
1400                                         handler[i], 0, pdev->name, iop_chan);
1401                         if (ret)
1402                                 goto err_free_iop_chan;
1403                 }
1404         }
1405
1406         spin_lock_init(&iop_chan->lock);
1407         INIT_LIST_HEAD(&iop_chan->chain);
1408         INIT_LIST_HEAD(&iop_chan->all_slots);
1409         iop_chan->common.device = dma_dev;
1410         list_add_tail(&iop_chan->common.device_node, &dma_dev->channels);
1411
1412         if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1413                 ret = iop_adma_memcpy_self_test(adev);
1414                 dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
1415                 if (ret)
1416                         goto err_free_iop_chan;
1417         }
1418
1419         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask) ||
1420                 dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) {
1421                 ret = iop_adma_xor_val_self_test(adev);
1422                 dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
1423                 if (ret)
1424                         goto err_free_iop_chan;
1425         }
1426
1427         dev_printk(KERN_INFO, &pdev->dev, "Intel(R) IOP: "
1428           "( %s%s%s%s%s%s%s%s%s%s)\n",
1429           dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "pq " : "",
1430           dma_has_cap(DMA_PQ_UPDATE, dma_dev->cap_mask) ? "pq_update " : "",
1431           dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask) ? "pq_val " : "",
1432           dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1433           dma_has_cap(DMA_DUAL_XOR, dma_dev->cap_mask) ? "dual_xor " : "",
1434           dma_has_cap(DMA_XOR_VAL, dma_dev->cap_mask) ? "xor_val " : "",
1435           dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)  ? "fill " : "",
1436           dma_has_cap(DMA_MEMCPY_CRC32C, dma_dev->cap_mask) ? "cpy+crc " : "",
1437           dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
1438           dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
1439
1440         dma_async_device_register(dma_dev);
1441         goto out;
1442
1443  err_free_iop_chan:
1444         kfree(iop_chan);
1445  err_free_dma:
1446         dma_free_coherent(&adev->pdev->dev, plat_data->pool_size,
1447                         adev->dma_desc_pool_virt, adev->dma_desc_pool);
1448  err_free_adev:
1449         kfree(adev);
1450  out:
1451         return ret;
1452 }
1453
1454 static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan)
1455 {
1456         struct iop_adma_desc_slot *sw_desc, *grp_start;
1457         dma_cookie_t cookie;
1458         int slot_cnt, slots_per_op;
1459
1460         dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1461
1462         spin_lock_bh(&iop_chan->lock);
1463         slot_cnt = iop_chan_memcpy_slot_count(0, &slots_per_op);
1464         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1465         if (sw_desc) {
1466                 grp_start = sw_desc->group_head;
1467
1468                 list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain);
1469                 async_tx_ack(&sw_desc->async_tx);
1470                 iop_desc_init_memcpy(grp_start, 0);
1471                 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1472                 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1473                 iop_desc_set_memcpy_src_addr(grp_start, 0);
1474
1475                 cookie = iop_chan->common.cookie;
1476                 cookie++;
1477                 if (cookie <= 1)
1478                         cookie = 2;
1479
1480                 /* initialize the completed cookie to be less than
1481                  * the most recently used cookie
1482                  */
1483                 iop_chan->completed_cookie = cookie - 1;
1484                 iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
1485
1486                 /* channel should not be busy */
1487                 BUG_ON(iop_chan_is_busy(iop_chan));
1488
1489                 /* clear any prior error-status bits */
1490                 iop_adma_device_clear_err_status(iop_chan);
1491
1492                 /* disable operation */
1493                 iop_chan_disable(iop_chan);
1494
1495                 /* set the descriptor address */
1496                 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1497
1498                 /* 1/ don't add pre-chained descriptors
1499                  * 2/ dummy read to flush next_desc write
1500                  */
1501                 BUG_ON(iop_desc_get_next_desc(sw_desc));
1502
1503                 /* run the descriptor */
1504                 iop_chan_enable(iop_chan);
1505         } else
1506                 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1507                          "failed to allocate null descriptor\n");
1508         spin_unlock_bh(&iop_chan->lock);
1509 }
1510
1511 static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan)
1512 {
1513         struct iop_adma_desc_slot *sw_desc, *grp_start;
1514         dma_cookie_t cookie;
1515         int slot_cnt, slots_per_op;
1516
1517         dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1518
1519         spin_lock_bh(&iop_chan->lock);
1520         slot_cnt = iop_chan_xor_slot_count(0, 2, &slots_per_op);
1521         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1522         if (sw_desc) {
1523                 grp_start = sw_desc->group_head;
1524                 list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain);
1525                 async_tx_ack(&sw_desc->async_tx);
1526                 iop_desc_init_null_xor(grp_start, 2, 0);
1527                 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1528                 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1529                 iop_desc_set_xor_src_addr(grp_start, 0, 0);
1530                 iop_desc_set_xor_src_addr(grp_start, 1, 0);
1531
1532                 cookie = iop_chan->common.cookie;
1533                 cookie++;
1534                 if (cookie <= 1)
1535                         cookie = 2;
1536
1537                 /* initialize the completed cookie to be less than
1538                  * the most recently used cookie
1539                  */
1540                 iop_chan->completed_cookie = cookie - 1;
1541                 iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
1542
1543                 /* channel should not be busy */
1544                 BUG_ON(iop_chan_is_busy(iop_chan));
1545
1546                 /* clear any prior error-status bits */
1547                 iop_adma_device_clear_err_status(iop_chan);
1548
1549                 /* disable operation */
1550                 iop_chan_disable(iop_chan);
1551
1552                 /* set the descriptor address */
1553                 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1554
1555                 /* 1/ don't add pre-chained descriptors
1556                  * 2/ dummy read to flush next_desc write
1557                  */
1558                 BUG_ON(iop_desc_get_next_desc(sw_desc));
1559
1560                 /* run the descriptor */
1561                 iop_chan_enable(iop_chan);
1562         } else
1563                 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1564                         "failed to allocate null descriptor\n");
1565         spin_unlock_bh(&iop_chan->lock);
1566 }
1567
1568 MODULE_ALIAS("platform:iop-adma");
1569
1570 static struct platform_driver iop_adma_driver = {
1571         .probe          = iop_adma_probe,
1572         .remove         = __devexit_p(iop_adma_remove),
1573         .driver         = {
1574                 .owner  = THIS_MODULE,
1575                 .name   = "iop-adma",
1576         },
1577 };
1578
1579 static int __init iop_adma_init (void)
1580 {
1581         return platform_driver_register(&iop_adma_driver);
1582 }
1583
1584 static void __exit iop_adma_exit (void)
1585 {
1586         platform_driver_unregister(&iop_adma_driver);
1587         return;
1588 }
1589 module_exit(iop_adma_exit);
1590 module_init(iop_adma_init);
1591
1592 MODULE_AUTHOR("Intel Corporation");
1593 MODULE_DESCRIPTION("IOP ADMA Engine Driver");
1594 MODULE_LICENSE("GPL");