async_tx: kill ->device_dependency_added
[linux-2.6.git] / drivers / dma / iop-adma.c
1 /*
2  * offload engine driver for the Intel Xscale series of i/o processors
3  * Copyright © 2006, Intel Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17  *
18  */
19
20 /*
21  * This driver supports the asynchrounous DMA copy and RAID engines available
22  * on the Intel Xscale(R) family of I/O Processors (IOP 32x, 33x, 134x)
23  */
24
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/async_tx.h>
28 #include <linux/delay.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/spinlock.h>
31 #include <linux/interrupt.h>
32 #include <linux/platform_device.h>
33 #include <linux/memory.h>
34 #include <linux/ioport.h>
35
36 #include <asm/arch/adma.h>
37
38 #define to_iop_adma_chan(chan) container_of(chan, struct iop_adma_chan, common)
39 #define to_iop_adma_device(dev) \
40         container_of(dev, struct iop_adma_device, common)
41 #define tx_to_iop_adma_slot(tx) \
42         container_of(tx, struct iop_adma_desc_slot, async_tx)
43
44 /**
45  * iop_adma_free_slots - flags descriptor slots for reuse
46  * @slot: Slot to free
47  * Caller must hold &iop_chan->lock while calling this function
48  */
49 static void iop_adma_free_slots(struct iop_adma_desc_slot *slot)
50 {
51         int stride = slot->slots_per_op;
52
53         while (stride--) {
54                 slot->slots_per_op = 0;
55                 slot = list_entry(slot->slot_node.next,
56                                 struct iop_adma_desc_slot,
57                                 slot_node);
58         }
59 }
60
61 static dma_cookie_t
62 iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc,
63         struct iop_adma_chan *iop_chan, dma_cookie_t cookie)
64 {
65         BUG_ON(desc->async_tx.cookie < 0);
66         if (desc->async_tx.cookie > 0) {
67                 cookie = desc->async_tx.cookie;
68                 desc->async_tx.cookie = 0;
69
70                 /* call the callback (must not sleep or submit new
71                  * operations to this channel)
72                  */
73                 if (desc->async_tx.callback)
74                         desc->async_tx.callback(
75                                 desc->async_tx.callback_param);
76
77                 /* unmap dma addresses
78                  * (unmap_single vs unmap_page?)
79                  */
80                 if (desc->group_head && desc->unmap_len) {
81                         struct iop_adma_desc_slot *unmap = desc->group_head;
82                         struct device *dev =
83                                 &iop_chan->device->pdev->dev;
84                         u32 len = unmap->unmap_len;
85                         u32 src_cnt = unmap->unmap_src_cnt;
86                         dma_addr_t addr = iop_desc_get_dest_addr(unmap,
87                                 iop_chan);
88
89                         dma_unmap_page(dev, addr, len, DMA_FROM_DEVICE);
90                         while (src_cnt--) {
91                                 addr = iop_desc_get_src_addr(unmap,
92                                                         iop_chan,
93                                                         src_cnt);
94                                 dma_unmap_page(dev, addr, len,
95                                         DMA_TO_DEVICE);
96                         }
97                         desc->group_head = NULL;
98                 }
99         }
100
101         /* run dependent operations */
102         async_tx_run_dependencies(&desc->async_tx);
103
104         return cookie;
105 }
106
107 static int
108 iop_adma_clean_slot(struct iop_adma_desc_slot *desc,
109         struct iop_adma_chan *iop_chan)
110 {
111         /* the client is allowed to attach dependent operations
112          * until 'ack' is set
113          */
114         if (!desc->async_tx.ack)
115                 return 0;
116
117         /* leave the last descriptor in the chain
118          * so we can append to it
119          */
120         if (desc->chain_node.next == &iop_chan->chain)
121                 return 1;
122
123         dev_dbg(iop_chan->device->common.dev,
124                 "\tfree slot: %d slots_per_op: %d\n",
125                 desc->idx, desc->slots_per_op);
126
127         list_del(&desc->chain_node);
128         iop_adma_free_slots(desc);
129
130         return 0;
131 }
132
133 static void __iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
134 {
135         struct iop_adma_desc_slot *iter, *_iter, *grp_start = NULL;
136         dma_cookie_t cookie = 0;
137         u32 current_desc = iop_chan_get_current_descriptor(iop_chan);
138         int busy = iop_chan_is_busy(iop_chan);
139         int seen_current = 0, slot_cnt = 0, slots_per_op = 0;
140
141         dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
142         /* free completed slots from the chain starting with
143          * the oldest descriptor
144          */
145         list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
146                                         chain_node) {
147                 pr_debug("\tcookie: %d slot: %d busy: %d "
148                         "this_desc: %#x next_desc: %#x ack: %d\n",
149                         iter->async_tx.cookie, iter->idx, busy,
150                         iter->async_tx.phys, iop_desc_get_next_desc(iter),
151                         iter->async_tx.ack);
152                 prefetch(_iter);
153                 prefetch(&_iter->async_tx);
154
155                 /* do not advance past the current descriptor loaded into the
156                  * hardware channel, subsequent descriptors are either in
157                  * process or have not been submitted
158                  */
159                 if (seen_current)
160                         break;
161
162                 /* stop the search if we reach the current descriptor and the
163                  * channel is busy, or if it appears that the current descriptor
164                  * needs to be re-read (i.e. has been appended to)
165                  */
166                 if (iter->async_tx.phys == current_desc) {
167                         BUG_ON(seen_current++);
168                         if (busy || iop_desc_get_next_desc(iter))
169                                 break;
170                 }
171
172                 /* detect the start of a group transaction */
173                 if (!slot_cnt && !slots_per_op) {
174                         slot_cnt = iter->slot_cnt;
175                         slots_per_op = iter->slots_per_op;
176                         if (slot_cnt <= slots_per_op) {
177                                 slot_cnt = 0;
178                                 slots_per_op = 0;
179                         }
180                 }
181
182                 if (slot_cnt) {
183                         pr_debug("\tgroup++\n");
184                         if (!grp_start)
185                                 grp_start = iter;
186                         slot_cnt -= slots_per_op;
187                 }
188
189                 /* all the members of a group are complete */
190                 if (slots_per_op != 0 && slot_cnt == 0) {
191                         struct iop_adma_desc_slot *grp_iter, *_grp_iter;
192                         int end_of_chain = 0;
193                         pr_debug("\tgroup end\n");
194
195                         /* collect the total results */
196                         if (grp_start->xor_check_result) {
197                                 u32 zero_sum_result = 0;
198                                 slot_cnt = grp_start->slot_cnt;
199                                 grp_iter = grp_start;
200
201                                 list_for_each_entry_from(grp_iter,
202                                         &iop_chan->chain, chain_node) {
203                                         zero_sum_result |=
204                                             iop_desc_get_zero_result(grp_iter);
205                                             pr_debug("\titer%d result: %d\n",
206                                             grp_iter->idx, zero_sum_result);
207                                         slot_cnt -= slots_per_op;
208                                         if (slot_cnt == 0)
209                                                 break;
210                                 }
211                                 pr_debug("\tgrp_start->xor_check_result: %p\n",
212                                         grp_start->xor_check_result);
213                                 *grp_start->xor_check_result = zero_sum_result;
214                         }
215
216                         /* clean up the group */
217                         slot_cnt = grp_start->slot_cnt;
218                         grp_iter = grp_start;
219                         list_for_each_entry_safe_from(grp_iter, _grp_iter,
220                                 &iop_chan->chain, chain_node) {
221                                 cookie = iop_adma_run_tx_complete_actions(
222                                         grp_iter, iop_chan, cookie);
223
224                                 slot_cnt -= slots_per_op;
225                                 end_of_chain = iop_adma_clean_slot(grp_iter,
226                                         iop_chan);
227
228                                 if (slot_cnt == 0 || end_of_chain)
229                                         break;
230                         }
231
232                         /* the group should be complete at this point */
233                         BUG_ON(slot_cnt);
234
235                         slots_per_op = 0;
236                         grp_start = NULL;
237                         if (end_of_chain)
238                                 break;
239                         else
240                                 continue;
241                 } else if (slots_per_op) /* wait for group completion */
242                         continue;
243
244                 /* write back zero sum results (single descriptor case) */
245                 if (iter->xor_check_result && iter->async_tx.cookie)
246                         *iter->xor_check_result =
247                                 iop_desc_get_zero_result(iter);
248
249                 cookie = iop_adma_run_tx_complete_actions(
250                                         iter, iop_chan, cookie);
251
252                 if (iop_adma_clean_slot(iter, iop_chan))
253                         break;
254         }
255
256         BUG_ON(!seen_current);
257
258         iop_chan_idle(busy, iop_chan);
259
260         if (cookie > 0) {
261                 iop_chan->completed_cookie = cookie;
262                 pr_debug("\tcompleted cookie %d\n", cookie);
263         }
264 }
265
266 static void
267 iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
268 {
269         spin_lock_bh(&iop_chan->lock);
270         __iop_adma_slot_cleanup(iop_chan);
271         spin_unlock_bh(&iop_chan->lock);
272 }
273
274 static void iop_adma_tasklet(unsigned long data)
275 {
276         struct iop_adma_chan *iop_chan = (struct iop_adma_chan *) data;
277
278         spin_lock(&iop_chan->lock);
279         __iop_adma_slot_cleanup(iop_chan);
280         spin_unlock(&iop_chan->lock);
281 }
282
283 static struct iop_adma_desc_slot *
284 iop_adma_alloc_slots(struct iop_adma_chan *iop_chan, int num_slots,
285                         int slots_per_op)
286 {
287         struct iop_adma_desc_slot *iter, *_iter, *alloc_start = NULL;
288         LIST_HEAD(chain);
289         int slots_found, retry = 0;
290
291         /* start search from the last allocated descrtiptor
292          * if a contiguous allocation can not be found start searching
293          * from the beginning of the list
294          */
295 retry:
296         slots_found = 0;
297         if (retry == 0)
298                 iter = iop_chan->last_used;
299         else
300                 iter = list_entry(&iop_chan->all_slots,
301                         struct iop_adma_desc_slot,
302                         slot_node);
303
304         list_for_each_entry_safe_continue(
305                 iter, _iter, &iop_chan->all_slots, slot_node) {
306                 prefetch(_iter);
307                 prefetch(&_iter->async_tx);
308                 if (iter->slots_per_op) {
309                         /* give up after finding the first busy slot
310                          * on the second pass through the list
311                          */
312                         if (retry)
313                                 break;
314
315                         slots_found = 0;
316                         continue;
317                 }
318
319                 /* start the allocation if the slot is correctly aligned */
320                 if (!slots_found++) {
321                         if (iop_desc_is_aligned(iter, slots_per_op))
322                                 alloc_start = iter;
323                         else {
324                                 slots_found = 0;
325                                 continue;
326                         }
327                 }
328
329                 if (slots_found == num_slots) {
330                         struct iop_adma_desc_slot *alloc_tail = NULL;
331                         struct iop_adma_desc_slot *last_used = NULL;
332                         iter = alloc_start;
333                         while (num_slots) {
334                                 int i;
335                                 dev_dbg(iop_chan->device->common.dev,
336                                         "allocated slot: %d "
337                                         "(desc %p phys: %#x) slots_per_op %d\n",
338                                         iter->idx, iter->hw_desc,
339                                         iter->async_tx.phys, slots_per_op);
340
341                                 /* pre-ack all but the last descriptor */
342                                 if (num_slots != slots_per_op)
343                                         iter->async_tx.ack = 1;
344                                 else
345                                         iter->async_tx.ack = 0;
346
347                                 list_add_tail(&iter->chain_node, &chain);
348                                 alloc_tail = iter;
349                                 iter->async_tx.cookie = 0;
350                                 iter->slot_cnt = num_slots;
351                                 iter->xor_check_result = NULL;
352                                 for (i = 0; i < slots_per_op; i++) {
353                                         iter->slots_per_op = slots_per_op - i;
354                                         last_used = iter;
355                                         iter = list_entry(iter->slot_node.next,
356                                                 struct iop_adma_desc_slot,
357                                                 slot_node);
358                                 }
359                                 num_slots -= slots_per_op;
360                         }
361                         alloc_tail->group_head = alloc_start;
362                         alloc_tail->async_tx.cookie = -EBUSY;
363                         list_splice(&chain, &alloc_tail->async_tx.tx_list);
364                         iop_chan->last_used = last_used;
365                         iop_desc_clear_next_desc(alloc_start);
366                         iop_desc_clear_next_desc(alloc_tail);
367                         return alloc_tail;
368                 }
369         }
370         if (!retry++)
371                 goto retry;
372
373         /* try to free some slots if the allocation fails */
374         tasklet_schedule(&iop_chan->irq_tasklet);
375
376         return NULL;
377 }
378
379 static dma_cookie_t
380 iop_desc_assign_cookie(struct iop_adma_chan *iop_chan,
381         struct iop_adma_desc_slot *desc)
382 {
383         dma_cookie_t cookie = iop_chan->common.cookie;
384         cookie++;
385         if (cookie < 0)
386                 cookie = 1;
387         iop_chan->common.cookie = desc->async_tx.cookie = cookie;
388         return cookie;
389 }
390
391 static void iop_adma_check_threshold(struct iop_adma_chan *iop_chan)
392 {
393         dev_dbg(iop_chan->device->common.dev, "pending: %d\n",
394                 iop_chan->pending);
395
396         if (iop_chan->pending >= IOP_ADMA_THRESHOLD) {
397                 iop_chan->pending = 0;
398                 iop_chan_append(iop_chan);
399         }
400 }
401
402 static dma_cookie_t
403 iop_adma_tx_submit(struct dma_async_tx_descriptor *tx)
404 {
405         struct iop_adma_desc_slot *sw_desc = tx_to_iop_adma_slot(tx);
406         struct iop_adma_chan *iop_chan = to_iop_adma_chan(tx->chan);
407         struct iop_adma_desc_slot *grp_start, *old_chain_tail;
408         int slot_cnt;
409         int slots_per_op;
410         dma_cookie_t cookie;
411
412         grp_start = sw_desc->group_head;
413         slot_cnt = grp_start->slot_cnt;
414         slots_per_op = grp_start->slots_per_op;
415
416         spin_lock_bh(&iop_chan->lock);
417         cookie = iop_desc_assign_cookie(iop_chan, sw_desc);
418
419         old_chain_tail = list_entry(iop_chan->chain.prev,
420                 struct iop_adma_desc_slot, chain_node);
421         list_splice_init(&sw_desc->async_tx.tx_list,
422                          &old_chain_tail->chain_node);
423
424         /* fix up the hardware chain */
425         iop_desc_set_next_desc(old_chain_tail, grp_start->async_tx.phys);
426
427         /* 1/ don't add pre-chained descriptors
428          * 2/ dummy read to flush next_desc write
429          */
430         BUG_ON(iop_desc_get_next_desc(sw_desc));
431
432         /* increment the pending count by the number of slots
433          * memcpy operations have a 1:1 (slot:operation) relation
434          * other operations are heavier and will pop the threshold
435          * more often.
436          */
437         iop_chan->pending += slot_cnt;
438         iop_adma_check_threshold(iop_chan);
439         spin_unlock_bh(&iop_chan->lock);
440
441         dev_dbg(iop_chan->device->common.dev, "%s cookie: %d slot: %d\n",
442                 __func__, sw_desc->async_tx.cookie, sw_desc->idx);
443
444         return cookie;
445 }
446
447 static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan);
448 static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan);
449
450 /* returns the number of allocated descriptors */
451 static int iop_adma_alloc_chan_resources(struct dma_chan *chan)
452 {
453         char *hw_desc;
454         int idx;
455         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
456         struct iop_adma_desc_slot *slot = NULL;
457         int init = iop_chan->slots_allocated ? 0 : 1;
458         struct iop_adma_platform_data *plat_data =
459                 iop_chan->device->pdev->dev.platform_data;
460         int num_descs_in_pool = plat_data->pool_size/IOP_ADMA_SLOT_SIZE;
461
462         /* Allocate descriptor slots */
463         do {
464                 idx = iop_chan->slots_allocated;
465                 if (idx == num_descs_in_pool)
466                         break;
467
468                 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
469                 if (!slot) {
470                         printk(KERN_INFO "IOP ADMA Channel only initialized"
471                                 " %d descriptor slots", idx);
472                         break;
473                 }
474                 hw_desc = (char *) iop_chan->device->dma_desc_pool_virt;
475                 slot->hw_desc = (void *) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
476
477                 dma_async_tx_descriptor_init(&slot->async_tx, chan);
478                 slot->async_tx.tx_submit = iop_adma_tx_submit;
479                 INIT_LIST_HEAD(&slot->chain_node);
480                 INIT_LIST_HEAD(&slot->slot_node);
481                 INIT_LIST_HEAD(&slot->async_tx.tx_list);
482                 hw_desc = (char *) iop_chan->device->dma_desc_pool;
483                 slot->async_tx.phys =
484                         (dma_addr_t) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
485                 slot->idx = idx;
486
487                 spin_lock_bh(&iop_chan->lock);
488                 iop_chan->slots_allocated++;
489                 list_add_tail(&slot->slot_node, &iop_chan->all_slots);
490                 spin_unlock_bh(&iop_chan->lock);
491         } while (iop_chan->slots_allocated < num_descs_in_pool);
492
493         if (idx && !iop_chan->last_used)
494                 iop_chan->last_used = list_entry(iop_chan->all_slots.next,
495                                         struct iop_adma_desc_slot,
496                                         slot_node);
497
498         dev_dbg(iop_chan->device->common.dev,
499                 "allocated %d descriptor slots last_used: %p\n",
500                 iop_chan->slots_allocated, iop_chan->last_used);
501
502         /* initialize the channel and the chain with a null operation */
503         if (init) {
504                 if (dma_has_cap(DMA_MEMCPY,
505                         iop_chan->device->common.cap_mask))
506                         iop_chan_start_null_memcpy(iop_chan);
507                 else if (dma_has_cap(DMA_XOR,
508                         iop_chan->device->common.cap_mask))
509                         iop_chan_start_null_xor(iop_chan);
510                 else
511                         BUG();
512         }
513
514         return (idx > 0) ? idx : -ENOMEM;
515 }
516
517 static struct dma_async_tx_descriptor *
518 iop_adma_prep_dma_interrupt(struct dma_chan *chan)
519 {
520         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
521         struct iop_adma_desc_slot *sw_desc, *grp_start;
522         int slot_cnt, slots_per_op;
523
524         dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
525
526         spin_lock_bh(&iop_chan->lock);
527         slot_cnt = iop_chan_interrupt_slot_count(&slots_per_op, iop_chan);
528         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
529         if (sw_desc) {
530                 grp_start = sw_desc->group_head;
531                 iop_desc_init_interrupt(grp_start, iop_chan);
532                 grp_start->unmap_len = 0;
533         }
534         spin_unlock_bh(&iop_chan->lock);
535
536         return sw_desc ? &sw_desc->async_tx : NULL;
537 }
538
539 static struct dma_async_tx_descriptor *
540 iop_adma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest,
541                          dma_addr_t dma_src, size_t len, unsigned long flags)
542 {
543         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
544         struct iop_adma_desc_slot *sw_desc, *grp_start;
545         int slot_cnt, slots_per_op;
546
547         if (unlikely(!len))
548                 return NULL;
549         BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT));
550
551         dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
552                 __func__, len);
553
554         spin_lock_bh(&iop_chan->lock);
555         slot_cnt = iop_chan_memcpy_slot_count(len, &slots_per_op);
556         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
557         if (sw_desc) {
558                 grp_start = sw_desc->group_head;
559                 iop_desc_init_memcpy(grp_start, flags);
560                 iop_desc_set_byte_count(grp_start, iop_chan, len);
561                 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
562                 iop_desc_set_memcpy_src_addr(grp_start, dma_src);
563                 sw_desc->unmap_src_cnt = 1;
564                 sw_desc->unmap_len = len;
565         }
566         spin_unlock_bh(&iop_chan->lock);
567
568         return sw_desc ? &sw_desc->async_tx : NULL;
569 }
570
571 static struct dma_async_tx_descriptor *
572 iop_adma_prep_dma_memset(struct dma_chan *chan, dma_addr_t dma_dest,
573                          int value, size_t len, unsigned long flags)
574 {
575         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
576         struct iop_adma_desc_slot *sw_desc, *grp_start;
577         int slot_cnt, slots_per_op;
578
579         if (unlikely(!len))
580                 return NULL;
581         BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT));
582
583         dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
584                 __func__, len);
585
586         spin_lock_bh(&iop_chan->lock);
587         slot_cnt = iop_chan_memset_slot_count(len, &slots_per_op);
588         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
589         if (sw_desc) {
590                 grp_start = sw_desc->group_head;
591                 iop_desc_init_memset(grp_start, flags);
592                 iop_desc_set_byte_count(grp_start, iop_chan, len);
593                 iop_desc_set_block_fill_val(grp_start, value);
594                 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
595                 sw_desc->unmap_src_cnt = 1;
596                 sw_desc->unmap_len = len;
597         }
598         spin_unlock_bh(&iop_chan->lock);
599
600         return sw_desc ? &sw_desc->async_tx : NULL;
601 }
602
603 static struct dma_async_tx_descriptor *
604 iop_adma_prep_dma_xor(struct dma_chan *chan, dma_addr_t dma_dest,
605                       dma_addr_t *dma_src, unsigned int src_cnt, size_t len,
606                       unsigned long flags)
607 {
608         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
609         struct iop_adma_desc_slot *sw_desc, *grp_start;
610         int slot_cnt, slots_per_op;
611
612         if (unlikely(!len))
613                 return NULL;
614         BUG_ON(unlikely(len > IOP_ADMA_XOR_MAX_BYTE_COUNT));
615
616         dev_dbg(iop_chan->device->common.dev,
617                 "%s src_cnt: %d len: %u flags: %lx\n",
618                 __func__, src_cnt, len, flags);
619
620         spin_lock_bh(&iop_chan->lock);
621         slot_cnt = iop_chan_xor_slot_count(len, src_cnt, &slots_per_op);
622         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
623         if (sw_desc) {
624                 grp_start = sw_desc->group_head;
625                 iop_desc_init_xor(grp_start, src_cnt, flags);
626                 iop_desc_set_byte_count(grp_start, iop_chan, len);
627                 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
628                 sw_desc->unmap_src_cnt = src_cnt;
629                 sw_desc->unmap_len = len;
630                 while (src_cnt--)
631                         iop_desc_set_xor_src_addr(grp_start, src_cnt,
632                                                   dma_src[src_cnt]);
633         }
634         spin_unlock_bh(&iop_chan->lock);
635
636         return sw_desc ? &sw_desc->async_tx : NULL;
637 }
638
639 static struct dma_async_tx_descriptor *
640 iop_adma_prep_dma_zero_sum(struct dma_chan *chan, dma_addr_t *dma_src,
641                            unsigned int src_cnt, size_t len, u32 *result,
642                            unsigned long flags)
643 {
644         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
645         struct iop_adma_desc_slot *sw_desc, *grp_start;
646         int slot_cnt, slots_per_op;
647
648         if (unlikely(!len))
649                 return NULL;
650
651         dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u\n",
652                 __func__, src_cnt, len);
653
654         spin_lock_bh(&iop_chan->lock);
655         slot_cnt = iop_chan_zero_sum_slot_count(len, src_cnt, &slots_per_op);
656         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
657         if (sw_desc) {
658                 grp_start = sw_desc->group_head;
659                 iop_desc_init_zero_sum(grp_start, src_cnt, flags);
660                 iop_desc_set_zero_sum_byte_count(grp_start, len);
661                 grp_start->xor_check_result = result;
662                 pr_debug("\t%s: grp_start->xor_check_result: %p\n",
663                         __func__, grp_start->xor_check_result);
664                 sw_desc->unmap_src_cnt = src_cnt;
665                 sw_desc->unmap_len = len;
666                 while (src_cnt--)
667                         iop_desc_set_zero_sum_src_addr(grp_start, src_cnt,
668                                                        dma_src[src_cnt]);
669         }
670         spin_unlock_bh(&iop_chan->lock);
671
672         return sw_desc ? &sw_desc->async_tx : NULL;
673 }
674
675 static void iop_adma_free_chan_resources(struct dma_chan *chan)
676 {
677         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
678         struct iop_adma_desc_slot *iter, *_iter;
679         int in_use_descs = 0;
680
681         iop_adma_slot_cleanup(iop_chan);
682
683         spin_lock_bh(&iop_chan->lock);
684         list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
685                                         chain_node) {
686                 in_use_descs++;
687                 list_del(&iter->chain_node);
688         }
689         list_for_each_entry_safe_reverse(
690                 iter, _iter, &iop_chan->all_slots, slot_node) {
691                 list_del(&iter->slot_node);
692                 kfree(iter);
693                 iop_chan->slots_allocated--;
694         }
695         iop_chan->last_used = NULL;
696
697         dev_dbg(iop_chan->device->common.dev, "%s slots_allocated %d\n",
698                 __func__, iop_chan->slots_allocated);
699         spin_unlock_bh(&iop_chan->lock);
700
701         /* one is ok since we left it on there on purpose */
702         if (in_use_descs > 1)
703                 printk(KERN_ERR "IOP: Freeing %d in use descriptors!\n",
704                         in_use_descs - 1);
705 }
706
707 /**
708  * iop_adma_is_complete - poll the status of an ADMA transaction
709  * @chan: ADMA channel handle
710  * @cookie: ADMA transaction identifier
711  */
712 static enum dma_status iop_adma_is_complete(struct dma_chan *chan,
713                                         dma_cookie_t cookie,
714                                         dma_cookie_t *done,
715                                         dma_cookie_t *used)
716 {
717         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
718         dma_cookie_t last_used;
719         dma_cookie_t last_complete;
720         enum dma_status ret;
721
722         last_used = chan->cookie;
723         last_complete = iop_chan->completed_cookie;
724
725         if (done)
726                 *done = last_complete;
727         if (used)
728                 *used = last_used;
729
730         ret = dma_async_is_complete(cookie, last_complete, last_used);
731         if (ret == DMA_SUCCESS)
732                 return ret;
733
734         iop_adma_slot_cleanup(iop_chan);
735
736         last_used = chan->cookie;
737         last_complete = iop_chan->completed_cookie;
738
739         if (done)
740                 *done = last_complete;
741         if (used)
742                 *used = last_used;
743
744         return dma_async_is_complete(cookie, last_complete, last_used);
745 }
746
747 static irqreturn_t iop_adma_eot_handler(int irq, void *data)
748 {
749         struct iop_adma_chan *chan = data;
750
751         dev_dbg(chan->device->common.dev, "%s\n", __func__);
752
753         tasklet_schedule(&chan->irq_tasklet);
754
755         iop_adma_device_clear_eot_status(chan);
756
757         return IRQ_HANDLED;
758 }
759
760 static irqreturn_t iop_adma_eoc_handler(int irq, void *data)
761 {
762         struct iop_adma_chan *chan = data;
763
764         dev_dbg(chan->device->common.dev, "%s\n", __func__);
765
766         tasklet_schedule(&chan->irq_tasklet);
767
768         iop_adma_device_clear_eoc_status(chan);
769
770         return IRQ_HANDLED;
771 }
772
773 static irqreturn_t iop_adma_err_handler(int irq, void *data)
774 {
775         struct iop_adma_chan *chan = data;
776         unsigned long status = iop_chan_get_status(chan);
777
778         dev_printk(KERN_ERR, chan->device->common.dev,
779                 "error ( %s%s%s%s%s%s%s)\n",
780                 iop_is_err_int_parity(status, chan) ? "int_parity " : "",
781                 iop_is_err_mcu_abort(status, chan) ? "mcu_abort " : "",
782                 iop_is_err_int_tabort(status, chan) ? "int_tabort " : "",
783                 iop_is_err_int_mabort(status, chan) ? "int_mabort " : "",
784                 iop_is_err_pci_tabort(status, chan) ? "pci_tabort " : "",
785                 iop_is_err_pci_mabort(status, chan) ? "pci_mabort " : "",
786                 iop_is_err_split_tx(status, chan) ? "split_tx " : "");
787
788         iop_adma_device_clear_err_status(chan);
789
790         BUG();
791
792         return IRQ_HANDLED;
793 }
794
795 static void iop_adma_issue_pending(struct dma_chan *chan)
796 {
797         struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
798
799         if (iop_chan->pending) {
800                 iop_chan->pending = 0;
801                 iop_chan_append(iop_chan);
802         }
803 }
804
805 /*
806  * Perform a transaction to verify the HW works.
807  */
808 #define IOP_ADMA_TEST_SIZE 2000
809
810 static int __devinit iop_adma_memcpy_self_test(struct iop_adma_device *device)
811 {
812         int i;
813         void *src, *dest;
814         dma_addr_t src_dma, dest_dma;
815         struct dma_chan *dma_chan;
816         dma_cookie_t cookie;
817         struct dma_async_tx_descriptor *tx;
818         int err = 0;
819         struct iop_adma_chan *iop_chan;
820
821         dev_dbg(device->common.dev, "%s\n", __func__);
822
823         src = kzalloc(sizeof(u8) * IOP_ADMA_TEST_SIZE, GFP_KERNEL);
824         if (!src)
825                 return -ENOMEM;
826         dest = kzalloc(sizeof(u8) * IOP_ADMA_TEST_SIZE, GFP_KERNEL);
827         if (!dest) {
828                 kfree(src);
829                 return -ENOMEM;
830         }
831
832         /* Fill in src buffer */
833         for (i = 0; i < IOP_ADMA_TEST_SIZE; i++)
834                 ((u8 *) src)[i] = (u8)i;
835
836         memset(dest, 0, IOP_ADMA_TEST_SIZE);
837
838         /* Start copy, using first DMA channel */
839         dma_chan = container_of(device->common.channels.next,
840                                 struct dma_chan,
841                                 device_node);
842         if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
843                 err = -ENODEV;
844                 goto out;
845         }
846
847         dest_dma = dma_map_single(dma_chan->device->dev, dest,
848                                 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
849         src_dma = dma_map_single(dma_chan->device->dev, src,
850                                 IOP_ADMA_TEST_SIZE, DMA_TO_DEVICE);
851         tx = iop_adma_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
852                                       IOP_ADMA_TEST_SIZE, 1);
853
854         cookie = iop_adma_tx_submit(tx);
855         iop_adma_issue_pending(dma_chan);
856         async_tx_ack(tx);
857         msleep(1);
858
859         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
860                         DMA_SUCCESS) {
861                 dev_printk(KERN_ERR, dma_chan->device->dev,
862                         "Self-test copy timed out, disabling\n");
863                 err = -ENODEV;
864                 goto free_resources;
865         }
866
867         iop_chan = to_iop_adma_chan(dma_chan);
868         dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
869                 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
870         if (memcmp(src, dest, IOP_ADMA_TEST_SIZE)) {
871                 dev_printk(KERN_ERR, dma_chan->device->dev,
872                         "Self-test copy failed compare, disabling\n");
873                 err = -ENODEV;
874                 goto free_resources;
875         }
876
877 free_resources:
878         iop_adma_free_chan_resources(dma_chan);
879 out:
880         kfree(src);
881         kfree(dest);
882         return err;
883 }
884
885 #define IOP_ADMA_NUM_SRC_TEST 4 /* must be <= 15 */
886 static int __devinit
887 iop_adma_xor_zero_sum_self_test(struct iop_adma_device *device)
888 {
889         int i, src_idx;
890         struct page *dest;
891         struct page *xor_srcs[IOP_ADMA_NUM_SRC_TEST];
892         struct page *zero_sum_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
893         dma_addr_t dma_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
894         dma_addr_t dma_addr, dest_dma;
895         struct dma_async_tx_descriptor *tx;
896         struct dma_chan *dma_chan;
897         dma_cookie_t cookie;
898         u8 cmp_byte = 0;
899         u32 cmp_word;
900         u32 zero_sum_result;
901         int err = 0;
902         struct iop_adma_chan *iop_chan;
903
904         dev_dbg(device->common.dev, "%s\n", __func__);
905
906         for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
907                 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
908                 if (!xor_srcs[src_idx])
909                         while (src_idx--) {
910                                 __free_page(xor_srcs[src_idx]);
911                                 return -ENOMEM;
912                         }
913         }
914
915         dest = alloc_page(GFP_KERNEL);
916         if (!dest)
917                 while (src_idx--) {
918                         __free_page(xor_srcs[src_idx]);
919                         return -ENOMEM;
920                 }
921
922         /* Fill in src buffers */
923         for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
924                 u8 *ptr = page_address(xor_srcs[src_idx]);
925                 for (i = 0; i < PAGE_SIZE; i++)
926                         ptr[i] = (1 << src_idx);
927         }
928
929         for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++)
930                 cmp_byte ^= (u8) (1 << src_idx);
931
932         cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
933                         (cmp_byte << 8) | cmp_byte;
934
935         memset(page_address(dest), 0, PAGE_SIZE);
936
937         dma_chan = container_of(device->common.channels.next,
938                                 struct dma_chan,
939                                 device_node);
940         if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
941                 err = -ENODEV;
942                 goto out;
943         }
944
945         /* test xor */
946         dest_dma = dma_map_page(dma_chan->device->dev, dest, 0,
947                                 PAGE_SIZE, DMA_FROM_DEVICE);
948         for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
949                 dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
950                                            0, PAGE_SIZE, DMA_TO_DEVICE);
951         tx = iop_adma_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
952                                    IOP_ADMA_NUM_SRC_TEST, PAGE_SIZE, 1);
953
954         cookie = iop_adma_tx_submit(tx);
955         iop_adma_issue_pending(dma_chan);
956         async_tx_ack(tx);
957         msleep(8);
958
959         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
960                 DMA_SUCCESS) {
961                 dev_printk(KERN_ERR, dma_chan->device->dev,
962                         "Self-test xor timed out, disabling\n");
963                 err = -ENODEV;
964                 goto free_resources;
965         }
966
967         iop_chan = to_iop_adma_chan(dma_chan);
968         dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
969                 PAGE_SIZE, DMA_FROM_DEVICE);
970         for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
971                 u32 *ptr = page_address(dest);
972                 if (ptr[i] != cmp_word) {
973                         dev_printk(KERN_ERR, dma_chan->device->dev,
974                                 "Self-test xor failed compare, disabling\n");
975                         err = -ENODEV;
976                         goto free_resources;
977                 }
978         }
979         dma_sync_single_for_device(&iop_chan->device->pdev->dev, dest_dma,
980                 PAGE_SIZE, DMA_TO_DEVICE);
981
982         /* skip zero sum if the capability is not present */
983         if (!dma_has_cap(DMA_ZERO_SUM, dma_chan->device->cap_mask))
984                 goto free_resources;
985
986         /* zero sum the sources with the destintation page */
987         for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
988                 zero_sum_srcs[i] = xor_srcs[i];
989         zero_sum_srcs[i] = dest;
990
991         zero_sum_result = 1;
992
993         for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
994                 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
995                                            zero_sum_srcs[i], 0, PAGE_SIZE,
996                                            DMA_TO_DEVICE);
997         tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs,
998                                         IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
999                                         &zero_sum_result, 1);
1000
1001         cookie = iop_adma_tx_submit(tx);
1002         iop_adma_issue_pending(dma_chan);
1003         async_tx_ack(tx);
1004         msleep(8);
1005
1006         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1007                 dev_printk(KERN_ERR, dma_chan->device->dev,
1008                         "Self-test zero sum timed out, disabling\n");
1009                 err = -ENODEV;
1010                 goto free_resources;
1011         }
1012
1013         if (zero_sum_result != 0) {
1014                 dev_printk(KERN_ERR, dma_chan->device->dev,
1015                         "Self-test zero sum failed compare, disabling\n");
1016                 err = -ENODEV;
1017                 goto free_resources;
1018         }
1019
1020         /* test memset */
1021         dma_addr = dma_map_page(dma_chan->device->dev, dest, 0,
1022                         PAGE_SIZE, DMA_FROM_DEVICE);
1023         tx = iop_adma_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE, 1);
1024
1025         cookie = iop_adma_tx_submit(tx);
1026         iop_adma_issue_pending(dma_chan);
1027         async_tx_ack(tx);
1028         msleep(8);
1029
1030         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1031                 dev_printk(KERN_ERR, dma_chan->device->dev,
1032                         "Self-test memset timed out, disabling\n");
1033                 err = -ENODEV;
1034                 goto free_resources;
1035         }
1036
1037         for (i = 0; i < PAGE_SIZE/sizeof(u32); i++) {
1038                 u32 *ptr = page_address(dest);
1039                 if (ptr[i]) {
1040                         dev_printk(KERN_ERR, dma_chan->device->dev,
1041                                 "Self-test memset failed compare, disabling\n");
1042                         err = -ENODEV;
1043                         goto free_resources;
1044                 }
1045         }
1046
1047         /* test for non-zero parity sum */
1048         zero_sum_result = 0;
1049         for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
1050                 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
1051                                            zero_sum_srcs[i], 0, PAGE_SIZE,
1052                                            DMA_TO_DEVICE);
1053         tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs,
1054                                         IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1055                                         &zero_sum_result, 1);
1056
1057         cookie = iop_adma_tx_submit(tx);
1058         iop_adma_issue_pending(dma_chan);
1059         async_tx_ack(tx);
1060         msleep(8);
1061
1062         if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1063                 dev_printk(KERN_ERR, dma_chan->device->dev,
1064                         "Self-test non-zero sum timed out, disabling\n");
1065                 err = -ENODEV;
1066                 goto free_resources;
1067         }
1068
1069         if (zero_sum_result != 1) {
1070                 dev_printk(KERN_ERR, dma_chan->device->dev,
1071                         "Self-test non-zero sum failed compare, disabling\n");
1072                 err = -ENODEV;
1073                 goto free_resources;
1074         }
1075
1076 free_resources:
1077         iop_adma_free_chan_resources(dma_chan);
1078 out:
1079         src_idx = IOP_ADMA_NUM_SRC_TEST;
1080         while (src_idx--)
1081                 __free_page(xor_srcs[src_idx]);
1082         __free_page(dest);
1083         return err;
1084 }
1085
1086 static int __devexit iop_adma_remove(struct platform_device *dev)
1087 {
1088         struct iop_adma_device *device = platform_get_drvdata(dev);
1089         struct dma_chan *chan, *_chan;
1090         struct iop_adma_chan *iop_chan;
1091         int i;
1092         struct iop_adma_platform_data *plat_data = dev->dev.platform_data;
1093
1094         dma_async_device_unregister(&device->common);
1095
1096         for (i = 0; i < 3; i++) {
1097                 unsigned int irq;
1098                 irq = platform_get_irq(dev, i);
1099                 free_irq(irq, device);
1100         }
1101
1102         dma_free_coherent(&dev->dev, plat_data->pool_size,
1103                         device->dma_desc_pool_virt, device->dma_desc_pool);
1104
1105         do {
1106                 struct resource *res;
1107                 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1108                 release_mem_region(res->start, res->end - res->start);
1109         } while (0);
1110
1111         list_for_each_entry_safe(chan, _chan, &device->common.channels,
1112                                 device_node) {
1113                 iop_chan = to_iop_adma_chan(chan);
1114                 list_del(&chan->device_node);
1115                 kfree(iop_chan);
1116         }
1117         kfree(device);
1118
1119         return 0;
1120 }
1121
1122 static int __devinit iop_adma_probe(struct platform_device *pdev)
1123 {
1124         struct resource *res;
1125         int ret = 0, i;
1126         struct iop_adma_device *adev;
1127         struct iop_adma_chan *iop_chan;
1128         struct dma_device *dma_dev;
1129         struct iop_adma_platform_data *plat_data = pdev->dev.platform_data;
1130
1131         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1132         if (!res)
1133                 return -ENODEV;
1134
1135         if (!devm_request_mem_region(&pdev->dev, res->start,
1136                                 res->end - res->start, pdev->name))
1137                 return -EBUSY;
1138
1139         adev = kzalloc(sizeof(*adev), GFP_KERNEL);
1140         if (!adev)
1141                 return -ENOMEM;
1142         dma_dev = &adev->common;
1143
1144         /* allocate coherent memory for hardware descriptors
1145          * note: writecombine gives slightly better performance, but
1146          * requires that we explicitly flush the writes
1147          */
1148         if ((adev->dma_desc_pool_virt = dma_alloc_writecombine(&pdev->dev,
1149                                         plat_data->pool_size,
1150                                         &adev->dma_desc_pool,
1151                                         GFP_KERNEL)) == NULL) {
1152                 ret = -ENOMEM;
1153                 goto err_free_adev;
1154         }
1155
1156         dev_dbg(&pdev->dev, "%s: allocted descriptor pool virt %p phys %p\n",
1157                 __func__, adev->dma_desc_pool_virt,
1158                 (void *) adev->dma_desc_pool);
1159
1160         adev->id = plat_data->hw_id;
1161
1162         /* discover transaction capabilites from the platform data */
1163         dma_dev->cap_mask = plat_data->cap_mask;
1164
1165         adev->pdev = pdev;
1166         platform_set_drvdata(pdev, adev);
1167
1168         INIT_LIST_HEAD(&dma_dev->channels);
1169
1170         /* set base routines */
1171         dma_dev->device_alloc_chan_resources = iop_adma_alloc_chan_resources;
1172         dma_dev->device_free_chan_resources = iop_adma_free_chan_resources;
1173         dma_dev->device_is_tx_complete = iop_adma_is_complete;
1174         dma_dev->device_issue_pending = iop_adma_issue_pending;
1175         dma_dev->dev = &pdev->dev;
1176
1177         /* set prep routines based on capability */
1178         if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1179                 dma_dev->device_prep_dma_memcpy = iop_adma_prep_dma_memcpy;
1180         if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask))
1181                 dma_dev->device_prep_dma_memset = iop_adma_prep_dma_memset;
1182         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1183                 dma_dev->max_xor = iop_adma_get_max_xor();
1184                 dma_dev->device_prep_dma_xor = iop_adma_prep_dma_xor;
1185         }
1186         if (dma_has_cap(DMA_ZERO_SUM, dma_dev->cap_mask))
1187                 dma_dev->device_prep_dma_zero_sum =
1188                         iop_adma_prep_dma_zero_sum;
1189         if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask))
1190                 dma_dev->device_prep_dma_interrupt =
1191                         iop_adma_prep_dma_interrupt;
1192
1193         iop_chan = kzalloc(sizeof(*iop_chan), GFP_KERNEL);
1194         if (!iop_chan) {
1195                 ret = -ENOMEM;
1196                 goto err_free_dma;
1197         }
1198         iop_chan->device = adev;
1199
1200         iop_chan->mmr_base = devm_ioremap(&pdev->dev, res->start,
1201                                         res->end - res->start);
1202         if (!iop_chan->mmr_base) {
1203                 ret = -ENOMEM;
1204                 goto err_free_iop_chan;
1205         }
1206         tasklet_init(&iop_chan->irq_tasklet, iop_adma_tasklet, (unsigned long)
1207                 iop_chan);
1208
1209         /* clear errors before enabling interrupts */
1210         iop_adma_device_clear_err_status(iop_chan);
1211
1212         for (i = 0; i < 3; i++) {
1213                 irq_handler_t handler[] = { iop_adma_eot_handler,
1214                                         iop_adma_eoc_handler,
1215                                         iop_adma_err_handler };
1216                 int irq = platform_get_irq(pdev, i);
1217                 if (irq < 0) {
1218                         ret = -ENXIO;
1219                         goto err_free_iop_chan;
1220                 } else {
1221                         ret = devm_request_irq(&pdev->dev, irq,
1222                                         handler[i], 0, pdev->name, iop_chan);
1223                         if (ret)
1224                                 goto err_free_iop_chan;
1225                 }
1226         }
1227
1228         spin_lock_init(&iop_chan->lock);
1229         init_timer(&iop_chan->cleanup_watchdog);
1230         iop_chan->cleanup_watchdog.data = (unsigned long) iop_chan;
1231         iop_chan->cleanup_watchdog.function = iop_adma_tasklet;
1232         INIT_LIST_HEAD(&iop_chan->chain);
1233         INIT_LIST_HEAD(&iop_chan->all_slots);
1234         INIT_RCU_HEAD(&iop_chan->common.rcu);
1235         iop_chan->common.device = dma_dev;
1236         list_add_tail(&iop_chan->common.device_node, &dma_dev->channels);
1237
1238         if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1239                 ret = iop_adma_memcpy_self_test(adev);
1240                 dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
1241                 if (ret)
1242                         goto err_free_iop_chan;
1243         }
1244
1245         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask) ||
1246                 dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) {
1247                 ret = iop_adma_xor_zero_sum_self_test(adev);
1248                 dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
1249                 if (ret)
1250                         goto err_free_iop_chan;
1251         }
1252
1253         dev_printk(KERN_INFO, &pdev->dev, "Intel(R) IOP: "
1254           "( %s%s%s%s%s%s%s%s%s%s)\n",
1255           dma_has_cap(DMA_PQ_XOR, dma_dev->cap_mask) ? "pq_xor " : "",
1256           dma_has_cap(DMA_PQ_UPDATE, dma_dev->cap_mask) ? "pq_update " : "",
1257           dma_has_cap(DMA_PQ_ZERO_SUM, dma_dev->cap_mask) ? "pq_zero_sum " : "",
1258           dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1259           dma_has_cap(DMA_DUAL_XOR, dma_dev->cap_mask) ? "dual_xor " : "",
1260           dma_has_cap(DMA_ZERO_SUM, dma_dev->cap_mask) ? "xor_zero_sum " : "",
1261           dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)  ? "fill " : "",
1262           dma_has_cap(DMA_MEMCPY_CRC32C, dma_dev->cap_mask) ? "cpy+crc " : "",
1263           dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
1264           dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
1265
1266         dma_async_device_register(dma_dev);
1267         goto out;
1268
1269  err_free_iop_chan:
1270         kfree(iop_chan);
1271  err_free_dma:
1272         dma_free_coherent(&adev->pdev->dev, plat_data->pool_size,
1273                         adev->dma_desc_pool_virt, adev->dma_desc_pool);
1274  err_free_adev:
1275         kfree(adev);
1276  out:
1277         return ret;
1278 }
1279
1280 static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan)
1281 {
1282         struct iop_adma_desc_slot *sw_desc, *grp_start;
1283         dma_cookie_t cookie;
1284         int slot_cnt, slots_per_op;
1285
1286         dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1287
1288         spin_lock_bh(&iop_chan->lock);
1289         slot_cnt = iop_chan_memcpy_slot_count(0, &slots_per_op);
1290         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1291         if (sw_desc) {
1292                 grp_start = sw_desc->group_head;
1293
1294                 list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain);
1295                 sw_desc->async_tx.ack = 1;
1296                 iop_desc_init_memcpy(grp_start, 0);
1297                 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1298                 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1299                 iop_desc_set_memcpy_src_addr(grp_start, 0);
1300
1301                 cookie = iop_chan->common.cookie;
1302                 cookie++;
1303                 if (cookie <= 1)
1304                         cookie = 2;
1305
1306                 /* initialize the completed cookie to be less than
1307                  * the most recently used cookie
1308                  */
1309                 iop_chan->completed_cookie = cookie - 1;
1310                 iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
1311
1312                 /* channel should not be busy */
1313                 BUG_ON(iop_chan_is_busy(iop_chan));
1314
1315                 /* clear any prior error-status bits */
1316                 iop_adma_device_clear_err_status(iop_chan);
1317
1318                 /* disable operation */
1319                 iop_chan_disable(iop_chan);
1320
1321                 /* set the descriptor address */
1322                 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1323
1324                 /* 1/ don't add pre-chained descriptors
1325                  * 2/ dummy read to flush next_desc write
1326                  */
1327                 BUG_ON(iop_desc_get_next_desc(sw_desc));
1328
1329                 /* run the descriptor */
1330                 iop_chan_enable(iop_chan);
1331         } else
1332                 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1333                          "failed to allocate null descriptor\n");
1334         spin_unlock_bh(&iop_chan->lock);
1335 }
1336
1337 static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan)
1338 {
1339         struct iop_adma_desc_slot *sw_desc, *grp_start;
1340         dma_cookie_t cookie;
1341         int slot_cnt, slots_per_op;
1342
1343         dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1344
1345         spin_lock_bh(&iop_chan->lock);
1346         slot_cnt = iop_chan_xor_slot_count(0, 2, &slots_per_op);
1347         sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1348         if (sw_desc) {
1349                 grp_start = sw_desc->group_head;
1350                 list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain);
1351                 sw_desc->async_tx.ack = 1;
1352                 iop_desc_init_null_xor(grp_start, 2, 0);
1353                 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1354                 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1355                 iop_desc_set_xor_src_addr(grp_start, 0, 0);
1356                 iop_desc_set_xor_src_addr(grp_start, 1, 0);
1357
1358                 cookie = iop_chan->common.cookie;
1359                 cookie++;
1360                 if (cookie <= 1)
1361                         cookie = 2;
1362
1363                 /* initialize the completed cookie to be less than
1364                  * the most recently used cookie
1365                  */
1366                 iop_chan->completed_cookie = cookie - 1;
1367                 iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
1368
1369                 /* channel should not be busy */
1370                 BUG_ON(iop_chan_is_busy(iop_chan));
1371
1372                 /* clear any prior error-status bits */
1373                 iop_adma_device_clear_err_status(iop_chan);
1374
1375                 /* disable operation */
1376                 iop_chan_disable(iop_chan);
1377
1378                 /* set the descriptor address */
1379                 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1380
1381                 /* 1/ don't add pre-chained descriptors
1382                  * 2/ dummy read to flush next_desc write
1383                  */
1384                 BUG_ON(iop_desc_get_next_desc(sw_desc));
1385
1386                 /* run the descriptor */
1387                 iop_chan_enable(iop_chan);
1388         } else
1389                 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1390                         "failed to allocate null descriptor\n");
1391         spin_unlock_bh(&iop_chan->lock);
1392 }
1393
1394 static struct platform_driver iop_adma_driver = {
1395         .probe          = iop_adma_probe,
1396         .remove         = iop_adma_remove,
1397         .driver         = {
1398                 .owner  = THIS_MODULE,
1399                 .name   = "iop-adma",
1400         },
1401 };
1402
1403 static int __init iop_adma_init (void)
1404 {
1405         return platform_driver_register(&iop_adma_driver);
1406 }
1407
1408 /* it's currently unsafe to unload this module */
1409 #if 0
1410 static void __exit iop_adma_exit (void)
1411 {
1412         platform_driver_unregister(&iop_adma_driver);
1413         return;
1414 }
1415 module_exit(iop_adma_exit);
1416 #endif
1417
1418 module_init(iop_adma_init);
1419
1420 MODULE_AUTHOR("Intel Corporation");
1421 MODULE_DESCRIPTION("IOP ADMA Engine Driver");
1422 MODULE_LICENSE("GPL");