[3/4] I/OAT: fix async_tx.callback checking
[linux-2.6.git] / drivers / dma / ioat_dma.c
1 /*
2  * Intel I/OAT DMA Linux driver
3  * Copyright(c) 2004 - 2007 Intel Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17  *
18  * The full GNU General Public License is included in this distribution in
19  * the file called "COPYING".
20  *
21  */
22
23 /*
24  * This driver supports an Intel I/OAT DMA engine, which does asynchronous
25  * copy operations.
26  */
27
28 #include <linux/init.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/interrupt.h>
32 #include <linux/dmaengine.h>
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/workqueue.h>
36 #include <linux/i7300_idle.h>
37 #include "ioatdma.h"
38 #include "ioatdma_registers.h"
39 #include "ioatdma_hw.h"
40
41 #define to_ioat_chan(chan) container_of(chan, struct ioat_dma_chan, common)
42 #define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common)
43 #define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
44 #define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, async_tx)
45
46 #define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80)
47 static int ioat_pending_level = 4;
48 module_param(ioat_pending_level, int, 0644);
49 MODULE_PARM_DESC(ioat_pending_level,
50                  "high-water mark for pushing ioat descriptors (default: 4)");
51
52 #define RESET_DELAY  msecs_to_jiffies(100)
53 #define WATCHDOG_DELAY  round_jiffies(msecs_to_jiffies(2000))
54 static void ioat_dma_chan_reset_part2(struct work_struct *work);
55 static void ioat_dma_chan_watchdog(struct work_struct *work);
56
57 /*
58  * workaround for IOAT ver.3.0 null descriptor issue
59  * (channel returns error when size is 0)
60  */
61 #define NULL_DESC_BUFFER_SIZE 1
62
63 /* internal functions */
64 static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan);
65 static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan);
66
67 static struct ioat_desc_sw *
68 ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan);
69 static struct ioat_desc_sw *
70 ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan);
71
72 static inline struct ioat_dma_chan *ioat_lookup_chan_by_index(
73                                                 struct ioatdma_device *device,
74                                                 int index)
75 {
76         return device->idx[index];
77 }
78
79 /**
80  * ioat_dma_do_interrupt - handler used for single vector interrupt mode
81  * @irq: interrupt id
82  * @data: interrupt data
83  */
84 static irqreturn_t ioat_dma_do_interrupt(int irq, void *data)
85 {
86         struct ioatdma_device *instance = data;
87         struct ioat_dma_chan *ioat_chan;
88         unsigned long attnstatus;
89         int bit;
90         u8 intrctrl;
91
92         intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET);
93
94         if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN))
95                 return IRQ_NONE;
96
97         if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) {
98                 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
99                 return IRQ_NONE;
100         }
101
102         attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET);
103         for_each_bit(bit, &attnstatus, BITS_PER_LONG) {
104                 ioat_chan = ioat_lookup_chan_by_index(instance, bit);
105                 tasklet_schedule(&ioat_chan->cleanup_task);
106         }
107
108         writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
109         return IRQ_HANDLED;
110 }
111
112 /**
113  * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode
114  * @irq: interrupt id
115  * @data: interrupt data
116  */
117 static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data)
118 {
119         struct ioat_dma_chan *ioat_chan = data;
120
121         tasklet_schedule(&ioat_chan->cleanup_task);
122
123         return IRQ_HANDLED;
124 }
125
126 static void ioat_dma_cleanup_tasklet(unsigned long data);
127
128 /**
129  * ioat_dma_enumerate_channels - find and initialize the device's channels
130  * @device: the device to be enumerated
131  */
132 static int ioat_dma_enumerate_channels(struct ioatdma_device *device)
133 {
134         u8 xfercap_scale;
135         u32 xfercap;
136         int i;
137         struct ioat_dma_chan *ioat_chan;
138
139         /*
140          * IOAT ver.3 workarounds
141          */
142         if (device->version == IOAT_VER_3_0) {
143                 u32 chan_err_mask;
144                 u16 dev_id;
145                 u32 dmauncerrsts;
146
147                 /*
148                  * Write CHANERRMSK_INT with 3E07h to mask out the errors
149                  * that can cause stability issues for IOAT ver.3
150                  */
151                 chan_err_mask = 0x3E07;
152                 pci_write_config_dword(device->pdev,
153                         IOAT_PCI_CHANERRMASK_INT_OFFSET,
154                         chan_err_mask);
155
156                 /*
157                  * Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit
158                  * (workaround for spurious config parity error after restart)
159                  */
160                 pci_read_config_word(device->pdev,
161                         IOAT_PCI_DEVICE_ID_OFFSET,
162                         &dev_id);
163                 if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) {
164                         dmauncerrsts = 0x10;
165                         pci_write_config_dword(device->pdev,
166                                 IOAT_PCI_DMAUNCERRSTS_OFFSET,
167                                 dmauncerrsts);
168                 }
169         }
170
171         device->common.chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
172         xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
173         xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale));
174
175 #ifdef  CONFIG_I7300_IDLE_IOAT_CHANNEL
176         if (i7300_idle_platform_probe(NULL, NULL) == 0) {
177                 device->common.chancnt--;
178         }
179 #endif
180         for (i = 0; i < device->common.chancnt; i++) {
181                 ioat_chan = kzalloc(sizeof(*ioat_chan), GFP_KERNEL);
182                 if (!ioat_chan) {
183                         device->common.chancnt = i;
184                         break;
185                 }
186
187                 ioat_chan->device = device;
188                 ioat_chan->reg_base = device->reg_base + (0x80 * (i + 1));
189                 ioat_chan->xfercap = xfercap;
190                 ioat_chan->desccount = 0;
191                 INIT_DELAYED_WORK(&ioat_chan->work, ioat_dma_chan_reset_part2);
192                 if (ioat_chan->device->version != IOAT_VER_1_2) {
193                         writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE
194                                         | IOAT_DMA_DCA_ANY_CPU,
195                                 ioat_chan->reg_base + IOAT_DCACTRL_OFFSET);
196                 }
197                 spin_lock_init(&ioat_chan->cleanup_lock);
198                 spin_lock_init(&ioat_chan->desc_lock);
199                 INIT_LIST_HEAD(&ioat_chan->free_desc);
200                 INIT_LIST_HEAD(&ioat_chan->used_desc);
201                 /* This should be made common somewhere in dmaengine.c */
202                 ioat_chan->common.device = &device->common;
203                 list_add_tail(&ioat_chan->common.device_node,
204                               &device->common.channels);
205                 device->idx[i] = ioat_chan;
206                 tasklet_init(&ioat_chan->cleanup_task,
207                              ioat_dma_cleanup_tasklet,
208                              (unsigned long) ioat_chan);
209                 tasklet_disable(&ioat_chan->cleanup_task);
210         }
211         return device->common.chancnt;
212 }
213
214 /**
215  * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended
216  *                                 descriptors to hw
217  * @chan: DMA channel handle
218  */
219 static inline void __ioat1_dma_memcpy_issue_pending(
220                                                 struct ioat_dma_chan *ioat_chan)
221 {
222         ioat_chan->pending = 0;
223         writeb(IOAT_CHANCMD_APPEND, ioat_chan->reg_base + IOAT1_CHANCMD_OFFSET);
224 }
225
226 static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan)
227 {
228         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
229
230         if (ioat_chan->pending > 0) {
231                 spin_lock_bh(&ioat_chan->desc_lock);
232                 __ioat1_dma_memcpy_issue_pending(ioat_chan);
233                 spin_unlock_bh(&ioat_chan->desc_lock);
234         }
235 }
236
237 static inline void __ioat2_dma_memcpy_issue_pending(
238                                                 struct ioat_dma_chan *ioat_chan)
239 {
240         ioat_chan->pending = 0;
241         writew(ioat_chan->dmacount,
242                ioat_chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET);
243 }
244
245 static void ioat2_dma_memcpy_issue_pending(struct dma_chan *chan)
246 {
247         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
248
249         if (ioat_chan->pending > 0) {
250                 spin_lock_bh(&ioat_chan->desc_lock);
251                 __ioat2_dma_memcpy_issue_pending(ioat_chan);
252                 spin_unlock_bh(&ioat_chan->desc_lock);
253         }
254 }
255
256
257 /**
258  * ioat_dma_chan_reset_part2 - reinit the channel after a reset
259  */
260 static void ioat_dma_chan_reset_part2(struct work_struct *work)
261 {
262         struct ioat_dma_chan *ioat_chan =
263                 container_of(work, struct ioat_dma_chan, work.work);
264         struct ioat_desc_sw *desc;
265
266         spin_lock_bh(&ioat_chan->cleanup_lock);
267         spin_lock_bh(&ioat_chan->desc_lock);
268
269         ioat_chan->completion_virt->low = 0;
270         ioat_chan->completion_virt->high = 0;
271         ioat_chan->pending = 0;
272
273         /*
274          * count the descriptors waiting, and be sure to do it
275          * right for both the CB1 line and the CB2 ring
276          */
277         ioat_chan->dmacount = 0;
278         if (ioat_chan->used_desc.prev) {
279                 desc = to_ioat_desc(ioat_chan->used_desc.prev);
280                 do {
281                         ioat_chan->dmacount++;
282                         desc = to_ioat_desc(desc->node.next);
283                 } while (&desc->node != ioat_chan->used_desc.next);
284         }
285
286         /*
287          * write the new starting descriptor address
288          * this puts channel engine into ARMED state
289          */
290         desc = to_ioat_desc(ioat_chan->used_desc.prev);
291         switch (ioat_chan->device->version) {
292         case IOAT_VER_1_2:
293                 writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
294                        ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
295                 writel(((u64) desc->async_tx.phys) >> 32,
296                        ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
297
298                 writeb(IOAT_CHANCMD_START, ioat_chan->reg_base
299                         + IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
300                 break;
301         case IOAT_VER_2_0:
302                 writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
303                        ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
304                 writel(((u64) desc->async_tx.phys) >> 32,
305                        ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
306
307                 /* tell the engine to go with what's left to be done */
308                 writew(ioat_chan->dmacount,
309                        ioat_chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET);
310
311                 break;
312         }
313         dev_err(&ioat_chan->device->pdev->dev,
314                 "chan%d reset - %d descs waiting, %d total desc\n",
315                 chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount);
316
317         spin_unlock_bh(&ioat_chan->desc_lock);
318         spin_unlock_bh(&ioat_chan->cleanup_lock);
319 }
320
321 /**
322  * ioat_dma_reset_channel - restart a channel
323  * @ioat_chan: IOAT DMA channel handle
324  */
325 static void ioat_dma_reset_channel(struct ioat_dma_chan *ioat_chan)
326 {
327         u32 chansts, chanerr;
328
329         if (!ioat_chan->used_desc.prev)
330                 return;
331
332         chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
333         chansts = (ioat_chan->completion_virt->low
334                                         & IOAT_CHANSTS_DMA_TRANSFER_STATUS);
335         if (chanerr) {
336                 dev_err(&ioat_chan->device->pdev->dev,
337                         "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n",
338                         chan_num(ioat_chan), chansts, chanerr);
339                 writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
340         }
341
342         /*
343          * whack it upside the head with a reset
344          * and wait for things to settle out.
345          * force the pending count to a really big negative
346          * to make sure no one forces an issue_pending
347          * while we're waiting.
348          */
349
350         spin_lock_bh(&ioat_chan->desc_lock);
351         ioat_chan->pending = INT_MIN;
352         writeb(IOAT_CHANCMD_RESET,
353                ioat_chan->reg_base
354                + IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
355         spin_unlock_bh(&ioat_chan->desc_lock);
356
357         /* schedule the 2nd half instead of sleeping a long time */
358         schedule_delayed_work(&ioat_chan->work, RESET_DELAY);
359 }
360
361 /**
362  * ioat_dma_chan_watchdog - watch for stuck channels
363  */
364 static void ioat_dma_chan_watchdog(struct work_struct *work)
365 {
366         struct ioatdma_device *device =
367                 container_of(work, struct ioatdma_device, work.work);
368         struct ioat_dma_chan *ioat_chan;
369         int i;
370
371         union {
372                 u64 full;
373                 struct {
374                         u32 low;
375                         u32 high;
376                 };
377         } completion_hw;
378         unsigned long compl_desc_addr_hw;
379
380         for (i = 0; i < device->common.chancnt; i++) {
381                 ioat_chan = ioat_lookup_chan_by_index(device, i);
382
383                 if (ioat_chan->device->version == IOAT_VER_1_2
384                         /* have we started processing anything yet */
385                     && ioat_chan->last_completion
386                         /* have we completed any since last watchdog cycle? */
387                     && (ioat_chan->last_completion ==
388                                 ioat_chan->watchdog_completion)
389                         /* has TCP stuck on one cookie since last watchdog? */
390                     && (ioat_chan->watchdog_tcp_cookie ==
391                                 ioat_chan->watchdog_last_tcp_cookie)
392                     && (ioat_chan->watchdog_tcp_cookie !=
393                                 ioat_chan->completed_cookie)
394                         /* is there something in the chain to be processed? */
395                         /* CB1 chain always has at least the last one processed */
396                     && (ioat_chan->used_desc.prev != ioat_chan->used_desc.next)
397                     && ioat_chan->pending == 0) {
398
399                         /*
400                          * check CHANSTS register for completed
401                          * descriptor address.
402                          * if it is different than completion writeback,
403                          * it is not zero
404                          * and it has changed since the last watchdog
405                          *     we can assume that channel
406                          *     is still working correctly
407                          *     and the problem is in completion writeback.
408                          *     update completion writeback
409                          *     with actual CHANSTS value
410                          * else
411                          *     try resetting the channel
412                          */
413
414                         completion_hw.low = readl(ioat_chan->reg_base +
415                                 IOAT_CHANSTS_OFFSET_LOW(ioat_chan->device->version));
416                         completion_hw.high = readl(ioat_chan->reg_base +
417                                 IOAT_CHANSTS_OFFSET_HIGH(ioat_chan->device->version));
418 #if (BITS_PER_LONG == 64)
419                         compl_desc_addr_hw =
420                                 completion_hw.full
421                                 & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
422 #else
423                         compl_desc_addr_hw =
424                                 completion_hw.low & IOAT_LOW_COMPLETION_MASK;
425 #endif
426
427                         if ((compl_desc_addr_hw != 0)
428                            && (compl_desc_addr_hw != ioat_chan->watchdog_completion)
429                            && (compl_desc_addr_hw != ioat_chan->last_compl_desc_addr_hw)) {
430                                 ioat_chan->last_compl_desc_addr_hw = compl_desc_addr_hw;
431                                 ioat_chan->completion_virt->low = completion_hw.low;
432                                 ioat_chan->completion_virt->high = completion_hw.high;
433                         } else {
434                                 ioat_dma_reset_channel(ioat_chan);
435                                 ioat_chan->watchdog_completion = 0;
436                                 ioat_chan->last_compl_desc_addr_hw = 0;
437                         }
438
439                 /*
440                  * for version 2.0 if there are descriptors yet to be processed
441                  * and the last completed hasn't changed since the last watchdog
442                  *      if they haven't hit the pending level
443                  *          issue the pending to push them through
444                  *      else
445                  *          try resetting the channel
446                  */
447                 } else if (ioat_chan->device->version == IOAT_VER_2_0
448                     && ioat_chan->used_desc.prev
449                     && ioat_chan->last_completion
450                     && ioat_chan->last_completion == ioat_chan->watchdog_completion) {
451
452                         if (ioat_chan->pending < ioat_pending_level)
453                                 ioat2_dma_memcpy_issue_pending(&ioat_chan->common);
454                         else {
455                                 ioat_dma_reset_channel(ioat_chan);
456                                 ioat_chan->watchdog_completion = 0;
457                         }
458                 } else {
459                         ioat_chan->last_compl_desc_addr_hw = 0;
460                         ioat_chan->watchdog_completion
461                                         = ioat_chan->last_completion;
462                 }
463
464                 ioat_chan->watchdog_last_tcp_cookie =
465                         ioat_chan->watchdog_tcp_cookie;
466         }
467
468         schedule_delayed_work(&device->work, WATCHDOG_DELAY);
469 }
470
471 static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
472 {
473         struct ioat_dma_chan *ioat_chan = to_ioat_chan(tx->chan);
474         struct ioat_desc_sw *first = tx_to_ioat_desc(tx);
475         struct ioat_desc_sw *prev, *new;
476         struct ioat_dma_descriptor *hw;
477         dma_cookie_t cookie;
478         LIST_HEAD(new_chain);
479         u32 copy;
480         size_t len;
481         dma_addr_t src, dst;
482         unsigned long orig_flags;
483         unsigned int desc_count = 0;
484
485         /* src and dest and len are stored in the initial descriptor */
486         len = first->len;
487         src = first->src;
488         dst = first->dst;
489         orig_flags = first->async_tx.flags;
490         new = first;
491
492         spin_lock_bh(&ioat_chan->desc_lock);
493         prev = to_ioat_desc(ioat_chan->used_desc.prev);
494         prefetch(prev->hw);
495         do {
496                 copy = min_t(size_t, len, ioat_chan->xfercap);
497
498                 async_tx_ack(&new->async_tx);
499
500                 hw = new->hw;
501                 hw->size = copy;
502                 hw->ctl = 0;
503                 hw->src_addr = src;
504                 hw->dst_addr = dst;
505                 hw->next = 0;
506
507                 /* chain together the physical address list for the HW */
508                 wmb();
509                 prev->hw->next = (u64) new->async_tx.phys;
510
511                 len -= copy;
512                 dst += copy;
513                 src += copy;
514
515                 list_add_tail(&new->node, &new_chain);
516                 desc_count++;
517                 prev = new;
518         } while (len && (new = ioat1_dma_get_next_descriptor(ioat_chan)));
519
520         if (!new) {
521                 dev_err(&ioat_chan->device->pdev->dev,
522                         "tx submit failed\n");
523                 spin_unlock_bh(&ioat_chan->desc_lock);
524                 return -ENOMEM;
525         }
526
527         hw->ctl = IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
528         if (first->async_tx.callback) {
529                 hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN;
530                 if (first != new) {
531                         /* move callback into to last desc */
532                         new->async_tx.callback = first->async_tx.callback;
533                         new->async_tx.callback_param
534                                         = first->async_tx.callback_param;
535                         first->async_tx.callback = NULL;
536                         first->async_tx.callback_param = NULL;
537                 }
538         }
539
540         new->tx_cnt = desc_count;
541         new->async_tx.flags = orig_flags; /* client is in control of this ack */
542
543         /* store the original values for use in later cleanup */
544         if (new != first) {
545                 new->src = first->src;
546                 new->dst = first->dst;
547                 new->len = first->len;
548         }
549
550         /* cookie incr and addition to used_list must be atomic */
551         cookie = ioat_chan->common.cookie;
552         cookie++;
553         if (cookie < 0)
554                 cookie = 1;
555         ioat_chan->common.cookie = new->async_tx.cookie = cookie;
556
557         /* write address into NextDescriptor field of last desc in chain */
558         to_ioat_desc(ioat_chan->used_desc.prev)->hw->next =
559                                                         first->async_tx.phys;
560         list_splice_tail(&new_chain, &ioat_chan->used_desc);
561
562         ioat_chan->dmacount += desc_count;
563         ioat_chan->pending += desc_count;
564         if (ioat_chan->pending >= ioat_pending_level)
565                 __ioat1_dma_memcpy_issue_pending(ioat_chan);
566         spin_unlock_bh(&ioat_chan->desc_lock);
567
568         return cookie;
569 }
570
571 static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx)
572 {
573         struct ioat_dma_chan *ioat_chan = to_ioat_chan(tx->chan);
574         struct ioat_desc_sw *first = tx_to_ioat_desc(tx);
575         struct ioat_desc_sw *new;
576         struct ioat_dma_descriptor *hw;
577         dma_cookie_t cookie;
578         u32 copy;
579         size_t len;
580         dma_addr_t src, dst;
581         unsigned long orig_flags;
582         unsigned int desc_count = 0;
583
584         /* src and dest and len are stored in the initial descriptor */
585         len = first->len;
586         src = first->src;
587         dst = first->dst;
588         orig_flags = first->async_tx.flags;
589         new = first;
590
591         /*
592          * ioat_chan->desc_lock is still in force in version 2 path
593          * it gets unlocked at end of this function
594          */
595         do {
596                 copy = min_t(size_t, len, ioat_chan->xfercap);
597
598                 async_tx_ack(&new->async_tx);
599
600                 hw = new->hw;
601                 hw->size = copy;
602                 hw->ctl = 0;
603                 hw->src_addr = src;
604                 hw->dst_addr = dst;
605
606                 len -= copy;
607                 dst += copy;
608                 src += copy;
609                 desc_count++;
610         } while (len && (new = ioat2_dma_get_next_descriptor(ioat_chan)));
611
612         if (!new) {
613                 dev_err(&ioat_chan->device->pdev->dev,
614                         "tx submit failed\n");
615                 spin_unlock_bh(&ioat_chan->desc_lock);
616                 return -ENOMEM;
617         }
618
619         hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
620         if (first->async_tx.callback) {
621                 hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN;
622                 if (first != new) {
623                         /* move callback into to last desc */
624                         new->async_tx.callback = first->async_tx.callback;
625                         new->async_tx.callback_param
626                                         = first->async_tx.callback_param;
627                         first->async_tx.callback = NULL;
628                         first->async_tx.callback_param = NULL;
629                 }
630         }
631
632         new->tx_cnt = desc_count;
633         new->async_tx.flags = orig_flags; /* client is in control of this ack */
634
635         /* store the original values for use in later cleanup */
636         if (new != first) {
637                 new->src = first->src;
638                 new->dst = first->dst;
639                 new->len = first->len;
640         }
641
642         /* cookie incr and addition to used_list must be atomic */
643         cookie = ioat_chan->common.cookie;
644         cookie++;
645         if (cookie < 0)
646                 cookie = 1;
647         ioat_chan->common.cookie = new->async_tx.cookie = cookie;
648
649         ioat_chan->dmacount += desc_count;
650         ioat_chan->pending += desc_count;
651         if (ioat_chan->pending >= ioat_pending_level)
652                 __ioat2_dma_memcpy_issue_pending(ioat_chan);
653         spin_unlock_bh(&ioat_chan->desc_lock);
654
655         return cookie;
656 }
657
658 /**
659  * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair
660  * @ioat_chan: the channel supplying the memory pool for the descriptors
661  * @flags: allocation flags
662  */
663 static struct ioat_desc_sw *ioat_dma_alloc_descriptor(
664                                         struct ioat_dma_chan *ioat_chan,
665                                         gfp_t flags)
666 {
667         struct ioat_dma_descriptor *desc;
668         struct ioat_desc_sw *desc_sw;
669         struct ioatdma_device *ioatdma_device;
670         dma_addr_t phys;
671
672         ioatdma_device = to_ioatdma_device(ioat_chan->common.device);
673         desc = pci_pool_alloc(ioatdma_device->dma_pool, flags, &phys);
674         if (unlikely(!desc))
675                 return NULL;
676
677         desc_sw = kzalloc(sizeof(*desc_sw), flags);
678         if (unlikely(!desc_sw)) {
679                 pci_pool_free(ioatdma_device->dma_pool, desc, phys);
680                 return NULL;
681         }
682
683         memset(desc, 0, sizeof(*desc));
684         dma_async_tx_descriptor_init(&desc_sw->async_tx, &ioat_chan->common);
685         switch (ioat_chan->device->version) {
686         case IOAT_VER_1_2:
687                 desc_sw->async_tx.tx_submit = ioat1_tx_submit;
688                 break;
689         case IOAT_VER_2_0:
690         case IOAT_VER_3_0:
691                 desc_sw->async_tx.tx_submit = ioat2_tx_submit;
692                 break;
693         }
694         INIT_LIST_HEAD(&desc_sw->async_tx.tx_list);
695
696         desc_sw->hw = desc;
697         desc_sw->async_tx.phys = phys;
698
699         return desc_sw;
700 }
701
702 static int ioat_initial_desc_count = 256;
703 module_param(ioat_initial_desc_count, int, 0644);
704 MODULE_PARM_DESC(ioat_initial_desc_count,
705                  "initial descriptors per channel (default: 256)");
706
707 /**
708  * ioat2_dma_massage_chan_desc - link the descriptors into a circle
709  * @ioat_chan: the channel to be massaged
710  */
711 static void ioat2_dma_massage_chan_desc(struct ioat_dma_chan *ioat_chan)
712 {
713         struct ioat_desc_sw *desc, *_desc;
714
715         /* setup used_desc */
716         ioat_chan->used_desc.next = ioat_chan->free_desc.next;
717         ioat_chan->used_desc.prev = NULL;
718
719         /* pull free_desc out of the circle so that every node is a hw
720          * descriptor, but leave it pointing to the list
721          */
722         ioat_chan->free_desc.prev->next = ioat_chan->free_desc.next;
723         ioat_chan->free_desc.next->prev = ioat_chan->free_desc.prev;
724
725         /* circle link the hw descriptors */
726         desc = to_ioat_desc(ioat_chan->free_desc.next);
727         desc->hw->next = to_ioat_desc(desc->node.next)->async_tx.phys;
728         list_for_each_entry_safe(desc, _desc, ioat_chan->free_desc.next, node) {
729                 desc->hw->next = to_ioat_desc(desc->node.next)->async_tx.phys;
730         }
731 }
732
733 /**
734  * ioat_dma_alloc_chan_resources - returns the number of allocated descriptors
735  * @chan: the channel to be filled out
736  */
737 static int ioat_dma_alloc_chan_resources(struct dma_chan *chan,
738                                          struct dma_client *client)
739 {
740         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
741         struct ioat_desc_sw *desc;
742         u16 chanctrl;
743         u32 chanerr;
744         int i;
745         LIST_HEAD(tmp_list);
746
747         /* have we already been set up? */
748         if (!list_empty(&ioat_chan->free_desc))
749                 return ioat_chan->desccount;
750
751         /* Setup register to interrupt and write completion status on error */
752         chanctrl = IOAT_CHANCTRL_ERR_INT_EN |
753                 IOAT_CHANCTRL_ANY_ERR_ABORT_EN |
754                 IOAT_CHANCTRL_ERR_COMPLETION_EN;
755         writew(chanctrl, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET);
756
757         chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
758         if (chanerr) {
759                 dev_err(&ioat_chan->device->pdev->dev,
760                         "CHANERR = %x, clearing\n", chanerr);
761                 writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
762         }
763
764         /* Allocate descriptors */
765         for (i = 0; i < ioat_initial_desc_count; i++) {
766                 desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_KERNEL);
767                 if (!desc) {
768                         dev_err(&ioat_chan->device->pdev->dev,
769                                 "Only %d initial descriptors\n", i);
770                         break;
771                 }
772                 list_add_tail(&desc->node, &tmp_list);
773         }
774         spin_lock_bh(&ioat_chan->desc_lock);
775         ioat_chan->desccount = i;
776         list_splice(&tmp_list, &ioat_chan->free_desc);
777         if (ioat_chan->device->version != IOAT_VER_1_2)
778                 ioat2_dma_massage_chan_desc(ioat_chan);
779         spin_unlock_bh(&ioat_chan->desc_lock);
780
781         /* allocate a completion writeback area */
782         /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
783         ioat_chan->completion_virt =
784                 pci_pool_alloc(ioat_chan->device->completion_pool,
785                                GFP_KERNEL,
786                                &ioat_chan->completion_addr);
787         memset(ioat_chan->completion_virt, 0,
788                sizeof(*ioat_chan->completion_virt));
789         writel(((u64) ioat_chan->completion_addr) & 0x00000000FFFFFFFF,
790                ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
791         writel(((u64) ioat_chan->completion_addr) >> 32,
792                ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
793
794         tasklet_enable(&ioat_chan->cleanup_task);
795         ioat_dma_start_null_desc(ioat_chan);  /* give chain to dma device */
796         return ioat_chan->desccount;
797 }
798
799 /**
800  * ioat_dma_free_chan_resources - release all the descriptors
801  * @chan: the channel to be cleaned
802  */
803 static void ioat_dma_free_chan_resources(struct dma_chan *chan)
804 {
805         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
806         struct ioatdma_device *ioatdma_device = to_ioatdma_device(chan->device);
807         struct ioat_desc_sw *desc, *_desc;
808         int in_use_descs = 0;
809
810         /* Before freeing channel resources first check
811          * if they have been previously allocated for this channel.
812          */
813         if (ioat_chan->desccount == 0)
814                 return;
815
816         tasklet_disable(&ioat_chan->cleanup_task);
817         ioat_dma_memcpy_cleanup(ioat_chan);
818
819         /* Delay 100ms after reset to allow internal DMA logic to quiesce
820          * before removing DMA descriptor resources.
821          */
822         writeb(IOAT_CHANCMD_RESET,
823                ioat_chan->reg_base
824                         + IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
825         mdelay(100);
826
827         spin_lock_bh(&ioat_chan->desc_lock);
828         switch (ioat_chan->device->version) {
829         case IOAT_VER_1_2:
830                 list_for_each_entry_safe(desc, _desc,
831                                          &ioat_chan->used_desc, node) {
832                         in_use_descs++;
833                         list_del(&desc->node);
834                         pci_pool_free(ioatdma_device->dma_pool, desc->hw,
835                                       desc->async_tx.phys);
836                         kfree(desc);
837                 }
838                 list_for_each_entry_safe(desc, _desc,
839                                          &ioat_chan->free_desc, node) {
840                         list_del(&desc->node);
841                         pci_pool_free(ioatdma_device->dma_pool, desc->hw,
842                                       desc->async_tx.phys);
843                         kfree(desc);
844                 }
845                 break;
846         case IOAT_VER_2_0:
847         case IOAT_VER_3_0:
848                 list_for_each_entry_safe(desc, _desc,
849                                          ioat_chan->free_desc.next, node) {
850                         list_del(&desc->node);
851                         pci_pool_free(ioatdma_device->dma_pool, desc->hw,
852                                       desc->async_tx.phys);
853                         kfree(desc);
854                 }
855                 desc = to_ioat_desc(ioat_chan->free_desc.next);
856                 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
857                               desc->async_tx.phys);
858                 kfree(desc);
859                 INIT_LIST_HEAD(&ioat_chan->free_desc);
860                 INIT_LIST_HEAD(&ioat_chan->used_desc);
861                 break;
862         }
863         spin_unlock_bh(&ioat_chan->desc_lock);
864
865         pci_pool_free(ioatdma_device->completion_pool,
866                       ioat_chan->completion_virt,
867                       ioat_chan->completion_addr);
868
869         /* one is ok since we left it on there on purpose */
870         if (in_use_descs > 1)
871                 dev_err(&ioat_chan->device->pdev->dev,
872                         "Freeing %d in use descriptors!\n",
873                         in_use_descs - 1);
874
875         ioat_chan->last_completion = ioat_chan->completion_addr = 0;
876         ioat_chan->pending = 0;
877         ioat_chan->dmacount = 0;
878         ioat_chan->desccount = 0;
879         ioat_chan->watchdog_completion = 0;
880         ioat_chan->last_compl_desc_addr_hw = 0;
881         ioat_chan->watchdog_tcp_cookie =
882                 ioat_chan->watchdog_last_tcp_cookie = 0;
883 }
884
885 /**
886  * ioat_dma_get_next_descriptor - return the next available descriptor
887  * @ioat_chan: IOAT DMA channel handle
888  *
889  * Gets the next descriptor from the chain, and must be called with the
890  * channel's desc_lock held.  Allocates more descriptors if the channel
891  * has run out.
892  */
893 static struct ioat_desc_sw *
894 ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan)
895 {
896         struct ioat_desc_sw *new;
897
898         if (!list_empty(&ioat_chan->free_desc)) {
899                 new = to_ioat_desc(ioat_chan->free_desc.next);
900                 list_del(&new->node);
901         } else {
902                 /* try to get another desc */
903                 new = ioat_dma_alloc_descriptor(ioat_chan, GFP_ATOMIC);
904                 if (!new) {
905                         dev_err(&ioat_chan->device->pdev->dev,
906                                 "alloc failed\n");
907                         return NULL;
908                 }
909         }
910
911         prefetch(new->hw);
912         return new;
913 }
914
915 static struct ioat_desc_sw *
916 ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan)
917 {
918         struct ioat_desc_sw *new;
919
920         /*
921          * used.prev points to where to start processing
922          * used.next points to next free descriptor
923          * if used.prev == NULL, there are none waiting to be processed
924          * if used.next == used.prev.prev, there is only one free descriptor,
925          *      and we need to use it to as a noop descriptor before
926          *      linking in a new set of descriptors, since the device
927          *      has probably already read the pointer to it
928          */
929         if (ioat_chan->used_desc.prev &&
930             ioat_chan->used_desc.next == ioat_chan->used_desc.prev->prev) {
931
932                 struct ioat_desc_sw *desc;
933                 struct ioat_desc_sw *noop_desc;
934                 int i;
935
936                 /* set up the noop descriptor */
937                 noop_desc = to_ioat_desc(ioat_chan->used_desc.next);
938                 /* set size to non-zero value (channel returns error when size is 0) */
939                 noop_desc->hw->size = NULL_DESC_BUFFER_SIZE;
940                 noop_desc->hw->ctl = IOAT_DMA_DESCRIPTOR_NUL;
941                 noop_desc->hw->src_addr = 0;
942                 noop_desc->hw->dst_addr = 0;
943
944                 ioat_chan->used_desc.next = ioat_chan->used_desc.next->next;
945                 ioat_chan->pending++;
946                 ioat_chan->dmacount++;
947
948                 /* try to get a few more descriptors */
949                 for (i = 16; i; i--) {
950                         desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_ATOMIC);
951                         if (!desc) {
952                                 dev_err(&ioat_chan->device->pdev->dev,
953                                         "alloc failed\n");
954                                 break;
955                         }
956                         list_add_tail(&desc->node, ioat_chan->used_desc.next);
957
958                         desc->hw->next
959                                 = to_ioat_desc(desc->node.next)->async_tx.phys;
960                         to_ioat_desc(desc->node.prev)->hw->next
961                                 = desc->async_tx.phys;
962                         ioat_chan->desccount++;
963                 }
964
965                 ioat_chan->used_desc.next = noop_desc->node.next;
966         }
967         new = to_ioat_desc(ioat_chan->used_desc.next);
968         prefetch(new);
969         ioat_chan->used_desc.next = new->node.next;
970
971         if (ioat_chan->used_desc.prev == NULL)
972                 ioat_chan->used_desc.prev = &new->node;
973
974         prefetch(new->hw);
975         return new;
976 }
977
978 static struct ioat_desc_sw *ioat_dma_get_next_descriptor(
979                                                 struct ioat_dma_chan *ioat_chan)
980 {
981         if (!ioat_chan)
982                 return NULL;
983
984         switch (ioat_chan->device->version) {
985         case IOAT_VER_1_2:
986                 return ioat1_dma_get_next_descriptor(ioat_chan);
987         case IOAT_VER_2_0:
988         case IOAT_VER_3_0:
989                 return ioat2_dma_get_next_descriptor(ioat_chan);
990         }
991         return NULL;
992 }
993
994 static struct dma_async_tx_descriptor *ioat1_dma_prep_memcpy(
995                                                 struct dma_chan *chan,
996                                                 dma_addr_t dma_dest,
997                                                 dma_addr_t dma_src,
998                                                 size_t len,
999                                                 unsigned long flags)
1000 {
1001         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
1002         struct ioat_desc_sw *new;
1003
1004         spin_lock_bh(&ioat_chan->desc_lock);
1005         new = ioat_dma_get_next_descriptor(ioat_chan);
1006         spin_unlock_bh(&ioat_chan->desc_lock);
1007
1008         if (new) {
1009                 new->len = len;
1010                 new->dst = dma_dest;
1011                 new->src = dma_src;
1012                 new->async_tx.flags = flags;
1013                 return &new->async_tx;
1014         } else {
1015                 dev_err(&ioat_chan->device->pdev->dev,
1016                         "chan%d - get_next_desc failed: %d descs waiting, %d total desc\n",
1017                         chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount);
1018                 return NULL;
1019         }
1020 }
1021
1022 static struct dma_async_tx_descriptor *ioat2_dma_prep_memcpy(
1023                                                 struct dma_chan *chan,
1024                                                 dma_addr_t dma_dest,
1025                                                 dma_addr_t dma_src,
1026                                                 size_t len,
1027                                                 unsigned long flags)
1028 {
1029         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
1030         struct ioat_desc_sw *new;
1031
1032         spin_lock_bh(&ioat_chan->desc_lock);
1033         new = ioat2_dma_get_next_descriptor(ioat_chan);
1034
1035         /*
1036          * leave ioat_chan->desc_lock set in ioat 2 path
1037          * it will get unlocked at end of tx_submit
1038          */
1039
1040         if (new) {
1041                 new->len = len;
1042                 new->dst = dma_dest;
1043                 new->src = dma_src;
1044                 new->async_tx.flags = flags;
1045                 return &new->async_tx;
1046         } else {
1047                 spin_unlock_bh(&ioat_chan->desc_lock);
1048                 dev_err(&ioat_chan->device->pdev->dev,
1049                         "chan%d - get_next_desc failed: %d descs waiting, %d total desc\n",
1050                         chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount);
1051                 return NULL;
1052         }
1053 }
1054
1055 static void ioat_dma_cleanup_tasklet(unsigned long data)
1056 {
1057         struct ioat_dma_chan *chan = (void *)data;
1058         ioat_dma_memcpy_cleanup(chan);
1059         writew(IOAT_CHANCTRL_INT_DISABLE,
1060                chan->reg_base + IOAT_CHANCTRL_OFFSET);
1061 }
1062
1063 static void
1064 ioat_dma_unmap(struct ioat_dma_chan *ioat_chan, struct ioat_desc_sw *desc)
1065 {
1066         /*
1067          * yes we are unmapping both _page and _single
1068          * alloc'd regions with unmap_page. Is this
1069          * *really* that bad?
1070          */
1071         if (!(desc->async_tx.flags & DMA_COMPL_SKIP_DEST_UNMAP))
1072                 pci_unmap_page(ioat_chan->device->pdev,
1073                                 pci_unmap_addr(desc, dst),
1074                                 pci_unmap_len(desc, len),
1075                                 PCI_DMA_FROMDEVICE);
1076
1077         if (!(desc->async_tx.flags & DMA_COMPL_SKIP_SRC_UNMAP))
1078                 pci_unmap_page(ioat_chan->device->pdev,
1079                                 pci_unmap_addr(desc, src),
1080                                 pci_unmap_len(desc, len),
1081                                 PCI_DMA_TODEVICE);
1082 }
1083
1084 /**
1085  * ioat_dma_memcpy_cleanup - cleanup up finished descriptors
1086  * @chan: ioat channel to be cleaned up
1087  */
1088 static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan)
1089 {
1090         unsigned long phys_complete;
1091         struct ioat_desc_sw *desc, *_desc;
1092         dma_cookie_t cookie = 0;
1093         unsigned long desc_phys;
1094         struct ioat_desc_sw *latest_desc;
1095
1096         prefetch(ioat_chan->completion_virt);
1097
1098         if (!spin_trylock_bh(&ioat_chan->cleanup_lock))
1099                 return;
1100
1101         /* The completion writeback can happen at any time,
1102            so reads by the driver need to be atomic operations
1103            The descriptor physical addresses are limited to 32-bits
1104            when the CPU can only do a 32-bit mov */
1105
1106 #if (BITS_PER_LONG == 64)
1107         phys_complete =
1108                 ioat_chan->completion_virt->full
1109                 & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
1110 #else
1111         phys_complete =
1112                 ioat_chan->completion_virt->low & IOAT_LOW_COMPLETION_MASK;
1113 #endif
1114
1115         if ((ioat_chan->completion_virt->full
1116                 & IOAT_CHANSTS_DMA_TRANSFER_STATUS) ==
1117                                 IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED) {
1118                 dev_err(&ioat_chan->device->pdev->dev,
1119                         "Channel halted, chanerr = %x\n",
1120                         readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET));
1121
1122                 /* TODO do something to salvage the situation */
1123         }
1124
1125         if (phys_complete == ioat_chan->last_completion) {
1126                 spin_unlock_bh(&ioat_chan->cleanup_lock);
1127                 /*
1128                  * perhaps we're stuck so hard that the watchdog can't go off?
1129                  * try to catch it after 2 seconds
1130                  */
1131                 if (ioat_chan->device->version != IOAT_VER_3_0) {
1132                         if (time_after(jiffies,
1133                                        ioat_chan->last_completion_time + HZ*WATCHDOG_DELAY)) {
1134                                 ioat_dma_chan_watchdog(&(ioat_chan->device->work.work));
1135                                 ioat_chan->last_completion_time = jiffies;
1136                         }
1137                 }
1138                 return;
1139         }
1140         ioat_chan->last_completion_time = jiffies;
1141
1142         cookie = 0;
1143         if (!spin_trylock_bh(&ioat_chan->desc_lock)) {
1144                 spin_unlock_bh(&ioat_chan->cleanup_lock);
1145                 return;
1146         }
1147
1148         switch (ioat_chan->device->version) {
1149         case IOAT_VER_1_2:
1150                 list_for_each_entry_safe(desc, _desc,
1151                                          &ioat_chan->used_desc, node) {
1152
1153                         /*
1154                          * Incoming DMA requests may use multiple descriptors,
1155                          * due to exceeding xfercap, perhaps. If so, only the
1156                          * last one will have a cookie, and require unmapping.
1157                          */
1158                         if (desc->async_tx.cookie) {
1159                                 cookie = desc->async_tx.cookie;
1160                                 ioat_dma_unmap(ioat_chan, desc);
1161                                 if (desc->async_tx.callback) {
1162                                         desc->async_tx.callback(desc->async_tx.callback_param);
1163                                         desc->async_tx.callback = NULL;
1164                                 }
1165                         }
1166
1167                         if (desc->async_tx.phys != phys_complete) {
1168                                 /*
1169                                  * a completed entry, but not the last, so clean
1170                                  * up if the client is done with the descriptor
1171                                  */
1172                                 if (async_tx_test_ack(&desc->async_tx)) {
1173                                         list_del(&desc->node);
1174                                         list_add_tail(&desc->node,
1175                                                       &ioat_chan->free_desc);
1176                                 } else
1177                                         desc->async_tx.cookie = 0;
1178                         } else {
1179                                 /*
1180                                  * last used desc. Do not remove, so we can
1181                                  * append from it, but don't look at it next
1182                                  * time, either
1183                                  */
1184                                 desc->async_tx.cookie = 0;
1185
1186                                 /* TODO check status bits? */
1187                                 break;
1188                         }
1189                 }
1190                 break;
1191         case IOAT_VER_2_0:
1192         case IOAT_VER_3_0:
1193                 /* has some other thread has already cleaned up? */
1194                 if (ioat_chan->used_desc.prev == NULL)
1195                         break;
1196
1197                 /* work backwards to find latest finished desc */
1198                 desc = to_ioat_desc(ioat_chan->used_desc.next);
1199                 latest_desc = NULL;
1200                 do {
1201                         desc = to_ioat_desc(desc->node.prev);
1202                         desc_phys = (unsigned long)desc->async_tx.phys
1203                                        & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
1204                         if (desc_phys == phys_complete) {
1205                                 latest_desc = desc;
1206                                 break;
1207                         }
1208                 } while (&desc->node != ioat_chan->used_desc.prev);
1209
1210                 if (latest_desc != NULL) {
1211
1212                         /* work forwards to clear finished descriptors */
1213                         for (desc = to_ioat_desc(ioat_chan->used_desc.prev);
1214                              &desc->node != latest_desc->node.next &&
1215                              &desc->node != ioat_chan->used_desc.next;
1216                              desc = to_ioat_desc(desc->node.next)) {
1217                                 if (desc->async_tx.cookie) {
1218                                         cookie = desc->async_tx.cookie;
1219                                         desc->async_tx.cookie = 0;
1220                                         ioat_dma_unmap(ioat_chan, desc);
1221                                         if (desc->async_tx.callback) {
1222                                                 desc->async_tx.callback(desc->async_tx.callback_param);
1223                                                 desc->async_tx.callback = NULL;
1224                                         }
1225                                 }
1226                         }
1227
1228                         /* move used.prev up beyond those that are finished */
1229                         if (&desc->node == ioat_chan->used_desc.next)
1230                                 ioat_chan->used_desc.prev = NULL;
1231                         else
1232                                 ioat_chan->used_desc.prev = &desc->node;
1233                 }
1234                 break;
1235         }
1236
1237         spin_unlock_bh(&ioat_chan->desc_lock);
1238
1239         ioat_chan->last_completion = phys_complete;
1240         if (cookie != 0)
1241                 ioat_chan->completed_cookie = cookie;
1242
1243         spin_unlock_bh(&ioat_chan->cleanup_lock);
1244 }
1245
1246 /**
1247  * ioat_dma_is_complete - poll the status of a IOAT DMA transaction
1248  * @chan: IOAT DMA channel handle
1249  * @cookie: DMA transaction identifier
1250  * @done: if not %NULL, updated with last completed transaction
1251  * @used: if not %NULL, updated with last used transaction
1252  */
1253 static enum dma_status ioat_dma_is_complete(struct dma_chan *chan,
1254                                             dma_cookie_t cookie,
1255                                             dma_cookie_t *done,
1256                                             dma_cookie_t *used)
1257 {
1258         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
1259         dma_cookie_t last_used;
1260         dma_cookie_t last_complete;
1261         enum dma_status ret;
1262
1263         last_used = chan->cookie;
1264         last_complete = ioat_chan->completed_cookie;
1265         ioat_chan->watchdog_tcp_cookie = cookie;
1266
1267         if (done)
1268                 *done = last_complete;
1269         if (used)
1270                 *used = last_used;
1271
1272         ret = dma_async_is_complete(cookie, last_complete, last_used);
1273         if (ret == DMA_SUCCESS)
1274                 return ret;
1275
1276         ioat_dma_memcpy_cleanup(ioat_chan);
1277
1278         last_used = chan->cookie;
1279         last_complete = ioat_chan->completed_cookie;
1280
1281         if (done)
1282                 *done = last_complete;
1283         if (used)
1284                 *used = last_used;
1285
1286         return dma_async_is_complete(cookie, last_complete, last_used);
1287 }
1288
1289 static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan)
1290 {
1291         struct ioat_desc_sw *desc;
1292
1293         spin_lock_bh(&ioat_chan->desc_lock);
1294
1295         desc = ioat_dma_get_next_descriptor(ioat_chan);
1296
1297         if (!desc) {
1298                 dev_err(&ioat_chan->device->pdev->dev,
1299                         "Unable to start null desc - get next desc failed\n");
1300                 spin_unlock_bh(&ioat_chan->desc_lock);
1301                 return;
1302         }
1303
1304         desc->hw->ctl = IOAT_DMA_DESCRIPTOR_NUL
1305                                 | IOAT_DMA_DESCRIPTOR_CTL_INT_GN
1306                                 | IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
1307         /* set size to non-zero value (channel returns error when size is 0) */
1308         desc->hw->size = NULL_DESC_BUFFER_SIZE;
1309         desc->hw->src_addr = 0;
1310         desc->hw->dst_addr = 0;
1311         async_tx_ack(&desc->async_tx);
1312         switch (ioat_chan->device->version) {
1313         case IOAT_VER_1_2:
1314                 desc->hw->next = 0;
1315                 list_add_tail(&desc->node, &ioat_chan->used_desc);
1316
1317                 writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
1318                        ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
1319                 writel(((u64) desc->async_tx.phys) >> 32,
1320                        ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
1321
1322                 writeb(IOAT_CHANCMD_START, ioat_chan->reg_base
1323                         + IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
1324                 break;
1325         case IOAT_VER_2_0:
1326         case IOAT_VER_3_0:
1327                 writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
1328                        ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
1329                 writel(((u64) desc->async_tx.phys) >> 32,
1330                        ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
1331
1332                 ioat_chan->dmacount++;
1333                 __ioat2_dma_memcpy_issue_pending(ioat_chan);
1334                 break;
1335         }
1336         spin_unlock_bh(&ioat_chan->desc_lock);
1337 }
1338
1339 /*
1340  * Perform a IOAT transaction to verify the HW works.
1341  */
1342 #define IOAT_TEST_SIZE 2000
1343
1344 static void ioat_dma_test_callback(void *dma_async_param)
1345 {
1346         printk(KERN_ERR "ioatdma: ioat_dma_test_callback(%p)\n",
1347                 dma_async_param);
1348 }
1349
1350 /**
1351  * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
1352  * @device: device to be tested
1353  */
1354 static int ioat_dma_self_test(struct ioatdma_device *device)
1355 {
1356         int i;
1357         u8 *src;
1358         u8 *dest;
1359         struct dma_chan *dma_chan;
1360         struct dma_async_tx_descriptor *tx;
1361         dma_addr_t dma_dest, dma_src;
1362         dma_cookie_t cookie;
1363         int err = 0;
1364
1365         src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
1366         if (!src)
1367                 return -ENOMEM;
1368         dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
1369         if (!dest) {
1370                 kfree(src);
1371                 return -ENOMEM;
1372         }
1373
1374         /* Fill in src buffer */
1375         for (i = 0; i < IOAT_TEST_SIZE; i++)
1376                 src[i] = (u8)i;
1377
1378         /* Start copy, using first DMA channel */
1379         dma_chan = container_of(device->common.channels.next,
1380                                 struct dma_chan,
1381                                 device_node);
1382         if (device->common.device_alloc_chan_resources(dma_chan, NULL) < 1) {
1383                 dev_err(&device->pdev->dev,
1384                         "selftest cannot allocate chan resource\n");
1385                 err = -ENODEV;
1386                 goto out;
1387         }
1388
1389         dma_src = dma_map_single(dma_chan->device->dev, src, IOAT_TEST_SIZE,
1390                                  DMA_TO_DEVICE);
1391         dma_dest = dma_map_single(dma_chan->device->dev, dest, IOAT_TEST_SIZE,
1392                                   DMA_FROM_DEVICE);
1393         tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src,
1394                                                    IOAT_TEST_SIZE, 0);
1395         if (!tx) {
1396                 dev_err(&device->pdev->dev,
1397                         "Self-test prep failed, disabling\n");
1398                 err = -ENODEV;
1399                 goto free_resources;
1400         }
1401
1402         async_tx_ack(tx);
1403         tx->callback = ioat_dma_test_callback;
1404         tx->callback_param = (void *)0x8086;
1405         cookie = tx->tx_submit(tx);
1406         if (cookie < 0) {
1407                 dev_err(&device->pdev->dev,
1408                         "Self-test setup failed, disabling\n");
1409                 err = -ENODEV;
1410                 goto free_resources;
1411         }
1412         device->common.device_issue_pending(dma_chan);
1413         msleep(1);
1414
1415         if (device->common.device_is_tx_complete(dma_chan, cookie, NULL, NULL)
1416                                         != DMA_SUCCESS) {
1417                 dev_err(&device->pdev->dev,
1418                         "Self-test copy timed out, disabling\n");
1419                 err = -ENODEV;
1420                 goto free_resources;
1421         }
1422         if (memcmp(src, dest, IOAT_TEST_SIZE)) {
1423                 dev_err(&device->pdev->dev,
1424                         "Self-test copy failed compare, disabling\n");
1425                 err = -ENODEV;
1426                 goto free_resources;
1427         }
1428
1429 free_resources:
1430         device->common.device_free_chan_resources(dma_chan);
1431 out:
1432         kfree(src);
1433         kfree(dest);
1434         return err;
1435 }
1436
1437 static char ioat_interrupt_style[32] = "msix";
1438 module_param_string(ioat_interrupt_style, ioat_interrupt_style,
1439                     sizeof(ioat_interrupt_style), 0644);
1440 MODULE_PARM_DESC(ioat_interrupt_style,
1441                  "set ioat interrupt style: msix (default), "
1442                  "msix-single-vector, msi, intx)");
1443
1444 /**
1445  * ioat_dma_setup_interrupts - setup interrupt handler
1446  * @device: ioat device
1447  */
1448 static int ioat_dma_setup_interrupts(struct ioatdma_device *device)
1449 {
1450         struct ioat_dma_chan *ioat_chan;
1451         int err, i, j, msixcnt;
1452         u8 intrctrl = 0;
1453
1454         if (!strcmp(ioat_interrupt_style, "msix"))
1455                 goto msix;
1456         if (!strcmp(ioat_interrupt_style, "msix-single-vector"))
1457                 goto msix_single_vector;
1458         if (!strcmp(ioat_interrupt_style, "msi"))
1459                 goto msi;
1460         if (!strcmp(ioat_interrupt_style, "intx"))
1461                 goto intx;
1462         dev_err(&device->pdev->dev, "invalid ioat_interrupt_style %s\n",
1463                 ioat_interrupt_style);
1464         goto err_no_irq;
1465
1466 msix:
1467         /* The number of MSI-X vectors should equal the number of channels */
1468         msixcnt = device->common.chancnt;
1469         for (i = 0; i < msixcnt; i++)
1470                 device->msix_entries[i].entry = i;
1471
1472         err = pci_enable_msix(device->pdev, device->msix_entries, msixcnt);
1473         if (err < 0)
1474                 goto msi;
1475         if (err > 0)
1476                 goto msix_single_vector;
1477
1478         for (i = 0; i < msixcnt; i++) {
1479                 ioat_chan = ioat_lookup_chan_by_index(device, i);
1480                 err = request_irq(device->msix_entries[i].vector,
1481                                   ioat_dma_do_interrupt_msix,
1482                                   0, "ioat-msix", ioat_chan);
1483                 if (err) {
1484                         for (j = 0; j < i; j++) {
1485                                 ioat_chan =
1486                                         ioat_lookup_chan_by_index(device, j);
1487                                 free_irq(device->msix_entries[j].vector,
1488                                          ioat_chan);
1489                         }
1490                         goto msix_single_vector;
1491                 }
1492         }
1493         intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL;
1494         device->irq_mode = msix_multi_vector;
1495         goto done;
1496
1497 msix_single_vector:
1498         device->msix_entries[0].entry = 0;
1499         err = pci_enable_msix(device->pdev, device->msix_entries, 1);
1500         if (err)
1501                 goto msi;
1502
1503         err = request_irq(device->msix_entries[0].vector, ioat_dma_do_interrupt,
1504                           0, "ioat-msix", device);
1505         if (err) {
1506                 pci_disable_msix(device->pdev);
1507                 goto msi;
1508         }
1509         device->irq_mode = msix_single_vector;
1510         goto done;
1511
1512 msi:
1513         err = pci_enable_msi(device->pdev);
1514         if (err)
1515                 goto intx;
1516
1517         err = request_irq(device->pdev->irq, ioat_dma_do_interrupt,
1518                           0, "ioat-msi", device);
1519         if (err) {
1520                 pci_disable_msi(device->pdev);
1521                 goto intx;
1522         }
1523         /*
1524          * CB 1.2 devices need a bit set in configuration space to enable MSI
1525          */
1526         if (device->version == IOAT_VER_1_2) {
1527                 u32 dmactrl;
1528                 pci_read_config_dword(device->pdev,
1529                                       IOAT_PCI_DMACTRL_OFFSET, &dmactrl);
1530                 dmactrl |= IOAT_PCI_DMACTRL_MSI_EN;
1531                 pci_write_config_dword(device->pdev,
1532                                        IOAT_PCI_DMACTRL_OFFSET, dmactrl);
1533         }
1534         device->irq_mode = msi;
1535         goto done;
1536
1537 intx:
1538         err = request_irq(device->pdev->irq, ioat_dma_do_interrupt,
1539                           IRQF_SHARED, "ioat-intx", device);
1540         if (err)
1541                 goto err_no_irq;
1542         device->irq_mode = intx;
1543
1544 done:
1545         intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN;
1546         writeb(intrctrl, device->reg_base + IOAT_INTRCTRL_OFFSET);
1547         return 0;
1548
1549 err_no_irq:
1550         /* Disable all interrupt generation */
1551         writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
1552         dev_err(&device->pdev->dev, "no usable interrupts\n");
1553         device->irq_mode = none;
1554         return -1;
1555 }
1556
1557 /**
1558  * ioat_dma_remove_interrupts - remove whatever interrupts were set
1559  * @device: ioat device
1560  */
1561 static void ioat_dma_remove_interrupts(struct ioatdma_device *device)
1562 {
1563         struct ioat_dma_chan *ioat_chan;
1564         int i;
1565
1566         /* Disable all interrupt generation */
1567         writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
1568
1569         switch (device->irq_mode) {
1570         case msix_multi_vector:
1571                 for (i = 0; i < device->common.chancnt; i++) {
1572                         ioat_chan = ioat_lookup_chan_by_index(device, i);
1573                         free_irq(device->msix_entries[i].vector, ioat_chan);
1574                 }
1575                 pci_disable_msix(device->pdev);
1576                 break;
1577         case msix_single_vector:
1578                 free_irq(device->msix_entries[0].vector, device);
1579                 pci_disable_msix(device->pdev);
1580                 break;
1581         case msi:
1582                 free_irq(device->pdev->irq, device);
1583                 pci_disable_msi(device->pdev);
1584                 break;
1585         case intx:
1586                 free_irq(device->pdev->irq, device);
1587                 break;
1588         case none:
1589                 dev_warn(&device->pdev->dev,
1590                          "call to %s without interrupts setup\n", __func__);
1591         }
1592         device->irq_mode = none;
1593 }
1594
1595 struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev,
1596                                       void __iomem *iobase)
1597 {
1598         int err;
1599         struct ioatdma_device *device;
1600
1601         device = kzalloc(sizeof(*device), GFP_KERNEL);
1602         if (!device) {
1603                 err = -ENOMEM;
1604                 goto err_kzalloc;
1605         }
1606         device->pdev = pdev;
1607         device->reg_base = iobase;
1608         device->version = readb(device->reg_base + IOAT_VER_OFFSET);
1609
1610         /* DMA coherent memory pool for DMA descriptor allocations */
1611         device->dma_pool = pci_pool_create("dma_desc_pool", pdev,
1612                                            sizeof(struct ioat_dma_descriptor),
1613                                            64, 0);
1614         if (!device->dma_pool) {
1615                 err = -ENOMEM;
1616                 goto err_dma_pool;
1617         }
1618
1619         device->completion_pool = pci_pool_create("completion_pool", pdev,
1620                                                   sizeof(u64), SMP_CACHE_BYTES,
1621                                                   SMP_CACHE_BYTES);
1622         if (!device->completion_pool) {
1623                 err = -ENOMEM;
1624                 goto err_completion_pool;
1625         }
1626
1627         INIT_LIST_HEAD(&device->common.channels);
1628         ioat_dma_enumerate_channels(device);
1629
1630         device->common.device_alloc_chan_resources =
1631                                                 ioat_dma_alloc_chan_resources;
1632         device->common.device_free_chan_resources =
1633                                                 ioat_dma_free_chan_resources;
1634         device->common.dev = &pdev->dev;
1635
1636         dma_cap_set(DMA_MEMCPY, device->common.cap_mask);
1637         device->common.device_is_tx_complete = ioat_dma_is_complete;
1638         switch (device->version) {
1639         case IOAT_VER_1_2:
1640                 device->common.device_prep_dma_memcpy = ioat1_dma_prep_memcpy;
1641                 device->common.device_issue_pending =
1642                                                 ioat1_dma_memcpy_issue_pending;
1643                 break;
1644         case IOAT_VER_2_0:
1645         case IOAT_VER_3_0:
1646                 device->common.device_prep_dma_memcpy = ioat2_dma_prep_memcpy;
1647                 device->common.device_issue_pending =
1648                                                 ioat2_dma_memcpy_issue_pending;
1649                 break;
1650         }
1651
1652         dev_err(&device->pdev->dev,
1653                 "Intel(R) I/OAT DMA Engine found,"
1654                 " %d channels, device version 0x%02x, driver version %s\n",
1655                 device->common.chancnt, device->version, IOAT_DMA_VERSION);
1656
1657         err = ioat_dma_setup_interrupts(device);
1658         if (err)
1659                 goto err_setup_interrupts;
1660
1661         err = ioat_dma_self_test(device);
1662         if (err)
1663                 goto err_self_test;
1664
1665         ioat_set_tcp_copy_break(device);
1666
1667         dma_async_device_register(&device->common);
1668
1669         if (device->version != IOAT_VER_3_0) {
1670                 INIT_DELAYED_WORK(&device->work, ioat_dma_chan_watchdog);
1671                 schedule_delayed_work(&device->work,
1672                                       WATCHDOG_DELAY);
1673         }
1674
1675         return device;
1676
1677 err_self_test:
1678         ioat_dma_remove_interrupts(device);
1679 err_setup_interrupts:
1680         pci_pool_destroy(device->completion_pool);
1681 err_completion_pool:
1682         pci_pool_destroy(device->dma_pool);
1683 err_dma_pool:
1684         kfree(device);
1685 err_kzalloc:
1686         dev_err(&pdev->dev,
1687                 "Intel(R) I/OAT DMA Engine initialization failed\n");
1688         return NULL;
1689 }
1690
1691 void ioat_dma_remove(struct ioatdma_device *device)
1692 {
1693         struct dma_chan *chan, *_chan;
1694         struct ioat_dma_chan *ioat_chan;
1695
1696         ioat_dma_remove_interrupts(device);
1697
1698         dma_async_device_unregister(&device->common);
1699
1700         pci_pool_destroy(device->dma_pool);
1701         pci_pool_destroy(device->completion_pool);
1702
1703         iounmap(device->reg_base);
1704         pci_release_regions(device->pdev);
1705         pci_disable_device(device->pdev);
1706
1707         if (device->version != IOAT_VER_3_0) {
1708                 cancel_delayed_work(&device->work);
1709         }
1710
1711         list_for_each_entry_safe(chan, _chan,
1712                                  &device->common.channels, device_node) {
1713                 ioat_chan = to_ioat_chan(chan);
1714                 list_del(&chan->device_node);
1715                 kfree(ioat_chan);
1716         }
1717         kfree(device);
1718 }
1719