ioat: move definitions to dma.h
[linux-2.6.git] / drivers / dma / ioat / dma.c
1 /*
2  * Intel I/OAT DMA Linux driver
3  * Copyright(c) 2004 - 2009 Intel Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17  *
18  * The full GNU General Public License is included in this distribution in
19  * the file called "COPYING".
20  *
21  */
22
23 /*
24  * This driver supports an Intel I/OAT DMA engine, which does asynchronous
25  * copy operations.
26  */
27
28 #include <linux/init.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/interrupt.h>
32 #include <linux/dmaengine.h>
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/workqueue.h>
36 #include <linux/i7300_idle.h>
37 #include "dma.h"
38 #include "registers.h"
39 #include "hw.h"
40
41 static int ioat_pending_level = 4;
42 module_param(ioat_pending_level, int, 0644);
43 MODULE_PARM_DESC(ioat_pending_level,
44                  "high-water mark for pushing ioat descriptors (default: 4)");
45
46 static void ioat_dma_chan_reset_part2(struct work_struct *work);
47 static void ioat_dma_chan_watchdog(struct work_struct *work);
48
49 /* internal functions */
50 static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan);
51 static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan);
52
53 static struct ioat_desc_sw *
54 ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan);
55 static struct ioat_desc_sw *
56 ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan);
57
58 static inline struct ioat_dma_chan *ioat_lookup_chan_by_index(
59                                                 struct ioatdma_device *device,
60                                                 int index)
61 {
62         return device->idx[index];
63 }
64
65 /**
66  * ioat_dma_do_interrupt - handler used for single vector interrupt mode
67  * @irq: interrupt id
68  * @data: interrupt data
69  */
70 static irqreturn_t ioat_dma_do_interrupt(int irq, void *data)
71 {
72         struct ioatdma_device *instance = data;
73         struct ioat_dma_chan *ioat_chan;
74         unsigned long attnstatus;
75         int bit;
76         u8 intrctrl;
77
78         intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET);
79
80         if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN))
81                 return IRQ_NONE;
82
83         if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) {
84                 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
85                 return IRQ_NONE;
86         }
87
88         attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET);
89         for_each_bit(bit, &attnstatus, BITS_PER_LONG) {
90                 ioat_chan = ioat_lookup_chan_by_index(instance, bit);
91                 tasklet_schedule(&ioat_chan->cleanup_task);
92         }
93
94         writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
95         return IRQ_HANDLED;
96 }
97
98 /**
99  * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode
100  * @irq: interrupt id
101  * @data: interrupt data
102  */
103 static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data)
104 {
105         struct ioat_dma_chan *ioat_chan = data;
106
107         tasklet_schedule(&ioat_chan->cleanup_task);
108
109         return IRQ_HANDLED;
110 }
111
112 static void ioat_dma_cleanup_tasklet(unsigned long data);
113
114 /**
115  * ioat_dma_enumerate_channels - find and initialize the device's channels
116  * @device: the device to be enumerated
117  */
118 static int ioat_dma_enumerate_channels(struct ioatdma_device *device)
119 {
120         u8 xfercap_scale;
121         u32 xfercap;
122         int i;
123         struct ioat_dma_chan *ioat_chan;
124
125         /*
126          * IOAT ver.3 workarounds
127          */
128         if (device->version == IOAT_VER_3_0) {
129                 u32 chan_err_mask;
130                 u16 dev_id;
131                 u32 dmauncerrsts;
132
133                 /*
134                  * Write CHANERRMSK_INT with 3E07h to mask out the errors
135                  * that can cause stability issues for IOAT ver.3
136                  */
137                 chan_err_mask = 0x3E07;
138                 pci_write_config_dword(device->pdev,
139                         IOAT_PCI_CHANERRMASK_INT_OFFSET,
140                         chan_err_mask);
141
142                 /*
143                  * Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit
144                  * (workaround for spurious config parity error after restart)
145                  */
146                 pci_read_config_word(device->pdev,
147                         IOAT_PCI_DEVICE_ID_OFFSET,
148                         &dev_id);
149                 if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) {
150                         dmauncerrsts = 0x10;
151                         pci_write_config_dword(device->pdev,
152                                 IOAT_PCI_DMAUNCERRSTS_OFFSET,
153                                 dmauncerrsts);
154                 }
155         }
156
157         device->common.chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
158         xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
159         xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale));
160
161 #ifdef  CONFIG_I7300_IDLE_IOAT_CHANNEL
162         if (i7300_idle_platform_probe(NULL, NULL, 1) == 0) {
163                 device->common.chancnt--;
164         }
165 #endif
166         for (i = 0; i < device->common.chancnt; i++) {
167                 ioat_chan = kzalloc(sizeof(*ioat_chan), GFP_KERNEL);
168                 if (!ioat_chan) {
169                         device->common.chancnt = i;
170                         break;
171                 }
172
173                 ioat_chan->device = device;
174                 ioat_chan->reg_base = device->reg_base + (0x80 * (i + 1));
175                 ioat_chan->xfercap = xfercap;
176                 ioat_chan->desccount = 0;
177                 INIT_DELAYED_WORK(&ioat_chan->work, ioat_dma_chan_reset_part2);
178                 if (ioat_chan->device->version == IOAT_VER_2_0)
179                         writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE |
180                                IOAT_DMA_DCA_ANY_CPU,
181                                ioat_chan->reg_base + IOAT_DCACTRL_OFFSET);
182                 else if (ioat_chan->device->version == IOAT_VER_3_0)
183                         writel(IOAT_DMA_DCA_ANY_CPU,
184                                ioat_chan->reg_base + IOAT_DCACTRL_OFFSET);
185                 spin_lock_init(&ioat_chan->cleanup_lock);
186                 spin_lock_init(&ioat_chan->desc_lock);
187                 INIT_LIST_HEAD(&ioat_chan->free_desc);
188                 INIT_LIST_HEAD(&ioat_chan->used_desc);
189                 /* This should be made common somewhere in dmaengine.c */
190                 ioat_chan->common.device = &device->common;
191                 list_add_tail(&ioat_chan->common.device_node,
192                               &device->common.channels);
193                 device->idx[i] = ioat_chan;
194                 tasklet_init(&ioat_chan->cleanup_task,
195                              ioat_dma_cleanup_tasklet,
196                              (unsigned long) ioat_chan);
197                 tasklet_disable(&ioat_chan->cleanup_task);
198         }
199         return device->common.chancnt;
200 }
201
202 /**
203  * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended
204  *                                 descriptors to hw
205  * @chan: DMA channel handle
206  */
207 static inline void __ioat1_dma_memcpy_issue_pending(
208                                                 struct ioat_dma_chan *ioat_chan)
209 {
210         ioat_chan->pending = 0;
211         writeb(IOAT_CHANCMD_APPEND, ioat_chan->reg_base + IOAT1_CHANCMD_OFFSET);
212 }
213
214 static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan)
215 {
216         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
217
218         if (ioat_chan->pending > 0) {
219                 spin_lock_bh(&ioat_chan->desc_lock);
220                 __ioat1_dma_memcpy_issue_pending(ioat_chan);
221                 spin_unlock_bh(&ioat_chan->desc_lock);
222         }
223 }
224
225 static inline void __ioat2_dma_memcpy_issue_pending(
226                                                 struct ioat_dma_chan *ioat_chan)
227 {
228         ioat_chan->pending = 0;
229         writew(ioat_chan->dmacount,
230                ioat_chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET);
231 }
232
233 static void ioat2_dma_memcpy_issue_pending(struct dma_chan *chan)
234 {
235         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
236
237         if (ioat_chan->pending > 0) {
238                 spin_lock_bh(&ioat_chan->desc_lock);
239                 __ioat2_dma_memcpy_issue_pending(ioat_chan);
240                 spin_unlock_bh(&ioat_chan->desc_lock);
241         }
242 }
243
244
245 /**
246  * ioat_dma_chan_reset_part2 - reinit the channel after a reset
247  */
248 static void ioat_dma_chan_reset_part2(struct work_struct *work)
249 {
250         struct ioat_dma_chan *ioat_chan =
251                 container_of(work, struct ioat_dma_chan, work.work);
252         struct ioat_desc_sw *desc;
253
254         spin_lock_bh(&ioat_chan->cleanup_lock);
255         spin_lock_bh(&ioat_chan->desc_lock);
256
257         ioat_chan->completion_virt->low = 0;
258         ioat_chan->completion_virt->high = 0;
259         ioat_chan->pending = 0;
260
261         /*
262          * count the descriptors waiting, and be sure to do it
263          * right for both the CB1 line and the CB2 ring
264          */
265         ioat_chan->dmacount = 0;
266         if (ioat_chan->used_desc.prev) {
267                 desc = to_ioat_desc(ioat_chan->used_desc.prev);
268                 do {
269                         ioat_chan->dmacount++;
270                         desc = to_ioat_desc(desc->node.next);
271                 } while (&desc->node != ioat_chan->used_desc.next);
272         }
273
274         /*
275          * write the new starting descriptor address
276          * this puts channel engine into ARMED state
277          */
278         desc = to_ioat_desc(ioat_chan->used_desc.prev);
279         switch (ioat_chan->device->version) {
280         case IOAT_VER_1_2:
281                 writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
282                        ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
283                 writel(((u64) desc->async_tx.phys) >> 32,
284                        ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
285
286                 writeb(IOAT_CHANCMD_START, ioat_chan->reg_base
287                         + IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
288                 break;
289         case IOAT_VER_2_0:
290                 writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
291                        ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
292                 writel(((u64) desc->async_tx.phys) >> 32,
293                        ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
294
295                 /* tell the engine to go with what's left to be done */
296                 writew(ioat_chan->dmacount,
297                        ioat_chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET);
298
299                 break;
300         }
301         dev_err(&ioat_chan->device->pdev->dev,
302                 "chan%d reset - %d descs waiting, %d total desc\n",
303                 chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount);
304
305         spin_unlock_bh(&ioat_chan->desc_lock);
306         spin_unlock_bh(&ioat_chan->cleanup_lock);
307 }
308
309 /**
310  * ioat_dma_reset_channel - restart a channel
311  * @ioat_chan: IOAT DMA channel handle
312  */
313 static void ioat_dma_reset_channel(struct ioat_dma_chan *ioat_chan)
314 {
315         u32 chansts, chanerr;
316
317         if (!ioat_chan->used_desc.prev)
318                 return;
319
320         chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
321         chansts = (ioat_chan->completion_virt->low
322                                         & IOAT_CHANSTS_DMA_TRANSFER_STATUS);
323         if (chanerr) {
324                 dev_err(&ioat_chan->device->pdev->dev,
325                         "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n",
326                         chan_num(ioat_chan), chansts, chanerr);
327                 writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
328         }
329
330         /*
331          * whack it upside the head with a reset
332          * and wait for things to settle out.
333          * force the pending count to a really big negative
334          * to make sure no one forces an issue_pending
335          * while we're waiting.
336          */
337
338         spin_lock_bh(&ioat_chan->desc_lock);
339         ioat_chan->pending = INT_MIN;
340         writeb(IOAT_CHANCMD_RESET,
341                ioat_chan->reg_base
342                + IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
343         spin_unlock_bh(&ioat_chan->desc_lock);
344
345         /* schedule the 2nd half instead of sleeping a long time */
346         schedule_delayed_work(&ioat_chan->work, RESET_DELAY);
347 }
348
349 /**
350  * ioat_dma_chan_watchdog - watch for stuck channels
351  */
352 static void ioat_dma_chan_watchdog(struct work_struct *work)
353 {
354         struct ioatdma_device *device =
355                 container_of(work, struct ioatdma_device, work.work);
356         struct ioat_dma_chan *ioat_chan;
357         int i;
358
359         union {
360                 u64 full;
361                 struct {
362                         u32 low;
363                         u32 high;
364                 };
365         } completion_hw;
366         unsigned long compl_desc_addr_hw;
367
368         for (i = 0; i < device->common.chancnt; i++) {
369                 ioat_chan = ioat_lookup_chan_by_index(device, i);
370
371                 if (ioat_chan->device->version == IOAT_VER_1_2
372                         /* have we started processing anything yet */
373                     && ioat_chan->last_completion
374                         /* have we completed any since last watchdog cycle? */
375                     && (ioat_chan->last_completion ==
376                                 ioat_chan->watchdog_completion)
377                         /* has TCP stuck on one cookie since last watchdog? */
378                     && (ioat_chan->watchdog_tcp_cookie ==
379                                 ioat_chan->watchdog_last_tcp_cookie)
380                     && (ioat_chan->watchdog_tcp_cookie !=
381                                 ioat_chan->completed_cookie)
382                         /* is there something in the chain to be processed? */
383                         /* CB1 chain always has at least the last one processed */
384                     && (ioat_chan->used_desc.prev != ioat_chan->used_desc.next)
385                     && ioat_chan->pending == 0) {
386
387                         /*
388                          * check CHANSTS register for completed
389                          * descriptor address.
390                          * if it is different than completion writeback,
391                          * it is not zero
392                          * and it has changed since the last watchdog
393                          *     we can assume that channel
394                          *     is still working correctly
395                          *     and the problem is in completion writeback.
396                          *     update completion writeback
397                          *     with actual CHANSTS value
398                          * else
399                          *     try resetting the channel
400                          */
401
402                         completion_hw.low = readl(ioat_chan->reg_base +
403                                 IOAT_CHANSTS_OFFSET_LOW(ioat_chan->device->version));
404                         completion_hw.high = readl(ioat_chan->reg_base +
405                                 IOAT_CHANSTS_OFFSET_HIGH(ioat_chan->device->version));
406 #if (BITS_PER_LONG == 64)
407                         compl_desc_addr_hw =
408                                 completion_hw.full
409                                 & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
410 #else
411                         compl_desc_addr_hw =
412                                 completion_hw.low & IOAT_LOW_COMPLETION_MASK;
413 #endif
414
415                         if ((compl_desc_addr_hw != 0)
416                            && (compl_desc_addr_hw != ioat_chan->watchdog_completion)
417                            && (compl_desc_addr_hw != ioat_chan->last_compl_desc_addr_hw)) {
418                                 ioat_chan->last_compl_desc_addr_hw = compl_desc_addr_hw;
419                                 ioat_chan->completion_virt->low = completion_hw.low;
420                                 ioat_chan->completion_virt->high = completion_hw.high;
421                         } else {
422                                 ioat_dma_reset_channel(ioat_chan);
423                                 ioat_chan->watchdog_completion = 0;
424                                 ioat_chan->last_compl_desc_addr_hw = 0;
425                         }
426
427                 /*
428                  * for version 2.0 if there are descriptors yet to be processed
429                  * and the last completed hasn't changed since the last watchdog
430                  *      if they haven't hit the pending level
431                  *          issue the pending to push them through
432                  *      else
433                  *          try resetting the channel
434                  */
435                 } else if (ioat_chan->device->version == IOAT_VER_2_0
436                     && ioat_chan->used_desc.prev
437                     && ioat_chan->last_completion
438                     && ioat_chan->last_completion == ioat_chan->watchdog_completion) {
439
440                         if (ioat_chan->pending < ioat_pending_level)
441                                 ioat2_dma_memcpy_issue_pending(&ioat_chan->common);
442                         else {
443                                 ioat_dma_reset_channel(ioat_chan);
444                                 ioat_chan->watchdog_completion = 0;
445                         }
446                 } else {
447                         ioat_chan->last_compl_desc_addr_hw = 0;
448                         ioat_chan->watchdog_completion
449                                         = ioat_chan->last_completion;
450                 }
451
452                 ioat_chan->watchdog_last_tcp_cookie =
453                         ioat_chan->watchdog_tcp_cookie;
454         }
455
456         schedule_delayed_work(&device->work, WATCHDOG_DELAY);
457 }
458
459 static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
460 {
461         struct ioat_dma_chan *ioat_chan = to_ioat_chan(tx->chan);
462         struct ioat_desc_sw *first = tx_to_ioat_desc(tx);
463         struct ioat_desc_sw *prev, *new;
464         struct ioat_dma_descriptor *hw;
465         dma_cookie_t cookie;
466         LIST_HEAD(new_chain);
467         u32 copy;
468         size_t len;
469         dma_addr_t src, dst;
470         unsigned long orig_flags;
471         unsigned int desc_count = 0;
472
473         /* src and dest and len are stored in the initial descriptor */
474         len = first->len;
475         src = first->src;
476         dst = first->dst;
477         orig_flags = first->async_tx.flags;
478         new = first;
479
480         spin_lock_bh(&ioat_chan->desc_lock);
481         prev = to_ioat_desc(ioat_chan->used_desc.prev);
482         prefetch(prev->hw);
483         do {
484                 copy = min_t(size_t, len, ioat_chan->xfercap);
485
486                 async_tx_ack(&new->async_tx);
487
488                 hw = new->hw;
489                 hw->size = copy;
490                 hw->ctl = 0;
491                 hw->src_addr = src;
492                 hw->dst_addr = dst;
493                 hw->next = 0;
494
495                 /* chain together the physical address list for the HW */
496                 wmb();
497                 prev->hw->next = (u64) new->async_tx.phys;
498
499                 len -= copy;
500                 dst += copy;
501                 src += copy;
502
503                 list_add_tail(&new->node, &new_chain);
504                 desc_count++;
505                 prev = new;
506         } while (len && (new = ioat1_dma_get_next_descriptor(ioat_chan)));
507
508         if (!new) {
509                 dev_err(&ioat_chan->device->pdev->dev,
510                         "tx submit failed\n");
511                 spin_unlock_bh(&ioat_chan->desc_lock);
512                 return -ENOMEM;
513         }
514
515         hw->ctl = IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
516         if (first->async_tx.callback) {
517                 hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN;
518                 if (first != new) {
519                         /* move callback into to last desc */
520                         new->async_tx.callback = first->async_tx.callback;
521                         new->async_tx.callback_param
522                                         = first->async_tx.callback_param;
523                         first->async_tx.callback = NULL;
524                         first->async_tx.callback_param = NULL;
525                 }
526         }
527
528         new->tx_cnt = desc_count;
529         new->async_tx.flags = orig_flags; /* client is in control of this ack */
530
531         /* store the original values for use in later cleanup */
532         if (new != first) {
533                 new->src = first->src;
534                 new->dst = first->dst;
535                 new->len = first->len;
536         }
537
538         /* cookie incr and addition to used_list must be atomic */
539         cookie = ioat_chan->common.cookie;
540         cookie++;
541         if (cookie < 0)
542                 cookie = 1;
543         ioat_chan->common.cookie = new->async_tx.cookie = cookie;
544
545         /* write address into NextDescriptor field of last desc in chain */
546         to_ioat_desc(ioat_chan->used_desc.prev)->hw->next =
547                                                         first->async_tx.phys;
548         list_splice_tail(&new_chain, &ioat_chan->used_desc);
549
550         ioat_chan->dmacount += desc_count;
551         ioat_chan->pending += desc_count;
552         if (ioat_chan->pending >= ioat_pending_level)
553                 __ioat1_dma_memcpy_issue_pending(ioat_chan);
554         spin_unlock_bh(&ioat_chan->desc_lock);
555
556         return cookie;
557 }
558
559 static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx)
560 {
561         struct ioat_dma_chan *ioat_chan = to_ioat_chan(tx->chan);
562         struct ioat_desc_sw *first = tx_to_ioat_desc(tx);
563         struct ioat_desc_sw *new;
564         struct ioat_dma_descriptor *hw;
565         dma_cookie_t cookie;
566         u32 copy;
567         size_t len;
568         dma_addr_t src, dst;
569         unsigned long orig_flags;
570         unsigned int desc_count = 0;
571
572         /* src and dest and len are stored in the initial descriptor */
573         len = first->len;
574         src = first->src;
575         dst = first->dst;
576         orig_flags = first->async_tx.flags;
577         new = first;
578
579         /*
580          * ioat_chan->desc_lock is still in force in version 2 path
581          * it gets unlocked at end of this function
582          */
583         do {
584                 copy = min_t(size_t, len, ioat_chan->xfercap);
585
586                 async_tx_ack(&new->async_tx);
587
588                 hw = new->hw;
589                 hw->size = copy;
590                 hw->ctl = 0;
591                 hw->src_addr = src;
592                 hw->dst_addr = dst;
593
594                 len -= copy;
595                 dst += copy;
596                 src += copy;
597                 desc_count++;
598         } while (len && (new = ioat2_dma_get_next_descriptor(ioat_chan)));
599
600         if (!new) {
601                 dev_err(&ioat_chan->device->pdev->dev,
602                         "tx submit failed\n");
603                 spin_unlock_bh(&ioat_chan->desc_lock);
604                 return -ENOMEM;
605         }
606
607         hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
608         if (first->async_tx.callback) {
609                 hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN;
610                 if (first != new) {
611                         /* move callback into to last desc */
612                         new->async_tx.callback = first->async_tx.callback;
613                         new->async_tx.callback_param
614                                         = first->async_tx.callback_param;
615                         first->async_tx.callback = NULL;
616                         first->async_tx.callback_param = NULL;
617                 }
618         }
619
620         new->tx_cnt = desc_count;
621         new->async_tx.flags = orig_flags; /* client is in control of this ack */
622
623         /* store the original values for use in later cleanup */
624         if (new != first) {
625                 new->src = first->src;
626                 new->dst = first->dst;
627                 new->len = first->len;
628         }
629
630         /* cookie incr and addition to used_list must be atomic */
631         cookie = ioat_chan->common.cookie;
632         cookie++;
633         if (cookie < 0)
634                 cookie = 1;
635         ioat_chan->common.cookie = new->async_tx.cookie = cookie;
636
637         ioat_chan->dmacount += desc_count;
638         ioat_chan->pending += desc_count;
639         if (ioat_chan->pending >= ioat_pending_level)
640                 __ioat2_dma_memcpy_issue_pending(ioat_chan);
641         spin_unlock_bh(&ioat_chan->desc_lock);
642
643         return cookie;
644 }
645
646 /**
647  * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair
648  * @ioat_chan: the channel supplying the memory pool for the descriptors
649  * @flags: allocation flags
650  */
651 static struct ioat_desc_sw *ioat_dma_alloc_descriptor(
652                                         struct ioat_dma_chan *ioat_chan,
653                                         gfp_t flags)
654 {
655         struct ioat_dma_descriptor *desc;
656         struct ioat_desc_sw *desc_sw;
657         struct ioatdma_device *ioatdma_device;
658         dma_addr_t phys;
659
660         ioatdma_device = to_ioatdma_device(ioat_chan->common.device);
661         desc = pci_pool_alloc(ioatdma_device->dma_pool, flags, &phys);
662         if (unlikely(!desc))
663                 return NULL;
664
665         desc_sw = kzalloc(sizeof(*desc_sw), flags);
666         if (unlikely(!desc_sw)) {
667                 pci_pool_free(ioatdma_device->dma_pool, desc, phys);
668                 return NULL;
669         }
670
671         memset(desc, 0, sizeof(*desc));
672         dma_async_tx_descriptor_init(&desc_sw->async_tx, &ioat_chan->common);
673         switch (ioat_chan->device->version) {
674         case IOAT_VER_1_2:
675                 desc_sw->async_tx.tx_submit = ioat1_tx_submit;
676                 break;
677         case IOAT_VER_2_0:
678         case IOAT_VER_3_0:
679                 desc_sw->async_tx.tx_submit = ioat2_tx_submit;
680                 break;
681         }
682
683         desc_sw->hw = desc;
684         desc_sw->async_tx.phys = phys;
685
686         return desc_sw;
687 }
688
689 static int ioat_initial_desc_count = 256;
690 module_param(ioat_initial_desc_count, int, 0644);
691 MODULE_PARM_DESC(ioat_initial_desc_count,
692                  "initial descriptors per channel (default: 256)");
693
694 /**
695  * ioat2_dma_massage_chan_desc - link the descriptors into a circle
696  * @ioat_chan: the channel to be massaged
697  */
698 static void ioat2_dma_massage_chan_desc(struct ioat_dma_chan *ioat_chan)
699 {
700         struct ioat_desc_sw *desc, *_desc;
701
702         /* setup used_desc */
703         ioat_chan->used_desc.next = ioat_chan->free_desc.next;
704         ioat_chan->used_desc.prev = NULL;
705
706         /* pull free_desc out of the circle so that every node is a hw
707          * descriptor, but leave it pointing to the list
708          */
709         ioat_chan->free_desc.prev->next = ioat_chan->free_desc.next;
710         ioat_chan->free_desc.next->prev = ioat_chan->free_desc.prev;
711
712         /* circle link the hw descriptors */
713         desc = to_ioat_desc(ioat_chan->free_desc.next);
714         desc->hw->next = to_ioat_desc(desc->node.next)->async_tx.phys;
715         list_for_each_entry_safe(desc, _desc, ioat_chan->free_desc.next, node) {
716                 desc->hw->next = to_ioat_desc(desc->node.next)->async_tx.phys;
717         }
718 }
719
720 /**
721  * ioat_dma_alloc_chan_resources - returns the number of allocated descriptors
722  * @chan: the channel to be filled out
723  */
724 static int ioat_dma_alloc_chan_resources(struct dma_chan *chan)
725 {
726         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
727         struct ioat_desc_sw *desc;
728         u16 chanctrl;
729         u32 chanerr;
730         int i;
731         LIST_HEAD(tmp_list);
732
733         /* have we already been set up? */
734         if (!list_empty(&ioat_chan->free_desc))
735                 return ioat_chan->desccount;
736
737         /* Setup register to interrupt and write completion status on error */
738         chanctrl = IOAT_CHANCTRL_ERR_INT_EN |
739                 IOAT_CHANCTRL_ANY_ERR_ABORT_EN |
740                 IOAT_CHANCTRL_ERR_COMPLETION_EN;
741         writew(chanctrl, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET);
742
743         chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
744         if (chanerr) {
745                 dev_err(&ioat_chan->device->pdev->dev,
746                         "CHANERR = %x, clearing\n", chanerr);
747                 writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
748         }
749
750         /* Allocate descriptors */
751         for (i = 0; i < ioat_initial_desc_count; i++) {
752                 desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_KERNEL);
753                 if (!desc) {
754                         dev_err(&ioat_chan->device->pdev->dev,
755                                 "Only %d initial descriptors\n", i);
756                         break;
757                 }
758                 list_add_tail(&desc->node, &tmp_list);
759         }
760         spin_lock_bh(&ioat_chan->desc_lock);
761         ioat_chan->desccount = i;
762         list_splice(&tmp_list, &ioat_chan->free_desc);
763         if (ioat_chan->device->version != IOAT_VER_1_2)
764                 ioat2_dma_massage_chan_desc(ioat_chan);
765         spin_unlock_bh(&ioat_chan->desc_lock);
766
767         /* allocate a completion writeback area */
768         /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
769         ioat_chan->completion_virt =
770                 pci_pool_alloc(ioat_chan->device->completion_pool,
771                                GFP_KERNEL,
772                                &ioat_chan->completion_addr);
773         memset(ioat_chan->completion_virt, 0,
774                sizeof(*ioat_chan->completion_virt));
775         writel(((u64) ioat_chan->completion_addr) & 0x00000000FFFFFFFF,
776                ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
777         writel(((u64) ioat_chan->completion_addr) >> 32,
778                ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
779
780         tasklet_enable(&ioat_chan->cleanup_task);
781         ioat_dma_start_null_desc(ioat_chan);  /* give chain to dma device */
782         return ioat_chan->desccount;
783 }
784
785 /**
786  * ioat_dma_free_chan_resources - release all the descriptors
787  * @chan: the channel to be cleaned
788  */
789 static void ioat_dma_free_chan_resources(struct dma_chan *chan)
790 {
791         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
792         struct ioatdma_device *ioatdma_device = to_ioatdma_device(chan->device);
793         struct ioat_desc_sw *desc, *_desc;
794         int in_use_descs = 0;
795
796         /* Before freeing channel resources first check
797          * if they have been previously allocated for this channel.
798          */
799         if (ioat_chan->desccount == 0)
800                 return;
801
802         tasklet_disable(&ioat_chan->cleanup_task);
803         ioat_dma_memcpy_cleanup(ioat_chan);
804
805         /* Delay 100ms after reset to allow internal DMA logic to quiesce
806          * before removing DMA descriptor resources.
807          */
808         writeb(IOAT_CHANCMD_RESET,
809                ioat_chan->reg_base
810                         + IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
811         mdelay(100);
812
813         spin_lock_bh(&ioat_chan->desc_lock);
814         switch (ioat_chan->device->version) {
815         case IOAT_VER_1_2:
816                 list_for_each_entry_safe(desc, _desc,
817                                          &ioat_chan->used_desc, node) {
818                         in_use_descs++;
819                         list_del(&desc->node);
820                         pci_pool_free(ioatdma_device->dma_pool, desc->hw,
821                                       desc->async_tx.phys);
822                         kfree(desc);
823                 }
824                 list_for_each_entry_safe(desc, _desc,
825                                          &ioat_chan->free_desc, node) {
826                         list_del(&desc->node);
827                         pci_pool_free(ioatdma_device->dma_pool, desc->hw,
828                                       desc->async_tx.phys);
829                         kfree(desc);
830                 }
831                 break;
832         case IOAT_VER_2_0:
833         case IOAT_VER_3_0:
834                 list_for_each_entry_safe(desc, _desc,
835                                          ioat_chan->free_desc.next, node) {
836                         list_del(&desc->node);
837                         pci_pool_free(ioatdma_device->dma_pool, desc->hw,
838                                       desc->async_tx.phys);
839                         kfree(desc);
840                 }
841                 desc = to_ioat_desc(ioat_chan->free_desc.next);
842                 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
843                               desc->async_tx.phys);
844                 kfree(desc);
845                 INIT_LIST_HEAD(&ioat_chan->free_desc);
846                 INIT_LIST_HEAD(&ioat_chan->used_desc);
847                 break;
848         }
849         spin_unlock_bh(&ioat_chan->desc_lock);
850
851         pci_pool_free(ioatdma_device->completion_pool,
852                       ioat_chan->completion_virt,
853                       ioat_chan->completion_addr);
854
855         /* one is ok since we left it on there on purpose */
856         if (in_use_descs > 1)
857                 dev_err(&ioat_chan->device->pdev->dev,
858                         "Freeing %d in use descriptors!\n",
859                         in_use_descs - 1);
860
861         ioat_chan->last_completion = ioat_chan->completion_addr = 0;
862         ioat_chan->pending = 0;
863         ioat_chan->dmacount = 0;
864         ioat_chan->desccount = 0;
865         ioat_chan->watchdog_completion = 0;
866         ioat_chan->last_compl_desc_addr_hw = 0;
867         ioat_chan->watchdog_tcp_cookie =
868                 ioat_chan->watchdog_last_tcp_cookie = 0;
869 }
870
871 /**
872  * ioat_dma_get_next_descriptor - return the next available descriptor
873  * @ioat_chan: IOAT DMA channel handle
874  *
875  * Gets the next descriptor from the chain, and must be called with the
876  * channel's desc_lock held.  Allocates more descriptors if the channel
877  * has run out.
878  */
879 static struct ioat_desc_sw *
880 ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan)
881 {
882         struct ioat_desc_sw *new;
883
884         if (!list_empty(&ioat_chan->free_desc)) {
885                 new = to_ioat_desc(ioat_chan->free_desc.next);
886                 list_del(&new->node);
887         } else {
888                 /* try to get another desc */
889                 new = ioat_dma_alloc_descriptor(ioat_chan, GFP_ATOMIC);
890                 if (!new) {
891                         dev_err(&ioat_chan->device->pdev->dev,
892                                 "alloc failed\n");
893                         return NULL;
894                 }
895         }
896
897         prefetch(new->hw);
898         return new;
899 }
900
901 static struct ioat_desc_sw *
902 ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan)
903 {
904         struct ioat_desc_sw *new;
905
906         /*
907          * used.prev points to where to start processing
908          * used.next points to next free descriptor
909          * if used.prev == NULL, there are none waiting to be processed
910          * if used.next == used.prev.prev, there is only one free descriptor,
911          *      and we need to use it to as a noop descriptor before
912          *      linking in a new set of descriptors, since the device
913          *      has probably already read the pointer to it
914          */
915         if (ioat_chan->used_desc.prev &&
916             ioat_chan->used_desc.next == ioat_chan->used_desc.prev->prev) {
917
918                 struct ioat_desc_sw *desc;
919                 struct ioat_desc_sw *noop_desc;
920                 int i;
921
922                 /* set up the noop descriptor */
923                 noop_desc = to_ioat_desc(ioat_chan->used_desc.next);
924                 /* set size to non-zero value (channel returns error when size is 0) */
925                 noop_desc->hw->size = NULL_DESC_BUFFER_SIZE;
926                 noop_desc->hw->ctl = IOAT_DMA_DESCRIPTOR_NUL;
927                 noop_desc->hw->src_addr = 0;
928                 noop_desc->hw->dst_addr = 0;
929
930                 ioat_chan->used_desc.next = ioat_chan->used_desc.next->next;
931                 ioat_chan->pending++;
932                 ioat_chan->dmacount++;
933
934                 /* try to get a few more descriptors */
935                 for (i = 16; i; i--) {
936                         desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_ATOMIC);
937                         if (!desc) {
938                                 dev_err(&ioat_chan->device->pdev->dev,
939                                         "alloc failed\n");
940                                 break;
941                         }
942                         list_add_tail(&desc->node, ioat_chan->used_desc.next);
943
944                         desc->hw->next
945                                 = to_ioat_desc(desc->node.next)->async_tx.phys;
946                         to_ioat_desc(desc->node.prev)->hw->next
947                                 = desc->async_tx.phys;
948                         ioat_chan->desccount++;
949                 }
950
951                 ioat_chan->used_desc.next = noop_desc->node.next;
952         }
953         new = to_ioat_desc(ioat_chan->used_desc.next);
954         prefetch(new);
955         ioat_chan->used_desc.next = new->node.next;
956
957         if (ioat_chan->used_desc.prev == NULL)
958                 ioat_chan->used_desc.prev = &new->node;
959
960         prefetch(new->hw);
961         return new;
962 }
963
964 static struct ioat_desc_sw *ioat_dma_get_next_descriptor(
965                                                 struct ioat_dma_chan *ioat_chan)
966 {
967         if (!ioat_chan)
968                 return NULL;
969
970         switch (ioat_chan->device->version) {
971         case IOAT_VER_1_2:
972                 return ioat1_dma_get_next_descriptor(ioat_chan);
973         case IOAT_VER_2_0:
974         case IOAT_VER_3_0:
975                 return ioat2_dma_get_next_descriptor(ioat_chan);
976         }
977         return NULL;
978 }
979
980 static struct dma_async_tx_descriptor *ioat1_dma_prep_memcpy(
981                                                 struct dma_chan *chan,
982                                                 dma_addr_t dma_dest,
983                                                 dma_addr_t dma_src,
984                                                 size_t len,
985                                                 unsigned long flags)
986 {
987         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
988         struct ioat_desc_sw *new;
989
990         spin_lock_bh(&ioat_chan->desc_lock);
991         new = ioat_dma_get_next_descriptor(ioat_chan);
992         spin_unlock_bh(&ioat_chan->desc_lock);
993
994         if (new) {
995                 new->len = len;
996                 new->dst = dma_dest;
997                 new->src = dma_src;
998                 new->async_tx.flags = flags;
999                 return &new->async_tx;
1000         } else {
1001                 dev_err(&ioat_chan->device->pdev->dev,
1002                         "chan%d - get_next_desc failed: %d descs waiting, %d total desc\n",
1003                         chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount);
1004                 return NULL;
1005         }
1006 }
1007
1008 static struct dma_async_tx_descriptor *ioat2_dma_prep_memcpy(
1009                                                 struct dma_chan *chan,
1010                                                 dma_addr_t dma_dest,
1011                                                 dma_addr_t dma_src,
1012                                                 size_t len,
1013                                                 unsigned long flags)
1014 {
1015         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
1016         struct ioat_desc_sw *new;
1017
1018         spin_lock_bh(&ioat_chan->desc_lock);
1019         new = ioat2_dma_get_next_descriptor(ioat_chan);
1020
1021         /*
1022          * leave ioat_chan->desc_lock set in ioat 2 path
1023          * it will get unlocked at end of tx_submit
1024          */
1025
1026         if (new) {
1027                 new->len = len;
1028                 new->dst = dma_dest;
1029                 new->src = dma_src;
1030                 new->async_tx.flags = flags;
1031                 return &new->async_tx;
1032         } else {
1033                 spin_unlock_bh(&ioat_chan->desc_lock);
1034                 dev_err(&ioat_chan->device->pdev->dev,
1035                         "chan%d - get_next_desc failed: %d descs waiting, %d total desc\n",
1036                         chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount);
1037                 return NULL;
1038         }
1039 }
1040
1041 static void ioat_dma_cleanup_tasklet(unsigned long data)
1042 {
1043         struct ioat_dma_chan *chan = (void *)data;
1044         ioat_dma_memcpy_cleanup(chan);
1045         writew(IOAT_CHANCTRL_INT_DISABLE,
1046                chan->reg_base + IOAT_CHANCTRL_OFFSET);
1047 }
1048
1049 static void
1050 ioat_dma_unmap(struct ioat_dma_chan *ioat_chan, struct ioat_desc_sw *desc)
1051 {
1052         if (!(desc->async_tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
1053                 if (desc->async_tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE)
1054                         pci_unmap_single(ioat_chan->device->pdev,
1055                                          pci_unmap_addr(desc, dst),
1056                                          pci_unmap_len(desc, len),
1057                                          PCI_DMA_FROMDEVICE);
1058                 else
1059                         pci_unmap_page(ioat_chan->device->pdev,
1060                                        pci_unmap_addr(desc, dst),
1061                                        pci_unmap_len(desc, len),
1062                                        PCI_DMA_FROMDEVICE);
1063         }
1064
1065         if (!(desc->async_tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
1066                 if (desc->async_tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE)
1067                         pci_unmap_single(ioat_chan->device->pdev,
1068                                          pci_unmap_addr(desc, src),
1069                                          pci_unmap_len(desc, len),
1070                                          PCI_DMA_TODEVICE);
1071                 else
1072                         pci_unmap_page(ioat_chan->device->pdev,
1073                                        pci_unmap_addr(desc, src),
1074                                        pci_unmap_len(desc, len),
1075                                        PCI_DMA_TODEVICE);
1076         }
1077 }
1078
1079 /**
1080  * ioat_dma_memcpy_cleanup - cleanup up finished descriptors
1081  * @chan: ioat channel to be cleaned up
1082  */
1083 static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan)
1084 {
1085         unsigned long phys_complete;
1086         struct ioat_desc_sw *desc, *_desc;
1087         dma_cookie_t cookie = 0;
1088         unsigned long desc_phys;
1089         struct ioat_desc_sw *latest_desc;
1090
1091         prefetch(ioat_chan->completion_virt);
1092
1093         if (!spin_trylock_bh(&ioat_chan->cleanup_lock))
1094                 return;
1095
1096         /* The completion writeback can happen at any time,
1097            so reads by the driver need to be atomic operations
1098            The descriptor physical addresses are limited to 32-bits
1099            when the CPU can only do a 32-bit mov */
1100
1101 #if (BITS_PER_LONG == 64)
1102         phys_complete =
1103                 ioat_chan->completion_virt->full
1104                 & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
1105 #else
1106         phys_complete =
1107                 ioat_chan->completion_virt->low & IOAT_LOW_COMPLETION_MASK;
1108 #endif
1109
1110         if ((ioat_chan->completion_virt->full
1111                 & IOAT_CHANSTS_DMA_TRANSFER_STATUS) ==
1112                                 IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED) {
1113                 dev_err(&ioat_chan->device->pdev->dev,
1114                         "Channel halted, chanerr = %x\n",
1115                         readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET));
1116
1117                 /* TODO do something to salvage the situation */
1118         }
1119
1120         if (phys_complete == ioat_chan->last_completion) {
1121                 spin_unlock_bh(&ioat_chan->cleanup_lock);
1122                 /*
1123                  * perhaps we're stuck so hard that the watchdog can't go off?
1124                  * try to catch it after 2 seconds
1125                  */
1126                 if (ioat_chan->device->version != IOAT_VER_3_0) {
1127                         if (time_after(jiffies,
1128                                        ioat_chan->last_completion_time + HZ*WATCHDOG_DELAY)) {
1129                                 ioat_dma_chan_watchdog(&(ioat_chan->device->work.work));
1130                                 ioat_chan->last_completion_time = jiffies;
1131                         }
1132                 }
1133                 return;
1134         }
1135         ioat_chan->last_completion_time = jiffies;
1136
1137         cookie = 0;
1138         if (!spin_trylock_bh(&ioat_chan->desc_lock)) {
1139                 spin_unlock_bh(&ioat_chan->cleanup_lock);
1140                 return;
1141         }
1142
1143         switch (ioat_chan->device->version) {
1144         case IOAT_VER_1_2:
1145                 list_for_each_entry_safe(desc, _desc,
1146                                          &ioat_chan->used_desc, node) {
1147
1148                         /*
1149                          * Incoming DMA requests may use multiple descriptors,
1150                          * due to exceeding xfercap, perhaps. If so, only the
1151                          * last one will have a cookie, and require unmapping.
1152                          */
1153                         if (desc->async_tx.cookie) {
1154                                 cookie = desc->async_tx.cookie;
1155                                 ioat_dma_unmap(ioat_chan, desc);
1156                                 if (desc->async_tx.callback) {
1157                                         desc->async_tx.callback(desc->async_tx.callback_param);
1158                                         desc->async_tx.callback = NULL;
1159                                 }
1160                         }
1161
1162                         if (desc->async_tx.phys != phys_complete) {
1163                                 /*
1164                                  * a completed entry, but not the last, so clean
1165                                  * up if the client is done with the descriptor
1166                                  */
1167                                 if (async_tx_test_ack(&desc->async_tx)) {
1168                                         list_move_tail(&desc->node,
1169                                                        &ioat_chan->free_desc);
1170                                 } else
1171                                         desc->async_tx.cookie = 0;
1172                         } else {
1173                                 /*
1174                                  * last used desc. Do not remove, so we can
1175                                  * append from it, but don't look at it next
1176                                  * time, either
1177                                  */
1178                                 desc->async_tx.cookie = 0;
1179
1180                                 /* TODO check status bits? */
1181                                 break;
1182                         }
1183                 }
1184                 break;
1185         case IOAT_VER_2_0:
1186         case IOAT_VER_3_0:
1187                 /* has some other thread has already cleaned up? */
1188                 if (ioat_chan->used_desc.prev == NULL)
1189                         break;
1190
1191                 /* work backwards to find latest finished desc */
1192                 desc = to_ioat_desc(ioat_chan->used_desc.next);
1193                 latest_desc = NULL;
1194                 do {
1195                         desc = to_ioat_desc(desc->node.prev);
1196                         desc_phys = (unsigned long)desc->async_tx.phys
1197                                        & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
1198                         if (desc_phys == phys_complete) {
1199                                 latest_desc = desc;
1200                                 break;
1201                         }
1202                 } while (&desc->node != ioat_chan->used_desc.prev);
1203
1204                 if (latest_desc != NULL) {
1205
1206                         /* work forwards to clear finished descriptors */
1207                         for (desc = to_ioat_desc(ioat_chan->used_desc.prev);
1208                              &desc->node != latest_desc->node.next &&
1209                              &desc->node != ioat_chan->used_desc.next;
1210                              desc = to_ioat_desc(desc->node.next)) {
1211                                 if (desc->async_tx.cookie) {
1212                                         cookie = desc->async_tx.cookie;
1213                                         desc->async_tx.cookie = 0;
1214                                         ioat_dma_unmap(ioat_chan, desc);
1215                                         if (desc->async_tx.callback) {
1216                                                 desc->async_tx.callback(desc->async_tx.callback_param);
1217                                                 desc->async_tx.callback = NULL;
1218                                         }
1219                                 }
1220                         }
1221
1222                         /* move used.prev up beyond those that are finished */
1223                         if (&desc->node == ioat_chan->used_desc.next)
1224                                 ioat_chan->used_desc.prev = NULL;
1225                         else
1226                                 ioat_chan->used_desc.prev = &desc->node;
1227                 }
1228                 break;
1229         }
1230
1231         spin_unlock_bh(&ioat_chan->desc_lock);
1232
1233         ioat_chan->last_completion = phys_complete;
1234         if (cookie != 0)
1235                 ioat_chan->completed_cookie = cookie;
1236
1237         spin_unlock_bh(&ioat_chan->cleanup_lock);
1238 }
1239
1240 /**
1241  * ioat_dma_is_complete - poll the status of a IOAT DMA transaction
1242  * @chan: IOAT DMA channel handle
1243  * @cookie: DMA transaction identifier
1244  * @done: if not %NULL, updated with last completed transaction
1245  * @used: if not %NULL, updated with last used transaction
1246  */
1247 static enum dma_status ioat_dma_is_complete(struct dma_chan *chan,
1248                                             dma_cookie_t cookie,
1249                                             dma_cookie_t *done,
1250                                             dma_cookie_t *used)
1251 {
1252         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
1253         dma_cookie_t last_used;
1254         dma_cookie_t last_complete;
1255         enum dma_status ret;
1256
1257         last_used = chan->cookie;
1258         last_complete = ioat_chan->completed_cookie;
1259         ioat_chan->watchdog_tcp_cookie = cookie;
1260
1261         if (done)
1262                 *done = last_complete;
1263         if (used)
1264                 *used = last_used;
1265
1266         ret = dma_async_is_complete(cookie, last_complete, last_used);
1267         if (ret == DMA_SUCCESS)
1268                 return ret;
1269
1270         ioat_dma_memcpy_cleanup(ioat_chan);
1271
1272         last_used = chan->cookie;
1273         last_complete = ioat_chan->completed_cookie;
1274
1275         if (done)
1276                 *done = last_complete;
1277         if (used)
1278                 *used = last_used;
1279
1280         return dma_async_is_complete(cookie, last_complete, last_used);
1281 }
1282
1283 static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan)
1284 {
1285         struct ioat_desc_sw *desc;
1286
1287         spin_lock_bh(&ioat_chan->desc_lock);
1288
1289         desc = ioat_dma_get_next_descriptor(ioat_chan);
1290
1291         if (!desc) {
1292                 dev_err(&ioat_chan->device->pdev->dev,
1293                         "Unable to start null desc - get next desc failed\n");
1294                 spin_unlock_bh(&ioat_chan->desc_lock);
1295                 return;
1296         }
1297
1298         desc->hw->ctl = IOAT_DMA_DESCRIPTOR_NUL
1299                                 | IOAT_DMA_DESCRIPTOR_CTL_INT_GN
1300                                 | IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
1301         /* set size to non-zero value (channel returns error when size is 0) */
1302         desc->hw->size = NULL_DESC_BUFFER_SIZE;
1303         desc->hw->src_addr = 0;
1304         desc->hw->dst_addr = 0;
1305         async_tx_ack(&desc->async_tx);
1306         switch (ioat_chan->device->version) {
1307         case IOAT_VER_1_2:
1308                 desc->hw->next = 0;
1309                 list_add_tail(&desc->node, &ioat_chan->used_desc);
1310
1311                 writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
1312                        ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
1313                 writel(((u64) desc->async_tx.phys) >> 32,
1314                        ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
1315
1316                 writeb(IOAT_CHANCMD_START, ioat_chan->reg_base
1317                         + IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
1318                 break;
1319         case IOAT_VER_2_0:
1320         case IOAT_VER_3_0:
1321                 writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
1322                        ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
1323                 writel(((u64) desc->async_tx.phys) >> 32,
1324                        ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
1325
1326                 ioat_chan->dmacount++;
1327                 __ioat2_dma_memcpy_issue_pending(ioat_chan);
1328                 break;
1329         }
1330         spin_unlock_bh(&ioat_chan->desc_lock);
1331 }
1332
1333 /*
1334  * Perform a IOAT transaction to verify the HW works.
1335  */
1336 #define IOAT_TEST_SIZE 2000
1337
1338 static void ioat_dma_test_callback(void *dma_async_param)
1339 {
1340         struct completion *cmp = dma_async_param;
1341
1342         complete(cmp);
1343 }
1344
1345 /**
1346  * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
1347  * @device: device to be tested
1348  */
1349 static int ioat_dma_self_test(struct ioatdma_device *device)
1350 {
1351         int i;
1352         u8 *src;
1353         u8 *dest;
1354         struct dma_chan *dma_chan;
1355         struct dma_async_tx_descriptor *tx;
1356         dma_addr_t dma_dest, dma_src;
1357         dma_cookie_t cookie;
1358         int err = 0;
1359         struct completion cmp;
1360         unsigned long tmo;
1361         unsigned long flags;
1362
1363         src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
1364         if (!src)
1365                 return -ENOMEM;
1366         dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
1367         if (!dest) {
1368                 kfree(src);
1369                 return -ENOMEM;
1370         }
1371
1372         /* Fill in src buffer */
1373         for (i = 0; i < IOAT_TEST_SIZE; i++)
1374                 src[i] = (u8)i;
1375
1376         /* Start copy, using first DMA channel */
1377         dma_chan = container_of(device->common.channels.next,
1378                                 struct dma_chan,
1379                                 device_node);
1380         if (device->common.device_alloc_chan_resources(dma_chan) < 1) {
1381                 dev_err(&device->pdev->dev,
1382                         "selftest cannot allocate chan resource\n");
1383                 err = -ENODEV;
1384                 goto out;
1385         }
1386
1387         dma_src = dma_map_single(dma_chan->device->dev, src, IOAT_TEST_SIZE,
1388                                  DMA_TO_DEVICE);
1389         dma_dest = dma_map_single(dma_chan->device->dev, dest, IOAT_TEST_SIZE,
1390                                   DMA_FROM_DEVICE);
1391         flags = DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_DEST_UNMAP_SINGLE;
1392         tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src,
1393                                                    IOAT_TEST_SIZE, flags);
1394         if (!tx) {
1395                 dev_err(&device->pdev->dev,
1396                         "Self-test prep failed, disabling\n");
1397                 err = -ENODEV;
1398                 goto free_resources;
1399         }
1400
1401         async_tx_ack(tx);
1402         init_completion(&cmp);
1403         tx->callback = ioat_dma_test_callback;
1404         tx->callback_param = &cmp;
1405         cookie = tx->tx_submit(tx);
1406         if (cookie < 0) {
1407                 dev_err(&device->pdev->dev,
1408                         "Self-test setup failed, disabling\n");
1409                 err = -ENODEV;
1410                 goto free_resources;
1411         }
1412         device->common.device_issue_pending(dma_chan);
1413
1414         tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
1415
1416         if (tmo == 0 ||
1417             device->common.device_is_tx_complete(dma_chan, cookie, NULL, NULL)
1418                                         != DMA_SUCCESS) {
1419                 dev_err(&device->pdev->dev,
1420                         "Self-test copy timed out, disabling\n");
1421                 err = -ENODEV;
1422                 goto free_resources;
1423         }
1424         if (memcmp(src, dest, IOAT_TEST_SIZE)) {
1425                 dev_err(&device->pdev->dev,
1426                         "Self-test copy failed compare, disabling\n");
1427                 err = -ENODEV;
1428                 goto free_resources;
1429         }
1430
1431 free_resources:
1432         device->common.device_free_chan_resources(dma_chan);
1433 out:
1434         kfree(src);
1435         kfree(dest);
1436         return err;
1437 }
1438
1439 static char ioat_interrupt_style[32] = "msix";
1440 module_param_string(ioat_interrupt_style, ioat_interrupt_style,
1441                     sizeof(ioat_interrupt_style), 0644);
1442 MODULE_PARM_DESC(ioat_interrupt_style,
1443                  "set ioat interrupt style: msix (default), "
1444                  "msix-single-vector, msi, intx)");
1445
1446 /**
1447  * ioat_dma_setup_interrupts - setup interrupt handler
1448  * @device: ioat device
1449  */
1450 static int ioat_dma_setup_interrupts(struct ioatdma_device *device)
1451 {
1452         struct ioat_dma_chan *ioat_chan;
1453         int err, i, j, msixcnt;
1454         u8 intrctrl = 0;
1455
1456         if (!strcmp(ioat_interrupt_style, "msix"))
1457                 goto msix;
1458         if (!strcmp(ioat_interrupt_style, "msix-single-vector"))
1459                 goto msix_single_vector;
1460         if (!strcmp(ioat_interrupt_style, "msi"))
1461                 goto msi;
1462         if (!strcmp(ioat_interrupt_style, "intx"))
1463                 goto intx;
1464         dev_err(&device->pdev->dev, "invalid ioat_interrupt_style %s\n",
1465                 ioat_interrupt_style);
1466         goto err_no_irq;
1467
1468 msix:
1469         /* The number of MSI-X vectors should equal the number of channels */
1470         msixcnt = device->common.chancnt;
1471         for (i = 0; i < msixcnt; i++)
1472                 device->msix_entries[i].entry = i;
1473
1474         err = pci_enable_msix(device->pdev, device->msix_entries, msixcnt);
1475         if (err < 0)
1476                 goto msi;
1477         if (err > 0)
1478                 goto msix_single_vector;
1479
1480         for (i = 0; i < msixcnt; i++) {
1481                 ioat_chan = ioat_lookup_chan_by_index(device, i);
1482                 err = request_irq(device->msix_entries[i].vector,
1483                                   ioat_dma_do_interrupt_msix,
1484                                   0, "ioat-msix", ioat_chan);
1485                 if (err) {
1486                         for (j = 0; j < i; j++) {
1487                                 ioat_chan =
1488                                         ioat_lookup_chan_by_index(device, j);
1489                                 free_irq(device->msix_entries[j].vector,
1490                                          ioat_chan);
1491                         }
1492                         goto msix_single_vector;
1493                 }
1494         }
1495         intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL;
1496         device->irq_mode = msix_multi_vector;
1497         goto done;
1498
1499 msix_single_vector:
1500         device->msix_entries[0].entry = 0;
1501         err = pci_enable_msix(device->pdev, device->msix_entries, 1);
1502         if (err)
1503                 goto msi;
1504
1505         err = request_irq(device->msix_entries[0].vector, ioat_dma_do_interrupt,
1506                           0, "ioat-msix", device);
1507         if (err) {
1508                 pci_disable_msix(device->pdev);
1509                 goto msi;
1510         }
1511         device->irq_mode = msix_single_vector;
1512         goto done;
1513
1514 msi:
1515         err = pci_enable_msi(device->pdev);
1516         if (err)
1517                 goto intx;
1518
1519         err = request_irq(device->pdev->irq, ioat_dma_do_interrupt,
1520                           0, "ioat-msi", device);
1521         if (err) {
1522                 pci_disable_msi(device->pdev);
1523                 goto intx;
1524         }
1525         /*
1526          * CB 1.2 devices need a bit set in configuration space to enable MSI
1527          */
1528         if (device->version == IOAT_VER_1_2) {
1529                 u32 dmactrl;
1530                 pci_read_config_dword(device->pdev,
1531                                       IOAT_PCI_DMACTRL_OFFSET, &dmactrl);
1532                 dmactrl |= IOAT_PCI_DMACTRL_MSI_EN;
1533                 pci_write_config_dword(device->pdev,
1534                                        IOAT_PCI_DMACTRL_OFFSET, dmactrl);
1535         }
1536         device->irq_mode = msi;
1537         goto done;
1538
1539 intx:
1540         err = request_irq(device->pdev->irq, ioat_dma_do_interrupt,
1541                           IRQF_SHARED, "ioat-intx", device);
1542         if (err)
1543                 goto err_no_irq;
1544         device->irq_mode = intx;
1545
1546 done:
1547         intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN;
1548         writeb(intrctrl, device->reg_base + IOAT_INTRCTRL_OFFSET);
1549         return 0;
1550
1551 err_no_irq:
1552         /* Disable all interrupt generation */
1553         writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
1554         dev_err(&device->pdev->dev, "no usable interrupts\n");
1555         device->irq_mode = none;
1556         return -1;
1557 }
1558
1559 /**
1560  * ioat_dma_remove_interrupts - remove whatever interrupts were set
1561  * @device: ioat device
1562  */
1563 static void ioat_dma_remove_interrupts(struct ioatdma_device *device)
1564 {
1565         struct ioat_dma_chan *ioat_chan;
1566         int i;
1567
1568         /* Disable all interrupt generation */
1569         writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
1570
1571         switch (device->irq_mode) {
1572         case msix_multi_vector:
1573                 for (i = 0; i < device->common.chancnt; i++) {
1574                         ioat_chan = ioat_lookup_chan_by_index(device, i);
1575                         free_irq(device->msix_entries[i].vector, ioat_chan);
1576                 }
1577                 pci_disable_msix(device->pdev);
1578                 break;
1579         case msix_single_vector:
1580                 free_irq(device->msix_entries[0].vector, device);
1581                 pci_disable_msix(device->pdev);
1582                 break;
1583         case msi:
1584                 free_irq(device->pdev->irq, device);
1585                 pci_disable_msi(device->pdev);
1586                 break;
1587         case intx:
1588                 free_irq(device->pdev->irq, device);
1589                 break;
1590         case none:
1591                 dev_warn(&device->pdev->dev,
1592                          "call to %s without interrupts setup\n", __func__);
1593         }
1594         device->irq_mode = none;
1595 }
1596
1597 struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev,
1598                                       void __iomem *iobase)
1599 {
1600         int err;
1601         struct ioatdma_device *device;
1602
1603         device = kzalloc(sizeof(*device), GFP_KERNEL);
1604         if (!device) {
1605                 err = -ENOMEM;
1606                 goto err_kzalloc;
1607         }
1608         device->pdev = pdev;
1609         device->reg_base = iobase;
1610         device->version = readb(device->reg_base + IOAT_VER_OFFSET);
1611
1612         /* DMA coherent memory pool for DMA descriptor allocations */
1613         device->dma_pool = pci_pool_create("dma_desc_pool", pdev,
1614                                            sizeof(struct ioat_dma_descriptor),
1615                                            64, 0);
1616         if (!device->dma_pool) {
1617                 err = -ENOMEM;
1618                 goto err_dma_pool;
1619         }
1620
1621         device->completion_pool = pci_pool_create("completion_pool", pdev,
1622                                                   sizeof(u64), SMP_CACHE_BYTES,
1623                                                   SMP_CACHE_BYTES);
1624         if (!device->completion_pool) {
1625                 err = -ENOMEM;
1626                 goto err_completion_pool;
1627         }
1628
1629         INIT_LIST_HEAD(&device->common.channels);
1630         ioat_dma_enumerate_channels(device);
1631
1632         device->common.device_alloc_chan_resources =
1633                                                 ioat_dma_alloc_chan_resources;
1634         device->common.device_free_chan_resources =
1635                                                 ioat_dma_free_chan_resources;
1636         device->common.dev = &pdev->dev;
1637
1638         dma_cap_set(DMA_MEMCPY, device->common.cap_mask);
1639         device->common.device_is_tx_complete = ioat_dma_is_complete;
1640         switch (device->version) {
1641         case IOAT_VER_1_2:
1642                 device->common.device_prep_dma_memcpy = ioat1_dma_prep_memcpy;
1643                 device->common.device_issue_pending =
1644                                                 ioat1_dma_memcpy_issue_pending;
1645                 break;
1646         case IOAT_VER_2_0:
1647         case IOAT_VER_3_0:
1648                 device->common.device_prep_dma_memcpy = ioat2_dma_prep_memcpy;
1649                 device->common.device_issue_pending =
1650                                                 ioat2_dma_memcpy_issue_pending;
1651                 break;
1652         }
1653
1654         dev_err(&device->pdev->dev,
1655                 "Intel(R) I/OAT DMA Engine found,"
1656                 " %d channels, device version 0x%02x, driver version %s\n",
1657                 device->common.chancnt, device->version, IOAT_DMA_VERSION);
1658
1659         if (!device->common.chancnt) {
1660                 dev_err(&device->pdev->dev,
1661                         "Intel(R) I/OAT DMA Engine problem found: "
1662                         "zero channels detected\n");
1663                 goto err_setup_interrupts;
1664         }
1665
1666         err = ioat_dma_setup_interrupts(device);
1667         if (err)
1668                 goto err_setup_interrupts;
1669
1670         err = ioat_dma_self_test(device);
1671         if (err)
1672                 goto err_self_test;
1673
1674         ioat_set_tcp_copy_break(device);
1675
1676         dma_async_device_register(&device->common);
1677
1678         if (device->version != IOAT_VER_3_0) {
1679                 INIT_DELAYED_WORK(&device->work, ioat_dma_chan_watchdog);
1680                 schedule_delayed_work(&device->work,
1681                                       WATCHDOG_DELAY);
1682         }
1683
1684         return device;
1685
1686 err_self_test:
1687         ioat_dma_remove_interrupts(device);
1688 err_setup_interrupts:
1689         pci_pool_destroy(device->completion_pool);
1690 err_completion_pool:
1691         pci_pool_destroy(device->dma_pool);
1692 err_dma_pool:
1693         kfree(device);
1694 err_kzalloc:
1695         dev_err(&pdev->dev,
1696                 "Intel(R) I/OAT DMA Engine initialization failed\n");
1697         return NULL;
1698 }
1699
1700 void ioat_dma_remove(struct ioatdma_device *device)
1701 {
1702         struct dma_chan *chan, *_chan;
1703         struct ioat_dma_chan *ioat_chan;
1704
1705         if (device->version != IOAT_VER_3_0)
1706                 cancel_delayed_work(&device->work);
1707
1708         ioat_dma_remove_interrupts(device);
1709
1710         dma_async_device_unregister(&device->common);
1711
1712         pci_pool_destroy(device->dma_pool);
1713         pci_pool_destroy(device->completion_pool);
1714
1715         iounmap(device->reg_base);
1716         pci_release_regions(device->pdev);
1717         pci_disable_device(device->pdev);
1718
1719         list_for_each_entry_safe(chan, _chan,
1720                                  &device->common.channels, device_node) {
1721                 ioat_chan = to_ioat_chan(chan);
1722                 list_del(&chan->device_node);
1723                 kfree(ioat_chan);
1724         }
1725         kfree(device);
1726 }
1727