2 * drivers/dma/imx-sdma.c
4 * This file contains a driver for the Freescale Smart DMA engine
6 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
8 * Based on code from Freescale:
10 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
12 * The code contained herein is licensed under the GNU General Public
13 * License. You may obtain a copy of the GNU General Public License
14 * Version 2 or later at the following locations:
16 * http://www.opensource.org/licenses/gpl-license.html
17 * http://www.gnu.org/copyleft/gpl.html
20 #include <linux/init.h>
21 #include <linux/types.h>
23 #include <linux/interrupt.h>
24 #include <linux/clk.h>
25 #include <linux/wait.h>
26 #include <linux/sched.h>
27 #include <linux/semaphore.h>
28 #include <linux/spinlock.h>
29 #include <linux/device.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/firmware.h>
32 #include <linux/slab.h>
33 #include <linux/platform_device.h>
34 #include <linux/dmaengine.h>
36 #include <linux/of_device.h>
39 #include <mach/sdma.h>
41 #include <mach/hardware.h>
43 #include "dmaengine.h"
46 #define SDMA_H_C0PTR 0x000
47 #define SDMA_H_INTR 0x004
48 #define SDMA_H_STATSTOP 0x008
49 #define SDMA_H_START 0x00c
50 #define SDMA_H_EVTOVR 0x010
51 #define SDMA_H_DSPOVR 0x014
52 #define SDMA_H_HOSTOVR 0x018
53 #define SDMA_H_EVTPEND 0x01c
54 #define SDMA_H_DSPENBL 0x020
55 #define SDMA_H_RESET 0x024
56 #define SDMA_H_EVTERR 0x028
57 #define SDMA_H_INTRMSK 0x02c
58 #define SDMA_H_PSW 0x030
59 #define SDMA_H_EVTERRDBG 0x034
60 #define SDMA_H_CONFIG 0x038
61 #define SDMA_ONCE_ENB 0x040
62 #define SDMA_ONCE_DATA 0x044
63 #define SDMA_ONCE_INSTR 0x048
64 #define SDMA_ONCE_STAT 0x04c
65 #define SDMA_ONCE_CMD 0x050
66 #define SDMA_EVT_MIRROR 0x054
67 #define SDMA_ILLINSTADDR 0x058
68 #define SDMA_CHN0ADDR 0x05c
69 #define SDMA_ONCE_RTB 0x060
70 #define SDMA_XTRIG_CONF1 0x070
71 #define SDMA_XTRIG_CONF2 0x074
72 #define SDMA_CHNENBL0_IMX35 0x200
73 #define SDMA_CHNENBL0_IMX31 0x080
74 #define SDMA_CHNPRI_0 0x100
77 * Buffer descriptor status values.
88 * Data Node descriptor status values.
90 #define DND_END_OF_FRAME 0x80
91 #define DND_END_OF_XFER 0x40
93 #define DND_UNUSED 0x01
96 * IPCV2 descriptor status values.
98 #define BD_IPCV2_END_OF_FRAME 0x40
100 #define IPCV2_MAX_NODES 50
102 * Error bit set in the CCB status field by the SDMA,
103 * in setbd routine, in case of a transfer error
105 #define DATA_ERROR 0x10000000
108 * Buffer descriptor commands.
113 #define C0_SETCTX 0x07
114 #define C0_GETCTX 0x03
115 #define C0_SETDM 0x01
116 #define C0_SETPM 0x04
117 #define C0_GETDM 0x02
118 #define C0_GETPM 0x08
120 * Change endianness indicator in the BD command field
122 #define CHANGE_ENDIANNESS 0x80
125 * Mode/Count of data node descriptors - IPCv2
127 struct sdma_mode_count {
128 u32 count : 16; /* size of the buffer pointed by this BD */
129 u32 status : 8; /* E,R,I,C,W,D status bits stored here */
130 u32 command : 8; /* command mostlky used for channel 0 */
136 struct sdma_buffer_descriptor {
137 struct sdma_mode_count mode;
138 u32 buffer_addr; /* address of the buffer described */
139 u32 ext_buffer_addr; /* extended buffer address */
140 } __attribute__ ((packed));
143 * struct sdma_channel_control - Channel control Block
145 * @current_bd_ptr current buffer descriptor processed
146 * @base_bd_ptr first element of buffer descriptor array
147 * @unused padding. The SDMA engine expects an array of 128 byte
150 struct sdma_channel_control {
154 } __attribute__ ((packed));
157 * struct sdma_state_registers - SDMA context for a channel
159 * @pc: program counter
160 * @t: test bit: status of arithmetic & test instruction
161 * @rpc: return program counter
162 * @sf: source fault while loading data
163 * @spc: loop start program counter
164 * @df: destination fault while storing data
165 * @epc: loop end program counter
168 struct sdma_state_registers {
180 } __attribute__ ((packed));
183 * struct sdma_context_data - sdma context specific to a channel
185 * @channel_state: channel state bits
186 * @gReg: general registers
187 * @mda: burst dma destination address register
188 * @msa: burst dma source address register
189 * @ms: burst dma status register
190 * @md: burst dma data register
191 * @pda: peripheral dma destination address register
192 * @psa: peripheral dma source address register
193 * @ps: peripheral dma status register
194 * @pd: peripheral dma data register
195 * @ca: CRC polynomial register
196 * @cs: CRC accumulator register
197 * @dda: dedicated core destination address register
198 * @dsa: dedicated core source address register
199 * @ds: dedicated core status register
200 * @dd: dedicated core data register
202 struct sdma_context_data {
203 struct sdma_state_registers channel_state;
227 } __attribute__ ((packed));
229 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
234 * struct sdma_channel - housekeeping for a SDMA channel
236 * @sdma pointer to the SDMA engine for this channel
237 * @channel the channel number, matches dmaengine chan_id + 1
238 * @direction transfer type. Needed for setting SDMA script
239 * @peripheral_type Peripheral type. Needed for setting SDMA script
240 * @event_id0 aka dma request line
241 * @event_id1 for channels that use 2 events
242 * @word_size peripheral access size
243 * @buf_tail ID of the buffer that was processed
244 * @done channel completion
245 * @num_bd max NUM_BD. number of descriptors currently handling
247 struct sdma_channel {
248 struct sdma_engine *sdma;
249 unsigned int channel;
250 enum dma_data_direction direction;
251 enum sdma_peripheral_type peripheral_type;
252 unsigned int event_id0;
253 unsigned int event_id1;
254 enum dma_slave_buswidth word_size;
255 unsigned int buf_tail;
256 struct completion done;
258 struct sdma_buffer_descriptor *bd;
260 unsigned int pc_from_device, pc_to_device;
262 dma_addr_t per_address;
263 u32 event_mask0, event_mask1;
265 u32 shp_addr, per_addr;
266 struct dma_chan chan;
268 struct dma_async_tx_descriptor desc;
269 enum dma_status status;
272 #define IMX_DMA_SG_LOOP (1 << 0)
274 #define MAX_DMA_CHANNELS 32
275 #define MXC_SDMA_DEFAULT_PRIORITY 1
276 #define MXC_SDMA_MIN_PRIORITY 1
277 #define MXC_SDMA_MAX_PRIORITY 7
279 #define SDMA_FIRMWARE_MAGIC 0x414d4453
282 * struct sdma_firmware_header - Layout of the firmware image
285 * @version_major increased whenever layout of struct sdma_script_start_addrs
287 * @version_minor firmware minor version (for binary compatible changes)
288 * @script_addrs_start offset of struct sdma_script_start_addrs in this image
289 * @num_script_addrs Number of script addresses in this image
290 * @ram_code_start offset of SDMA ram image in this firmware image
291 * @ram_code_size size of SDMA ram image
292 * @script_addrs Stores the start address of the SDMA scripts
293 * (in SDMA memory space)
295 struct sdma_firmware_header {
299 u32 script_addrs_start;
300 u32 num_script_addrs;
306 IMX31_SDMA, /* runs on i.mx31 */
307 IMX35_SDMA, /* runs on i.mx35 and later */
312 struct device_dma_parameters dma_parms;
313 struct sdma_channel channel[MAX_DMA_CHANNELS];
314 struct sdma_channel_control *channel_control;
316 enum sdma_devtype devtype;
317 unsigned int num_events;
318 struct sdma_context_data *context;
319 dma_addr_t context_phys;
320 struct dma_device dma_device;
322 struct sdma_script_start_addrs *script_addrs;
325 static struct platform_device_id sdma_devtypes[] = {
327 .name = "imx31-sdma",
328 .driver_data = IMX31_SDMA,
330 .name = "imx35-sdma",
331 .driver_data = IMX35_SDMA,
336 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
338 static const struct of_device_id sdma_dt_ids[] = {
339 { .compatible = "fsl,imx31-sdma", .data = &sdma_devtypes[IMX31_SDMA], },
340 { .compatible = "fsl,imx35-sdma", .data = &sdma_devtypes[IMX35_SDMA], },
343 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
345 #define SDMA_H_CONFIG_DSPDMA (1 << 12) /* indicates if the DSPDMA is used */
346 #define SDMA_H_CONFIG_RTD_PINS (1 << 11) /* indicates if Real-Time Debug pins are enabled */
347 #define SDMA_H_CONFIG_ACR (1 << 4) /* indicates if AHB freq /core freq = 2 or 1 */
348 #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/
350 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
352 u32 chnenbl0 = (sdma->devtype == IMX31_SDMA ? SDMA_CHNENBL0_IMX31 :
353 SDMA_CHNENBL0_IMX35);
354 return chnenbl0 + event * 4;
357 static int sdma_config_ownership(struct sdma_channel *sdmac,
358 bool event_override, bool mcu_override, bool dsp_override)
360 struct sdma_engine *sdma = sdmac->sdma;
361 int channel = sdmac->channel;
364 if (event_override && mcu_override && dsp_override)
367 evt = __raw_readl(sdma->regs + SDMA_H_EVTOVR);
368 mcu = __raw_readl(sdma->regs + SDMA_H_HOSTOVR);
369 dsp = __raw_readl(sdma->regs + SDMA_H_DSPOVR);
372 dsp &= ~(1 << channel);
374 dsp |= (1 << channel);
377 evt &= ~(1 << channel);
379 evt |= (1 << channel);
382 mcu &= ~(1 << channel);
384 mcu |= (1 << channel);
386 __raw_writel(evt, sdma->regs + SDMA_H_EVTOVR);
387 __raw_writel(mcu, sdma->regs + SDMA_H_HOSTOVR);
388 __raw_writel(dsp, sdma->regs + SDMA_H_DSPOVR);
394 * sdma_run_channel - run a channel and wait till it's done
396 static int sdma_run_channel(struct sdma_channel *sdmac)
398 struct sdma_engine *sdma = sdmac->sdma;
399 int channel = sdmac->channel;
402 init_completion(&sdmac->done);
404 __raw_writel(1 << channel, sdma->regs + SDMA_H_START);
406 ret = wait_for_completion_timeout(&sdmac->done, HZ);
408 return ret ? 0 : -ETIMEDOUT;
411 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
414 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
419 buf_virt = dma_alloc_coherent(NULL,
421 &buf_phys, GFP_KERNEL);
425 bd0->mode.command = C0_SETPM;
426 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
427 bd0->mode.count = size / 2;
428 bd0->buffer_addr = buf_phys;
429 bd0->ext_buffer_addr = address;
431 memcpy(buf_virt, buf, size);
433 ret = sdma_run_channel(&sdma->channel[0]);
435 dma_free_coherent(NULL, size, buf_virt, buf_phys);
440 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
442 struct sdma_engine *sdma = sdmac->sdma;
443 int channel = sdmac->channel;
445 u32 chnenbl = chnenbl_ofs(sdma, event);
447 val = __raw_readl(sdma->regs + chnenbl);
448 val |= (1 << channel);
449 __raw_writel(val, sdma->regs + chnenbl);
452 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
454 struct sdma_engine *sdma = sdmac->sdma;
455 int channel = sdmac->channel;
456 u32 chnenbl = chnenbl_ofs(sdma, event);
459 val = __raw_readl(sdma->regs + chnenbl);
460 val &= ~(1 << channel);
461 __raw_writel(val, sdma->regs + chnenbl);
464 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
466 struct sdma_buffer_descriptor *bd;
469 * loop mode. Iterate over descriptors, re-setup them and
470 * call callback function.
473 bd = &sdmac->bd[sdmac->buf_tail];
475 if (bd->mode.status & BD_DONE)
478 if (bd->mode.status & BD_RROR)
479 sdmac->status = DMA_ERROR;
481 sdmac->status = DMA_IN_PROGRESS;
483 bd->mode.status |= BD_DONE;
485 sdmac->buf_tail %= sdmac->num_bd;
487 if (sdmac->desc.callback)
488 sdmac->desc.callback(sdmac->desc.callback_param);
492 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
494 struct sdma_buffer_descriptor *bd;
498 * non loop mode. Iterate over all descriptors, collect
499 * errors and call callback function
501 for (i = 0; i < sdmac->num_bd; i++) {
504 if (bd->mode.status & (BD_DONE | BD_RROR))
509 sdmac->status = DMA_ERROR;
511 sdmac->status = DMA_SUCCESS;
513 dma_cookie_complete(&sdmac->desc);
514 if (sdmac->desc.callback)
515 sdmac->desc.callback(sdmac->desc.callback_param);
516 sdmac->last_completed = sdmac->desc.cookie;
519 static void mxc_sdma_handle_channel(struct sdma_channel *sdmac)
521 complete(&sdmac->done);
523 /* not interested in channel 0 interrupts */
524 if (sdmac->channel == 0)
527 if (sdmac->flags & IMX_DMA_SG_LOOP)
528 sdma_handle_channel_loop(sdmac);
530 mxc_sdma_handle_channel_normal(sdmac);
533 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
535 struct sdma_engine *sdma = dev_id;
538 stat = __raw_readl(sdma->regs + SDMA_H_INTR);
539 __raw_writel(stat, sdma->regs + SDMA_H_INTR);
542 int channel = fls(stat) - 1;
543 struct sdma_channel *sdmac = &sdma->channel[channel];
545 mxc_sdma_handle_channel(sdmac);
547 stat &= ~(1 << channel);
554 * sets the pc of SDMA script according to the peripheral type
556 static void sdma_get_pc(struct sdma_channel *sdmac,
557 enum sdma_peripheral_type peripheral_type)
559 struct sdma_engine *sdma = sdmac->sdma;
560 int per_2_emi = 0, emi_2_per = 0;
562 * These are needed once we start to support transfers between
563 * two peripherals or memory-to-memory transfers
565 int per_2_per = 0, emi_2_emi = 0;
567 sdmac->pc_from_device = 0;
568 sdmac->pc_to_device = 0;
570 switch (peripheral_type) {
571 case IMX_DMATYPE_MEMORY:
572 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
574 case IMX_DMATYPE_DSP:
575 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
576 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
578 case IMX_DMATYPE_FIRI:
579 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
580 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
582 case IMX_DMATYPE_UART:
583 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
584 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
586 case IMX_DMATYPE_UART_SP:
587 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
588 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
590 case IMX_DMATYPE_ATA:
591 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
592 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
594 case IMX_DMATYPE_CSPI:
595 case IMX_DMATYPE_EXT:
596 case IMX_DMATYPE_SSI:
597 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
598 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
600 case IMX_DMATYPE_SSI_SP:
601 case IMX_DMATYPE_MMC:
602 case IMX_DMATYPE_SDHC:
603 case IMX_DMATYPE_CSPI_SP:
604 case IMX_DMATYPE_ESAI:
605 case IMX_DMATYPE_MSHC_SP:
606 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
607 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
609 case IMX_DMATYPE_ASRC:
610 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
611 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
612 per_2_per = sdma->script_addrs->per_2_per_addr;
614 case IMX_DMATYPE_MSHC:
615 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
616 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
618 case IMX_DMATYPE_CCM:
619 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
621 case IMX_DMATYPE_SPDIF:
622 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
623 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
625 case IMX_DMATYPE_IPU_MEMORY:
626 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
632 sdmac->pc_from_device = per_2_emi;
633 sdmac->pc_to_device = emi_2_per;
636 static int sdma_load_context(struct sdma_channel *sdmac)
638 struct sdma_engine *sdma = sdmac->sdma;
639 int channel = sdmac->channel;
641 struct sdma_context_data *context = sdma->context;
642 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
645 if (sdmac->direction == DMA_FROM_DEVICE) {
646 load_address = sdmac->pc_from_device;
648 load_address = sdmac->pc_to_device;
651 if (load_address < 0)
654 dev_dbg(sdma->dev, "load_address = %d\n", load_address);
655 dev_dbg(sdma->dev, "wml = 0x%08x\n", sdmac->watermark_level);
656 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
657 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
658 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", sdmac->event_mask0);
659 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", sdmac->event_mask1);
661 memset(context, 0, sizeof(*context));
662 context->channel_state.pc = load_address;
664 /* Send by context the event mask,base address for peripheral
665 * and watermark level
667 context->gReg[0] = sdmac->event_mask1;
668 context->gReg[1] = sdmac->event_mask0;
669 context->gReg[2] = sdmac->per_addr;
670 context->gReg[6] = sdmac->shp_addr;
671 context->gReg[7] = sdmac->watermark_level;
673 bd0->mode.command = C0_SETDM;
674 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
675 bd0->mode.count = sizeof(*context) / 4;
676 bd0->buffer_addr = sdma->context_phys;
677 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
679 ret = sdma_run_channel(&sdma->channel[0]);
684 static void sdma_disable_channel(struct sdma_channel *sdmac)
686 struct sdma_engine *sdma = sdmac->sdma;
687 int channel = sdmac->channel;
689 __raw_writel(1 << channel, sdma->regs + SDMA_H_STATSTOP);
690 sdmac->status = DMA_ERROR;
693 static int sdma_config_channel(struct sdma_channel *sdmac)
697 sdma_disable_channel(sdmac);
699 sdmac->event_mask0 = 0;
700 sdmac->event_mask1 = 0;
704 if (sdmac->event_id0) {
705 if (sdmac->event_id0 > 32)
707 sdma_event_enable(sdmac, sdmac->event_id0);
710 switch (sdmac->peripheral_type) {
711 case IMX_DMATYPE_DSP:
712 sdma_config_ownership(sdmac, false, true, true);
714 case IMX_DMATYPE_MEMORY:
715 sdma_config_ownership(sdmac, false, true, false);
718 sdma_config_ownership(sdmac, true, true, false);
722 sdma_get_pc(sdmac, sdmac->peripheral_type);
724 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
725 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
726 /* Handle multiple event channels differently */
727 if (sdmac->event_id1) {
728 sdmac->event_mask1 = 1 << (sdmac->event_id1 % 32);
729 if (sdmac->event_id1 > 31)
730 sdmac->watermark_level |= 1 << 31;
731 sdmac->event_mask0 = 1 << (sdmac->event_id0 % 32);
732 if (sdmac->event_id0 > 31)
733 sdmac->watermark_level |= 1 << 30;
735 sdmac->event_mask0 = 1 << sdmac->event_id0;
736 sdmac->event_mask1 = 1 << (sdmac->event_id0 - 32);
738 /* Watermark Level */
739 sdmac->watermark_level |= sdmac->watermark_level;
741 sdmac->shp_addr = sdmac->per_address;
743 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
746 ret = sdma_load_context(sdmac);
751 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
752 unsigned int priority)
754 struct sdma_engine *sdma = sdmac->sdma;
755 int channel = sdmac->channel;
757 if (priority < MXC_SDMA_MIN_PRIORITY
758 || priority > MXC_SDMA_MAX_PRIORITY) {
762 __raw_writel(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
767 static int sdma_request_channel(struct sdma_channel *sdmac)
769 struct sdma_engine *sdma = sdmac->sdma;
770 int channel = sdmac->channel;
773 sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL);
779 memset(sdmac->bd, 0, PAGE_SIZE);
781 sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
782 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
784 clk_enable(sdma->clk);
786 sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
788 init_completion(&sdmac->done);
798 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
800 __raw_writel(1 << channel, sdma->regs + SDMA_H_START);
803 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
805 return container_of(chan, struct sdma_channel, chan);
808 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
810 struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
811 struct sdma_engine *sdma = sdmac->sdma;
814 spin_lock_irq(&sdmac->lock);
816 cookie = dma_cookie_assign(tx);
818 sdma_enable_channel(sdma, sdmac->channel);
820 spin_unlock_irq(&sdmac->lock);
825 static int sdma_alloc_chan_resources(struct dma_chan *chan)
827 struct sdma_channel *sdmac = to_sdma_chan(chan);
828 struct imx_dma_data *data = chan->private;
834 switch (data->priority) {
838 case DMA_PRIO_MEDIUM:
847 sdmac->peripheral_type = data->peripheral_type;
848 sdmac->event_id0 = data->dma_request;
849 ret = sdma_set_channel_priority(sdmac, prio);
853 ret = sdma_request_channel(sdmac);
857 dma_async_tx_descriptor_init(&sdmac->desc, chan);
858 sdmac->desc.tx_submit = sdma_tx_submit;
859 /* txd.flags will be overwritten in prep funcs */
860 sdmac->desc.flags = DMA_CTRL_ACK;
865 static void sdma_free_chan_resources(struct dma_chan *chan)
867 struct sdma_channel *sdmac = to_sdma_chan(chan);
868 struct sdma_engine *sdma = sdmac->sdma;
870 sdma_disable_channel(sdmac);
872 if (sdmac->event_id0)
873 sdma_event_disable(sdmac, sdmac->event_id0);
874 if (sdmac->event_id1)
875 sdma_event_disable(sdmac, sdmac->event_id1);
877 sdmac->event_id0 = 0;
878 sdmac->event_id1 = 0;
880 sdma_set_channel_priority(sdmac, 0);
882 dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
884 clk_disable(sdma->clk);
887 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
888 struct dma_chan *chan, struct scatterlist *sgl,
889 unsigned int sg_len, enum dma_transfer_direction direction,
890 unsigned long flags, void *context)
892 struct sdma_channel *sdmac = to_sdma_chan(chan);
893 struct sdma_engine *sdma = sdmac->sdma;
895 int channel = sdmac->channel;
896 struct scatterlist *sg;
898 if (sdmac->status == DMA_IN_PROGRESS)
900 sdmac->status = DMA_IN_PROGRESS;
904 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
907 sdmac->direction = direction;
908 ret = sdma_load_context(sdmac);
912 if (sg_len > NUM_BD) {
913 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
914 channel, sg_len, NUM_BD);
919 for_each_sg(sgl, sg, sg_len, i) {
920 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
923 bd->buffer_addr = sg->dma_address;
927 if (count > 0xffff) {
928 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
929 channel, count, 0xffff);
934 bd->mode.count = count;
936 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
941 switch (sdmac->word_size) {
942 case DMA_SLAVE_BUSWIDTH_4_BYTES:
943 bd->mode.command = 0;
944 if (count & 3 || sg->dma_address & 3)
947 case DMA_SLAVE_BUSWIDTH_2_BYTES:
948 bd->mode.command = 2;
949 if (count & 1 || sg->dma_address & 1)
952 case DMA_SLAVE_BUSWIDTH_1_BYTE:
953 bd->mode.command = 1;
959 param = BD_DONE | BD_EXTD | BD_CONT;
961 if (i + 1 == sg_len) {
967 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
968 i, count, sg->dma_address,
969 param & BD_WRAP ? "wrap" : "",
970 param & BD_INTR ? " intr" : "");
972 bd->mode.status = param;
975 sdmac->num_bd = sg_len;
976 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
980 sdmac->status = DMA_ERROR;
984 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
985 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
986 size_t period_len, enum dma_transfer_direction direction,
989 struct sdma_channel *sdmac = to_sdma_chan(chan);
990 struct sdma_engine *sdma = sdmac->sdma;
991 int num_periods = buf_len / period_len;
992 int channel = sdmac->channel;
993 int ret, i = 0, buf = 0;
995 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
997 if (sdmac->status == DMA_IN_PROGRESS)
1000 sdmac->status = DMA_IN_PROGRESS;
1002 sdmac->flags |= IMX_DMA_SG_LOOP;
1003 sdmac->direction = direction;
1004 ret = sdma_load_context(sdmac);
1008 if (num_periods > NUM_BD) {
1009 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1010 channel, num_periods, NUM_BD);
1014 if (period_len > 0xffff) {
1015 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1016 channel, period_len, 0xffff);
1020 while (buf < buf_len) {
1021 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1024 bd->buffer_addr = dma_addr;
1026 bd->mode.count = period_len;
1028 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1030 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1031 bd->mode.command = 0;
1033 bd->mode.command = sdmac->word_size;
1035 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1036 if (i + 1 == num_periods)
1039 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
1040 i, period_len, dma_addr,
1041 param & BD_WRAP ? "wrap" : "",
1042 param & BD_INTR ? " intr" : "");
1044 bd->mode.status = param;
1046 dma_addr += period_len;
1052 sdmac->num_bd = num_periods;
1053 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1055 return &sdmac->desc;
1057 sdmac->status = DMA_ERROR;
1061 static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1064 struct sdma_channel *sdmac = to_sdma_chan(chan);
1065 struct dma_slave_config *dmaengine_cfg = (void *)arg;
1068 case DMA_TERMINATE_ALL:
1069 sdma_disable_channel(sdmac);
1071 case DMA_SLAVE_CONFIG:
1072 if (dmaengine_cfg->direction == DMA_FROM_DEVICE) {
1073 sdmac->per_address = dmaengine_cfg->src_addr;
1074 sdmac->watermark_level = dmaengine_cfg->src_maxburst;
1075 sdmac->word_size = dmaengine_cfg->src_addr_width;
1077 sdmac->per_address = dmaengine_cfg->dst_addr;
1078 sdmac->watermark_level = dmaengine_cfg->dst_maxburst;
1079 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1081 return sdma_config_channel(sdmac);
1089 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1090 dma_cookie_t cookie,
1091 struct dma_tx_state *txstate)
1093 struct sdma_channel *sdmac = to_sdma_chan(chan);
1094 dma_cookie_t last_used;
1096 last_used = chan->cookie;
1098 dma_set_tx_state(txstate, chan->completed_cookie, last_used,
1099 sdmac->chn_count - sdmac->chn_real_count);
1101 return sdmac->status;
1104 static void sdma_issue_pending(struct dma_chan *chan)
1106 struct sdma_channel *sdmac = to_sdma_chan(chan);
1107 struct sdma_engine *sdma = sdmac->sdma;
1109 if (sdmac->status == DMA_IN_PROGRESS)
1110 sdma_enable_channel(sdma, sdmac->channel);
1113 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1115 static void sdma_add_scripts(struct sdma_engine *sdma,
1116 const struct sdma_script_start_addrs *addr)
1118 s32 *addr_arr = (u32 *)addr;
1119 s32 *saddr_arr = (u32 *)sdma->script_addrs;
1122 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1123 if (addr_arr[i] > 0)
1124 saddr_arr[i] = addr_arr[i];
1127 static int __init sdma_get_firmware(struct sdma_engine *sdma,
1128 const char *fw_name)
1130 const struct firmware *fw;
1131 const struct sdma_firmware_header *header;
1133 const struct sdma_script_start_addrs *addr;
1134 unsigned short *ram_code;
1136 ret = request_firmware(&fw, fw_name, sdma->dev);
1140 if (fw->size < sizeof(*header))
1143 header = (struct sdma_firmware_header *)fw->data;
1145 if (header->magic != SDMA_FIRMWARE_MAGIC)
1147 if (header->ram_code_start + header->ram_code_size > fw->size)
1150 addr = (void *)header + header->script_addrs_start;
1151 ram_code = (void *)header + header->ram_code_start;
1153 clk_enable(sdma->clk);
1154 /* download the RAM image for SDMA */
1155 sdma_load_script(sdma, ram_code,
1156 header->ram_code_size,
1157 addr->ram_code_start_addr);
1158 clk_disable(sdma->clk);
1160 sdma_add_scripts(sdma, addr);
1162 dev_info(sdma->dev, "loaded firmware %d.%d\n",
1163 header->version_major,
1164 header->version_minor);
1167 release_firmware(fw);
1172 static int __init sdma_init(struct sdma_engine *sdma)
1175 dma_addr_t ccb_phys;
1177 switch (sdma->devtype) {
1179 sdma->num_events = 32;
1182 sdma->num_events = 48;
1185 dev_err(sdma->dev, "Unknown sdma type %d. aborting\n",
1190 clk_enable(sdma->clk);
1192 /* Be sure SDMA has not started yet */
1193 __raw_writel(0, sdma->regs + SDMA_H_C0PTR);
1195 sdma->channel_control = dma_alloc_coherent(NULL,
1196 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1197 sizeof(struct sdma_context_data),
1198 &ccb_phys, GFP_KERNEL);
1200 if (!sdma->channel_control) {
1205 sdma->context = (void *)sdma->channel_control +
1206 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1207 sdma->context_phys = ccb_phys +
1208 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1210 /* Zero-out the CCB structures array just allocated */
1211 memset(sdma->channel_control, 0,
1212 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1214 /* disable all channels */
1215 for (i = 0; i < sdma->num_events; i++)
1216 __raw_writel(0, sdma->regs + chnenbl_ofs(sdma, i));
1218 /* All channels have priority 0 */
1219 for (i = 0; i < MAX_DMA_CHANNELS; i++)
1220 __raw_writel(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1222 ret = sdma_request_channel(&sdma->channel[0]);
1226 sdma_config_ownership(&sdma->channel[0], false, true, false);
1228 /* Set Command Channel (Channel Zero) */
1229 __raw_writel(0x4050, sdma->regs + SDMA_CHN0ADDR);
1231 /* Set bits of CONFIG register but with static context switching */
1232 /* FIXME: Check whether to set ACR bit depending on clock ratios */
1233 __raw_writel(0, sdma->regs + SDMA_H_CONFIG);
1235 __raw_writel(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1237 /* Set bits of CONFIG register with given context switching mode */
1238 __raw_writel(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
1240 /* Initializes channel's priorities */
1241 sdma_set_channel_priority(&sdma->channel[0], 7);
1243 clk_disable(sdma->clk);
1248 clk_disable(sdma->clk);
1249 dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1253 static int __init sdma_probe(struct platform_device *pdev)
1255 const struct of_device_id *of_id =
1256 of_match_device(sdma_dt_ids, &pdev->dev);
1257 struct device_node *np = pdev->dev.of_node;
1258 const char *fw_name;
1261 struct resource *iores;
1262 struct sdma_platform_data *pdata = pdev->dev.platform_data;
1264 struct sdma_engine *sdma;
1266 sdma = kzalloc(sizeof(*sdma), GFP_KERNEL);
1270 sdma->dev = &pdev->dev;
1272 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1273 irq = platform_get_irq(pdev, 0);
1274 if (!iores || irq < 0) {
1279 if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) {
1281 goto err_request_region;
1284 sdma->clk = clk_get(&pdev->dev, NULL);
1285 if (IS_ERR(sdma->clk)) {
1286 ret = PTR_ERR(sdma->clk);
1290 sdma->regs = ioremap(iores->start, resource_size(iores));
1296 ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma);
1298 goto err_request_irq;
1300 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1301 if (!sdma->script_addrs) {
1307 pdev->id_entry = of_id->data;
1308 sdma->devtype = pdev->id_entry->driver_data;
1310 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1311 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1313 INIT_LIST_HEAD(&sdma->dma_device.channels);
1314 /* Initialize channel parameters */
1315 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1316 struct sdma_channel *sdmac = &sdma->channel[i];
1319 spin_lock_init(&sdmac->lock);
1321 sdmac->chan.device = &sdma->dma_device;
1325 * Add the channel to the DMAC list. Do not add channel 0 though
1326 * because we need it internally in the SDMA driver. This also means
1327 * that channel 0 in dmaengine counting matches sdma channel 1.
1330 list_add_tail(&sdmac->chan.device_node,
1331 &sdma->dma_device.channels);
1334 ret = sdma_init(sdma);
1338 if (pdata && pdata->script_addrs)
1339 sdma_add_scripts(sdma, pdata->script_addrs);
1342 sdma_get_firmware(sdma, pdata->fw_name);
1345 * Because that device tree does not encode ROM script address,
1346 * the RAM script in firmware is mandatory for device tree
1347 * probe, otherwise it fails.
1349 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1352 dev_err(&pdev->dev, "failed to get firmware name\n");
1356 ret = sdma_get_firmware(sdma, fw_name);
1358 dev_err(&pdev->dev, "failed to get firmware\n");
1363 sdma->dma_device.dev = &pdev->dev;
1365 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1366 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1367 sdma->dma_device.device_tx_status = sdma_tx_status;
1368 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1369 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1370 sdma->dma_device.device_control = sdma_control;
1371 sdma->dma_device.device_issue_pending = sdma_issue_pending;
1372 sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1373 dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1375 ret = dma_async_device_register(&sdma->dma_device);
1377 dev_err(&pdev->dev, "unable to register\n");
1381 dev_info(sdma->dev, "initialized\n");
1386 kfree(sdma->script_addrs);
1388 free_irq(irq, sdma);
1390 iounmap(sdma->regs);
1394 release_mem_region(iores->start, resource_size(iores));
1401 static int __exit sdma_remove(struct platform_device *pdev)
1406 static struct platform_driver sdma_driver = {
1409 .of_match_table = sdma_dt_ids,
1411 .id_table = sdma_devtypes,
1412 .remove = __exit_p(sdma_remove),
1415 static int __init sdma_module_init(void)
1417 return platform_driver_probe(&sdma_driver, sdma_probe);
1419 module_init(sdma_module_init);
1421 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1422 MODULE_DESCRIPTION("i.MX SDMA driver");
1423 MODULE_LICENSE("GPL");