dmaengine/dw_dmac: Reconfigure interrupt and chan_cfg register on resume
[linux-2.6.git] / drivers / dma / imx-sdma.c
1 /*
2  * drivers/dma/imx-sdma.c
3  *
4  * This file contains a driver for the Freescale Smart DMA engine
5  *
6  * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
7  *
8  * Based on code from Freescale:
9  *
10  * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
11  *
12  * The code contained herein is licensed under the GNU General Public
13  * License. You may obtain a copy of the GNU General Public License
14  * Version 2 or later at the following locations:
15  *
16  * http://www.opensource.org/licenses/gpl-license.html
17  * http://www.gnu.org/copyleft/gpl.html
18  */
19
20 #include <linux/init.h>
21 #include <linux/types.h>
22 #include <linux/mm.h>
23 #include <linux/interrupt.h>
24 #include <linux/clk.h>
25 #include <linux/wait.h>
26 #include <linux/sched.h>
27 #include <linux/semaphore.h>
28 #include <linux/spinlock.h>
29 #include <linux/device.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/firmware.h>
32 #include <linux/slab.h>
33 #include <linux/platform_device.h>
34 #include <linux/dmaengine.h>
35 #include <linux/of.h>
36 #include <linux/of_device.h>
37
38 #include <asm/irq.h>
39 #include <mach/sdma.h>
40 #include <mach/dma.h>
41 #include <mach/hardware.h>
42
43 #include "dmaengine.h"
44
45 /* SDMA registers */
46 #define SDMA_H_C0PTR            0x000
47 #define SDMA_H_INTR             0x004
48 #define SDMA_H_STATSTOP         0x008
49 #define SDMA_H_START            0x00c
50 #define SDMA_H_EVTOVR           0x010
51 #define SDMA_H_DSPOVR           0x014
52 #define SDMA_H_HOSTOVR          0x018
53 #define SDMA_H_EVTPEND          0x01c
54 #define SDMA_H_DSPENBL          0x020
55 #define SDMA_H_RESET            0x024
56 #define SDMA_H_EVTERR           0x028
57 #define SDMA_H_INTRMSK          0x02c
58 #define SDMA_H_PSW              0x030
59 #define SDMA_H_EVTERRDBG        0x034
60 #define SDMA_H_CONFIG           0x038
61 #define SDMA_ONCE_ENB           0x040
62 #define SDMA_ONCE_DATA          0x044
63 #define SDMA_ONCE_INSTR         0x048
64 #define SDMA_ONCE_STAT          0x04c
65 #define SDMA_ONCE_CMD           0x050
66 #define SDMA_EVT_MIRROR         0x054
67 #define SDMA_ILLINSTADDR        0x058
68 #define SDMA_CHN0ADDR           0x05c
69 #define SDMA_ONCE_RTB           0x060
70 #define SDMA_XTRIG_CONF1        0x070
71 #define SDMA_XTRIG_CONF2        0x074
72 #define SDMA_CHNENBL0_IMX35     0x200
73 #define SDMA_CHNENBL0_IMX31     0x080
74 #define SDMA_CHNPRI_0           0x100
75
76 /*
77  * Buffer descriptor status values.
78  */
79 #define BD_DONE  0x01
80 #define BD_WRAP  0x02
81 #define BD_CONT  0x04
82 #define BD_INTR  0x08
83 #define BD_RROR  0x10
84 #define BD_LAST  0x20
85 #define BD_EXTD  0x80
86
87 /*
88  * Data Node descriptor status values.
89  */
90 #define DND_END_OF_FRAME  0x80
91 #define DND_END_OF_XFER   0x40
92 #define DND_DONE          0x20
93 #define DND_UNUSED        0x01
94
95 /*
96  * IPCV2 descriptor status values.
97  */
98 #define BD_IPCV2_END_OF_FRAME  0x40
99
100 #define IPCV2_MAX_NODES        50
101 /*
102  * Error bit set in the CCB status field by the SDMA,
103  * in setbd routine, in case of a transfer error
104  */
105 #define DATA_ERROR  0x10000000
106
107 /*
108  * Buffer descriptor commands.
109  */
110 #define C0_ADDR             0x01
111 #define C0_LOAD             0x02
112 #define C0_DUMP             0x03
113 #define C0_SETCTX           0x07
114 #define C0_GETCTX           0x03
115 #define C0_SETDM            0x01
116 #define C0_SETPM            0x04
117 #define C0_GETDM            0x02
118 #define C0_GETPM            0x08
119 /*
120  * Change endianness indicator in the BD command field
121  */
122 #define CHANGE_ENDIANNESS   0x80
123
124 /*
125  * Mode/Count of data node descriptors - IPCv2
126  */
127 struct sdma_mode_count {
128         u32 count   : 16; /* size of the buffer pointed by this BD */
129         u32 status  :  8; /* E,R,I,C,W,D status bits stored here */
130         u32 command :  8; /* command mostlky used for channel 0 */
131 };
132
133 /*
134  * Buffer descriptor
135  */
136 struct sdma_buffer_descriptor {
137         struct sdma_mode_count  mode;
138         u32 buffer_addr;        /* address of the buffer described */
139         u32 ext_buffer_addr;    /* extended buffer address */
140 } __attribute__ ((packed));
141
142 /**
143  * struct sdma_channel_control - Channel control Block
144  *
145  * @current_bd_ptr      current buffer descriptor processed
146  * @base_bd_ptr         first element of buffer descriptor array
147  * @unused              padding. The SDMA engine expects an array of 128 byte
148  *                      control blocks
149  */
150 struct sdma_channel_control {
151         u32 current_bd_ptr;
152         u32 base_bd_ptr;
153         u32 unused[2];
154 } __attribute__ ((packed));
155
156 /**
157  * struct sdma_state_registers - SDMA context for a channel
158  *
159  * @pc:         program counter
160  * @t:          test bit: status of arithmetic & test instruction
161  * @rpc:        return program counter
162  * @sf:         source fault while loading data
163  * @spc:        loop start program counter
164  * @df:         destination fault while storing data
165  * @epc:        loop end program counter
166  * @lm:         loop mode
167  */
168 struct sdma_state_registers {
169         u32 pc     :14;
170         u32 unused1: 1;
171         u32 t      : 1;
172         u32 rpc    :14;
173         u32 unused0: 1;
174         u32 sf     : 1;
175         u32 spc    :14;
176         u32 unused2: 1;
177         u32 df     : 1;
178         u32 epc    :14;
179         u32 lm     : 2;
180 } __attribute__ ((packed));
181
182 /**
183  * struct sdma_context_data - sdma context specific to a channel
184  *
185  * @channel_state:      channel state bits
186  * @gReg:               general registers
187  * @mda:                burst dma destination address register
188  * @msa:                burst dma source address register
189  * @ms:                 burst dma status register
190  * @md:                 burst dma data register
191  * @pda:                peripheral dma destination address register
192  * @psa:                peripheral dma source address register
193  * @ps:                 peripheral dma status register
194  * @pd:                 peripheral dma data register
195  * @ca:                 CRC polynomial register
196  * @cs:                 CRC accumulator register
197  * @dda:                dedicated core destination address register
198  * @dsa:                dedicated core source address register
199  * @ds:                 dedicated core status register
200  * @dd:                 dedicated core data register
201  */
202 struct sdma_context_data {
203         struct sdma_state_registers  channel_state;
204         u32  gReg[8];
205         u32  mda;
206         u32  msa;
207         u32  ms;
208         u32  md;
209         u32  pda;
210         u32  psa;
211         u32  ps;
212         u32  pd;
213         u32  ca;
214         u32  cs;
215         u32  dda;
216         u32  dsa;
217         u32  ds;
218         u32  dd;
219         u32  scratch0;
220         u32  scratch1;
221         u32  scratch2;
222         u32  scratch3;
223         u32  scratch4;
224         u32  scratch5;
225         u32  scratch6;
226         u32  scratch7;
227 } __attribute__ ((packed));
228
229 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
230
231 struct sdma_engine;
232
233 /**
234  * struct sdma_channel - housekeeping for a SDMA channel
235  *
236  * @sdma                pointer to the SDMA engine for this channel
237  * @channel             the channel number, matches dmaengine chan_id + 1
238  * @direction           transfer type. Needed for setting SDMA script
239  * @peripheral_type     Peripheral type. Needed for setting SDMA script
240  * @event_id0           aka dma request line
241  * @event_id1           for channels that use 2 events
242  * @word_size           peripheral access size
243  * @buf_tail            ID of the buffer that was processed
244  * @done                channel completion
245  * @num_bd              max NUM_BD. number of descriptors currently handling
246  */
247 struct sdma_channel {
248         struct sdma_engine              *sdma;
249         unsigned int                    channel;
250         enum dma_data_direction         direction;
251         enum sdma_peripheral_type       peripheral_type;
252         unsigned int                    event_id0;
253         unsigned int                    event_id1;
254         enum dma_slave_buswidth         word_size;
255         unsigned int                    buf_tail;
256         struct completion               done;
257         unsigned int                    num_bd;
258         struct sdma_buffer_descriptor   *bd;
259         dma_addr_t                      bd_phys;
260         unsigned int                    pc_from_device, pc_to_device;
261         unsigned long                   flags;
262         dma_addr_t                      per_address;
263         u32                             event_mask0, event_mask1;
264         u32                             watermark_level;
265         u32                             shp_addr, per_addr;
266         struct dma_chan                 chan;
267         spinlock_t                      lock;
268         struct dma_async_tx_descriptor  desc;
269         enum dma_status                 status;
270 };
271
272 #define IMX_DMA_SG_LOOP         (1 << 0)
273
274 #define MAX_DMA_CHANNELS 32
275 #define MXC_SDMA_DEFAULT_PRIORITY 1
276 #define MXC_SDMA_MIN_PRIORITY 1
277 #define MXC_SDMA_MAX_PRIORITY 7
278
279 #define SDMA_FIRMWARE_MAGIC 0x414d4453
280
281 /**
282  * struct sdma_firmware_header - Layout of the firmware image
283  *
284  * @magic               "SDMA"
285  * @version_major       increased whenever layout of struct sdma_script_start_addrs
286  *                      changes.
287  * @version_minor       firmware minor version (for binary compatible changes)
288  * @script_addrs_start  offset of struct sdma_script_start_addrs in this image
289  * @num_script_addrs    Number of script addresses in this image
290  * @ram_code_start      offset of SDMA ram image in this firmware image
291  * @ram_code_size       size of SDMA ram image
292  * @script_addrs        Stores the start address of the SDMA scripts
293  *                      (in SDMA memory space)
294  */
295 struct sdma_firmware_header {
296         u32     magic;
297         u32     version_major;
298         u32     version_minor;
299         u32     script_addrs_start;
300         u32     num_script_addrs;
301         u32     ram_code_start;
302         u32     ram_code_size;
303 };
304
305 enum sdma_devtype {
306         IMX31_SDMA,     /* runs on i.mx31 */
307         IMX35_SDMA,     /* runs on i.mx35 and later */
308 };
309
310 struct sdma_engine {
311         struct device                   *dev;
312         struct device_dma_parameters    dma_parms;
313         struct sdma_channel             channel[MAX_DMA_CHANNELS];
314         struct sdma_channel_control     *channel_control;
315         void __iomem                    *regs;
316         enum sdma_devtype               devtype;
317         unsigned int                    num_events;
318         struct sdma_context_data        *context;
319         dma_addr_t                      context_phys;
320         struct dma_device               dma_device;
321         struct clk                      *clk;
322         struct sdma_script_start_addrs  *script_addrs;
323 };
324
325 static struct platform_device_id sdma_devtypes[] = {
326         {
327                 .name = "imx31-sdma",
328                 .driver_data = IMX31_SDMA,
329         }, {
330                 .name = "imx35-sdma",
331                 .driver_data = IMX35_SDMA,
332         }, {
333                 /* sentinel */
334         }
335 };
336 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
337
338 static const struct of_device_id sdma_dt_ids[] = {
339         { .compatible = "fsl,imx31-sdma", .data = &sdma_devtypes[IMX31_SDMA], },
340         { .compatible = "fsl,imx35-sdma", .data = &sdma_devtypes[IMX35_SDMA], },
341         { /* sentinel */ }
342 };
343 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
344
345 #define SDMA_H_CONFIG_DSPDMA    (1 << 12) /* indicates if the DSPDMA is used */
346 #define SDMA_H_CONFIG_RTD_PINS  (1 << 11) /* indicates if Real-Time Debug pins are enabled */
347 #define SDMA_H_CONFIG_ACR       (1 << 4)  /* indicates if AHB freq /core freq = 2 or 1 */
348 #define SDMA_H_CONFIG_CSM       (3)       /* indicates which context switch mode is selected*/
349
350 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
351 {
352         u32 chnenbl0 = (sdma->devtype == IMX31_SDMA ? SDMA_CHNENBL0_IMX31 :
353                                                       SDMA_CHNENBL0_IMX35);
354         return chnenbl0 + event * 4;
355 }
356
357 static int sdma_config_ownership(struct sdma_channel *sdmac,
358                 bool event_override, bool mcu_override, bool dsp_override)
359 {
360         struct sdma_engine *sdma = sdmac->sdma;
361         int channel = sdmac->channel;
362         u32 evt, mcu, dsp;
363
364         if (event_override && mcu_override && dsp_override)
365                 return -EINVAL;
366
367         evt = __raw_readl(sdma->regs + SDMA_H_EVTOVR);
368         mcu = __raw_readl(sdma->regs + SDMA_H_HOSTOVR);
369         dsp = __raw_readl(sdma->regs + SDMA_H_DSPOVR);
370
371         if (dsp_override)
372                 dsp &= ~(1 << channel);
373         else
374                 dsp |= (1 << channel);
375
376         if (event_override)
377                 evt &= ~(1 << channel);
378         else
379                 evt |= (1 << channel);
380
381         if (mcu_override)
382                 mcu &= ~(1 << channel);
383         else
384                 mcu |= (1 << channel);
385
386         __raw_writel(evt, sdma->regs + SDMA_H_EVTOVR);
387         __raw_writel(mcu, sdma->regs + SDMA_H_HOSTOVR);
388         __raw_writel(dsp, sdma->regs + SDMA_H_DSPOVR);
389
390         return 0;
391 }
392
393 /*
394  * sdma_run_channel - run a channel and wait till it's done
395  */
396 static int sdma_run_channel(struct sdma_channel *sdmac)
397 {
398         struct sdma_engine *sdma = sdmac->sdma;
399         int channel = sdmac->channel;
400         int ret;
401
402         init_completion(&sdmac->done);
403
404         __raw_writel(1 << channel, sdma->regs + SDMA_H_START);
405
406         ret = wait_for_completion_timeout(&sdmac->done, HZ);
407
408         return ret ? 0 : -ETIMEDOUT;
409 }
410
411 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
412                 u32 address)
413 {
414         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
415         void *buf_virt;
416         dma_addr_t buf_phys;
417         int ret;
418
419         buf_virt = dma_alloc_coherent(NULL,
420                         size,
421                         &buf_phys, GFP_KERNEL);
422         if (!buf_virt)
423                 return -ENOMEM;
424
425         bd0->mode.command = C0_SETPM;
426         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
427         bd0->mode.count = size / 2;
428         bd0->buffer_addr = buf_phys;
429         bd0->ext_buffer_addr = address;
430
431         memcpy(buf_virt, buf, size);
432
433         ret = sdma_run_channel(&sdma->channel[0]);
434
435         dma_free_coherent(NULL, size, buf_virt, buf_phys);
436
437         return ret;
438 }
439
440 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
441 {
442         struct sdma_engine *sdma = sdmac->sdma;
443         int channel = sdmac->channel;
444         u32 val;
445         u32 chnenbl = chnenbl_ofs(sdma, event);
446
447         val = __raw_readl(sdma->regs + chnenbl);
448         val |= (1 << channel);
449         __raw_writel(val, sdma->regs + chnenbl);
450 }
451
452 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
453 {
454         struct sdma_engine *sdma = sdmac->sdma;
455         int channel = sdmac->channel;
456         u32 chnenbl = chnenbl_ofs(sdma, event);
457         u32 val;
458
459         val = __raw_readl(sdma->regs + chnenbl);
460         val &= ~(1 << channel);
461         __raw_writel(val, sdma->regs + chnenbl);
462 }
463
464 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
465 {
466         struct sdma_buffer_descriptor *bd;
467
468         /*
469          * loop mode. Iterate over descriptors, re-setup them and
470          * call callback function.
471          */
472         while (1) {
473                 bd = &sdmac->bd[sdmac->buf_tail];
474
475                 if (bd->mode.status & BD_DONE)
476                         break;
477
478                 if (bd->mode.status & BD_RROR)
479                         sdmac->status = DMA_ERROR;
480                 else
481                         sdmac->status = DMA_IN_PROGRESS;
482
483                 bd->mode.status |= BD_DONE;
484                 sdmac->buf_tail++;
485                 sdmac->buf_tail %= sdmac->num_bd;
486
487                 if (sdmac->desc.callback)
488                         sdmac->desc.callback(sdmac->desc.callback_param);
489         }
490 }
491
492 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
493 {
494         struct sdma_buffer_descriptor *bd;
495         int i, error = 0;
496
497         /*
498          * non loop mode. Iterate over all descriptors, collect
499          * errors and call callback function
500          */
501         for (i = 0; i < sdmac->num_bd; i++) {
502                 bd = &sdmac->bd[i];
503
504                  if (bd->mode.status & (BD_DONE | BD_RROR))
505                         error = -EIO;
506         }
507
508         if (error)
509                 sdmac->status = DMA_ERROR;
510         else
511                 sdmac->status = DMA_SUCCESS;
512
513         dma_cookie_complete(&sdmac->desc);
514         if (sdmac->desc.callback)
515                 sdmac->desc.callback(sdmac->desc.callback_param);
516         sdmac->last_completed = sdmac->desc.cookie;
517 }
518
519 static void mxc_sdma_handle_channel(struct sdma_channel *sdmac)
520 {
521         complete(&sdmac->done);
522
523         /* not interested in channel 0 interrupts */
524         if (sdmac->channel == 0)
525                 return;
526
527         if (sdmac->flags & IMX_DMA_SG_LOOP)
528                 sdma_handle_channel_loop(sdmac);
529         else
530                 mxc_sdma_handle_channel_normal(sdmac);
531 }
532
533 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
534 {
535         struct sdma_engine *sdma = dev_id;
536         u32 stat;
537
538         stat = __raw_readl(sdma->regs + SDMA_H_INTR);
539         __raw_writel(stat, sdma->regs + SDMA_H_INTR);
540
541         while (stat) {
542                 int channel = fls(stat) - 1;
543                 struct sdma_channel *sdmac = &sdma->channel[channel];
544
545                 mxc_sdma_handle_channel(sdmac);
546
547                 stat &= ~(1 << channel);
548         }
549
550         return IRQ_HANDLED;
551 }
552
553 /*
554  * sets the pc of SDMA script according to the peripheral type
555  */
556 static void sdma_get_pc(struct sdma_channel *sdmac,
557                 enum sdma_peripheral_type peripheral_type)
558 {
559         struct sdma_engine *sdma = sdmac->sdma;
560         int per_2_emi = 0, emi_2_per = 0;
561         /*
562          * These are needed once we start to support transfers between
563          * two peripherals or memory-to-memory transfers
564          */
565         int per_2_per = 0, emi_2_emi = 0;
566
567         sdmac->pc_from_device = 0;
568         sdmac->pc_to_device = 0;
569
570         switch (peripheral_type) {
571         case IMX_DMATYPE_MEMORY:
572                 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
573                 break;
574         case IMX_DMATYPE_DSP:
575                 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
576                 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
577                 break;
578         case IMX_DMATYPE_FIRI:
579                 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
580                 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
581                 break;
582         case IMX_DMATYPE_UART:
583                 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
584                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
585                 break;
586         case IMX_DMATYPE_UART_SP:
587                 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
588                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
589                 break;
590         case IMX_DMATYPE_ATA:
591                 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
592                 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
593                 break;
594         case IMX_DMATYPE_CSPI:
595         case IMX_DMATYPE_EXT:
596         case IMX_DMATYPE_SSI:
597                 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
598                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
599                 break;
600         case IMX_DMATYPE_SSI_SP:
601         case IMX_DMATYPE_MMC:
602         case IMX_DMATYPE_SDHC:
603         case IMX_DMATYPE_CSPI_SP:
604         case IMX_DMATYPE_ESAI:
605         case IMX_DMATYPE_MSHC_SP:
606                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
607                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
608                 break;
609         case IMX_DMATYPE_ASRC:
610                 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
611                 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
612                 per_2_per = sdma->script_addrs->per_2_per_addr;
613                 break;
614         case IMX_DMATYPE_MSHC:
615                 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
616                 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
617                 break;
618         case IMX_DMATYPE_CCM:
619                 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
620                 break;
621         case IMX_DMATYPE_SPDIF:
622                 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
623                 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
624                 break;
625         case IMX_DMATYPE_IPU_MEMORY:
626                 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
627                 break;
628         default:
629                 break;
630         }
631
632         sdmac->pc_from_device = per_2_emi;
633         sdmac->pc_to_device = emi_2_per;
634 }
635
636 static int sdma_load_context(struct sdma_channel *sdmac)
637 {
638         struct sdma_engine *sdma = sdmac->sdma;
639         int channel = sdmac->channel;
640         int load_address;
641         struct sdma_context_data *context = sdma->context;
642         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
643         int ret;
644
645         if (sdmac->direction == DMA_FROM_DEVICE) {
646                 load_address = sdmac->pc_from_device;
647         } else {
648                 load_address = sdmac->pc_to_device;
649         }
650
651         if (load_address < 0)
652                 return load_address;
653
654         dev_dbg(sdma->dev, "load_address = %d\n", load_address);
655         dev_dbg(sdma->dev, "wml = 0x%08x\n", sdmac->watermark_level);
656         dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
657         dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
658         dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", sdmac->event_mask0);
659         dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", sdmac->event_mask1);
660
661         memset(context, 0, sizeof(*context));
662         context->channel_state.pc = load_address;
663
664         /* Send by context the event mask,base address for peripheral
665          * and watermark level
666          */
667         context->gReg[0] = sdmac->event_mask1;
668         context->gReg[1] = sdmac->event_mask0;
669         context->gReg[2] = sdmac->per_addr;
670         context->gReg[6] = sdmac->shp_addr;
671         context->gReg[7] = sdmac->watermark_level;
672
673         bd0->mode.command = C0_SETDM;
674         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
675         bd0->mode.count = sizeof(*context) / 4;
676         bd0->buffer_addr = sdma->context_phys;
677         bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
678
679         ret = sdma_run_channel(&sdma->channel[0]);
680
681         return ret;
682 }
683
684 static void sdma_disable_channel(struct sdma_channel *sdmac)
685 {
686         struct sdma_engine *sdma = sdmac->sdma;
687         int channel = sdmac->channel;
688
689         __raw_writel(1 << channel, sdma->regs + SDMA_H_STATSTOP);
690         sdmac->status = DMA_ERROR;
691 }
692
693 static int sdma_config_channel(struct sdma_channel *sdmac)
694 {
695         int ret;
696
697         sdma_disable_channel(sdmac);
698
699         sdmac->event_mask0 = 0;
700         sdmac->event_mask1 = 0;
701         sdmac->shp_addr = 0;
702         sdmac->per_addr = 0;
703
704         if (sdmac->event_id0) {
705                 if (sdmac->event_id0 > 32)
706                         return -EINVAL;
707                 sdma_event_enable(sdmac, sdmac->event_id0);
708         }
709
710         switch (sdmac->peripheral_type) {
711         case IMX_DMATYPE_DSP:
712                 sdma_config_ownership(sdmac, false, true, true);
713                 break;
714         case IMX_DMATYPE_MEMORY:
715                 sdma_config_ownership(sdmac, false, true, false);
716                 break;
717         default:
718                 sdma_config_ownership(sdmac, true, true, false);
719                 break;
720         }
721
722         sdma_get_pc(sdmac, sdmac->peripheral_type);
723
724         if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
725                         (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
726                 /* Handle multiple event channels differently */
727                 if (sdmac->event_id1) {
728                         sdmac->event_mask1 = 1 << (sdmac->event_id1 % 32);
729                         if (sdmac->event_id1 > 31)
730                                 sdmac->watermark_level |= 1 << 31;
731                         sdmac->event_mask0 = 1 << (sdmac->event_id0 % 32);
732                         if (sdmac->event_id0 > 31)
733                                 sdmac->watermark_level |= 1 << 30;
734                 } else {
735                         sdmac->event_mask0 = 1 << sdmac->event_id0;
736                         sdmac->event_mask1 = 1 << (sdmac->event_id0 - 32);
737                 }
738                 /* Watermark Level */
739                 sdmac->watermark_level |= sdmac->watermark_level;
740                 /* Address */
741                 sdmac->shp_addr = sdmac->per_address;
742         } else {
743                 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
744         }
745
746         ret = sdma_load_context(sdmac);
747
748         return ret;
749 }
750
751 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
752                 unsigned int priority)
753 {
754         struct sdma_engine *sdma = sdmac->sdma;
755         int channel = sdmac->channel;
756
757         if (priority < MXC_SDMA_MIN_PRIORITY
758             || priority > MXC_SDMA_MAX_PRIORITY) {
759                 return -EINVAL;
760         }
761
762         __raw_writel(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
763
764         return 0;
765 }
766
767 static int sdma_request_channel(struct sdma_channel *sdmac)
768 {
769         struct sdma_engine *sdma = sdmac->sdma;
770         int channel = sdmac->channel;
771         int ret = -EBUSY;
772
773         sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL);
774         if (!sdmac->bd) {
775                 ret = -ENOMEM;
776                 goto out;
777         }
778
779         memset(sdmac->bd, 0, PAGE_SIZE);
780
781         sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
782         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
783
784         clk_enable(sdma->clk);
785
786         sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
787
788         init_completion(&sdmac->done);
789
790         sdmac->buf_tail = 0;
791
792         return 0;
793 out:
794
795         return ret;
796 }
797
798 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
799 {
800         __raw_writel(1 << channel, sdma->regs + SDMA_H_START);
801 }
802
803 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
804 {
805         return container_of(chan, struct sdma_channel, chan);
806 }
807
808 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
809 {
810         struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
811         struct sdma_engine *sdma = sdmac->sdma;
812         dma_cookie_t cookie;
813
814         spin_lock_irq(&sdmac->lock);
815
816         cookie = dma_cookie_assign(tx);
817
818         sdma_enable_channel(sdma, sdmac->channel);
819
820         spin_unlock_irq(&sdmac->lock);
821
822         return cookie;
823 }
824
825 static int sdma_alloc_chan_resources(struct dma_chan *chan)
826 {
827         struct sdma_channel *sdmac = to_sdma_chan(chan);
828         struct imx_dma_data *data = chan->private;
829         int prio, ret;
830
831         if (!data)
832                 return -EINVAL;
833
834         switch (data->priority) {
835         case DMA_PRIO_HIGH:
836                 prio = 3;
837                 break;
838         case DMA_PRIO_MEDIUM:
839                 prio = 2;
840                 break;
841         case DMA_PRIO_LOW:
842         default:
843                 prio = 1;
844                 break;
845         }
846
847         sdmac->peripheral_type = data->peripheral_type;
848         sdmac->event_id0 = data->dma_request;
849         ret = sdma_set_channel_priority(sdmac, prio);
850         if (ret)
851                 return ret;
852
853         ret = sdma_request_channel(sdmac);
854         if (ret)
855                 return ret;
856
857         dma_async_tx_descriptor_init(&sdmac->desc, chan);
858         sdmac->desc.tx_submit = sdma_tx_submit;
859         /* txd.flags will be overwritten in prep funcs */
860         sdmac->desc.flags = DMA_CTRL_ACK;
861
862         return 0;
863 }
864
865 static void sdma_free_chan_resources(struct dma_chan *chan)
866 {
867         struct sdma_channel *sdmac = to_sdma_chan(chan);
868         struct sdma_engine *sdma = sdmac->sdma;
869
870         sdma_disable_channel(sdmac);
871
872         if (sdmac->event_id0)
873                 sdma_event_disable(sdmac, sdmac->event_id0);
874         if (sdmac->event_id1)
875                 sdma_event_disable(sdmac, sdmac->event_id1);
876
877         sdmac->event_id0 = 0;
878         sdmac->event_id1 = 0;
879
880         sdma_set_channel_priority(sdmac, 0);
881
882         dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
883
884         clk_disable(sdma->clk);
885 }
886
887 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
888                 struct dma_chan *chan, struct scatterlist *sgl,
889                 unsigned int sg_len, enum dma_data_direction direction,
890                 unsigned long flags)
891 {
892         struct sdma_channel *sdmac = to_sdma_chan(chan);
893         struct sdma_engine *sdma = sdmac->sdma;
894         int ret, i, count;
895         int channel = sdmac->channel;
896         struct scatterlist *sg;
897
898         if (sdmac->status == DMA_IN_PROGRESS)
899                 return NULL;
900         sdmac->status = DMA_IN_PROGRESS;
901
902         sdmac->flags = 0;
903
904         dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
905                         sg_len, channel);
906
907         sdmac->direction = direction;
908         ret = sdma_load_context(sdmac);
909         if (ret)
910                 goto err_out;
911
912         if (sg_len > NUM_BD) {
913                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
914                                 channel, sg_len, NUM_BD);
915                 ret = -EINVAL;
916                 goto err_out;
917         }
918
919         for_each_sg(sgl, sg, sg_len, i) {
920                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
921                 int param;
922
923                 bd->buffer_addr = sg->dma_address;
924
925                 count = sg->length;
926
927                 if (count > 0xffff) {
928                         dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
929                                         channel, count, 0xffff);
930                         ret = -EINVAL;
931                         goto err_out;
932                 }
933
934                 bd->mode.count = count;
935
936                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
937                         ret =  -EINVAL;
938                         goto err_out;
939                 }
940
941                 switch (sdmac->word_size) {
942                 case DMA_SLAVE_BUSWIDTH_4_BYTES:
943                         bd->mode.command = 0;
944                         if (count & 3 || sg->dma_address & 3)
945                                 return NULL;
946                         break;
947                 case DMA_SLAVE_BUSWIDTH_2_BYTES:
948                         bd->mode.command = 2;
949                         if (count & 1 || sg->dma_address & 1)
950                                 return NULL;
951                         break;
952                 case DMA_SLAVE_BUSWIDTH_1_BYTE:
953                         bd->mode.command = 1;
954                         break;
955                 default:
956                         return NULL;
957                 }
958
959                 param = BD_DONE | BD_EXTD | BD_CONT;
960
961                 if (i + 1 == sg_len) {
962                         param |= BD_INTR;
963                         param |= BD_LAST;
964                         param &= ~BD_CONT;
965                 }
966
967                 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
968                                 i, count, sg->dma_address,
969                                 param & BD_WRAP ? "wrap" : "",
970                                 param & BD_INTR ? " intr" : "");
971
972                 bd->mode.status = param;
973         }
974
975         sdmac->num_bd = sg_len;
976         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
977
978         return &sdmac->desc;
979 err_out:
980         sdmac->status = DMA_ERROR;
981         return NULL;
982 }
983
984 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
985                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
986                 size_t period_len, enum dma_data_direction direction)
987 {
988         struct sdma_channel *sdmac = to_sdma_chan(chan);
989         struct sdma_engine *sdma = sdmac->sdma;
990         int num_periods = buf_len / period_len;
991         int channel = sdmac->channel;
992         int ret, i = 0, buf = 0;
993
994         dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
995
996         if (sdmac->status == DMA_IN_PROGRESS)
997                 return NULL;
998
999         sdmac->status = DMA_IN_PROGRESS;
1000
1001         sdmac->flags |= IMX_DMA_SG_LOOP;
1002         sdmac->direction = direction;
1003         ret = sdma_load_context(sdmac);
1004         if (ret)
1005                 goto err_out;
1006
1007         if (num_periods > NUM_BD) {
1008                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1009                                 channel, num_periods, NUM_BD);
1010                 goto err_out;
1011         }
1012
1013         if (period_len > 0xffff) {
1014                 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1015                                 channel, period_len, 0xffff);
1016                 goto err_out;
1017         }
1018
1019         while (buf < buf_len) {
1020                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1021                 int param;
1022
1023                 bd->buffer_addr = dma_addr;
1024
1025                 bd->mode.count = period_len;
1026
1027                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1028                         goto err_out;
1029                 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1030                         bd->mode.command = 0;
1031                 else
1032                         bd->mode.command = sdmac->word_size;
1033
1034                 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1035                 if (i + 1 == num_periods)
1036                         param |= BD_WRAP;
1037
1038                 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
1039                                 i, period_len, dma_addr,
1040                                 param & BD_WRAP ? "wrap" : "",
1041                                 param & BD_INTR ? " intr" : "");
1042
1043                 bd->mode.status = param;
1044
1045                 dma_addr += period_len;
1046                 buf += period_len;
1047
1048                 i++;
1049         }
1050
1051         sdmac->num_bd = num_periods;
1052         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1053
1054         return &sdmac->desc;
1055 err_out:
1056         sdmac->status = DMA_ERROR;
1057         return NULL;
1058 }
1059
1060 static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1061                 unsigned long arg)
1062 {
1063         struct sdma_channel *sdmac = to_sdma_chan(chan);
1064         struct dma_slave_config *dmaengine_cfg = (void *)arg;
1065
1066         switch (cmd) {
1067         case DMA_TERMINATE_ALL:
1068                 sdma_disable_channel(sdmac);
1069                 return 0;
1070         case DMA_SLAVE_CONFIG:
1071                 if (dmaengine_cfg->direction == DMA_FROM_DEVICE) {
1072                         sdmac->per_address = dmaengine_cfg->src_addr;
1073                         sdmac->watermark_level = dmaengine_cfg->src_maxburst;
1074                         sdmac->word_size = dmaengine_cfg->src_addr_width;
1075                 } else {
1076                         sdmac->per_address = dmaengine_cfg->dst_addr;
1077                         sdmac->watermark_level = dmaengine_cfg->dst_maxburst;
1078                         sdmac->word_size = dmaengine_cfg->dst_addr_width;
1079                 }
1080                 return sdma_config_channel(sdmac);
1081         default:
1082                 return -ENOSYS;
1083         }
1084
1085         return -EINVAL;
1086 }
1087
1088 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1089                                             dma_cookie_t cookie,
1090                                             struct dma_tx_state *txstate)
1091 {
1092         struct sdma_channel *sdmac = to_sdma_chan(chan);
1093         dma_cookie_t last_used;
1094
1095         last_used = chan->cookie;
1096
1097 <<<<<<< HEAD
1098         dma_set_tx_state(txstate, sdmac->last_completed, last_used, 0);
1099 =======
1100         dma_set_tx_state(txstate, chan->completed_cookie, last_used,
1101                         sdmac->chn_count - sdmac->chn_real_count);
1102 >>>>>>> 4d4e58d... dmaengine: move last completed cookie into generic dma_chan structure
1103
1104         return sdmac->status;
1105 }
1106
1107 static void sdma_issue_pending(struct dma_chan *chan)
1108 {
1109         struct sdma_channel *sdmac = to_sdma_chan(chan);
1110         struct sdma_engine *sdma = sdmac->sdma;
1111
1112         if (sdmac->status == DMA_IN_PROGRESS)
1113                 sdma_enable_channel(sdma, sdmac->channel);
1114 }
1115
1116 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1117
1118 static void sdma_add_scripts(struct sdma_engine *sdma,
1119                 const struct sdma_script_start_addrs *addr)
1120 {
1121         s32 *addr_arr = (u32 *)addr;
1122         s32 *saddr_arr = (u32 *)sdma->script_addrs;
1123         int i;
1124
1125         for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1126                 if (addr_arr[i] > 0)
1127                         saddr_arr[i] = addr_arr[i];
1128 }
1129
1130 static int __init sdma_get_firmware(struct sdma_engine *sdma,
1131                 const char *fw_name)
1132 {
1133         const struct firmware *fw;
1134         const struct sdma_firmware_header *header;
1135         int ret;
1136         const struct sdma_script_start_addrs *addr;
1137         unsigned short *ram_code;
1138
1139         ret = request_firmware(&fw, fw_name, sdma->dev);
1140         if (ret)
1141                 return ret;
1142
1143         if (fw->size < sizeof(*header))
1144                 goto err_firmware;
1145
1146         header = (struct sdma_firmware_header *)fw->data;
1147
1148         if (header->magic != SDMA_FIRMWARE_MAGIC)
1149                 goto err_firmware;
1150         if (header->ram_code_start + header->ram_code_size > fw->size)
1151                 goto err_firmware;
1152
1153         addr = (void *)header + header->script_addrs_start;
1154         ram_code = (void *)header + header->ram_code_start;
1155
1156         clk_enable(sdma->clk);
1157         /* download the RAM image for SDMA */
1158         sdma_load_script(sdma, ram_code,
1159                         header->ram_code_size,
1160                         addr->ram_code_start_addr);
1161         clk_disable(sdma->clk);
1162
1163         sdma_add_scripts(sdma, addr);
1164
1165         dev_info(sdma->dev, "loaded firmware %d.%d\n",
1166                         header->version_major,
1167                         header->version_minor);
1168
1169 err_firmware:
1170         release_firmware(fw);
1171
1172         return ret;
1173 }
1174
1175 static int __init sdma_init(struct sdma_engine *sdma)
1176 {
1177         int i, ret;
1178         dma_addr_t ccb_phys;
1179
1180         switch (sdma->devtype) {
1181         case IMX31_SDMA:
1182                 sdma->num_events = 32;
1183                 break;
1184         case IMX35_SDMA:
1185                 sdma->num_events = 48;
1186                 break;
1187         default:
1188                 dev_err(sdma->dev, "Unknown sdma type %d. aborting\n",
1189                         sdma->devtype);
1190                 return -ENODEV;
1191         }
1192
1193         clk_enable(sdma->clk);
1194
1195         /* Be sure SDMA has not started yet */
1196         __raw_writel(0, sdma->regs + SDMA_H_C0PTR);
1197
1198         sdma->channel_control = dma_alloc_coherent(NULL,
1199                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1200                         sizeof(struct sdma_context_data),
1201                         &ccb_phys, GFP_KERNEL);
1202
1203         if (!sdma->channel_control) {
1204                 ret = -ENOMEM;
1205                 goto err_dma_alloc;
1206         }
1207
1208         sdma->context = (void *)sdma->channel_control +
1209                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1210         sdma->context_phys = ccb_phys +
1211                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1212
1213         /* Zero-out the CCB structures array just allocated */
1214         memset(sdma->channel_control, 0,
1215                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1216
1217         /* disable all channels */
1218         for (i = 0; i < sdma->num_events; i++)
1219                 __raw_writel(0, sdma->regs + chnenbl_ofs(sdma, i));
1220
1221         /* All channels have priority 0 */
1222         for (i = 0; i < MAX_DMA_CHANNELS; i++)
1223                 __raw_writel(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1224
1225         ret = sdma_request_channel(&sdma->channel[0]);
1226         if (ret)
1227                 goto err_dma_alloc;
1228
1229         sdma_config_ownership(&sdma->channel[0], false, true, false);
1230
1231         /* Set Command Channel (Channel Zero) */
1232         __raw_writel(0x4050, sdma->regs + SDMA_CHN0ADDR);
1233
1234         /* Set bits of CONFIG register but with static context switching */
1235         /* FIXME: Check whether to set ACR bit depending on clock ratios */
1236         __raw_writel(0, sdma->regs + SDMA_H_CONFIG);
1237
1238         __raw_writel(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1239
1240         /* Set bits of CONFIG register with given context switching mode */
1241         __raw_writel(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
1242
1243         /* Initializes channel's priorities */
1244         sdma_set_channel_priority(&sdma->channel[0], 7);
1245
1246         clk_disable(sdma->clk);
1247
1248         return 0;
1249
1250 err_dma_alloc:
1251         clk_disable(sdma->clk);
1252         dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1253         return ret;
1254 }
1255
1256 static int __init sdma_probe(struct platform_device *pdev)
1257 {
1258         const struct of_device_id *of_id =
1259                         of_match_device(sdma_dt_ids, &pdev->dev);
1260         struct device_node *np = pdev->dev.of_node;
1261         const char *fw_name;
1262         int ret;
1263         int irq;
1264         struct resource *iores;
1265         struct sdma_platform_data *pdata = pdev->dev.platform_data;
1266         int i;
1267         struct sdma_engine *sdma;
1268
1269         sdma = kzalloc(sizeof(*sdma), GFP_KERNEL);
1270         if (!sdma)
1271                 return -ENOMEM;
1272
1273         sdma->dev = &pdev->dev;
1274
1275         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1276         irq = platform_get_irq(pdev, 0);
1277         if (!iores || irq < 0) {
1278                 ret = -EINVAL;
1279                 goto err_irq;
1280         }
1281
1282         if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) {
1283                 ret = -EBUSY;
1284                 goto err_request_region;
1285         }
1286
1287         sdma->clk = clk_get(&pdev->dev, NULL);
1288         if (IS_ERR(sdma->clk)) {
1289                 ret = PTR_ERR(sdma->clk);
1290                 goto err_clk;
1291         }
1292
1293         sdma->regs = ioremap(iores->start, resource_size(iores));
1294         if (!sdma->regs) {
1295                 ret = -ENOMEM;
1296                 goto err_ioremap;
1297         }
1298
1299         ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma);
1300         if (ret)
1301                 goto err_request_irq;
1302
1303         sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1304         if (!sdma->script_addrs) {
1305                 ret = -ENOMEM;
1306                 goto err_alloc;
1307         }
1308
1309         if (of_id)
1310                 pdev->id_entry = of_id->data;
1311         sdma->devtype = pdev->id_entry->driver_data;
1312
1313         dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1314         dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1315
1316         INIT_LIST_HEAD(&sdma->dma_device.channels);
1317         /* Initialize channel parameters */
1318         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1319                 struct sdma_channel *sdmac = &sdma->channel[i];
1320
1321                 sdmac->sdma = sdma;
1322                 spin_lock_init(&sdmac->lock);
1323
1324                 sdmac->chan.device = &sdma->dma_device;
1325                 sdmac->channel = i;
1326
1327                 /*
1328                  * Add the channel to the DMAC list. Do not add channel 0 though
1329                  * because we need it internally in the SDMA driver. This also means
1330                  * that channel 0 in dmaengine counting matches sdma channel 1.
1331                  */
1332                 if (i)
1333                         list_add_tail(&sdmac->chan.device_node,
1334                                         &sdma->dma_device.channels);
1335         }
1336
1337         ret = sdma_init(sdma);
1338         if (ret)
1339                 goto err_init;
1340
1341         if (pdata && pdata->script_addrs)
1342                 sdma_add_scripts(sdma, pdata->script_addrs);
1343
1344         if (pdata) {
1345                 sdma_get_firmware(sdma, pdata->fw_name);
1346         } else {
1347                 /*
1348                  * Because that device tree does not encode ROM script address,
1349                  * the RAM script in firmware is mandatory for device tree
1350                  * probe, otherwise it fails.
1351                  */
1352                 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1353                                               &fw_name);
1354                 if (ret) {
1355                         dev_err(&pdev->dev, "failed to get firmware name\n");
1356                         goto err_init;
1357                 }
1358
1359                 ret = sdma_get_firmware(sdma, fw_name);
1360                 if (ret) {
1361                         dev_err(&pdev->dev, "failed to get firmware\n");
1362                         goto err_init;
1363                 }
1364         }
1365
1366         sdma->dma_device.dev = &pdev->dev;
1367
1368         sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1369         sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1370         sdma->dma_device.device_tx_status = sdma_tx_status;
1371         sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1372         sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1373         sdma->dma_device.device_control = sdma_control;
1374         sdma->dma_device.device_issue_pending = sdma_issue_pending;
1375         sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1376         dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1377
1378         ret = dma_async_device_register(&sdma->dma_device);
1379         if (ret) {
1380                 dev_err(&pdev->dev, "unable to register\n");
1381                 goto err_init;
1382         }
1383
1384         dev_info(sdma->dev, "initialized\n");
1385
1386         return 0;
1387
1388 err_init:
1389         kfree(sdma->script_addrs);
1390 err_alloc:
1391         free_irq(irq, sdma);
1392 err_request_irq:
1393         iounmap(sdma->regs);
1394 err_ioremap:
1395         clk_put(sdma->clk);
1396 err_clk:
1397         release_mem_region(iores->start, resource_size(iores));
1398 err_request_region:
1399 err_irq:
1400         kfree(sdma);
1401         return ret;
1402 }
1403
1404 static int __exit sdma_remove(struct platform_device *pdev)
1405 {
1406         return -EBUSY;
1407 }
1408
1409 static struct platform_driver sdma_driver = {
1410         .driver         = {
1411                 .name   = "imx-sdma",
1412                 .of_match_table = sdma_dt_ids,
1413         },
1414         .id_table       = sdma_devtypes,
1415         .remove         = __exit_p(sdma_remove),
1416 };
1417
1418 static int __init sdma_module_init(void)
1419 {
1420         return platform_driver_probe(&sdma_driver, sdma_probe);
1421 }
1422 module_init(sdma_module_init);
1423
1424 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1425 MODULE_DESCRIPTION("i.MX SDMA driver");
1426 MODULE_LICENSE("GPL");