Merge branch 'gpiolib' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6
[linux-2.6.git] / drivers / dma / imx-sdma.c
1 /*
2  * drivers/dma/imx-sdma.c
3  *
4  * This file contains a driver for the Freescale Smart DMA engine
5  *
6  * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
7  *
8  * Based on code from Freescale:
9  *
10  * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
11  *
12  * The code contained herein is licensed under the GNU General Public
13  * License. You may obtain a copy of the GNU General Public License
14  * Version 2 or later at the following locations:
15  *
16  * http://www.opensource.org/licenses/gpl-license.html
17  * http://www.gnu.org/copyleft/gpl.html
18  */
19
20 #include <linux/init.h>
21 #include <linux/types.h>
22 #include <linux/mm.h>
23 #include <linux/interrupt.h>
24 #include <linux/clk.h>
25 #include <linux/wait.h>
26 #include <linux/sched.h>
27 #include <linux/semaphore.h>
28 #include <linux/spinlock.h>
29 #include <linux/device.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/firmware.h>
32 #include <linux/slab.h>
33 #include <linux/platform_device.h>
34 #include <linux/dmaengine.h>
35 #include <linux/of.h>
36 #include <linux/of_device.h>
37
38 #include <asm/irq.h>
39 #include <mach/sdma.h>
40 #include <mach/dma.h>
41 #include <mach/hardware.h>
42
43 /* SDMA registers */
44 #define SDMA_H_C0PTR            0x000
45 #define SDMA_H_INTR             0x004
46 #define SDMA_H_STATSTOP         0x008
47 #define SDMA_H_START            0x00c
48 #define SDMA_H_EVTOVR           0x010
49 #define SDMA_H_DSPOVR           0x014
50 #define SDMA_H_HOSTOVR          0x018
51 #define SDMA_H_EVTPEND          0x01c
52 #define SDMA_H_DSPENBL          0x020
53 #define SDMA_H_RESET            0x024
54 #define SDMA_H_EVTERR           0x028
55 #define SDMA_H_INTRMSK          0x02c
56 #define SDMA_H_PSW              0x030
57 #define SDMA_H_EVTERRDBG        0x034
58 #define SDMA_H_CONFIG           0x038
59 #define SDMA_ONCE_ENB           0x040
60 #define SDMA_ONCE_DATA          0x044
61 #define SDMA_ONCE_INSTR         0x048
62 #define SDMA_ONCE_STAT          0x04c
63 #define SDMA_ONCE_CMD           0x050
64 #define SDMA_EVT_MIRROR         0x054
65 #define SDMA_ILLINSTADDR        0x058
66 #define SDMA_CHN0ADDR           0x05c
67 #define SDMA_ONCE_RTB           0x060
68 #define SDMA_XTRIG_CONF1        0x070
69 #define SDMA_XTRIG_CONF2        0x074
70 #define SDMA_CHNENBL0_IMX35     0x200
71 #define SDMA_CHNENBL0_IMX31     0x080
72 #define SDMA_CHNPRI_0           0x100
73
74 /*
75  * Buffer descriptor status values.
76  */
77 #define BD_DONE  0x01
78 #define BD_WRAP  0x02
79 #define BD_CONT  0x04
80 #define BD_INTR  0x08
81 #define BD_RROR  0x10
82 #define BD_LAST  0x20
83 #define BD_EXTD  0x80
84
85 /*
86  * Data Node descriptor status values.
87  */
88 #define DND_END_OF_FRAME  0x80
89 #define DND_END_OF_XFER   0x40
90 #define DND_DONE          0x20
91 #define DND_UNUSED        0x01
92
93 /*
94  * IPCV2 descriptor status values.
95  */
96 #define BD_IPCV2_END_OF_FRAME  0x40
97
98 #define IPCV2_MAX_NODES        50
99 /*
100  * Error bit set in the CCB status field by the SDMA,
101  * in setbd routine, in case of a transfer error
102  */
103 #define DATA_ERROR  0x10000000
104
105 /*
106  * Buffer descriptor commands.
107  */
108 #define C0_ADDR             0x01
109 #define C0_LOAD             0x02
110 #define C0_DUMP             0x03
111 #define C0_SETCTX           0x07
112 #define C0_GETCTX           0x03
113 #define C0_SETDM            0x01
114 #define C0_SETPM            0x04
115 #define C0_GETDM            0x02
116 #define C0_GETPM            0x08
117 /*
118  * Change endianness indicator in the BD command field
119  */
120 #define CHANGE_ENDIANNESS   0x80
121
122 /*
123  * Mode/Count of data node descriptors - IPCv2
124  */
125 struct sdma_mode_count {
126         u32 count   : 16; /* size of the buffer pointed by this BD */
127         u32 status  :  8; /* E,R,I,C,W,D status bits stored here */
128         u32 command :  8; /* command mostlky used for channel 0 */
129 };
130
131 /*
132  * Buffer descriptor
133  */
134 struct sdma_buffer_descriptor {
135         struct sdma_mode_count  mode;
136         u32 buffer_addr;        /* address of the buffer described */
137         u32 ext_buffer_addr;    /* extended buffer address */
138 } __attribute__ ((packed));
139
140 /**
141  * struct sdma_channel_control - Channel control Block
142  *
143  * @current_bd_ptr      current buffer descriptor processed
144  * @base_bd_ptr         first element of buffer descriptor array
145  * @unused              padding. The SDMA engine expects an array of 128 byte
146  *                      control blocks
147  */
148 struct sdma_channel_control {
149         u32 current_bd_ptr;
150         u32 base_bd_ptr;
151         u32 unused[2];
152 } __attribute__ ((packed));
153
154 /**
155  * struct sdma_state_registers - SDMA context for a channel
156  *
157  * @pc:         program counter
158  * @t:          test bit: status of arithmetic & test instruction
159  * @rpc:        return program counter
160  * @sf:         source fault while loading data
161  * @spc:        loop start program counter
162  * @df:         destination fault while storing data
163  * @epc:        loop end program counter
164  * @lm:         loop mode
165  */
166 struct sdma_state_registers {
167         u32 pc     :14;
168         u32 unused1: 1;
169         u32 t      : 1;
170         u32 rpc    :14;
171         u32 unused0: 1;
172         u32 sf     : 1;
173         u32 spc    :14;
174         u32 unused2: 1;
175         u32 df     : 1;
176         u32 epc    :14;
177         u32 lm     : 2;
178 } __attribute__ ((packed));
179
180 /**
181  * struct sdma_context_data - sdma context specific to a channel
182  *
183  * @channel_state:      channel state bits
184  * @gReg:               general registers
185  * @mda:                burst dma destination address register
186  * @msa:                burst dma source address register
187  * @ms:                 burst dma status register
188  * @md:                 burst dma data register
189  * @pda:                peripheral dma destination address register
190  * @psa:                peripheral dma source address register
191  * @ps:                 peripheral dma status register
192  * @pd:                 peripheral dma data register
193  * @ca:                 CRC polynomial register
194  * @cs:                 CRC accumulator register
195  * @dda:                dedicated core destination address register
196  * @dsa:                dedicated core source address register
197  * @ds:                 dedicated core status register
198  * @dd:                 dedicated core data register
199  */
200 struct sdma_context_data {
201         struct sdma_state_registers  channel_state;
202         u32  gReg[8];
203         u32  mda;
204         u32  msa;
205         u32  ms;
206         u32  md;
207         u32  pda;
208         u32  psa;
209         u32  ps;
210         u32  pd;
211         u32  ca;
212         u32  cs;
213         u32  dda;
214         u32  dsa;
215         u32  ds;
216         u32  dd;
217         u32  scratch0;
218         u32  scratch1;
219         u32  scratch2;
220         u32  scratch3;
221         u32  scratch4;
222         u32  scratch5;
223         u32  scratch6;
224         u32  scratch7;
225 } __attribute__ ((packed));
226
227 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
228
229 struct sdma_engine;
230
231 /**
232  * struct sdma_channel - housekeeping for a SDMA channel
233  *
234  * @sdma                pointer to the SDMA engine for this channel
235  * @channel             the channel number, matches dmaengine chan_id + 1
236  * @direction           transfer type. Needed for setting SDMA script
237  * @peripheral_type     Peripheral type. Needed for setting SDMA script
238  * @event_id0           aka dma request line
239  * @event_id1           for channels that use 2 events
240  * @word_size           peripheral access size
241  * @buf_tail            ID of the buffer that was processed
242  * @done                channel completion
243  * @num_bd              max NUM_BD. number of descriptors currently handling
244  */
245 struct sdma_channel {
246         struct sdma_engine              *sdma;
247         unsigned int                    channel;
248         enum dma_data_direction         direction;
249         enum sdma_peripheral_type       peripheral_type;
250         unsigned int                    event_id0;
251         unsigned int                    event_id1;
252         enum dma_slave_buswidth         word_size;
253         unsigned int                    buf_tail;
254         struct completion               done;
255         unsigned int                    num_bd;
256         struct sdma_buffer_descriptor   *bd;
257         dma_addr_t                      bd_phys;
258         unsigned int                    pc_from_device, pc_to_device;
259         unsigned long                   flags;
260         dma_addr_t                      per_address;
261         u32                             event_mask0, event_mask1;
262         u32                             watermark_level;
263         u32                             shp_addr, per_addr;
264         struct dma_chan                 chan;
265         spinlock_t                      lock;
266         struct dma_async_tx_descriptor  desc;
267         dma_cookie_t                    last_completed;
268         enum dma_status                 status;
269 };
270
271 #define IMX_DMA_SG_LOOP         (1 << 0)
272
273 #define MAX_DMA_CHANNELS 32
274 #define MXC_SDMA_DEFAULT_PRIORITY 1
275 #define MXC_SDMA_MIN_PRIORITY 1
276 #define MXC_SDMA_MAX_PRIORITY 7
277
278 #define SDMA_FIRMWARE_MAGIC 0x414d4453
279
280 /**
281  * struct sdma_firmware_header - Layout of the firmware image
282  *
283  * @magic               "SDMA"
284  * @version_major       increased whenever layout of struct sdma_script_start_addrs
285  *                      changes.
286  * @version_minor       firmware minor version (for binary compatible changes)
287  * @script_addrs_start  offset of struct sdma_script_start_addrs in this image
288  * @num_script_addrs    Number of script addresses in this image
289  * @ram_code_start      offset of SDMA ram image in this firmware image
290  * @ram_code_size       size of SDMA ram image
291  * @script_addrs        Stores the start address of the SDMA scripts
292  *                      (in SDMA memory space)
293  */
294 struct sdma_firmware_header {
295         u32     magic;
296         u32     version_major;
297         u32     version_minor;
298         u32     script_addrs_start;
299         u32     num_script_addrs;
300         u32     ram_code_start;
301         u32     ram_code_size;
302 };
303
304 enum sdma_devtype {
305         IMX31_SDMA,     /* runs on i.mx31 */
306         IMX35_SDMA,     /* runs on i.mx35 and later */
307 };
308
309 struct sdma_engine {
310         struct device                   *dev;
311         struct device_dma_parameters    dma_parms;
312         struct sdma_channel             channel[MAX_DMA_CHANNELS];
313         struct sdma_channel_control     *channel_control;
314         void __iomem                    *regs;
315         enum sdma_devtype               devtype;
316         unsigned int                    num_events;
317         struct sdma_context_data        *context;
318         dma_addr_t                      context_phys;
319         struct dma_device               dma_device;
320         struct clk                      *clk;
321         struct sdma_script_start_addrs  *script_addrs;
322 };
323
324 static struct platform_device_id sdma_devtypes[] = {
325         {
326                 .name = "imx31-sdma",
327                 .driver_data = IMX31_SDMA,
328         }, {
329                 .name = "imx35-sdma",
330                 .driver_data = IMX35_SDMA,
331         }, {
332                 /* sentinel */
333         }
334 };
335 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
336
337 static const struct of_device_id sdma_dt_ids[] = {
338         { .compatible = "fsl,imx31-sdma", .data = &sdma_devtypes[IMX31_SDMA], },
339         { .compatible = "fsl,imx35-sdma", .data = &sdma_devtypes[IMX35_SDMA], },
340         { /* sentinel */ }
341 };
342 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
343
344 #define SDMA_H_CONFIG_DSPDMA    (1 << 12) /* indicates if the DSPDMA is used */
345 #define SDMA_H_CONFIG_RTD_PINS  (1 << 11) /* indicates if Real-Time Debug pins are enabled */
346 #define SDMA_H_CONFIG_ACR       (1 << 4)  /* indicates if AHB freq /core freq = 2 or 1 */
347 #define SDMA_H_CONFIG_CSM       (3)       /* indicates which context switch mode is selected*/
348
349 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
350 {
351         u32 chnenbl0 = (sdma->devtype == IMX31_SDMA ? SDMA_CHNENBL0_IMX31 :
352                                                       SDMA_CHNENBL0_IMX35);
353         return chnenbl0 + event * 4;
354 }
355
356 static int sdma_config_ownership(struct sdma_channel *sdmac,
357                 bool event_override, bool mcu_override, bool dsp_override)
358 {
359         struct sdma_engine *sdma = sdmac->sdma;
360         int channel = sdmac->channel;
361         u32 evt, mcu, dsp;
362
363         if (event_override && mcu_override && dsp_override)
364                 return -EINVAL;
365
366         evt = __raw_readl(sdma->regs + SDMA_H_EVTOVR);
367         mcu = __raw_readl(sdma->regs + SDMA_H_HOSTOVR);
368         dsp = __raw_readl(sdma->regs + SDMA_H_DSPOVR);
369
370         if (dsp_override)
371                 dsp &= ~(1 << channel);
372         else
373                 dsp |= (1 << channel);
374
375         if (event_override)
376                 evt &= ~(1 << channel);
377         else
378                 evt |= (1 << channel);
379
380         if (mcu_override)
381                 mcu &= ~(1 << channel);
382         else
383                 mcu |= (1 << channel);
384
385         __raw_writel(evt, sdma->regs + SDMA_H_EVTOVR);
386         __raw_writel(mcu, sdma->regs + SDMA_H_HOSTOVR);
387         __raw_writel(dsp, sdma->regs + SDMA_H_DSPOVR);
388
389         return 0;
390 }
391
392 /*
393  * sdma_run_channel - run a channel and wait till it's done
394  */
395 static int sdma_run_channel(struct sdma_channel *sdmac)
396 {
397         struct sdma_engine *sdma = sdmac->sdma;
398         int channel = sdmac->channel;
399         int ret;
400
401         init_completion(&sdmac->done);
402
403         __raw_writel(1 << channel, sdma->regs + SDMA_H_START);
404
405         ret = wait_for_completion_timeout(&sdmac->done, HZ);
406
407         return ret ? 0 : -ETIMEDOUT;
408 }
409
410 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
411                 u32 address)
412 {
413         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
414         void *buf_virt;
415         dma_addr_t buf_phys;
416         int ret;
417
418         buf_virt = dma_alloc_coherent(NULL,
419                         size,
420                         &buf_phys, GFP_KERNEL);
421         if (!buf_virt)
422                 return -ENOMEM;
423
424         bd0->mode.command = C0_SETPM;
425         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
426         bd0->mode.count = size / 2;
427         bd0->buffer_addr = buf_phys;
428         bd0->ext_buffer_addr = address;
429
430         memcpy(buf_virt, buf, size);
431
432         ret = sdma_run_channel(&sdma->channel[0]);
433
434         dma_free_coherent(NULL, size, buf_virt, buf_phys);
435
436         return ret;
437 }
438
439 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
440 {
441         struct sdma_engine *sdma = sdmac->sdma;
442         int channel = sdmac->channel;
443         u32 val;
444         u32 chnenbl = chnenbl_ofs(sdma, event);
445
446         val = __raw_readl(sdma->regs + chnenbl);
447         val |= (1 << channel);
448         __raw_writel(val, sdma->regs + chnenbl);
449 }
450
451 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
452 {
453         struct sdma_engine *sdma = sdmac->sdma;
454         int channel = sdmac->channel;
455         u32 chnenbl = chnenbl_ofs(sdma, event);
456         u32 val;
457
458         val = __raw_readl(sdma->regs + chnenbl);
459         val &= ~(1 << channel);
460         __raw_writel(val, sdma->regs + chnenbl);
461 }
462
463 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
464 {
465         struct sdma_buffer_descriptor *bd;
466
467         /*
468          * loop mode. Iterate over descriptors, re-setup them and
469          * call callback function.
470          */
471         while (1) {
472                 bd = &sdmac->bd[sdmac->buf_tail];
473
474                 if (bd->mode.status & BD_DONE)
475                         break;
476
477                 if (bd->mode.status & BD_RROR)
478                         sdmac->status = DMA_ERROR;
479                 else
480                         sdmac->status = DMA_IN_PROGRESS;
481
482                 bd->mode.status |= BD_DONE;
483                 sdmac->buf_tail++;
484                 sdmac->buf_tail %= sdmac->num_bd;
485
486                 if (sdmac->desc.callback)
487                         sdmac->desc.callback(sdmac->desc.callback_param);
488         }
489 }
490
491 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
492 {
493         struct sdma_buffer_descriptor *bd;
494         int i, error = 0;
495
496         /*
497          * non loop mode. Iterate over all descriptors, collect
498          * errors and call callback function
499          */
500         for (i = 0; i < sdmac->num_bd; i++) {
501                 bd = &sdmac->bd[i];
502
503                  if (bd->mode.status & (BD_DONE | BD_RROR))
504                         error = -EIO;
505         }
506
507         if (error)
508                 sdmac->status = DMA_ERROR;
509         else
510                 sdmac->status = DMA_SUCCESS;
511
512         if (sdmac->desc.callback)
513                 sdmac->desc.callback(sdmac->desc.callback_param);
514         sdmac->last_completed = sdmac->desc.cookie;
515 }
516
517 static void mxc_sdma_handle_channel(struct sdma_channel *sdmac)
518 {
519         complete(&sdmac->done);
520
521         /* not interested in channel 0 interrupts */
522         if (sdmac->channel == 0)
523                 return;
524
525         if (sdmac->flags & IMX_DMA_SG_LOOP)
526                 sdma_handle_channel_loop(sdmac);
527         else
528                 mxc_sdma_handle_channel_normal(sdmac);
529 }
530
531 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
532 {
533         struct sdma_engine *sdma = dev_id;
534         u32 stat;
535
536         stat = __raw_readl(sdma->regs + SDMA_H_INTR);
537         __raw_writel(stat, sdma->regs + SDMA_H_INTR);
538
539         while (stat) {
540                 int channel = fls(stat) - 1;
541                 struct sdma_channel *sdmac = &sdma->channel[channel];
542
543                 mxc_sdma_handle_channel(sdmac);
544
545                 stat &= ~(1 << channel);
546         }
547
548         return IRQ_HANDLED;
549 }
550
551 /*
552  * sets the pc of SDMA script according to the peripheral type
553  */
554 static void sdma_get_pc(struct sdma_channel *sdmac,
555                 enum sdma_peripheral_type peripheral_type)
556 {
557         struct sdma_engine *sdma = sdmac->sdma;
558         int per_2_emi = 0, emi_2_per = 0;
559         /*
560          * These are needed once we start to support transfers between
561          * two peripherals or memory-to-memory transfers
562          */
563         int per_2_per = 0, emi_2_emi = 0;
564
565         sdmac->pc_from_device = 0;
566         sdmac->pc_to_device = 0;
567
568         switch (peripheral_type) {
569         case IMX_DMATYPE_MEMORY:
570                 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
571                 break;
572         case IMX_DMATYPE_DSP:
573                 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
574                 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
575                 break;
576         case IMX_DMATYPE_FIRI:
577                 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
578                 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
579                 break;
580         case IMX_DMATYPE_UART:
581                 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
582                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
583                 break;
584         case IMX_DMATYPE_UART_SP:
585                 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
586                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
587                 break;
588         case IMX_DMATYPE_ATA:
589                 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
590                 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
591                 break;
592         case IMX_DMATYPE_CSPI:
593         case IMX_DMATYPE_EXT:
594         case IMX_DMATYPE_SSI:
595                 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
596                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
597                 break;
598         case IMX_DMATYPE_SSI_SP:
599         case IMX_DMATYPE_MMC:
600         case IMX_DMATYPE_SDHC:
601         case IMX_DMATYPE_CSPI_SP:
602         case IMX_DMATYPE_ESAI:
603         case IMX_DMATYPE_MSHC_SP:
604                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
605                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
606                 break;
607         case IMX_DMATYPE_ASRC:
608                 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
609                 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
610                 per_2_per = sdma->script_addrs->per_2_per_addr;
611                 break;
612         case IMX_DMATYPE_MSHC:
613                 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
614                 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
615                 break;
616         case IMX_DMATYPE_CCM:
617                 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
618                 break;
619         case IMX_DMATYPE_SPDIF:
620                 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
621                 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
622                 break;
623         case IMX_DMATYPE_IPU_MEMORY:
624                 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
625                 break;
626         default:
627                 break;
628         }
629
630         sdmac->pc_from_device = per_2_emi;
631         sdmac->pc_to_device = emi_2_per;
632 }
633
634 static int sdma_load_context(struct sdma_channel *sdmac)
635 {
636         struct sdma_engine *sdma = sdmac->sdma;
637         int channel = sdmac->channel;
638         int load_address;
639         struct sdma_context_data *context = sdma->context;
640         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
641         int ret;
642
643         if (sdmac->direction == DMA_FROM_DEVICE) {
644                 load_address = sdmac->pc_from_device;
645         } else {
646                 load_address = sdmac->pc_to_device;
647         }
648
649         if (load_address < 0)
650                 return load_address;
651
652         dev_dbg(sdma->dev, "load_address = %d\n", load_address);
653         dev_dbg(sdma->dev, "wml = 0x%08x\n", sdmac->watermark_level);
654         dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
655         dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
656         dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", sdmac->event_mask0);
657         dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", sdmac->event_mask1);
658
659         memset(context, 0, sizeof(*context));
660         context->channel_state.pc = load_address;
661
662         /* Send by context the event mask,base address for peripheral
663          * and watermark level
664          */
665         context->gReg[0] = sdmac->event_mask1;
666         context->gReg[1] = sdmac->event_mask0;
667         context->gReg[2] = sdmac->per_addr;
668         context->gReg[6] = sdmac->shp_addr;
669         context->gReg[7] = sdmac->watermark_level;
670
671         bd0->mode.command = C0_SETDM;
672         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
673         bd0->mode.count = sizeof(*context) / 4;
674         bd0->buffer_addr = sdma->context_phys;
675         bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
676
677         ret = sdma_run_channel(&sdma->channel[0]);
678
679         return ret;
680 }
681
682 static void sdma_disable_channel(struct sdma_channel *sdmac)
683 {
684         struct sdma_engine *sdma = sdmac->sdma;
685         int channel = sdmac->channel;
686
687         __raw_writel(1 << channel, sdma->regs + SDMA_H_STATSTOP);
688         sdmac->status = DMA_ERROR;
689 }
690
691 static int sdma_config_channel(struct sdma_channel *sdmac)
692 {
693         int ret;
694
695         sdma_disable_channel(sdmac);
696
697         sdmac->event_mask0 = 0;
698         sdmac->event_mask1 = 0;
699         sdmac->shp_addr = 0;
700         sdmac->per_addr = 0;
701
702         if (sdmac->event_id0) {
703                 if (sdmac->event_id0 > 32)
704                         return -EINVAL;
705                 sdma_event_enable(sdmac, sdmac->event_id0);
706         }
707
708         switch (sdmac->peripheral_type) {
709         case IMX_DMATYPE_DSP:
710                 sdma_config_ownership(sdmac, false, true, true);
711                 break;
712         case IMX_DMATYPE_MEMORY:
713                 sdma_config_ownership(sdmac, false, true, false);
714                 break;
715         default:
716                 sdma_config_ownership(sdmac, true, true, false);
717                 break;
718         }
719
720         sdma_get_pc(sdmac, sdmac->peripheral_type);
721
722         if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
723                         (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
724                 /* Handle multiple event channels differently */
725                 if (sdmac->event_id1) {
726                         sdmac->event_mask1 = 1 << (sdmac->event_id1 % 32);
727                         if (sdmac->event_id1 > 31)
728                                 sdmac->watermark_level |= 1 << 31;
729                         sdmac->event_mask0 = 1 << (sdmac->event_id0 % 32);
730                         if (sdmac->event_id0 > 31)
731                                 sdmac->watermark_level |= 1 << 30;
732                 } else {
733                         sdmac->event_mask0 = 1 << sdmac->event_id0;
734                         sdmac->event_mask1 = 1 << (sdmac->event_id0 - 32);
735                 }
736                 /* Watermark Level */
737                 sdmac->watermark_level |= sdmac->watermark_level;
738                 /* Address */
739                 sdmac->shp_addr = sdmac->per_address;
740         } else {
741                 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
742         }
743
744         ret = sdma_load_context(sdmac);
745
746         return ret;
747 }
748
749 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
750                 unsigned int priority)
751 {
752         struct sdma_engine *sdma = sdmac->sdma;
753         int channel = sdmac->channel;
754
755         if (priority < MXC_SDMA_MIN_PRIORITY
756             || priority > MXC_SDMA_MAX_PRIORITY) {
757                 return -EINVAL;
758         }
759
760         __raw_writel(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
761
762         return 0;
763 }
764
765 static int sdma_request_channel(struct sdma_channel *sdmac)
766 {
767         struct sdma_engine *sdma = sdmac->sdma;
768         int channel = sdmac->channel;
769         int ret = -EBUSY;
770
771         sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL);
772         if (!sdmac->bd) {
773                 ret = -ENOMEM;
774                 goto out;
775         }
776
777         memset(sdmac->bd, 0, PAGE_SIZE);
778
779         sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
780         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
781
782         clk_enable(sdma->clk);
783
784         sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
785
786         init_completion(&sdmac->done);
787
788         sdmac->buf_tail = 0;
789
790         return 0;
791 out:
792
793         return ret;
794 }
795
796 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
797 {
798         __raw_writel(1 << channel, sdma->regs + SDMA_H_START);
799 }
800
801 static dma_cookie_t sdma_assign_cookie(struct sdma_channel *sdmac)
802 {
803         dma_cookie_t cookie = sdmac->chan.cookie;
804
805         if (++cookie < 0)
806                 cookie = 1;
807
808         sdmac->chan.cookie = cookie;
809         sdmac->desc.cookie = cookie;
810
811         return cookie;
812 }
813
814 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
815 {
816         return container_of(chan, struct sdma_channel, chan);
817 }
818
819 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
820 {
821         struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
822         struct sdma_engine *sdma = sdmac->sdma;
823         dma_cookie_t cookie;
824
825         spin_lock_irq(&sdmac->lock);
826
827         cookie = sdma_assign_cookie(sdmac);
828
829         sdma_enable_channel(sdma, sdmac->channel);
830
831         spin_unlock_irq(&sdmac->lock);
832
833         return cookie;
834 }
835
836 static int sdma_alloc_chan_resources(struct dma_chan *chan)
837 {
838         struct sdma_channel *sdmac = to_sdma_chan(chan);
839         struct imx_dma_data *data = chan->private;
840         int prio, ret;
841
842         if (!data)
843                 return -EINVAL;
844
845         switch (data->priority) {
846         case DMA_PRIO_HIGH:
847                 prio = 3;
848                 break;
849         case DMA_PRIO_MEDIUM:
850                 prio = 2;
851                 break;
852         case DMA_PRIO_LOW:
853         default:
854                 prio = 1;
855                 break;
856         }
857
858         sdmac->peripheral_type = data->peripheral_type;
859         sdmac->event_id0 = data->dma_request;
860         ret = sdma_set_channel_priority(sdmac, prio);
861         if (ret)
862                 return ret;
863
864         ret = sdma_request_channel(sdmac);
865         if (ret)
866                 return ret;
867
868         dma_async_tx_descriptor_init(&sdmac->desc, chan);
869         sdmac->desc.tx_submit = sdma_tx_submit;
870         /* txd.flags will be overwritten in prep funcs */
871         sdmac->desc.flags = DMA_CTRL_ACK;
872
873         return 0;
874 }
875
876 static void sdma_free_chan_resources(struct dma_chan *chan)
877 {
878         struct sdma_channel *sdmac = to_sdma_chan(chan);
879         struct sdma_engine *sdma = sdmac->sdma;
880
881         sdma_disable_channel(sdmac);
882
883         if (sdmac->event_id0)
884                 sdma_event_disable(sdmac, sdmac->event_id0);
885         if (sdmac->event_id1)
886                 sdma_event_disable(sdmac, sdmac->event_id1);
887
888         sdmac->event_id0 = 0;
889         sdmac->event_id1 = 0;
890
891         sdma_set_channel_priority(sdmac, 0);
892
893         dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
894
895         clk_disable(sdma->clk);
896 }
897
898 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
899                 struct dma_chan *chan, struct scatterlist *sgl,
900                 unsigned int sg_len, enum dma_data_direction direction,
901                 unsigned long flags)
902 {
903         struct sdma_channel *sdmac = to_sdma_chan(chan);
904         struct sdma_engine *sdma = sdmac->sdma;
905         int ret, i, count;
906         int channel = sdmac->channel;
907         struct scatterlist *sg;
908
909         if (sdmac->status == DMA_IN_PROGRESS)
910                 return NULL;
911         sdmac->status = DMA_IN_PROGRESS;
912
913         sdmac->flags = 0;
914
915         dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
916                         sg_len, channel);
917
918         sdmac->direction = direction;
919         ret = sdma_load_context(sdmac);
920         if (ret)
921                 goto err_out;
922
923         if (sg_len > NUM_BD) {
924                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
925                                 channel, sg_len, NUM_BD);
926                 ret = -EINVAL;
927                 goto err_out;
928         }
929
930         for_each_sg(sgl, sg, sg_len, i) {
931                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
932                 int param;
933
934                 bd->buffer_addr = sg->dma_address;
935
936                 count = sg->length;
937
938                 if (count > 0xffff) {
939                         dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
940                                         channel, count, 0xffff);
941                         ret = -EINVAL;
942                         goto err_out;
943                 }
944
945                 bd->mode.count = count;
946
947                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
948                         ret =  -EINVAL;
949                         goto err_out;
950                 }
951
952                 switch (sdmac->word_size) {
953                 case DMA_SLAVE_BUSWIDTH_4_BYTES:
954                         bd->mode.command = 0;
955                         if (count & 3 || sg->dma_address & 3)
956                                 return NULL;
957                         break;
958                 case DMA_SLAVE_BUSWIDTH_2_BYTES:
959                         bd->mode.command = 2;
960                         if (count & 1 || sg->dma_address & 1)
961                                 return NULL;
962                         break;
963                 case DMA_SLAVE_BUSWIDTH_1_BYTE:
964                         bd->mode.command = 1;
965                         break;
966                 default:
967                         return NULL;
968                 }
969
970                 param = BD_DONE | BD_EXTD | BD_CONT;
971
972                 if (i + 1 == sg_len) {
973                         param |= BD_INTR;
974                         param |= BD_LAST;
975                         param &= ~BD_CONT;
976                 }
977
978                 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
979                                 i, count, sg->dma_address,
980                                 param & BD_WRAP ? "wrap" : "",
981                                 param & BD_INTR ? " intr" : "");
982
983                 bd->mode.status = param;
984         }
985
986         sdmac->num_bd = sg_len;
987         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
988
989         return &sdmac->desc;
990 err_out:
991         sdmac->status = DMA_ERROR;
992         return NULL;
993 }
994
995 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
996                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
997                 size_t period_len, enum dma_data_direction direction)
998 {
999         struct sdma_channel *sdmac = to_sdma_chan(chan);
1000         struct sdma_engine *sdma = sdmac->sdma;
1001         int num_periods = buf_len / period_len;
1002         int channel = sdmac->channel;
1003         int ret, i = 0, buf = 0;
1004
1005         dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1006
1007         if (sdmac->status == DMA_IN_PROGRESS)
1008                 return NULL;
1009
1010         sdmac->status = DMA_IN_PROGRESS;
1011
1012         sdmac->flags |= IMX_DMA_SG_LOOP;
1013         sdmac->direction = direction;
1014         ret = sdma_load_context(sdmac);
1015         if (ret)
1016                 goto err_out;
1017
1018         if (num_periods > NUM_BD) {
1019                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1020                                 channel, num_periods, NUM_BD);
1021                 goto err_out;
1022         }
1023
1024         if (period_len > 0xffff) {
1025                 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1026                                 channel, period_len, 0xffff);
1027                 goto err_out;
1028         }
1029
1030         while (buf < buf_len) {
1031                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1032                 int param;
1033
1034                 bd->buffer_addr = dma_addr;
1035
1036                 bd->mode.count = period_len;
1037
1038                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1039                         goto err_out;
1040                 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1041                         bd->mode.command = 0;
1042                 else
1043                         bd->mode.command = sdmac->word_size;
1044
1045                 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1046                 if (i + 1 == num_periods)
1047                         param |= BD_WRAP;
1048
1049                 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
1050                                 i, period_len, dma_addr,
1051                                 param & BD_WRAP ? "wrap" : "",
1052                                 param & BD_INTR ? " intr" : "");
1053
1054                 bd->mode.status = param;
1055
1056                 dma_addr += period_len;
1057                 buf += period_len;
1058
1059                 i++;
1060         }
1061
1062         sdmac->num_bd = num_periods;
1063         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1064
1065         return &sdmac->desc;
1066 err_out:
1067         sdmac->status = DMA_ERROR;
1068         return NULL;
1069 }
1070
1071 static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1072                 unsigned long arg)
1073 {
1074         struct sdma_channel *sdmac = to_sdma_chan(chan);
1075         struct dma_slave_config *dmaengine_cfg = (void *)arg;
1076
1077         switch (cmd) {
1078         case DMA_TERMINATE_ALL:
1079                 sdma_disable_channel(sdmac);
1080                 return 0;
1081         case DMA_SLAVE_CONFIG:
1082                 if (dmaengine_cfg->direction == DMA_FROM_DEVICE) {
1083                         sdmac->per_address = dmaengine_cfg->src_addr;
1084                         sdmac->watermark_level = dmaengine_cfg->src_maxburst;
1085                         sdmac->word_size = dmaengine_cfg->src_addr_width;
1086                 } else {
1087                         sdmac->per_address = dmaengine_cfg->dst_addr;
1088                         sdmac->watermark_level = dmaengine_cfg->dst_maxburst;
1089                         sdmac->word_size = dmaengine_cfg->dst_addr_width;
1090                 }
1091                 return sdma_config_channel(sdmac);
1092         default:
1093                 return -ENOSYS;
1094         }
1095
1096         return -EINVAL;
1097 }
1098
1099 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1100                                             dma_cookie_t cookie,
1101                                             struct dma_tx_state *txstate)
1102 {
1103         struct sdma_channel *sdmac = to_sdma_chan(chan);
1104         dma_cookie_t last_used;
1105
1106         last_used = chan->cookie;
1107
1108         dma_set_tx_state(txstate, sdmac->last_completed, last_used, 0);
1109
1110         return sdmac->status;
1111 }
1112
1113 static void sdma_issue_pending(struct dma_chan *chan)
1114 {
1115         /*
1116          * Nothing to do. We only have a single descriptor
1117          */
1118 }
1119
1120 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1121
1122 static void sdma_add_scripts(struct sdma_engine *sdma,
1123                 const struct sdma_script_start_addrs *addr)
1124 {
1125         s32 *addr_arr = (u32 *)addr;
1126         s32 *saddr_arr = (u32 *)sdma->script_addrs;
1127         int i;
1128
1129         for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1130                 if (addr_arr[i] > 0)
1131                         saddr_arr[i] = addr_arr[i];
1132 }
1133
1134 static int __init sdma_get_firmware(struct sdma_engine *sdma,
1135                 const char *fw_name)
1136 {
1137         const struct firmware *fw;
1138         const struct sdma_firmware_header *header;
1139         int ret;
1140         const struct sdma_script_start_addrs *addr;
1141         unsigned short *ram_code;
1142
1143         ret = request_firmware(&fw, fw_name, sdma->dev);
1144         if (ret)
1145                 return ret;
1146
1147         if (fw->size < sizeof(*header))
1148                 goto err_firmware;
1149
1150         header = (struct sdma_firmware_header *)fw->data;
1151
1152         if (header->magic != SDMA_FIRMWARE_MAGIC)
1153                 goto err_firmware;
1154         if (header->ram_code_start + header->ram_code_size > fw->size)
1155                 goto err_firmware;
1156
1157         addr = (void *)header + header->script_addrs_start;
1158         ram_code = (void *)header + header->ram_code_start;
1159
1160         clk_enable(sdma->clk);
1161         /* download the RAM image for SDMA */
1162         sdma_load_script(sdma, ram_code,
1163                         header->ram_code_size,
1164                         addr->ram_code_start_addr);
1165         clk_disable(sdma->clk);
1166
1167         sdma_add_scripts(sdma, addr);
1168
1169         dev_info(sdma->dev, "loaded firmware %d.%d\n",
1170                         header->version_major,
1171                         header->version_minor);
1172
1173 err_firmware:
1174         release_firmware(fw);
1175
1176         return ret;
1177 }
1178
1179 static int __init sdma_init(struct sdma_engine *sdma)
1180 {
1181         int i, ret;
1182         dma_addr_t ccb_phys;
1183
1184         switch (sdma->devtype) {
1185         case IMX31_SDMA:
1186                 sdma->num_events = 32;
1187                 break;
1188         case IMX35_SDMA:
1189                 sdma->num_events = 48;
1190                 break;
1191         default:
1192                 dev_err(sdma->dev, "Unknown sdma type %d. aborting\n",
1193                         sdma->devtype);
1194                 return -ENODEV;
1195         }
1196
1197         clk_enable(sdma->clk);
1198
1199         /* Be sure SDMA has not started yet */
1200         __raw_writel(0, sdma->regs + SDMA_H_C0PTR);
1201
1202         sdma->channel_control = dma_alloc_coherent(NULL,
1203                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1204                         sizeof(struct sdma_context_data),
1205                         &ccb_phys, GFP_KERNEL);
1206
1207         if (!sdma->channel_control) {
1208                 ret = -ENOMEM;
1209                 goto err_dma_alloc;
1210         }
1211
1212         sdma->context = (void *)sdma->channel_control +
1213                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1214         sdma->context_phys = ccb_phys +
1215                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1216
1217         /* Zero-out the CCB structures array just allocated */
1218         memset(sdma->channel_control, 0,
1219                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1220
1221         /* disable all channels */
1222         for (i = 0; i < sdma->num_events; i++)
1223                 __raw_writel(0, sdma->regs + chnenbl_ofs(sdma, i));
1224
1225         /* All channels have priority 0 */
1226         for (i = 0; i < MAX_DMA_CHANNELS; i++)
1227                 __raw_writel(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1228
1229         ret = sdma_request_channel(&sdma->channel[0]);
1230         if (ret)
1231                 goto err_dma_alloc;
1232
1233         sdma_config_ownership(&sdma->channel[0], false, true, false);
1234
1235         /* Set Command Channel (Channel Zero) */
1236         __raw_writel(0x4050, sdma->regs + SDMA_CHN0ADDR);
1237
1238         /* Set bits of CONFIG register but with static context switching */
1239         /* FIXME: Check whether to set ACR bit depending on clock ratios */
1240         __raw_writel(0, sdma->regs + SDMA_H_CONFIG);
1241
1242         __raw_writel(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1243
1244         /* Set bits of CONFIG register with given context switching mode */
1245         __raw_writel(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
1246
1247         /* Initializes channel's priorities */
1248         sdma_set_channel_priority(&sdma->channel[0], 7);
1249
1250         clk_disable(sdma->clk);
1251
1252         return 0;
1253
1254 err_dma_alloc:
1255         clk_disable(sdma->clk);
1256         dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1257         return ret;
1258 }
1259
1260 static int __init sdma_probe(struct platform_device *pdev)
1261 {
1262         const struct of_device_id *of_id =
1263                         of_match_device(sdma_dt_ids, &pdev->dev);
1264         struct device_node *np = pdev->dev.of_node;
1265         const char *fw_name;
1266         int ret;
1267         int irq;
1268         struct resource *iores;
1269         struct sdma_platform_data *pdata = pdev->dev.platform_data;
1270         int i;
1271         struct sdma_engine *sdma;
1272
1273         sdma = kzalloc(sizeof(*sdma), GFP_KERNEL);
1274         if (!sdma)
1275                 return -ENOMEM;
1276
1277         sdma->dev = &pdev->dev;
1278
1279         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1280         irq = platform_get_irq(pdev, 0);
1281         if (!iores || irq < 0) {
1282                 ret = -EINVAL;
1283                 goto err_irq;
1284         }
1285
1286         if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) {
1287                 ret = -EBUSY;
1288                 goto err_request_region;
1289         }
1290
1291         sdma->clk = clk_get(&pdev->dev, NULL);
1292         if (IS_ERR(sdma->clk)) {
1293                 ret = PTR_ERR(sdma->clk);
1294                 goto err_clk;
1295         }
1296
1297         sdma->regs = ioremap(iores->start, resource_size(iores));
1298         if (!sdma->regs) {
1299                 ret = -ENOMEM;
1300                 goto err_ioremap;
1301         }
1302
1303         ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma);
1304         if (ret)
1305                 goto err_request_irq;
1306
1307         sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1308         if (!sdma->script_addrs)
1309                 goto err_alloc;
1310
1311         if (of_id)
1312                 pdev->id_entry = of_id->data;
1313         sdma->devtype = pdev->id_entry->driver_data;
1314
1315         dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1316         dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1317
1318         INIT_LIST_HEAD(&sdma->dma_device.channels);
1319         /* Initialize channel parameters */
1320         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1321                 struct sdma_channel *sdmac = &sdma->channel[i];
1322
1323                 sdmac->sdma = sdma;
1324                 spin_lock_init(&sdmac->lock);
1325
1326                 sdmac->chan.device = &sdma->dma_device;
1327                 sdmac->channel = i;
1328
1329                 /*
1330                  * Add the channel to the DMAC list. Do not add channel 0 though
1331                  * because we need it internally in the SDMA driver. This also means
1332                  * that channel 0 in dmaengine counting matches sdma channel 1.
1333                  */
1334                 if (i)
1335                         list_add_tail(&sdmac->chan.device_node,
1336                                         &sdma->dma_device.channels);
1337         }
1338
1339         ret = sdma_init(sdma);
1340         if (ret)
1341                 goto err_init;
1342
1343         if (pdata && pdata->script_addrs)
1344                 sdma_add_scripts(sdma, pdata->script_addrs);
1345
1346         if (pdata) {
1347                 sdma_get_firmware(sdma, pdata->fw_name);
1348         } else {
1349                 /*
1350                  * Because that device tree does not encode ROM script address,
1351                  * the RAM script in firmware is mandatory for device tree
1352                  * probe, otherwise it fails.
1353                  */
1354                 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1355                                               &fw_name);
1356                 if (ret) {
1357                         dev_err(&pdev->dev, "failed to get firmware name\n");
1358                         goto err_init;
1359                 }
1360
1361                 ret = sdma_get_firmware(sdma, fw_name);
1362                 if (ret) {
1363                         dev_err(&pdev->dev, "failed to get firmware\n");
1364                         goto err_init;
1365                 }
1366         }
1367
1368         sdma->dma_device.dev = &pdev->dev;
1369
1370         sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1371         sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1372         sdma->dma_device.device_tx_status = sdma_tx_status;
1373         sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1374         sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1375         sdma->dma_device.device_control = sdma_control;
1376         sdma->dma_device.device_issue_pending = sdma_issue_pending;
1377         sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1378         dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1379
1380         ret = dma_async_device_register(&sdma->dma_device);
1381         if (ret) {
1382                 dev_err(&pdev->dev, "unable to register\n");
1383                 goto err_init;
1384         }
1385
1386         dev_info(sdma->dev, "initialized\n");
1387
1388         return 0;
1389
1390 err_init:
1391         kfree(sdma->script_addrs);
1392 err_alloc:
1393         free_irq(irq, sdma);
1394 err_request_irq:
1395         iounmap(sdma->regs);
1396 err_ioremap:
1397         clk_put(sdma->clk);
1398 err_clk:
1399         release_mem_region(iores->start, resource_size(iores));
1400 err_request_region:
1401 err_irq:
1402         kfree(sdma);
1403         return ret;
1404 }
1405
1406 static int __exit sdma_remove(struct platform_device *pdev)
1407 {
1408         return -EBUSY;
1409 }
1410
1411 static struct platform_driver sdma_driver = {
1412         .driver         = {
1413                 .name   = "imx-sdma",
1414                 .of_match_table = sdma_dt_ids,
1415         },
1416         .id_table       = sdma_devtypes,
1417         .remove         = __exit_p(sdma_remove),
1418 };
1419
1420 static int __init sdma_module_init(void)
1421 {
1422         return platform_driver_probe(&sdma_driver, sdma_probe);
1423 }
1424 module_init(sdma_module_init);
1425
1426 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1427 MODULE_DESCRIPTION("i.MX SDMA driver");
1428 MODULE_LICENSE("GPL");