dmaengine: imx-sdma: pass sdma firmware name via platform data
[linux-2.6.git] / drivers / dma / imx-sdma.c
1 /*
2  * drivers/dma/imx-sdma.c
3  *
4  * This file contains a driver for the Freescale Smart DMA engine
5  *
6  * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
7  *
8  * Based on code from Freescale:
9  *
10  * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
11  *
12  * The code contained herein is licensed under the GNU General Public
13  * License. You may obtain a copy of the GNU General Public License
14  * Version 2 or later at the following locations:
15  *
16  * http://www.opensource.org/licenses/gpl-license.html
17  * http://www.gnu.org/copyleft/gpl.html
18  */
19
20 #include <linux/init.h>
21 #include <linux/types.h>
22 #include <linux/mm.h>
23 #include <linux/interrupt.h>
24 #include <linux/clk.h>
25 #include <linux/wait.h>
26 #include <linux/sched.h>
27 #include <linux/semaphore.h>
28 #include <linux/spinlock.h>
29 #include <linux/device.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/firmware.h>
32 #include <linux/slab.h>
33 #include <linux/platform_device.h>
34 #include <linux/dmaengine.h>
35
36 #include <asm/irq.h>
37 #include <mach/sdma.h>
38 #include <mach/dma.h>
39 #include <mach/hardware.h>
40
41 /* SDMA registers */
42 #define SDMA_H_C0PTR            0x000
43 #define SDMA_H_INTR             0x004
44 #define SDMA_H_STATSTOP         0x008
45 #define SDMA_H_START            0x00c
46 #define SDMA_H_EVTOVR           0x010
47 #define SDMA_H_DSPOVR           0x014
48 #define SDMA_H_HOSTOVR          0x018
49 #define SDMA_H_EVTPEND          0x01c
50 #define SDMA_H_DSPENBL          0x020
51 #define SDMA_H_RESET            0x024
52 #define SDMA_H_EVTERR           0x028
53 #define SDMA_H_INTRMSK          0x02c
54 #define SDMA_H_PSW              0x030
55 #define SDMA_H_EVTERRDBG        0x034
56 #define SDMA_H_CONFIG           0x038
57 #define SDMA_ONCE_ENB           0x040
58 #define SDMA_ONCE_DATA          0x044
59 #define SDMA_ONCE_INSTR         0x048
60 #define SDMA_ONCE_STAT          0x04c
61 #define SDMA_ONCE_CMD           0x050
62 #define SDMA_EVT_MIRROR         0x054
63 #define SDMA_ILLINSTADDR        0x058
64 #define SDMA_CHN0ADDR           0x05c
65 #define SDMA_ONCE_RTB           0x060
66 #define SDMA_XTRIG_CONF1        0x070
67 #define SDMA_XTRIG_CONF2        0x074
68 #define SDMA_CHNENBL0_V2        0x200
69 #define SDMA_CHNENBL0_V1        0x080
70 #define SDMA_CHNPRI_0           0x100
71
72 /*
73  * Buffer descriptor status values.
74  */
75 #define BD_DONE  0x01
76 #define BD_WRAP  0x02
77 #define BD_CONT  0x04
78 #define BD_INTR  0x08
79 #define BD_RROR  0x10
80 #define BD_LAST  0x20
81 #define BD_EXTD  0x80
82
83 /*
84  * Data Node descriptor status values.
85  */
86 #define DND_END_OF_FRAME  0x80
87 #define DND_END_OF_XFER   0x40
88 #define DND_DONE          0x20
89 #define DND_UNUSED        0x01
90
91 /*
92  * IPCV2 descriptor status values.
93  */
94 #define BD_IPCV2_END_OF_FRAME  0x40
95
96 #define IPCV2_MAX_NODES        50
97 /*
98  * Error bit set in the CCB status field by the SDMA,
99  * in setbd routine, in case of a transfer error
100  */
101 #define DATA_ERROR  0x10000000
102
103 /*
104  * Buffer descriptor commands.
105  */
106 #define C0_ADDR             0x01
107 #define C0_LOAD             0x02
108 #define C0_DUMP             0x03
109 #define C0_SETCTX           0x07
110 #define C0_GETCTX           0x03
111 #define C0_SETDM            0x01
112 #define C0_SETPM            0x04
113 #define C0_GETDM            0x02
114 #define C0_GETPM            0x08
115 /*
116  * Change endianness indicator in the BD command field
117  */
118 #define CHANGE_ENDIANNESS   0x80
119
120 /*
121  * Mode/Count of data node descriptors - IPCv2
122  */
123 struct sdma_mode_count {
124         u32 count   : 16; /* size of the buffer pointed by this BD */
125         u32 status  :  8; /* E,R,I,C,W,D status bits stored here */
126         u32 command :  8; /* command mostlky used for channel 0 */
127 };
128
129 /*
130  * Buffer descriptor
131  */
132 struct sdma_buffer_descriptor {
133         struct sdma_mode_count  mode;
134         u32 buffer_addr;        /* address of the buffer described */
135         u32 ext_buffer_addr;    /* extended buffer address */
136 } __attribute__ ((packed));
137
138 /**
139  * struct sdma_channel_control - Channel control Block
140  *
141  * @current_bd_ptr      current buffer descriptor processed
142  * @base_bd_ptr         first element of buffer descriptor array
143  * @unused              padding. The SDMA engine expects an array of 128 byte
144  *                      control blocks
145  */
146 struct sdma_channel_control {
147         u32 current_bd_ptr;
148         u32 base_bd_ptr;
149         u32 unused[2];
150 } __attribute__ ((packed));
151
152 /**
153  * struct sdma_state_registers - SDMA context for a channel
154  *
155  * @pc:         program counter
156  * @t:          test bit: status of arithmetic & test instruction
157  * @rpc:        return program counter
158  * @sf:         source fault while loading data
159  * @spc:        loop start program counter
160  * @df:         destination fault while storing data
161  * @epc:        loop end program counter
162  * @lm:         loop mode
163  */
164 struct sdma_state_registers {
165         u32 pc     :14;
166         u32 unused1: 1;
167         u32 t      : 1;
168         u32 rpc    :14;
169         u32 unused0: 1;
170         u32 sf     : 1;
171         u32 spc    :14;
172         u32 unused2: 1;
173         u32 df     : 1;
174         u32 epc    :14;
175         u32 lm     : 2;
176 } __attribute__ ((packed));
177
178 /**
179  * struct sdma_context_data - sdma context specific to a channel
180  *
181  * @channel_state:      channel state bits
182  * @gReg:               general registers
183  * @mda:                burst dma destination address register
184  * @msa:                burst dma source address register
185  * @ms:                 burst dma status register
186  * @md:                 burst dma data register
187  * @pda:                peripheral dma destination address register
188  * @psa:                peripheral dma source address register
189  * @ps:                 peripheral dma status register
190  * @pd:                 peripheral dma data register
191  * @ca:                 CRC polynomial register
192  * @cs:                 CRC accumulator register
193  * @dda:                dedicated core destination address register
194  * @dsa:                dedicated core source address register
195  * @ds:                 dedicated core status register
196  * @dd:                 dedicated core data register
197  */
198 struct sdma_context_data {
199         struct sdma_state_registers  channel_state;
200         u32  gReg[8];
201         u32  mda;
202         u32  msa;
203         u32  ms;
204         u32  md;
205         u32  pda;
206         u32  psa;
207         u32  ps;
208         u32  pd;
209         u32  ca;
210         u32  cs;
211         u32  dda;
212         u32  dsa;
213         u32  ds;
214         u32  dd;
215         u32  scratch0;
216         u32  scratch1;
217         u32  scratch2;
218         u32  scratch3;
219         u32  scratch4;
220         u32  scratch5;
221         u32  scratch6;
222         u32  scratch7;
223 } __attribute__ ((packed));
224
225 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
226
227 struct sdma_engine;
228
229 /**
230  * struct sdma_channel - housekeeping for a SDMA channel
231  *
232  * @sdma                pointer to the SDMA engine for this channel
233  * @channel             the channel number, matches dmaengine chan_id + 1
234  * @direction           transfer type. Needed for setting SDMA script
235  * @peripheral_type     Peripheral type. Needed for setting SDMA script
236  * @event_id0           aka dma request line
237  * @event_id1           for channels that use 2 events
238  * @word_size           peripheral access size
239  * @buf_tail            ID of the buffer that was processed
240  * @done                channel completion
241  * @num_bd              max NUM_BD. number of descriptors currently handling
242  */
243 struct sdma_channel {
244         struct sdma_engine              *sdma;
245         unsigned int                    channel;
246         enum dma_data_direction         direction;
247         enum sdma_peripheral_type       peripheral_type;
248         unsigned int                    event_id0;
249         unsigned int                    event_id1;
250         enum dma_slave_buswidth         word_size;
251         unsigned int                    buf_tail;
252         struct completion               done;
253         unsigned int                    num_bd;
254         struct sdma_buffer_descriptor   *bd;
255         dma_addr_t                      bd_phys;
256         unsigned int                    pc_from_device, pc_to_device;
257         unsigned long                   flags;
258         dma_addr_t                      per_address;
259         u32                             event_mask0, event_mask1;
260         u32                             watermark_level;
261         u32                             shp_addr, per_addr;
262         struct dma_chan                 chan;
263         spinlock_t                      lock;
264         struct dma_async_tx_descriptor  desc;
265         dma_cookie_t                    last_completed;
266         enum dma_status                 status;
267 };
268
269 #define IMX_DMA_SG_LOOP         (1 << 0)
270
271 #define MAX_DMA_CHANNELS 32
272 #define MXC_SDMA_DEFAULT_PRIORITY 1
273 #define MXC_SDMA_MIN_PRIORITY 1
274 #define MXC_SDMA_MAX_PRIORITY 7
275
276 #define SDMA_FIRMWARE_MAGIC 0x414d4453
277
278 /**
279  * struct sdma_firmware_header - Layout of the firmware image
280  *
281  * @magic               "SDMA"
282  * @version_major       increased whenever layout of struct sdma_script_start_addrs
283  *                      changes.
284  * @version_minor       firmware minor version (for binary compatible changes)
285  * @script_addrs_start  offset of struct sdma_script_start_addrs in this image
286  * @num_script_addrs    Number of script addresses in this image
287  * @ram_code_start      offset of SDMA ram image in this firmware image
288  * @ram_code_size       size of SDMA ram image
289  * @script_addrs        Stores the start address of the SDMA scripts
290  *                      (in SDMA memory space)
291  */
292 struct sdma_firmware_header {
293         u32     magic;
294         u32     version_major;
295         u32     version_minor;
296         u32     script_addrs_start;
297         u32     num_script_addrs;
298         u32     ram_code_start;
299         u32     ram_code_size;
300 };
301
302 struct sdma_engine {
303         struct device                   *dev;
304         struct device_dma_parameters    dma_parms;
305         struct sdma_channel             channel[MAX_DMA_CHANNELS];
306         struct sdma_channel_control     *channel_control;
307         void __iomem                    *regs;
308         unsigned int                    version;
309         unsigned int                    num_events;
310         struct sdma_context_data        *context;
311         dma_addr_t                      context_phys;
312         struct dma_device               dma_device;
313         struct clk                      *clk;
314         struct sdma_script_start_addrs  *script_addrs;
315 };
316
317 #define SDMA_H_CONFIG_DSPDMA    (1 << 12) /* indicates if the DSPDMA is used */
318 #define SDMA_H_CONFIG_RTD_PINS  (1 << 11) /* indicates if Real-Time Debug pins are enabled */
319 #define SDMA_H_CONFIG_ACR       (1 << 4)  /* indicates if AHB freq /core freq = 2 or 1 */
320 #define SDMA_H_CONFIG_CSM       (3)       /* indicates which context switch mode is selected*/
321
322 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
323 {
324         u32 chnenbl0 = (sdma->version == 2 ? SDMA_CHNENBL0_V2 : SDMA_CHNENBL0_V1);
325
326         return chnenbl0 + event * 4;
327 }
328
329 static int sdma_config_ownership(struct sdma_channel *sdmac,
330                 bool event_override, bool mcu_override, bool dsp_override)
331 {
332         struct sdma_engine *sdma = sdmac->sdma;
333         int channel = sdmac->channel;
334         u32 evt, mcu, dsp;
335
336         if (event_override && mcu_override && dsp_override)
337                 return -EINVAL;
338
339         evt = __raw_readl(sdma->regs + SDMA_H_EVTOVR);
340         mcu = __raw_readl(sdma->regs + SDMA_H_HOSTOVR);
341         dsp = __raw_readl(sdma->regs + SDMA_H_DSPOVR);
342
343         if (dsp_override)
344                 dsp &= ~(1 << channel);
345         else
346                 dsp |= (1 << channel);
347
348         if (event_override)
349                 evt &= ~(1 << channel);
350         else
351                 evt |= (1 << channel);
352
353         if (mcu_override)
354                 mcu &= ~(1 << channel);
355         else
356                 mcu |= (1 << channel);
357
358         __raw_writel(evt, sdma->regs + SDMA_H_EVTOVR);
359         __raw_writel(mcu, sdma->regs + SDMA_H_HOSTOVR);
360         __raw_writel(dsp, sdma->regs + SDMA_H_DSPOVR);
361
362         return 0;
363 }
364
365 /*
366  * sdma_run_channel - run a channel and wait till it's done
367  */
368 static int sdma_run_channel(struct sdma_channel *sdmac)
369 {
370         struct sdma_engine *sdma = sdmac->sdma;
371         int channel = sdmac->channel;
372         int ret;
373
374         init_completion(&sdmac->done);
375
376         __raw_writel(1 << channel, sdma->regs + SDMA_H_START);
377
378         ret = wait_for_completion_timeout(&sdmac->done, HZ);
379
380         return ret ? 0 : -ETIMEDOUT;
381 }
382
383 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
384                 u32 address)
385 {
386         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
387         void *buf_virt;
388         dma_addr_t buf_phys;
389         int ret;
390
391         buf_virt = dma_alloc_coherent(NULL,
392                         size,
393                         &buf_phys, GFP_KERNEL);
394         if (!buf_virt)
395                 return -ENOMEM;
396
397         bd0->mode.command = C0_SETPM;
398         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
399         bd0->mode.count = size / 2;
400         bd0->buffer_addr = buf_phys;
401         bd0->ext_buffer_addr = address;
402
403         memcpy(buf_virt, buf, size);
404
405         ret = sdma_run_channel(&sdma->channel[0]);
406
407         dma_free_coherent(NULL, size, buf_virt, buf_phys);
408
409         return ret;
410 }
411
412 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
413 {
414         struct sdma_engine *sdma = sdmac->sdma;
415         int channel = sdmac->channel;
416         u32 val;
417         u32 chnenbl = chnenbl_ofs(sdma, event);
418
419         val = __raw_readl(sdma->regs + chnenbl);
420         val |= (1 << channel);
421         __raw_writel(val, sdma->regs + chnenbl);
422 }
423
424 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
425 {
426         struct sdma_engine *sdma = sdmac->sdma;
427         int channel = sdmac->channel;
428         u32 chnenbl = chnenbl_ofs(sdma, event);
429         u32 val;
430
431         val = __raw_readl(sdma->regs + chnenbl);
432         val &= ~(1 << channel);
433         __raw_writel(val, sdma->regs + chnenbl);
434 }
435
436 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
437 {
438         struct sdma_buffer_descriptor *bd;
439
440         /*
441          * loop mode. Iterate over descriptors, re-setup them and
442          * call callback function.
443          */
444         while (1) {
445                 bd = &sdmac->bd[sdmac->buf_tail];
446
447                 if (bd->mode.status & BD_DONE)
448                         break;
449
450                 if (bd->mode.status & BD_RROR)
451                         sdmac->status = DMA_ERROR;
452                 else
453                         sdmac->status = DMA_IN_PROGRESS;
454
455                 bd->mode.status |= BD_DONE;
456                 sdmac->buf_tail++;
457                 sdmac->buf_tail %= sdmac->num_bd;
458
459                 if (sdmac->desc.callback)
460                         sdmac->desc.callback(sdmac->desc.callback_param);
461         }
462 }
463
464 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
465 {
466         struct sdma_buffer_descriptor *bd;
467         int i, error = 0;
468
469         /*
470          * non loop mode. Iterate over all descriptors, collect
471          * errors and call callback function
472          */
473         for (i = 0; i < sdmac->num_bd; i++) {
474                 bd = &sdmac->bd[i];
475
476                  if (bd->mode.status & (BD_DONE | BD_RROR))
477                         error = -EIO;
478         }
479
480         if (error)
481                 sdmac->status = DMA_ERROR;
482         else
483                 sdmac->status = DMA_SUCCESS;
484
485         if (sdmac->desc.callback)
486                 sdmac->desc.callback(sdmac->desc.callback_param);
487         sdmac->last_completed = sdmac->desc.cookie;
488 }
489
490 static void mxc_sdma_handle_channel(struct sdma_channel *sdmac)
491 {
492         complete(&sdmac->done);
493
494         /* not interested in channel 0 interrupts */
495         if (sdmac->channel == 0)
496                 return;
497
498         if (sdmac->flags & IMX_DMA_SG_LOOP)
499                 sdma_handle_channel_loop(sdmac);
500         else
501                 mxc_sdma_handle_channel_normal(sdmac);
502 }
503
504 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
505 {
506         struct sdma_engine *sdma = dev_id;
507         u32 stat;
508
509         stat = __raw_readl(sdma->regs + SDMA_H_INTR);
510         __raw_writel(stat, sdma->regs + SDMA_H_INTR);
511
512         while (stat) {
513                 int channel = fls(stat) - 1;
514                 struct sdma_channel *sdmac = &sdma->channel[channel];
515
516                 mxc_sdma_handle_channel(sdmac);
517
518                 stat &= ~(1 << channel);
519         }
520
521         return IRQ_HANDLED;
522 }
523
524 /*
525  * sets the pc of SDMA script according to the peripheral type
526  */
527 static void sdma_get_pc(struct sdma_channel *sdmac,
528                 enum sdma_peripheral_type peripheral_type)
529 {
530         struct sdma_engine *sdma = sdmac->sdma;
531         int per_2_emi = 0, emi_2_per = 0;
532         /*
533          * These are needed once we start to support transfers between
534          * two peripherals or memory-to-memory transfers
535          */
536         int per_2_per = 0, emi_2_emi = 0;
537
538         sdmac->pc_from_device = 0;
539         sdmac->pc_to_device = 0;
540
541         switch (peripheral_type) {
542         case IMX_DMATYPE_MEMORY:
543                 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
544                 break;
545         case IMX_DMATYPE_DSP:
546                 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
547                 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
548                 break;
549         case IMX_DMATYPE_FIRI:
550                 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
551                 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
552                 break;
553         case IMX_DMATYPE_UART:
554                 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
555                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
556                 break;
557         case IMX_DMATYPE_UART_SP:
558                 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
559                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
560                 break;
561         case IMX_DMATYPE_ATA:
562                 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
563                 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
564                 break;
565         case IMX_DMATYPE_CSPI:
566         case IMX_DMATYPE_EXT:
567         case IMX_DMATYPE_SSI:
568                 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
569                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
570                 break;
571         case IMX_DMATYPE_SSI_SP:
572         case IMX_DMATYPE_MMC:
573         case IMX_DMATYPE_SDHC:
574         case IMX_DMATYPE_CSPI_SP:
575         case IMX_DMATYPE_ESAI:
576         case IMX_DMATYPE_MSHC_SP:
577                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
578                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
579                 break;
580         case IMX_DMATYPE_ASRC:
581                 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
582                 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
583                 per_2_per = sdma->script_addrs->per_2_per_addr;
584                 break;
585         case IMX_DMATYPE_MSHC:
586                 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
587                 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
588                 break;
589         case IMX_DMATYPE_CCM:
590                 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
591                 break;
592         case IMX_DMATYPE_SPDIF:
593                 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
594                 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
595                 break;
596         case IMX_DMATYPE_IPU_MEMORY:
597                 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
598                 break;
599         default:
600                 break;
601         }
602
603         sdmac->pc_from_device = per_2_emi;
604         sdmac->pc_to_device = emi_2_per;
605 }
606
607 static int sdma_load_context(struct sdma_channel *sdmac)
608 {
609         struct sdma_engine *sdma = sdmac->sdma;
610         int channel = sdmac->channel;
611         int load_address;
612         struct sdma_context_data *context = sdma->context;
613         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
614         int ret;
615
616         if (sdmac->direction == DMA_FROM_DEVICE) {
617                 load_address = sdmac->pc_from_device;
618         } else {
619                 load_address = sdmac->pc_to_device;
620         }
621
622         if (load_address < 0)
623                 return load_address;
624
625         dev_dbg(sdma->dev, "load_address = %d\n", load_address);
626         dev_dbg(sdma->dev, "wml = 0x%08x\n", sdmac->watermark_level);
627         dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
628         dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
629         dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", sdmac->event_mask0);
630         dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", sdmac->event_mask1);
631
632         memset(context, 0, sizeof(*context));
633         context->channel_state.pc = load_address;
634
635         /* Send by context the event mask,base address for peripheral
636          * and watermark level
637          */
638         context->gReg[0] = sdmac->event_mask1;
639         context->gReg[1] = sdmac->event_mask0;
640         context->gReg[2] = sdmac->per_addr;
641         context->gReg[6] = sdmac->shp_addr;
642         context->gReg[7] = sdmac->watermark_level;
643
644         bd0->mode.command = C0_SETDM;
645         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
646         bd0->mode.count = sizeof(*context) / 4;
647         bd0->buffer_addr = sdma->context_phys;
648         bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
649
650         ret = sdma_run_channel(&sdma->channel[0]);
651
652         return ret;
653 }
654
655 static void sdma_disable_channel(struct sdma_channel *sdmac)
656 {
657         struct sdma_engine *sdma = sdmac->sdma;
658         int channel = sdmac->channel;
659
660         __raw_writel(1 << channel, sdma->regs + SDMA_H_STATSTOP);
661         sdmac->status = DMA_ERROR;
662 }
663
664 static int sdma_config_channel(struct sdma_channel *sdmac)
665 {
666         int ret;
667
668         sdma_disable_channel(sdmac);
669
670         sdmac->event_mask0 = 0;
671         sdmac->event_mask1 = 0;
672         sdmac->shp_addr = 0;
673         sdmac->per_addr = 0;
674
675         if (sdmac->event_id0) {
676                 if (sdmac->event_id0 > 32)
677                         return -EINVAL;
678                 sdma_event_enable(sdmac, sdmac->event_id0);
679         }
680
681         switch (sdmac->peripheral_type) {
682         case IMX_DMATYPE_DSP:
683                 sdma_config_ownership(sdmac, false, true, true);
684                 break;
685         case IMX_DMATYPE_MEMORY:
686                 sdma_config_ownership(sdmac, false, true, false);
687                 break;
688         default:
689                 sdma_config_ownership(sdmac, true, true, false);
690                 break;
691         }
692
693         sdma_get_pc(sdmac, sdmac->peripheral_type);
694
695         if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
696                         (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
697                 /* Handle multiple event channels differently */
698                 if (sdmac->event_id1) {
699                         sdmac->event_mask1 = 1 << (sdmac->event_id1 % 32);
700                         if (sdmac->event_id1 > 31)
701                                 sdmac->watermark_level |= 1 << 31;
702                         sdmac->event_mask0 = 1 << (sdmac->event_id0 % 32);
703                         if (sdmac->event_id0 > 31)
704                                 sdmac->watermark_level |= 1 << 30;
705                 } else {
706                         sdmac->event_mask0 = 1 << sdmac->event_id0;
707                         sdmac->event_mask1 = 1 << (sdmac->event_id0 - 32);
708                 }
709                 /* Watermark Level */
710                 sdmac->watermark_level |= sdmac->watermark_level;
711                 /* Address */
712                 sdmac->shp_addr = sdmac->per_address;
713         } else {
714                 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
715         }
716
717         ret = sdma_load_context(sdmac);
718
719         return ret;
720 }
721
722 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
723                 unsigned int priority)
724 {
725         struct sdma_engine *sdma = sdmac->sdma;
726         int channel = sdmac->channel;
727
728         if (priority < MXC_SDMA_MIN_PRIORITY
729             || priority > MXC_SDMA_MAX_PRIORITY) {
730                 return -EINVAL;
731         }
732
733         __raw_writel(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
734
735         return 0;
736 }
737
738 static int sdma_request_channel(struct sdma_channel *sdmac)
739 {
740         struct sdma_engine *sdma = sdmac->sdma;
741         int channel = sdmac->channel;
742         int ret = -EBUSY;
743
744         sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL);
745         if (!sdmac->bd) {
746                 ret = -ENOMEM;
747                 goto out;
748         }
749
750         memset(sdmac->bd, 0, PAGE_SIZE);
751
752         sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
753         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
754
755         clk_enable(sdma->clk);
756
757         sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
758
759         init_completion(&sdmac->done);
760
761         sdmac->buf_tail = 0;
762
763         return 0;
764 out:
765
766         return ret;
767 }
768
769 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
770 {
771         __raw_writel(1 << channel, sdma->regs + SDMA_H_START);
772 }
773
774 static dma_cookie_t sdma_assign_cookie(struct sdma_channel *sdmac)
775 {
776         dma_cookie_t cookie = sdmac->chan.cookie;
777
778         if (++cookie < 0)
779                 cookie = 1;
780
781         sdmac->chan.cookie = cookie;
782         sdmac->desc.cookie = cookie;
783
784         return cookie;
785 }
786
787 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
788 {
789         return container_of(chan, struct sdma_channel, chan);
790 }
791
792 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
793 {
794         struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
795         struct sdma_engine *sdma = sdmac->sdma;
796         dma_cookie_t cookie;
797
798         spin_lock_irq(&sdmac->lock);
799
800         cookie = sdma_assign_cookie(sdmac);
801
802         sdma_enable_channel(sdma, sdmac->channel);
803
804         spin_unlock_irq(&sdmac->lock);
805
806         return cookie;
807 }
808
809 static int sdma_alloc_chan_resources(struct dma_chan *chan)
810 {
811         struct sdma_channel *sdmac = to_sdma_chan(chan);
812         struct imx_dma_data *data = chan->private;
813         int prio, ret;
814
815         if (!data)
816                 return -EINVAL;
817
818         switch (data->priority) {
819         case DMA_PRIO_HIGH:
820                 prio = 3;
821                 break;
822         case DMA_PRIO_MEDIUM:
823                 prio = 2;
824                 break;
825         case DMA_PRIO_LOW:
826         default:
827                 prio = 1;
828                 break;
829         }
830
831         sdmac->peripheral_type = data->peripheral_type;
832         sdmac->event_id0 = data->dma_request;
833         ret = sdma_set_channel_priority(sdmac, prio);
834         if (ret)
835                 return ret;
836
837         ret = sdma_request_channel(sdmac);
838         if (ret)
839                 return ret;
840
841         dma_async_tx_descriptor_init(&sdmac->desc, chan);
842         sdmac->desc.tx_submit = sdma_tx_submit;
843         /* txd.flags will be overwritten in prep funcs */
844         sdmac->desc.flags = DMA_CTRL_ACK;
845
846         return 0;
847 }
848
849 static void sdma_free_chan_resources(struct dma_chan *chan)
850 {
851         struct sdma_channel *sdmac = to_sdma_chan(chan);
852         struct sdma_engine *sdma = sdmac->sdma;
853
854         sdma_disable_channel(sdmac);
855
856         if (sdmac->event_id0)
857                 sdma_event_disable(sdmac, sdmac->event_id0);
858         if (sdmac->event_id1)
859                 sdma_event_disable(sdmac, sdmac->event_id1);
860
861         sdmac->event_id0 = 0;
862         sdmac->event_id1 = 0;
863
864         sdma_set_channel_priority(sdmac, 0);
865
866         dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
867
868         clk_disable(sdma->clk);
869 }
870
871 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
872                 struct dma_chan *chan, struct scatterlist *sgl,
873                 unsigned int sg_len, enum dma_data_direction direction,
874                 unsigned long flags)
875 {
876         struct sdma_channel *sdmac = to_sdma_chan(chan);
877         struct sdma_engine *sdma = sdmac->sdma;
878         int ret, i, count;
879         int channel = sdmac->channel;
880         struct scatterlist *sg;
881
882         if (sdmac->status == DMA_IN_PROGRESS)
883                 return NULL;
884         sdmac->status = DMA_IN_PROGRESS;
885
886         sdmac->flags = 0;
887
888         dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
889                         sg_len, channel);
890
891         sdmac->direction = direction;
892         ret = sdma_load_context(sdmac);
893         if (ret)
894                 goto err_out;
895
896         if (sg_len > NUM_BD) {
897                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
898                                 channel, sg_len, NUM_BD);
899                 ret = -EINVAL;
900                 goto err_out;
901         }
902
903         for_each_sg(sgl, sg, sg_len, i) {
904                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
905                 int param;
906
907                 bd->buffer_addr = sg->dma_address;
908
909                 count = sg->length;
910
911                 if (count > 0xffff) {
912                         dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
913                                         channel, count, 0xffff);
914                         ret = -EINVAL;
915                         goto err_out;
916                 }
917
918                 bd->mode.count = count;
919
920                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
921                         ret =  -EINVAL;
922                         goto err_out;
923                 }
924
925                 switch (sdmac->word_size) {
926                 case DMA_SLAVE_BUSWIDTH_4_BYTES:
927                         bd->mode.command = 0;
928                         if (count & 3 || sg->dma_address & 3)
929                                 return NULL;
930                         break;
931                 case DMA_SLAVE_BUSWIDTH_2_BYTES:
932                         bd->mode.command = 2;
933                         if (count & 1 || sg->dma_address & 1)
934                                 return NULL;
935                         break;
936                 case DMA_SLAVE_BUSWIDTH_1_BYTE:
937                         bd->mode.command = 1;
938                         break;
939                 default:
940                         return NULL;
941                 }
942
943                 param = BD_DONE | BD_EXTD | BD_CONT;
944
945                 if (i + 1 == sg_len) {
946                         param |= BD_INTR;
947                         param |= BD_LAST;
948                         param &= ~BD_CONT;
949                 }
950
951                 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
952                                 i, count, sg->dma_address,
953                                 param & BD_WRAP ? "wrap" : "",
954                                 param & BD_INTR ? " intr" : "");
955
956                 bd->mode.status = param;
957         }
958
959         sdmac->num_bd = sg_len;
960         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
961
962         return &sdmac->desc;
963 err_out:
964         sdmac->status = DMA_ERROR;
965         return NULL;
966 }
967
968 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
969                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
970                 size_t period_len, enum dma_data_direction direction)
971 {
972         struct sdma_channel *sdmac = to_sdma_chan(chan);
973         struct sdma_engine *sdma = sdmac->sdma;
974         int num_periods = buf_len / period_len;
975         int channel = sdmac->channel;
976         int ret, i = 0, buf = 0;
977
978         dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
979
980         if (sdmac->status == DMA_IN_PROGRESS)
981                 return NULL;
982
983         sdmac->status = DMA_IN_PROGRESS;
984
985         sdmac->flags |= IMX_DMA_SG_LOOP;
986         sdmac->direction = direction;
987         ret = sdma_load_context(sdmac);
988         if (ret)
989                 goto err_out;
990
991         if (num_periods > NUM_BD) {
992                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
993                                 channel, num_periods, NUM_BD);
994                 goto err_out;
995         }
996
997         if (period_len > 0xffff) {
998                 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
999                                 channel, period_len, 0xffff);
1000                 goto err_out;
1001         }
1002
1003         while (buf < buf_len) {
1004                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1005                 int param;
1006
1007                 bd->buffer_addr = dma_addr;
1008
1009                 bd->mode.count = period_len;
1010
1011                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1012                         goto err_out;
1013                 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1014                         bd->mode.command = 0;
1015                 else
1016                         bd->mode.command = sdmac->word_size;
1017
1018                 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1019                 if (i + 1 == num_periods)
1020                         param |= BD_WRAP;
1021
1022                 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
1023                                 i, period_len, dma_addr,
1024                                 param & BD_WRAP ? "wrap" : "",
1025                                 param & BD_INTR ? " intr" : "");
1026
1027                 bd->mode.status = param;
1028
1029                 dma_addr += period_len;
1030                 buf += period_len;
1031
1032                 i++;
1033         }
1034
1035         sdmac->num_bd = num_periods;
1036         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1037
1038         return &sdmac->desc;
1039 err_out:
1040         sdmac->status = DMA_ERROR;
1041         return NULL;
1042 }
1043
1044 static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1045                 unsigned long arg)
1046 {
1047         struct sdma_channel *sdmac = to_sdma_chan(chan);
1048         struct dma_slave_config *dmaengine_cfg = (void *)arg;
1049
1050         switch (cmd) {
1051         case DMA_TERMINATE_ALL:
1052                 sdma_disable_channel(sdmac);
1053                 return 0;
1054         case DMA_SLAVE_CONFIG:
1055                 if (dmaengine_cfg->direction == DMA_FROM_DEVICE) {
1056                         sdmac->per_address = dmaengine_cfg->src_addr;
1057                         sdmac->watermark_level = dmaengine_cfg->src_maxburst;
1058                         sdmac->word_size = dmaengine_cfg->src_addr_width;
1059                 } else {
1060                         sdmac->per_address = dmaengine_cfg->dst_addr;
1061                         sdmac->watermark_level = dmaengine_cfg->dst_maxburst;
1062                         sdmac->word_size = dmaengine_cfg->dst_addr_width;
1063                 }
1064                 return sdma_config_channel(sdmac);
1065         default:
1066                 return -ENOSYS;
1067         }
1068
1069         return -EINVAL;
1070 }
1071
1072 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1073                                             dma_cookie_t cookie,
1074                                             struct dma_tx_state *txstate)
1075 {
1076         struct sdma_channel *sdmac = to_sdma_chan(chan);
1077         dma_cookie_t last_used;
1078
1079         last_used = chan->cookie;
1080
1081         dma_set_tx_state(txstate, sdmac->last_completed, last_used, 0);
1082
1083         return sdmac->status;
1084 }
1085
1086 static void sdma_issue_pending(struct dma_chan *chan)
1087 {
1088         /*
1089          * Nothing to do. We only have a single descriptor
1090          */
1091 }
1092
1093 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1094
1095 static void sdma_add_scripts(struct sdma_engine *sdma,
1096                 const struct sdma_script_start_addrs *addr)
1097 {
1098         s32 *addr_arr = (u32 *)addr;
1099         s32 *saddr_arr = (u32 *)sdma->script_addrs;
1100         int i;
1101
1102         for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1103                 if (addr_arr[i] > 0)
1104                         saddr_arr[i] = addr_arr[i];
1105 }
1106
1107 static int __init sdma_get_firmware(struct sdma_engine *sdma,
1108                 const char *fw_name)
1109 {
1110         const struct firmware *fw;
1111         char *fwname;
1112         const struct sdma_firmware_header *header;
1113         int ret;
1114         const struct sdma_script_start_addrs *addr;
1115         unsigned short *ram_code;
1116
1117         fwname = kasprintf(GFP_KERNEL, "%s", fw_name);
1118         if (!fwname)
1119                 return -ENOMEM;
1120
1121         ret = request_firmware(&fw, fwname, sdma->dev);
1122         if (ret) {
1123                 kfree(fwname);
1124                 return ret;
1125         }
1126         kfree(fwname);
1127
1128         if (fw->size < sizeof(*header))
1129                 goto err_firmware;
1130
1131         header = (struct sdma_firmware_header *)fw->data;
1132
1133         if (header->magic != SDMA_FIRMWARE_MAGIC)
1134                 goto err_firmware;
1135         if (header->ram_code_start + header->ram_code_size > fw->size)
1136                 goto err_firmware;
1137
1138         addr = (void *)header + header->script_addrs_start;
1139         ram_code = (void *)header + header->ram_code_start;
1140
1141         clk_enable(sdma->clk);
1142         /* download the RAM image for SDMA */
1143         sdma_load_script(sdma, ram_code,
1144                         header->ram_code_size,
1145                         addr->ram_code_start_addr);
1146         clk_disable(sdma->clk);
1147
1148         sdma_add_scripts(sdma, addr);
1149
1150         dev_info(sdma->dev, "loaded firmware %d.%d\n",
1151                         header->version_major,
1152                         header->version_minor);
1153
1154 err_firmware:
1155         release_firmware(fw);
1156
1157         return ret;
1158 }
1159
1160 static int __init sdma_init(struct sdma_engine *sdma)
1161 {
1162         int i, ret;
1163         dma_addr_t ccb_phys;
1164
1165         switch (sdma->version) {
1166         case 1:
1167                 sdma->num_events = 32;
1168                 break;
1169         case 2:
1170                 sdma->num_events = 48;
1171                 break;
1172         default:
1173                 dev_err(sdma->dev, "Unknown version %d. aborting\n", sdma->version);
1174                 return -ENODEV;
1175         }
1176
1177         clk_enable(sdma->clk);
1178
1179         /* Be sure SDMA has not started yet */
1180         __raw_writel(0, sdma->regs + SDMA_H_C0PTR);
1181
1182         sdma->channel_control = dma_alloc_coherent(NULL,
1183                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1184                         sizeof(struct sdma_context_data),
1185                         &ccb_phys, GFP_KERNEL);
1186
1187         if (!sdma->channel_control) {
1188                 ret = -ENOMEM;
1189                 goto err_dma_alloc;
1190         }
1191
1192         sdma->context = (void *)sdma->channel_control +
1193                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1194         sdma->context_phys = ccb_phys +
1195                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1196
1197         /* Zero-out the CCB structures array just allocated */
1198         memset(sdma->channel_control, 0,
1199                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1200
1201         /* disable all channels */
1202         for (i = 0; i < sdma->num_events; i++)
1203                 __raw_writel(0, sdma->regs + chnenbl_ofs(sdma, i));
1204
1205         /* All channels have priority 0 */
1206         for (i = 0; i < MAX_DMA_CHANNELS; i++)
1207                 __raw_writel(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1208
1209         ret = sdma_request_channel(&sdma->channel[0]);
1210         if (ret)
1211                 goto err_dma_alloc;
1212
1213         sdma_config_ownership(&sdma->channel[0], false, true, false);
1214
1215         /* Set Command Channel (Channel Zero) */
1216         __raw_writel(0x4050, sdma->regs + SDMA_CHN0ADDR);
1217
1218         /* Set bits of CONFIG register but with static context switching */
1219         /* FIXME: Check whether to set ACR bit depending on clock ratios */
1220         __raw_writel(0, sdma->regs + SDMA_H_CONFIG);
1221
1222         __raw_writel(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1223
1224         /* Set bits of CONFIG register with given context switching mode */
1225         __raw_writel(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
1226
1227         /* Initializes channel's priorities */
1228         sdma_set_channel_priority(&sdma->channel[0], 7);
1229
1230         clk_disable(sdma->clk);
1231
1232         return 0;
1233
1234 err_dma_alloc:
1235         clk_disable(sdma->clk);
1236         dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1237         return ret;
1238 }
1239
1240 static int __init sdma_probe(struct platform_device *pdev)
1241 {
1242         int ret;
1243         int irq;
1244         struct resource *iores;
1245         struct sdma_platform_data *pdata = pdev->dev.platform_data;
1246         int i;
1247         struct sdma_engine *sdma;
1248
1249         sdma = kzalloc(sizeof(*sdma), GFP_KERNEL);
1250         if (!sdma)
1251                 return -ENOMEM;
1252
1253         sdma->dev = &pdev->dev;
1254
1255         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1256         irq = platform_get_irq(pdev, 0);
1257         if (!iores || irq < 0 || !pdata) {
1258                 ret = -EINVAL;
1259                 goto err_irq;
1260         }
1261
1262         if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) {
1263                 ret = -EBUSY;
1264                 goto err_request_region;
1265         }
1266
1267         sdma->clk = clk_get(&pdev->dev, NULL);
1268         if (IS_ERR(sdma->clk)) {
1269                 ret = PTR_ERR(sdma->clk);
1270                 goto err_clk;
1271         }
1272
1273         sdma->regs = ioremap(iores->start, resource_size(iores));
1274         if (!sdma->regs) {
1275                 ret = -ENOMEM;
1276                 goto err_ioremap;
1277         }
1278
1279         ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma);
1280         if (ret)
1281                 goto err_request_irq;
1282
1283         sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1284         if (!sdma->script_addrs)
1285                 goto err_alloc;
1286
1287         sdma->version = pdata->sdma_version;
1288
1289         dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1290         dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1291
1292         INIT_LIST_HEAD(&sdma->dma_device.channels);
1293         /* Initialize channel parameters */
1294         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1295                 struct sdma_channel *sdmac = &sdma->channel[i];
1296
1297                 sdmac->sdma = sdma;
1298                 spin_lock_init(&sdmac->lock);
1299
1300                 sdmac->chan.device = &sdma->dma_device;
1301                 sdmac->channel = i;
1302
1303                 /*
1304                  * Add the channel to the DMAC list. Do not add channel 0 though
1305                  * because we need it internally in the SDMA driver. This also means
1306                  * that channel 0 in dmaengine counting matches sdma channel 1.
1307                  */
1308                 if (i)
1309                         list_add_tail(&sdmac->chan.device_node,
1310                                         &sdma->dma_device.channels);
1311         }
1312
1313         ret = sdma_init(sdma);
1314         if (ret)
1315                 goto err_init;
1316
1317         if (pdata->script_addrs)
1318                 sdma_add_scripts(sdma, pdata->script_addrs);
1319
1320         sdma_get_firmware(sdma, pdata->fw_name);
1321
1322         sdma->dma_device.dev = &pdev->dev;
1323
1324         sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1325         sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1326         sdma->dma_device.device_tx_status = sdma_tx_status;
1327         sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1328         sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1329         sdma->dma_device.device_control = sdma_control;
1330         sdma->dma_device.device_issue_pending = sdma_issue_pending;
1331         sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1332         dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1333
1334         ret = dma_async_device_register(&sdma->dma_device);
1335         if (ret) {
1336                 dev_err(&pdev->dev, "unable to register\n");
1337                 goto err_init;
1338         }
1339
1340         dev_info(sdma->dev, "initialized\n");
1341
1342         return 0;
1343
1344 err_init:
1345         kfree(sdma->script_addrs);
1346 err_alloc:
1347         free_irq(irq, sdma);
1348 err_request_irq:
1349         iounmap(sdma->regs);
1350 err_ioremap:
1351         clk_put(sdma->clk);
1352 err_clk:
1353         release_mem_region(iores->start, resource_size(iores));
1354 err_request_region:
1355 err_irq:
1356         kfree(sdma);
1357         return ret;
1358 }
1359
1360 static int __exit sdma_remove(struct platform_device *pdev)
1361 {
1362         return -EBUSY;
1363 }
1364
1365 static struct platform_driver sdma_driver = {
1366         .driver         = {
1367                 .name   = "imx-sdma",
1368         },
1369         .remove         = __exit_p(sdma_remove),
1370 };
1371
1372 static int __init sdma_module_init(void)
1373 {
1374         return platform_driver_probe(&sdma_driver, sdma_probe);
1375 }
1376 module_init(sdma_module_init);
1377
1378 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1379 MODULE_DESCRIPTION("i.MX SDMA driver");
1380 MODULE_LICENSE("GPL");